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authorJim Grosbach <grosbach@apple.com>2010-12-04 00:20:40 +0000
committerJim Grosbach <grosbach@apple.com>2010-12-04 00:20:40 +0000
commitceab50198ee0d1aa2468d868111e3cf7c0c56ebd (patch)
treebb2d01bbbd70ca04036a0c6dae7385bb43a67baf
parentb7bbd461223924e7fa05d98dbeadfc4b4a0093d1 (diff)
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Encode condition code for Thumb1 conditional branch instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120865 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMInstrThumb.td9
1 files changed, 6 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index f0fcdd4..a8681ae 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -475,10 +475,13 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
// a two-value operand where a dag node expects two operands. :(
let isBranch = 1, isTerminator = 1 in
- def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
- "b$cc\t$target",
+ def tBcc : T1I<(outs), (ins brtarget:$target, pred:$p), IIC_Br,
+ "b${p}\t$target",
[/*(ARMbrcond bb:$target, imm:$cc)*/]>,
- T1Encoding<{1,1,0,1,?,?}>;
+ T1Encoding<{1,1,0,1,?,?}> {
+ bits<4> p;
+ let Inst{11-8} = p;
+}
// Compare and branch on zero / non-zero
let isBranch = 1, isTerminator = 1 in {