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authorHal Finkel <hfinkel@anl.gov>2012-03-22 05:28:19 +0000
committerHal Finkel <hfinkel@anl.gov>2012-03-22 05:28:19 +0000
commitf2f6182f6a88cf4b8d8cb95686d68aa14ddb6857 (patch)
tree2863a8aa823335232946291d2258919900c0027a
parenteabe3ad57d824c2b07016352fd97ce85777b6f9d (diff)
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PPC::DBG_VALUE must use Reg+Imm frame-index elimination even for large offsets. Fixes PR12203.
I don't have a small test case yet, but I'll try to construct one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153240 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/PowerPC/PPCRegisterInfo.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 2976f01..ef13571 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -554,7 +554,8 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// clear can be encoded. This is extremely uncommon, because normally you
// only "std" to a stack slot that is at least 4-byte aligned, but it can
// happen in invalid code.
- if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
+ if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
+ (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) {
if (isIXAddr)
Offset >>= 2; // The actual encoded value has the low two bits zero.
MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);