Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.

This update was done with the following bash script:

  find test/CodeGen -name "*.ll" | \
  while read NAME; do
    echo "$NAME"
    if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
      TEMP=`mktemp -t temp`
      cp $NAME $TEMP
      sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
      while read FUNC; do
        sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
      done
      sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
      sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
      sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
      sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
      mv $TEMP $NAME
    fi
  done


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8

937 files changed, 8028 insertions, 8028 deletions

diff --git a/test/CodeGen/AArch64/addsub.ll b/test/CodeGen/AArch64/addsub.ll
index c0e1cc9..4d46d04 100644
--- a/test/CodeGen/AArch64/addsub.ll
+++ b/test/CodeGen/AArch64/addsub.ll
@@ -9,7 +9,7 @@
 
 ; Add pure 12-bit immediates:
 define void @add_small() {
-; CHECK: add_small:
+; CHECK-LABEL: add_small:
 
 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4095
   %val32 = load i32* @var_i32
@@ -26,7 +26,7 @@ define void @add_small() {
 
 ; Add 12-bit immediates, shifted left by 12 bits
 define void @add_med() {
-; CHECK: add_med:
+; CHECK-LABEL: add_med:
 
 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
   %val32 = load i32* @var_i32
@@ -43,7 +43,7 @@ define void @add_med() {
 
 ; Subtract 12-bit immediates
 define void @sub_small() {
-; CHECK: sub_small:
+; CHECK-LABEL: sub_small:
 
 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4095
   %val32 = load i32* @var_i32
@@ -60,7 +60,7 @@ define void @sub_small() {
 
 ; Subtract 12-bit immediates, shifted left by 12 bits
 define void @sub_med() {
-; CHECK: sub_med:
+; CHECK-LABEL: sub_med:
 
 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
   %val32 = load i32* @var_i32
diff --git a/test/CodeGen/AArch64/addsub_ext.ll b/test/CodeGen/AArch64/addsub_ext.ll
index 0bda0f9..f0e11c6 100644
--- a/test/CodeGen/AArch64/addsub_ext.ll
+++ b/test/CodeGen/AArch64/addsub_ext.ll
@@ -6,7 +6,7 @@
 @var64 = global i64 0
 
 define void @addsub_i8rhs() {
-; CHECK: addsub_i8rhs:
+; CHECK-LABEL: addsub_i8rhs:
     %val8_tmp = load i8* @var8
     %lhs32 = load i32* @var32
     %lhs64 = load i64* @var64
@@ -81,7 +81,7 @@ end:
 }
 
 define void @addsub_i16rhs() {
-; CHECK: addsub_i16rhs:
+; CHECK-LABEL: addsub_i16rhs:
     %val16_tmp = load i16* @var16
     %lhs32 = load i32* @var32
     %lhs64 = load i64* @var64
@@ -159,7 +159,7 @@ end:
 ; example), but the remaining instructions are probably not idiomatic
 ; in the face of "add/sub (shifted register)" so I don't intend to.
 define void @addsub_i32rhs() {
-; CHECK: addsub_i32rhs:
+; CHECK-LABEL: addsub_i32rhs:
     %val32_tmp = load i32* @var32
     %lhs64 = load i64* @var64
 
diff --git a/test/CodeGen/AArch64/atomic-ops-not-barriers.ll b/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
index 9888a74..da095a0 100644
--- a/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
+++ b/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
 
 define i32 @foo(i32* %var, i1 %cond) {
-; CHECK: foo:
+; CHECK-LABEL: foo:
   br i1 %cond, label %atomic_ver, label %simple_ver
 simple_ver:
   %oldval = load i32* %var
diff --git a/test/CodeGen/AArch64/basic-pic.ll b/test/CodeGen/AArch64/basic-pic.ll
index 1f0b282..1b14be2 100644
--- a/test/CodeGen/AArch64/basic-pic.ll
+++ b/test/CodeGen/AArch64/basic-pic.ll
@@ -6,7 +6,7 @@
 ; CHECK-ELF: RELOCATION RECORDS FOR [.rela.text]
 
 define i32 @get_globalvar() {
-; CHECK: get_globalvar:
+; CHECK-LABEL: get_globalvar:
 
   %val = load i32* @var
 ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
@@ -19,7 +19,7 @@ define i32 @get_globalvar() {
 }
 
 define i32* @get_globalvaraddr() {
-; CHECK: get_globalvaraddr:
+; CHECK-LABEL: get_globalvaraddr:
 
   %val = load i32* @var
 ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
@@ -33,7 +33,7 @@ define i32* @get_globalvaraddr() {
 @hiddenvar = hidden global i32 0
 
 define i32 @get_hiddenvar() {
-; CHECK: get_hiddenvar:
+; CHECK-LABEL: get_hiddenvar:
 
   %val = load i32* @hiddenvar
 ; CHECK: adrp x[[HI:[0-9]+]], hiddenvar
@@ -45,7 +45,7 @@ define i32 @get_hiddenvar() {
 }
 
 define i32* @get_hiddenvaraddr() {
-; CHECK: get_hiddenvaraddr:
+; CHECK-LABEL: get_hiddenvaraddr:
 
   %val = load i32* @hiddenvar
 ; CHECK: adrp [[HI:x[0-9]+]], hiddenvar
@@ -57,7 +57,7 @@ define i32* @get_hiddenvaraddr() {
 }
 
 define void()* @get_func() {
-; CHECK: get_func:
+; CHECK-LABEL: get_func:
 
   ret void()* bitcast(void()*()* @get_func to void()*)
 ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:get_func
diff --git a/test/CodeGen/AArch64/bitfield-insert.ll b/test/CodeGen/AArch64/bitfield-insert.ll
index fe2aedb..1f04608 100644
--- a/test/CodeGen/AArch64/bitfield-insert.ll
+++ b/test/CodeGen/AArch64/bitfield-insert.ll
@@ -6,7 +6,7 @@
 %struct.foo = type { i8, [2 x i8], i8 }
 
 define [1 x i64] @from_clang([1 x i64] %f.coerce, i32 %n) nounwind readnone {
-; CHECK: from_clang:
+; CHECK-LABEL: from_clang:
 ; CHECK: bfi w0, w1, #3, #4
 ; CHECK-NEXT: ret
 
diff --git a/test/CodeGen/AArch64/breg.ll b/test/CodeGen/AArch64/breg.ll
index 38ed473..1ed5b9b 100644
--- a/test/CodeGen/AArch64/breg.ll
+++ b/test/CodeGen/AArch64/breg.ll
@@ -3,7 +3,7 @@
 @stored_label = global i8* null
 
 define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
   %lab = load i8** @stored_label
   indirectbr i8* %lab, [label  %otherlab, label %retlab]
 ; CHECK: adrp {{x[0-9]+}}, stored_label
diff --git a/test/CodeGen/AArch64/callee-save.ll b/test/CodeGen/AArch64/callee-save.ll
index c66aa5b..52243b0 100644
--- a/test/CodeGen/AArch64/callee-save.ll
+++ b/test/CodeGen/AArch64/callee-save.ll
@@ -3,7 +3,7 @@
 @var = global float 0.0
 
 define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 
 ; CHECK: stp d14, d15, [sp
 ; CHECK: stp d12, d13, [sp
diff --git a/test/CodeGen/AArch64/code-model-large-abs.ll b/test/CodeGen/AArch64/code-model-large-abs.ll
index a365568..b387f28 100644
--- a/test/CodeGen/AArch64/code-model-large-abs.ll
+++ b/test/CodeGen/AArch64/code-model-large-abs.ll
@@ -6,7 +6,7 @@
 @var64 = global i64 0
 
 define i8* @global_addr() {
-; CHECK: global_addr:
+; CHECK-LABEL: global_addr:
   ret i8* @var8
   ; The movz/movk calculation should end up returned directly in x0.
 ; CHECK: movz x0, #:abs_g3:var8
@@ -17,7 +17,7 @@ define i8* @global_addr() {
 }
 
 define i8 @global_i8() {
-; CHECK: global_i8:
+; CHECK-LABEL: global_i8:
   %val = load i8* @var8
   ret i8 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
@@ -28,7 +28,7 @@ define i8 @global_i8() {
 }
 
 define i16 @global_i16() {
-; CHECK: global_i16:
+; CHECK-LABEL: global_i16:
   %val = load i16* @var16
   ret i16 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
@@ -39,7 +39,7 @@ define i16 @global_i16() {
 }
 
 define i32 @global_i32() {
-; CHECK: global_i32:
+; CHECK-LABEL: global_i32:
   %val = load i32* @var32
   ret i32 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
@@ -50,7 +50,7 @@ define i32 @global_i32() {
 }
 
 define i64 @global_i64() {
-; CHECK: global_i64:
+; CHECK-LABEL: global_i64:
   %val = load i64* @var64
   ret i64 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
diff --git a/test/CodeGen/AArch64/compare-branch.ll b/test/CodeGen/AArch64/compare-branch.ll
index 62f4cd5..75efd9d 100644
--- a/test/CodeGen/AArch64/compare-branch.ll
+++ b/test/CodeGen/AArch64/compare-branch.ll
@@ -4,7 +4,7 @@
 @var64 = global i64 0
 
 define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 
   %val1 = load volatile i32* @var32
   %tst1 = icmp eq i32 %val1, 0
diff --git a/test/CodeGen/AArch64/dp1.ll b/test/CodeGen/AArch64/dp1.ll
index 83aa8b4..6a8d55c 100644
--- a/test/CodeGen/AArch64/dp1.ll
+++ b/test/CodeGen/AArch64/dp1.ll
@@ -4,7 +4,7 @@
 @var64 = global i64 0
 
 define void @rev_i32() {
-; CHECK: rev_i32:
+; CHECK-LABEL: rev_i32:
     %val0_tmp = load i32* @var32
     %val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
 ; CHECK: rev	{{w[0-9]+}}, {{w[0-9]+}}
@@ -13,7 +13,7 @@ define void @rev_i32() {
 }
 
 define void @rev_i64() {
-; CHECK: rev_i64:
+; CHECK-LABEL: rev_i64:
     %val0_tmp = load i64* @var64
     %val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
 ; CHECK: rev	{{x[0-9]+}}, {{x[0-9]+}}
@@ -22,7 +22,7 @@ define void @rev_i64() {
 }
 
 define void @rev32_i64() {
-; CHECK: rev32_i64:
+; CHECK-LABEL: rev32_i64:
     %val0_tmp = load i64* @var64
     %val1_tmp = shl i64 %val0_tmp, 32
     %val5_tmp = sub i64 64, 32
@@ -35,7 +35,7 @@ define void @rev32_i64() {
 }
 
 define void @rev16_i32() {
-; CHECK: rev16_i32:
+; CHECK-LABEL: rev16_i32:
     %val0_tmp = load i32* @var32
     %val1_tmp = shl i32 %val0_tmp, 16
     %val2_tmp = lshr i32 %val0_tmp, 16
@@ -47,7 +47,7 @@ define void @rev16_i32() {
 }
 
 define void @clz_zerodef_i32() {
-; CHECK: clz_zerodef_i32:
+; CHECK-LABEL: clz_zerodef_i32:
     %val0_tmp = load i32* @var32
     %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0)
 ; CHECK: clz	{{w[0-9]+}}, {{w[0-9]+}}
@@ -56,7 +56,7 @@ define void @clz_zerodef_i32() {
 }
 
 define void @clz_zerodef_i64() {
-; CHECK: clz_zerodef_i64:
+; CHECK-LABEL: clz_zerodef_i64:
     %val0_tmp = load i64* @var64
     %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0)
 ; CHECK: clz	{{x[0-9]+}}, {{x[0-9]+}}
@@ -65,7 +65,7 @@ define void @clz_zerodef_i64() {
 }
 
 define void @clz_zeroundef_i32() {
-; CHECK: clz_zeroundef_i32:
+; CHECK-LABEL: clz_zeroundef_i32:
     %val0_tmp = load i32* @var32
     %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1)
 ; CHECK: clz	{{w[0-9]+}}, {{w[0-9]+}}
@@ -74,7 +74,7 @@ define void @clz_zeroundef_i32() {
 }
 
 define void @clz_zeroundef_i64() {
-; CHECK: clz_zeroundef_i64:
+; CHECK-LABEL: clz_zeroundef_i64:
     %val0_tmp = load i64* @var64
     %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1)
 ; CHECK: clz	{{x[0-9]+}}, {{x[0-9]+}}
@@ -83,7 +83,7 @@ define void @clz_zeroundef_i64() {
 }
 
 define void @cttz_zerodef_i32() {
-; CHECK: cttz_zerodef_i32:
+; CHECK-LABEL: cttz_zerodef_i32:
     %val0_tmp = load i32* @var32
     %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0)
 ; CHECK: rbit   [[REVERSED:w[0-9]+]], {{w[0-9]+}}
@@ -93,7 +93,7 @@ define void @cttz_zerodef_i32() {
 }
 
 define void @cttz_zerodef_i64() {
-; CHECK: cttz_zerodef_i64:
+; CHECK-LABEL: cttz_zerodef_i64:
     %val0_tmp = load i64* @var64
     %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0)
 ; CHECK: rbit   [[REVERSED:x[0-9]+]], {{x[0-9]+}}
@@ -103,7 +103,7 @@ define void @cttz_zerodef_i64() {
 }
 
 define void @cttz_zeroundef_i32() {
-; CHECK: cttz_zeroundef_i32:
+; CHECK-LABEL: cttz_zeroundef_i32:
     %val0_tmp = load i32* @var32
     %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1)
 ; CHECK: rbit   [[REVERSED:w[0-9]+]], {{w[0-9]+}}
@@ -113,7 +113,7 @@ define void @cttz_zeroundef_i32() {
 }
 
 define void @cttz_zeroundef_i64() {
-; CHECK: cttz_zeroundef_i64:
+; CHECK-LABEL: cttz_zeroundef_i64:
     %val0_tmp = load i64* @var64
     %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1)
 ; CHECK: rbit   [[REVERSED:x[0-9]+]], {{x[0-9]+}}
@@ -125,7 +125,7 @@ define void @cttz_zeroundef_i64() {
 ; These two are just compilation tests really: the operation's set to Expand in
 ; ISelLowering.
 define void @ctpop_i32() {
-; CHECK: ctpop_i32:
+; CHECK-LABEL: ctpop_i32:
     %val0_tmp = load i32* @var32
     %val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp)
     store volatile i32 %val4_tmp, i32* @var32
@@ -133,7 +133,7 @@ define void @ctpop_i32() {
 }
 
 define void @ctpop_i64() {
-; CHECK: ctpop_i64:
+; CHECK-LABEL: ctpop_i64:
     %val0_tmp = load i64* @var64
     %val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp)
     store volatile i64 %val4_tmp, i64* @var64
diff --git a/test/CodeGen/AArch64/dp2.ll b/test/CodeGen/AArch64/dp2.ll
index a5ebc2f..48b0701 100644
--- a/test/CodeGen/AArch64/dp2.ll
+++ b/test/CodeGen/AArch64/dp2.ll
@@ -6,7 +6,7 @@
 @var64_1 = global i64 0
 
 define void @rorv_i64() {
-; CHECK: rorv_i64:
+; CHECK-LABEL: rorv_i64:
     %val0_tmp = load i64* @var64_0
     %val1_tmp = load i64* @var64_1
     %val2_tmp = sub i64 64, %val1_tmp
@@ -19,7 +19,7 @@ define void @rorv_i64() {
 }
 
 define void @asrv_i64() {
-; CHECK: asrv_i64:
+; CHECK-LABEL: asrv_i64:
     %val0_tmp = load i64* @var64_0
     %val1_tmp = load i64* @var64_1
     %val4_tmp = ashr i64 %val0_tmp, %val1_tmp
@@ -29,7 +29,7 @@ define void @asrv_i64() {
 }
 
 define void @lsrv_i64() {
-; CHECK: lsrv_i64:
+; CHECK-LABEL: lsrv_i64:
     %val0_tmp = load i64* @var64_0
     %val1_tmp = load i64* @var64_1
     %val4_tmp = lshr i64 %val0_tmp, %val1_tmp
@@ -39,7 +39,7 @@ define void @lsrv_i64() {
 }
 
 define void @lslv_i64() {
-; CHECK: lslv_i64:
+; CHECK-LABEL: lslv_i64:
     %val0_tmp = load i64* @var64_0
     %val1_tmp = load i64* @var64_1
     %val4_tmp = shl i64 %val0_tmp, %val1_tmp
@@ -49,7 +49,7 @@ define void @lslv_i64() {
 }
 
 define void @udiv_i64() {
-; CHECK: udiv_i64:
+; CHECK-LABEL: udiv_i64:
     %val0_tmp = load i64* @var64_0
     %val1_tmp = load i64* @var64_1
     %val4_tmp = udiv i64 %val0_tmp, %val1_tmp
@@ -59,7 +59,7 @@ define void @udiv_i64() {
 }
 
 define void @sdiv_i64() {
-; CHECK: sdiv_i64:
+; CHECK-LABEL: sdiv_i64:
     %val0_tmp = load i64* @var64_0
     %val1_tmp = load i64* @var64_1
     %val4_tmp = sdiv i64 %val0_tmp, %val1_tmp
@@ -70,7 +70,7 @@ define void @sdiv_i64() {
 
 
 define void @lsrv_i32() {
-; CHECK: lsrv_i32:
+; CHECK-LABEL: lsrv_i32:
     %val0_tmp = load i32* @var32_0
     %val1_tmp = load i32* @var32_1
     %val2_tmp = add i32 1, %val1_tmp
@@ -81,7 +81,7 @@ define void @lsrv_i32() {
 }
 
 define void @lslv_i32() {
-; CHECK: lslv_i32:
+; CHECK-LABEL: lslv_i32:
     %val0_tmp = load i32* @var32_0
     %val1_tmp = load i32* @var32_1
     %val2_tmp = add i32 1, %val1_tmp
@@ -92,7 +92,7 @@ define void @lslv_i32() {
 }
 
 define void @rorv_i32() {
-; CHECK: rorv_i32:
+; CHECK-LABEL: rorv_i32:
     %val0_tmp = load i32* @var32_0
     %val6_tmp = load i32* @var32_1
     %val1_tmp = add i32 1, %val6_tmp
@@ -106,7 +106,7 @@ define void @rorv_i32() {
 }
 
 define void @asrv_i32() {
-; CHECK: asrv_i32:
+; CHECK-LABEL: asrv_i32:
     %val0_tmp = load i32* @var32_0
     %val1_tmp = load i32* @var32_1
     %val2_tmp = add i32 1, %val1_tmp
@@ -117,7 +117,7 @@ define void @asrv_i32() {
 }
 
 define void @sdiv_i32() {
-; CHECK: sdiv_i32:
+; CHECK-LABEL: sdiv_i32:
     %val0_tmp = load i32* @var32_0
     %val1_tmp = load i32* @var32_1
     %val4_tmp = sdiv i32 %val0_tmp, %val1_tmp
@@ -127,7 +127,7 @@ define void @sdiv_i32() {
 }
 
 define void @udiv_i32() {
-; CHECK: udiv_i32:
+; CHECK-LABEL: udiv_i32:
     %val0_tmp = load i32* @var32_0
     %val1_tmp = load i32* @var32_1
     %val4_tmp = udiv i32 %val0_tmp, %val1_tmp
diff --git a/test/CodeGen/AArch64/extract.ll b/test/CodeGen/AArch64/extract.ll
index 0626781..62d9ed2 100644
--- a/test/CodeGen/AArch64/extract.ll
+++ b/test/CodeGen/AArch64/extract.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 define i64 @ror_i64(i64 %in) {
-; CHECK: ror_i64:
+; CHECK-LABEL: ror_i64:
     %left = shl i64 %in, 19
     %right = lshr i64 %in, 45
     %val5 = or i64 %left, %right
@@ -10,7 +10,7 @@ define i64 @ror_i64(i64 %in) {
 }
 
 define i32 @ror_i32(i32 %in) {
-; CHECK: ror_i32:
+; CHECK-LABEL: ror_i32:
     %left = shl i32 %in, 9
     %right = lshr i32 %in, 23
     %val5 = or i32 %left, %right
@@ -19,7 +19,7 @@ define i32 @ror_i32(i32 %in) {
 }
 
 define i32 @extr_i32(i32 %lhs, i32 %rhs) {
-; CHECK: extr_i32:
+; CHECK-LABEL: extr_i32:
   %left = shl i32 %lhs, 6
   %right = lshr i32 %rhs, 26
   %val = or i32 %left, %right
@@ -31,7 +31,7 @@ define i32 @extr_i32(i32 %lhs, i32 %rhs) {
 }
 
 define i64 @extr_i64(i64 %lhs, i64 %rhs) {
-; CHECK: extr_i64:
+; CHECK-LABEL: extr_i64:
   %right = lshr i64 %rhs, 40
   %left = shl i64 %lhs, 24
   %val = or i64 %right, %left
@@ -45,7 +45,7 @@ define i64 @extr_i64(i64 %lhs, i64 %rhs) {
 ; Regression test: a bad experimental pattern crept into git which optimised
 ; this pattern to a single EXTR.
 define i32 @extr_regress(i32 %a, i32 %b) {
-; CHECK: extr_regress:
+; CHECK-LABEL: extr_regress:
 
     %sh1 = shl i32 %a, 14
     %sh2 = lshr i32 %b, 14
diff --git a/test/CodeGen/AArch64/fastcc-reserved.ll b/test/CodeGen/AArch64/fastcc-reserved.ll
index e40aa30..c6c0505 100644
--- a/test/CodeGen/AArch64/fastcc-reserved.ll
+++ b/test/CodeGen/AArch64/fastcc-reserved.ll
@@ -7,7 +7,7 @@
 declare fastcc void @will_pop([8 x i32], i32 %val)
 
 define fastcc void @foo(i32 %in) {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 
   %addr = alloca i8, i32 %in
 
@@ -34,7 +34,7 @@ define fastcc void @foo(i32 %in) {
 declare void @wont_pop([8 x i32], i32 %val)
 
 define void @foo1(i32 %in) {
-; CHECK: foo1:
+; CHECK-LABEL: foo1:
 
   %addr = alloca i8, i32 %in
 ; Normal frame setup again
diff --git a/test/CodeGen/AArch64/fastcc.ll b/test/CodeGen/AArch64/fastcc.ll
index 41cde94..a4cd378 100644
--- a/test/CodeGen/AArch64/fastcc.ll
+++ b/test/CodeGen/AArch64/fastcc.ll
@@ -5,10 +5,10 @@
 ; stack, so try to make sure this is respected.
 
 define fastcc void @func_stack0() {
-; CHECK: func_stack0:
+; CHECK-LABEL: func_stack0:
 ; CHECK: sub sp, sp, #48
 
-; CHECK-TAIL: func_stack0:
+; CHECK-TAIL-LABEL: func_stack0:
 ; CHECK-TAIL: sub sp, sp, #48
 
 
@@ -45,10 +45,10 @@ define fastcc void @func_stack0() {
 }
 
 define fastcc void @func_stack8([8 x i32], i32 %stacked) {
-; CHECK: func_stack8:
+; CHECK-LABEL: func_stack8:
 ; CHECK: sub sp, sp, #48
 
-; CHECK-TAIL: func_stack8:
+; CHECK-TAIL-LABEL: func_stack8:
 ; CHECK-TAIL: sub sp, sp, #48
 
 
@@ -84,10 +84,10 @@ define fastcc void @func_stack8([8 x i32], i32 %stacked) {
 }
 
 define fastcc void @func_stack32([8 x i32], i128 %stacked0, i128 %stacked1) {
-; CHECK: func_stack32:
+; CHECK-LABEL: func_stack32:
 ; CHECK: sub sp, sp, #48
 
-; CHECK-TAIL: func_stack32:
+; CHECK-TAIL-LABEL: func_stack32:
 ; CHECK-TAIL: sub sp, sp, #48
 
 
diff --git a/test/CodeGen/AArch64/floatdp_1source.ll b/test/CodeGen/AArch64/floatdp_1source.ll
index c94ba9b..3d7f8f0 100644
--- a/test/CodeGen/AArch64/floatdp_1source.ll
+++ b/test/CodeGen/AArch64/floatdp_1source.ll
@@ -26,7 +26,7 @@ declare float @nearbyintf(float) readonly
 declare double @nearbyint(double) readonly
 
 define void @simple_float() {
-; CHECK: simple_float:
+; CHECK-LABEL: simple_float:
   %val1 = load volatile float* @varfloat
 
   %valabs = call float @fabsf(float %val1)
@@ -65,7 +65,7 @@ define void @simple_float() {
 }
 
 define void @simple_double() {
-; CHECK: simple_double:
+; CHECK-LABEL: simple_double:
   %val1 = load volatile double* @vardouble
 
   %valabs = call double @fabs(double %val1)
@@ -104,7 +104,7 @@ define void @simple_double() {
 }
 
 define void @converts() {
-; CHECK: converts:
+; CHECK-LABEL: converts:
 
   %val16 = load volatile half* @varhalf
   %val32 = load volatile float* @varfloat
diff --git a/test/CodeGen/AArch64/fp-dp3.ll b/test/CodeGen/AArch64/fp-dp3.ll
index 09d9072..3a9a6fc 100644
--- a/test/CodeGen/AArch64/fp-dp3.ll
+++ b/test/CodeGen/AArch64/fp-dp3.ll
@@ -46,7 +46,7 @@ define float @test_fnmsub(float %a, float %b, float %c) {
 
 define double @testd_fmadd(double %a, double %b, double %c) {
 ; CHECK-LABEL: testd_fmadd:
-; CHECK-NOFAST: testd_fmadd:
+; CHECK-NOFAST-LABEL: testd_fmadd:
   %val = call double @llvm.fma.f64(double %a, double %b, double %c)
 ; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
 ; CHECK-NOFAST: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@@ -55,7 +55,7 @@ define double @testd_fmadd(double %a, double %b, double %c) {
 
 define double @testd_fmsub(double %a, double %b, double %c) {
 ; CHECK-LABEL: testd_fmsub:
-; CHECK-NOFAST: testd_fmsub:
+; CHECK-NOFAST-LABEL: testd_fmsub:
   %nega = fsub double -0.0, %a
   %val = call double @llvm.fma.f64(double %nega, double %b, double %c)
 ; CHECK: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@@ -65,7 +65,7 @@ define double @testd_fmsub(double %a, double %b, double %c) {
 
 define double @testd_fnmadd(double %a, double %b, double %c) {
 ; CHECK-LABEL: testd_fnmadd:
-; CHECK-NOFAST: testd_fnmadd:
+; CHECK-NOFAST-LABEL: testd_fnmadd:
   %negc = fsub double -0.0, %c
   %val = call double @llvm.fma.f64(double %a, double %b, double %negc)
 ; CHECK: fnmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@@ -75,7 +75,7 @@ define double @testd_fnmadd(double %a, double %b, double %c) {
 
 define double @testd_fnmsub(double %a, double %b, double %c) {
 ; CHECK-LABEL: testd_fnmsub:
-; CHECK-NOFAST: testd_fnmsub:
+; CHECK-NOFAST-LABEL: testd_fnmsub:
   %nega = fsub double -0.0, %a
   %negc = fsub double -0.0, %c
   %val = call double @llvm.fma.f64(double %nega, double %b, double %negc)
diff --git a/test/CodeGen/AArch64/fpimm.ll b/test/CodeGen/AArch64/fpimm.ll
index fd28aee..ccf7c8a 100644
--- a/test/CodeGen/AArch64/fpimm.ll
+++ b/test/CodeGen/AArch64/fpimm.ll
@@ -4,7 +4,7 @@
 @varf64 = global double 0.0
 
 define void @check_float() {
-; CHECK: check_float:
+; CHECK-LABEL: check_float:
 
   %val = load float* @varf32
   %newval1 = fadd float %val, 8.5
@@ -19,7 +19,7 @@ define void @check_float() {
 }
 
 define void @check_double() {
-; CHECK: check_double:
+; CHECK-LABEL: check_double:
 
   %val = load double* @varf64
   %newval1 = fadd double %val, 8.5
diff --git a/test/CodeGen/AArch64/func-argpassing.ll b/test/CodeGen/AArch64/func-argpassing.ll
index 7367107..15f8e76 100644
--- a/test/CodeGen/AArch64/func-argpassing.ll
+++ b/test/CodeGen/AArch64/func-argpassing.ll
@@ -11,7 +11,7 @@
 @varstruct = global %myStruct zeroinitializer
 
 define void @take_i8s(i8 %val1, i8 %val2) {
-; CHECK: take_i8s:
+; CHECK-LABEL: take_i8s:
     store i8 %val2, i8* @var8
     ; Not using w1 may be technically allowed, but it would indicate a
     ; problem in itself.
@@ -20,7 +20,7 @@ define void @take_i8s(i8 %val1, i8 %val2) {
 }
 
 define void @add_floats(float %val1, float %val2) {
-; CHECK: add_floats:
+; CHECK-LABEL: add_floats:
     %newval = fadd float %val1, %val2
 ; CHECK: fadd [[ADDRES:s[0-9]+]], s0, s1
     store float %newval, float* @varfloat
@@ -31,7 +31,7 @@ define void @add_floats(float %val1, float %val2) {
 ; byval pointers should be allocated to the stack and copied as if
 ; with memcpy.
 define void @take_struct(%myStruct* byval %structval) {
-; CHECK: take_struct:
+; CHECK-LABEL: take_struct:
     %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
     %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
 
@@ -51,7 +51,7 @@ define void @take_struct(%myStruct* byval %structval) {
 
 ; %structval should be at sp + 16
 define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) {
-; CHECK: check_byval_align:
+; CHECK-LABEL: check_byval_align:
 
     %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
     %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
@@ -72,7 +72,7 @@ define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %st
 }
 
 define i32 @return_int() {
-; CHECK: return_int:
+; CHECK-LABEL: return_int:
     %val = load i32* @var32
     ret i32 %val
 ; CHECK: ldr w0, [{{x[0-9]+}}, #:lo12:var32]
@@ -81,7 +81,7 @@ define i32 @return_int() {
 }
 
 define double @return_double() {
-; CHECK: return_double:
+; CHECK-LABEL: return_double:
     ret double 3.14
 ; CHECK: ldr d0, [{{x[0-9]+}}, #:lo12:.LCPI
 }
@@ -90,7 +90,7 @@ define double @return_double() {
 ; small enough to go into registers. Not all that pretty, but it
 ; works.
 define [2 x i64] @return_struct() {
-; CHECK: return_struct:
+; CHECK-LABEL: return_struct:
     %addr = bitcast %myStruct* @varstruct to [2 x i64]*
     %val = load [2 x i64]* %addr
     ret [2 x i64] %val
@@ -107,7 +107,7 @@ define [2 x i64] @return_struct() {
 ; structs larger than 16 bytes, but C semantics can still be provided
 ; if LLVM does it to %myStruct too. So this is the simplest check
 define void @return_large_struct(%myStruct* sret %retval) {
-; CHECK: return_large_struct:
+; CHECK-LABEL: return_large_struct:
     %addr0 = getelementptr %myStruct* %retval, i64 0, i32 0
     %addr1 = getelementptr %myStruct* %retval, i64 0, i32 1
     %addr2 = getelementptr %myStruct* %retval, i64 0, i32 2
@@ -128,7 +128,7 @@ define void @return_large_struct(%myStruct* sret %retval) {
 define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45,
                           i32* %var6, %myStruct* byval %struct, i32* byval %stacked,
                           double %notstacked) {
-; CHECK: struct_on_stack:
+; CHECK-LABEL: struct_on_stack:
     %addr = getelementptr %myStruct* %struct, i64 0, i32 0
     %val64 = load i64* %addr
     store i64 %val64, i64* @var64
@@ -148,7 +148,7 @@ define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var
 define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
                          float %var4, float %var5, float %var6, float %var7,
                          float %var8) {
-; CHECK: stacked_fpu:
+; CHECK-LABEL: stacked_fpu:
     store float %var8, float* @varfloat
     ; Beware as above: the offset would be different on big-endian
     ; machines if the first ldr were changed to use s-registers.
diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll
index 13b689c..b12130b 100644
--- a/test/CodeGen/AArch64/func-calls.ll
+++ b/test/CodeGen/AArch64/func-calls.ll
@@ -17,7 +17,7 @@ declare void @take_i8s(i8 %val1, i8 %val2)
 declare void @take_floats(float %val1, float %val2)
 
 define void @simple_args() {
-; CHECK: simple_args:
+; CHECK-LABEL: simple_args:
   %char1 = load i8* @var8
   %char2 = load i8* @var8_2
   call void @take_i8s(i8 %char1, i8 %char2)
@@ -41,7 +41,7 @@ declare [2 x i64] @return_smallstruct()
 declare void @return_large_struct(%myStruct* sret %retval)
 
 define void @simple_rets() {
-; CHECK: simple_rets:
+; CHECK-LABEL: simple_rets:
 
   %int = call i32 @return_int()
   store i32 %int, i32* @var32
@@ -106,7 +106,7 @@ declare void @check_i128_regalign(i32 %val0, i128 %val1)
 
 
 define void @check_i128_align() {
-; CHECK: check_i128_align:
+; CHECK-LABEL: check_i128_align:
   %val = load i128* @var128
   call void @check_i128_stackalign(i32 0, i32 1, i32 2, i32 3,
                                    i32 4, i32 5, i32 6, i32 7,
@@ -130,7 +130,7 @@ define void @check_i128_align() {
 @fptr = global void()* null
 
 define void @check_indirect_call() {
-; CHECK: check_indirect_call:
+; CHECK-LABEL: check_indirect_call:
   %func = load void()** @fptr
   call void %func()
 ; CHECK: ldr [[FPTR:x[0-9]+]], [{{x[0-9]+}}, #:lo12:fptr]
diff --git a/test/CodeGen/AArch64/got-abuse.ll b/test/CodeGen/AArch64/got-abuse.ll
index c474e58..8b06031 100644
--- a/test/CodeGen/AArch64/got-abuse.ll
+++ b/test/CodeGen/AArch64/got-abuse.ll
@@ -13,7 +13,7 @@ declare void @consume(i32)
 declare void @func()
 
 define void @foo() nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 entry:
   call void @consume(i32 ptrtoint (void ()* @func to i32))
 ; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:func
diff --git a/test/CodeGen/AArch64/i128-align.ll b/test/CodeGen/AArch64/i128-align.ll
index 8eeaa2f..21ca7ed 100644
--- a/test/CodeGen/AArch64/i128-align.ll
+++ b/test/CodeGen/AArch64/i128-align.ll
@@ -5,7 +5,7 @@
 @var = global %struct zeroinitializer
 
 define i64 @check_size() {
-; CHECK: check_size:
+; CHECK-LABEL: check_size:
   %starti = ptrtoint %struct* @var to i64
 
   %endp = getelementptr %struct* @var, i64 1
@@ -17,7 +17,7 @@ define i64 @check_size() {
 }
 
 define i64 @check_field() {
-; CHECK: check_field:
+; CHECK-LABEL: check_field:
   %starti = ptrtoint %struct* @var to i64
 
   %endp = getelementptr %struct* @var, i64 0, i32 1
diff --git a/test/CodeGen/AArch64/ldst-regoffset.ll b/test/CodeGen/AArch64/ldst-regoffset.ll
index 4593512..c83fb52 100644
--- a/test/CodeGen/AArch64/ldst-regoffset.ll
+++ b/test/CodeGen/AArch64/ldst-regoffset.ll
@@ -9,7 +9,7 @@
 @var_double = global double 0.0
 
 define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_8bit:
+; CHECK-LABEL: ldst_8bit:
 
    %addr8_sxtw = getelementptr i8* %base, i32 %off32
    %val8_sxtw = load volatile i8* %addr8_sxtw
@@ -37,7 +37,7 @@ define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) {
 
 
 define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_16bit:
+; CHECK-LABEL: ldst_16bit:
 
    %addr8_sxtwN = getelementptr i16* %base, i32 %off32
    %val8_sxtwN = load volatile i16* %addr8_sxtwN
@@ -91,7 +91,7 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) {
 }
 
 define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_32bit:
+; CHECK-LABEL: ldst_32bit:
 
    %addr_sxtwN = getelementptr i32* %base, i32 %off32
    %val_sxtwN = load volatile i32* %addr_sxtwN
@@ -143,7 +143,7 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) {
 }
 
 define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_64bit:
+; CHECK-LABEL: ldst_64bit:
 
    %addr_sxtwN = getelementptr i64* %base, i32 %off32
    %val_sxtwN = load volatile i64* %addr_sxtwN
@@ -191,7 +191,7 @@ define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) {
 }
 
 define void @ldst_float(float* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_float:
+; CHECK-LABEL: ldst_float:
 
    %addr_sxtwN = getelementptr float* %base, i32 %off32
    %val_sxtwN = load volatile float* %addr_sxtwN
@@ -238,7 +238,7 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) {
 }
 
 define void @ldst_double(double* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_double:
+; CHECK-LABEL: ldst_double:
 
    %addr_sxtwN = getelementptr double* %base, i32 %off32
    %val_sxtwN = load volatile double* %addr_sxtwN
@@ -286,7 +286,7 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) {
 
 
 define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_128bit:
+; CHECK-LABEL: ldst_128bit:
 
    %addr_sxtwN = getelementptr fp128* %base, i32 %off32
    %val_sxtwN = load volatile fp128* %addr_sxtwN
diff --git a/test/CodeGen/AArch64/ldst-unscaledimm.ll b/test/CodeGen/AArch64/ldst-unscaledimm.ll
index 78a3c83..03dedcc 100644
--- a/test/CodeGen/AArch64/ldst-unscaledimm.ll
+++ b/test/CodeGen/AArch64/ldst-unscaledimm.ll
@@ -11,7 +11,7 @@
 @varptr = global i8* null
 
 define void @ldst_8bit() {
-; CHECK: ldst_8bit:
+; CHECK-LABEL: ldst_8bit:
 
 ; No architectural support for loads to 16-bit or 8-bit since we
 ; promote i8 during lowering.
@@ -72,7 +72,7 @@ define void @ldst_8bit() {
 }
 
 define void @ldst_16bit() {
-; CHECK: ldst_16bit:
+; CHECK-LABEL: ldst_16bit:
 
 ; No architectural support for loads to 16-bit or 16-bit since we
 ; promote i16 during lowering.
@@ -140,7 +140,7 @@ define void @ldst_16bit() {
 }
 
 define void @ldst_32bit() {
-; CHECK: ldst_32bit:
+; CHECK-LABEL: ldst_32bit:
 
   %addr_8bit = load i8** @varptr
 
@@ -186,7 +186,7 @@ define void @ldst_32bit() {
 }
 
 define void @ldst_float() {
-; CHECK: ldst_float:
+; CHECK-LABEL: ldst_float:
 
   %addr_8bit = load i8** @varptr
   %addrfp_8 = getelementptr i8* %addr_8bit, i64 -5
@@ -202,7 +202,7 @@ define void @ldst_float() {
 }
 
 define void @ldst_double() {
-; CHECK: ldst_double:
+; CHECK-LABEL: ldst_double:
 
   %addr_8bit = load i8** @varptr
   %addrfp_8 = getelementptr i8* %addr_8bit, i64 4
diff --git a/test/CodeGen/AArch64/ldst-unsignedimm.ll b/test/CodeGen/AArch64/ldst-unsignedimm.ll
index 1e7540d..77cef4e 100644
--- a/test/CodeGen/AArch64/ldst-unsignedimm.ll
+++ b/test/CodeGen/AArch64/ldst-unsignedimm.ll
@@ -9,7 +9,7 @@
 @var_double = global double 0.0
 
 define void @ldst_8bit() {
-; CHECK: ldst_8bit:
+; CHECK-LABEL: ldst_8bit:
 
 ; No architectural support for loads to 16-bit or 8-bit since we
 ; promote i8 during lowering.
@@ -63,7 +63,7 @@ define void @ldst_8bit() {
 }
 
 define void @ldst_16bit() {
-; CHECK: ldst_16bit:
+; CHECK-LABEL: ldst_16bit:
 
 ; No architectural support for load volatiles to 16-bit promote i16 during
 ; lowering.
@@ -117,7 +117,7 @@ define void @ldst_16bit() {
 }
 
 define void @ldst_32bit() {
-; CHECK: ldst_32bit:
+; CHECK-LABEL: ldst_32bit:
 
 ; Straight 32-bit load/store
   %val32_noext = load volatile i32* @var_32bit
@@ -225,7 +225,7 @@ define void @ldst_complex_offsets() {
 }
 
 define void @ldst_float() {
-; CHECK: ldst_float:
+; CHECK-LABEL: ldst_float:
 
    %valfp = load volatile float* @var_float
 ; CHECK: adrp {{x[0-9]+}}, var_float
@@ -238,7 +238,7 @@ define void @ldst_float() {
 }
 
 define void @ldst_double() {
-; CHECK: ldst_double:
+; CHECK-LABEL: ldst_double:
 
    %valfp = load volatile double* @var_double
 ; CHECK: adrp {{x[0-9]+}}, var_double
diff --git a/test/CodeGen/AArch64/literal_pools.ll b/test/CodeGen/AArch64/literal_pools.ll
index 9cfa8c5..b82f290 100644
--- a/test/CodeGen/AArch64/literal_pools.ll
+++ b/test/CodeGen/AArch64/literal_pools.ll
@@ -5,7 +5,7 @@
 @var64 = global i64 0
 
 define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
     %val32 = load i32* @var32
     %val64 = load i64* @var64
 
@@ -60,7 +60,7 @@ define void @foo() {
 @vardouble = global double 0.0
 
 define void @floating_lits() {
-; CHECK: floating_lits:
+; CHECK-LABEL: floating_lits:
 
   %floatval = load float* @varfloat
   %newfloat = fadd float %floatval, 128.0
diff --git a/test/CodeGen/AArch64/local_vars.ll b/test/CodeGen/AArch64/local_vars.ll
index 5cbf5a3..b5cef85 100644
--- a/test/CodeGen/AArch64/local_vars.ll
+++ b/test/CodeGen/AArch64/local_vars.ll
@@ -24,7 +24,7 @@ define void @trivial_func() nounwind {
 }
 
 define void @trivial_fp_func() {
-; CHECK-WITHFP: trivial_fp_func:
+; CHECK-WITHFP-LABEL: trivial_fp_func:
 
 ; CHECK-WITHFP: sub sp, sp, #16
 ; CHECK-WITHFP: stp x29, x30, [sp]
@@ -43,7 +43,7 @@ define void @trivial_fp_func() {
 
 define void @stack_local() {
   %local_var = alloca i64
-; CHECK: stack_local:
+; CHECK-LABEL: stack_local:
 ; CHECK: sub sp, sp, #16
 
   %val = load i64* @var
diff --git a/test/CodeGen/AArch64/logical_shifted_reg.ll b/test/CodeGen/AArch64/logical_shifted_reg.ll
index bbbfcc1..a08ba20 100644
--- a/test/CodeGen/AArch64/logical_shifted_reg.ll
+++ b/test/CodeGen/AArch64/logical_shifted_reg.ll
@@ -7,7 +7,7 @@
 @var2_64 = global i64 0
 
 define void @logical_32bit() {
-; CHECK: logical_32bit:
+; CHECK-LABEL: logical_32bit:
   %val1 = load i32* @var1_32
   %val2 = load i32* @var2_32
 
@@ -97,7 +97,7 @@ define void @logical_32bit() {
 }
 
 define void @logical_64bit() {
-; CHECK: logical_64bit:
+; CHECK-LABEL: logical_64bit:
   %val1 = load i64* @var1_64
   %val2 = load i64* @var2_64
 
@@ -190,7 +190,7 @@ define void @logical_64bit() {
 }
 
 define void @flag_setting() {
-; CHECK: flag_setting:
+; CHECK-LABEL: flag_setting:
   %val1 = load i64* @var1_64
   %val2 = load i64* @var2_64
 
diff --git a/test/CodeGen/AArch64/regress-tail-livereg.ll b/test/CodeGen/AArch64/regress-tail-livereg.ll
index 3216775..053249c 100644
--- a/test/CodeGen/AArch64/regress-tail-livereg.ll
+++ b/test/CodeGen/AArch64/regress-tail-livereg.ll
@@ -4,7 +4,7 @@
 declare void @bar()
 
 define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
        %func = load void()** @var
 
        ; Calling a function encourages @foo to use a callee-saved register,
diff --git a/test/CodeGen/AArch64/sibling-call.ll b/test/CodeGen/AArch64/sibling-call.ll
index 6df4e7e..20f1062 100644
--- a/test/CodeGen/AArch64/sibling-call.ll
+++ b/test/CodeGen/AArch64/sibling-call.ll
@@ -5,7 +5,7 @@ declare void @callee_stack8([8 x i32], i64)
 declare void @callee_stack16([8 x i32], i64, i64)
 
 define void @caller_to0_from0() nounwind {
-; CHECK: caller_to0_from0:
+; CHECK-LABEL: caller_to0_from0:
 ; CHECK-NEXT: // BB
   tail call void @callee_stack0()
   ret void
@@ -13,7 +13,7 @@ define void @caller_to0_from0() nounwind {
 }
 
 define void @caller_to0_from8([8 x i32], i64) nounwind{
-; CHECK: caller_to0_from8:
+; CHECK-LABEL: caller_to0_from8:
 ; CHECK-NEXT: // BB
 
   tail call void @callee_stack0()
@@ -22,7 +22,7 @@ define void @caller_to0_from8([8 x i32], i64) nounwind{
 }
 
 define void @caller_to8_from0() {
-; CHECK: caller_to8_from0:
+; CHECK-LABEL: caller_to8_from0:
 
 ; Caller isn't going to clean up any extra stack we allocate, so it
 ; can't be a tail call.
@@ -32,7 +32,7 @@ define void @caller_to8_from0() {
 }
 
 define void @caller_to8_from8([8 x i32], i64 %a) {
-; CHECK: caller_to8_from8:
+; CHECK-LABEL: caller_to8_from8:
 ; CHECK-NOT: sub sp, sp,
 
 ; This should reuse our stack area for the 42
@@ -43,7 +43,7 @@ define void @caller_to8_from8([8 x i32], i64 %a) {
 }
 
 define void @caller_to16_from8([8 x i32], i64 %a) {
-; CHECK: caller_to16_from8:
+; CHECK-LABEL: caller_to16_from8:
 
 ; Shouldn't be a tail call: we can't use SP+8 because our caller might
 ; have something there. This may sound obvious but implementation does
@@ -54,7 +54,7 @@ define void @caller_to16_from8([8 x i32], i64 %a) {
 }
 
 define void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
-; CHECK: caller_to8_from24:
+; CHECK-LABEL: caller_to8_from24:
 ; CHECK-NOT: sub sp, sp
 
 ; Reuse our area, putting "42" at incoming sp
@@ -65,7 +65,7 @@ define void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
 }
 
 define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
-; CHECK: caller_to16_from16:
+; CHECK-LABEL: caller_to16_from16:
 ; CHECK-NOT: sub sp, sp,
 
 ; Here we want to make sure that both loads happen before the stores:
@@ -85,7 +85,7 @@ define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
 @func = global void(i32)* null
 
 define void @indirect_tail() {
-; CHECK: indirect_tail:
+; CHECK-LABEL: indirect_tail:
 ; CHECK-NOT: sub sp, sp
 
   %fptr = load void(i32)** @func
diff --git a/test/CodeGen/AArch64/tail-call.ll b/test/CodeGen/AArch64/tail-call.ll
index f323b15..81885f1 100644
--- a/test/CodeGen/AArch64/tail-call.ll
+++ b/test/CodeGen/AArch64/tail-call.ll
@@ -5,7 +5,7 @@ declare fastcc void @callee_stack8([8 x i32], i64)
 declare fastcc void @callee_stack16([8 x i32], i64, i64)
 
 define fastcc void @caller_to0_from0() nounwind {
-; CHECK: caller_to0_from0:
+; CHECK-LABEL: caller_to0_from0:
 ; CHECK-NEXT: // BB
   tail call fastcc void @callee_stack0()
   ret void
@@ -13,7 +13,7 @@ define fastcc void @caller_to0_from0() nounwind {
 }
 
 define fastcc void @caller_to0_from8([8 x i32], i64) {
-; CHECK: caller_to0_from8:
+; CHECK-LABEL: caller_to0_from8:
 
   tail call fastcc void @callee_stack0()
   ret void
@@ -22,7 +22,7 @@ define fastcc void @caller_to0_from8([8 x i32], i64) {
 }
 
 define fastcc void @caller_to8_from0() {
-; CHECK: caller_to8_from0:
+; CHECK-LABEL: caller_to8_from0:
 ; CHECK: sub sp, sp, #32
 
 ; Key point is that the "42" should go #16 below incoming stack
@@ -35,7 +35,7 @@ define fastcc void @caller_to8_from0() {
 }
 
 define fastcc void @caller_to8_from8([8 x i32], i64 %a) {
-; CHECK: caller_to8_from8:
+; CHECK-LABEL: caller_to8_from8:
 ; CHECK: sub sp, sp, #16
 
 ; Key point is that the "%a" should go where at SP on entry.
@@ -47,7 +47,7 @@ define fastcc void @caller_to8_from8([8 x i32], i64 %a) {
 }
 
 define fastcc void @caller_to16_from8([8 x i32], i64 %a) {
-; CHECK: caller_to16_from8:
+; CHECK-LABEL: caller_to16_from8:
 ; CHECK: sub sp, sp, #16
 
 ; Important point is that the call reuses the "dead" argument space
@@ -63,7 +63,7 @@ define fastcc void @caller_to16_from8([8 x i32], i64 %a) {
 
 
 define fastcc void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
-; CHECK: caller_to8_from24:
+; CHECK-LABEL: caller_to8_from24:
 ; CHECK: sub sp, sp, #16
 
 ; Key point is that the "%a" should go where at #16 above SP on entry.
@@ -76,7 +76,7 @@ define fastcc void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
 
 
 define fastcc void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
-; CHECK: caller_to16_from16:
+; CHECK-LABEL: caller_to16_from16:
 ; CHECK: sub sp, sp, #16
 
 ; Here we want to make sure that both loads happen before the stores:
diff --git a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
index 0bfe331..e7c0129 100644
--- a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
+++ b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
@@ -4,7 +4,7 @@
 @dequant_coef = external global [6 x [4 x [4 x i32]]]		; <[6 x [4 x [4 x i32]]]*> [#uses=1]
 @A = external global [4 x [4 x i32]]		; <[4 x [4 x i32]]*> [#uses=1]
 
-; CHECK: dct_luma_sp:
+; CHECK-LABEL: dct_luma_sp:
 define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) {
 entry:
 ; Make sure to use base-updating stores for saving callee-saved registers.
diff --git a/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll b/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
index e1e60e6..ee99c70 100644
--- a/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
+++ b/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 ; pr4843
 define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind {
-;CHECK: v2regbug:
+;CHECK-LABEL: v2regbug:
 ;CHECK: vzip.16
 	%tmp1 = load <4 x i16>* %B
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1>
diff --git a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
index 0fe3b39..e2ff164 100644
--- a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
+++ b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
@@ -4,7 +4,7 @@
 %0 = type { double, double }
 
 define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: bl __aeabi_dadd
 ; CHECK-NOT: strd
 ; CHECK: mov
diff --git a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
index a8afc20..4fb2be0 100644
--- a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
+++ b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
@@ -12,7 +12,7 @@ entry:
   %3 = fmul float %0, %1                          ; <float> [#uses=1]
   %4 = fadd float 0.000000e+00, %3                ; <float> [#uses=1]
   %5 = fsub float 1.000000e+00, %4                ; <float> [#uses=1]
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: vmov.f32 s{{[0-9]+}}, #1.000000e+00
   %6 = fsub float 1.000000e+00, undef             ; <float> [#uses=2]
   %7 = fsub float %2, undef                       ; <float> [#uses=1]
diff --git a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
index 0ae7f84..35995b7 100644
--- a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
+++ b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
@@ -6,10 +6,10 @@
 
 define zeroext i8 @t(%struct.foo* %this) noreturn optsize {
 entry:
-; ARM:       t:
+; ARM-LABEL:       t:
 ; ARM:       str r2, [r1], r0
 
-; THUMB:     t:
+; THUMB-LABEL:     t:
 ; THUMB-NOT: str r0, [r1], r0
 ; THUMB:     str r1, [r0]
   %0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1]
diff --git a/test/CodeGen/ARM/2010-11-29-PrologueBug.ll b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
index da4d157..4179d8c 100644
--- a/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
+++ b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
@@ -4,7 +4,7 @@
 
 define i32* @t(i32* %x) nounwind {
 entry:
-; ARM: t:
+; ARM-LABEL: t:
 ; ARM: push
 ; ARM: mov r7, sp
 ; ARM: bl _foo
@@ -12,7 +12,7 @@ entry:
 ; ARM: bl _foo
 ; ARM: pop {r7, pc}
 
-; THUMB2: t:
+; THUMB2-LABEL: t:
 ; THUMB2: push
 ; THUMB2: mov r7, sp
 ; THUMB2: blx _foo
diff --git a/test/CodeGen/ARM/2010-12-07-PEIBug.ll b/test/CodeGen/ARM/2010-12-07-PEIBug.ll
index 4879f4e..eef6abd 100644
--- a/test/CodeGen/ARM/2010-12-07-PEIBug.ll
+++ b/test/CodeGen/ARM/2010-12-07-PEIBug.ll
@@ -3,7 +3,7 @@
 
 define hidden void @foo() nounwind ssp {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: mov r7, sp
 ; CHECK-NEXT: vpush {d8}
 ; CHECK-NEXT: vpush {d10, d11}
diff --git a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
index e84ce0e..f689d49 100644
--- a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
+++ b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
@@ -9,7 +9,7 @@
 @oStruct = external global %struct.Outer, align 4
 
 define void @main() nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK-NOT: ldrd
 ; CHECK: mul
 for.body.lr.ph:
diff --git a/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll b/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
index 0fe88bd..caa0be5 100644
--- a/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
+++ b/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
@@ -8,7 +8,7 @@
 ; rdar://9172742
 
 define i32 @t() nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 entry:
   br label %bb2
 
diff --git a/test/CodeGen/ARM/2011-04-07-schediv.ll b/test/CodeGen/ARM/2011-04-07-schediv.ll
index 19f756f..f3dd3dd 100644
--- a/test/CodeGen/ARM/2011-04-07-schediv.ll
+++ b/test/CodeGen/ARM/2011-04-07-schediv.ll
@@ -12,7 +12,7 @@ entry:
 
 ; Make sure the scheduler schedules all uses of the preincrement
 ; induction variable before defining the postincrement value.
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: %bb
 ; CHECK-NOT: mov
 bb:                                               ; preds = %entry, %bb
diff --git a/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
index 568718c..348ec9f 100644
--- a/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
+++ b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
@@ -4,7 +4,7 @@
 ; rdar://9266679
 
 define zeroext i1 @t(i32* nocapture %A, i32 %size, i32 %value) nounwind readonly ssp {
-; CHECK: t:
+; CHECK-LABEL: t:
 entry:
   br label %for.cond
 
diff --git a/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll b/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
index 5409f8c..bc496b9 100644
--- a/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
+++ b/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
@@ -10,7 +10,7 @@
 @infoBlock = external global %struct.InformationBlock
 
 define hidden void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: ldr.w
 ; CHECK: ldr.w
 ; CHECK-NOT: ldm
diff --git a/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll b/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll
index 0ff4f51..e795ec5 100644
--- a/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll
+++ b/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll
@@ -23,7 +23,7 @@
 ;
 ; rdar://11116189
 define i64 @t(i64 %aInput) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movs [[REG:(r[0-9]+)]], #0
 ; CHECK: movt [[REG]], #46540
 ; CHECK: adds r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
diff --git a/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll b/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
index 2f55204..647ebd6 100644
--- a/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
+++ b/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
@@ -13,7 +13,7 @@
 ; v4i8
 ;
 define void @sextload_v4i8_c(<4 x i8>* %v) nounwind {
-;CHECK: sextload_v4i8_c:
+;CHECK-LABEL: sextload_v4i8_c:
 entry:
   %0 = load <4 x i8>* %v, align 8
   %v0  = sext <4 x i8> %0 to <4 x i32>
@@ -26,7 +26,7 @@ entry:
 ; v2i8
 ;
 define void @sextload_v2i8_c(<2 x i8>* %v) nounwind {
-;CHECK: sextload_v2i8_c:
+;CHECK-LABEL: sextload_v2i8_c:
 entry:
   %0   = load <2 x i8>* %v, align 8
   %v0  = sext <2 x i8>  %0 to <2 x i64>
@@ -39,7 +39,7 @@ entry:
 ; v2i16
 ;
 define void @sextload_v2i16_c(<2 x i16>* %v) nounwind {
-;CHECK: sextload_v2i16_c:
+;CHECK-LABEL: sextload_v2i16_c:
 entry:
   %0   = load <2 x i16>* %v, align 8
   %v0  = sext <2 x i16>  %0 to <2 x i64>
@@ -54,7 +54,7 @@ entry:
 ; v4i8
 ;
 define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind {
-;CHECK: sextload_v4i8_v:
+;CHECK-LABEL: sextload_v4i8_v:
 entry:
   %0 = load <4 x i8>* %v, align 8
   %v0  = sext <4 x i8> %0 to <4 x i32>
@@ -70,7 +70,7 @@ entry:
 ; v2i8
 ;
 define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind {
-;CHECK: sextload_v2i8_v:
+;CHECK-LABEL: sextload_v2i8_v:
 entry:
   %0 = load <2 x i8>* %v, align 8
   %v0  = sext <2 x i8> %0 to <2 x i64>
@@ -86,7 +86,7 @@ entry:
 ; v2i16
 ;
 define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind {
-;CHECK: sextload_v2i16_v:
+;CHECK-LABEL: sextload_v2i16_v:
 entry:
   %0 = load <2 x i16>* %v, align 8
   %v0  = sext <2 x i16> %0 to <2 x i64>
@@ -104,7 +104,7 @@ entry:
 ; v4i8 x v4i16
 ;
 define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind {
-;CHECK: sextload_v4i8_vs:
+;CHECK-LABEL: sextload_v4i8_vs:
 entry:
   %0 = load <4 x i8>* %v, align 8
   %v0  = sext <4 x i8> %0 to <4 x i32>
@@ -120,7 +120,7 @@ entry:
 ; v2i8
 ; v2i8 x v2i16
 define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind {
-;CHECK: sextload_v2i8_vs:
+;CHECK-LABEL: sextload_v2i8_vs:
 entry:
   %0 = load <2 x i8>* %v, align 8
   %v0  = sext <2 x i8> %0 to <2 x i64>
@@ -136,7 +136,7 @@ entry:
 ; v2i16
 ; v2i16 x v2i32
 define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind {
-;CHECK: sextload_v2i16_vs:
+;CHECK-LABEL: sextload_v2i16_vs:
 entry:
   %0 = load <2 x i16>* %v, align 8
   %v0  = sext <2 x i16> %0 to <2 x i64>
diff --git a/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll b/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll
index e761ffe..3bdbb3c 100644
--- a/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll
+++ b/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll
@@ -4,7 +4,7 @@
 ; rdar://12300648
 
 define i32 @t(i32 %x) {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK-NOT: movw
   %tmp = add i32 %x, -65535
   ret i32 %tmp
diff --git a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
index 645e68b..b8bea1f 100644
--- a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
+++ b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
@@ -23,7 +23,7 @@ entry:
   ret void
 }
 
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
 ; CHECK: movt [[BASE]], :upper16:static_val
 ; ldm is not formed when the coalescer failed to coalesce everything.
@@ -53,7 +53,7 @@ entry:
   ret void
 }
 
-; CHECK: main_fixed_arg:
+; CHECK-LABEL: main_fixed_arg:
 ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
 ; CHECK: movt [[BASE]], :upper16:static_val
 ; ldm is not formed when the coalescer failed to coalesce everything.
diff --git a/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll b/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll
index f239510..a59533c 100644
--- a/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll
+++ b/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll
@@ -6,7 +6,7 @@
 
 declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval %val);
 
-; CHECK: main:
+; CHECK-LABEL: main:
 define i32 @main() nounwind {
 entry:
 ; CHECK: ldrb	{{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1
diff --git a/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll b/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
index fcc6a7f..0028eec 100644
--- a/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
+++ b/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
@@ -5,7 +5,7 @@
 
 declare void @f(%struct.s* %p);
 
-; CHECK: t:
+; CHECK-LABEL: t:
 define void @t(i32 %a, %struct.s* byval %s) nounwind {
 entry:
 
@@ -20,7 +20,7 @@ entry:
   ret void
 }
 
-; CHECK: caller:
+; CHECK-LABEL: caller:
 define void @caller() {
 
 ; CHECK:      ldm     r0, {r1, r2, r3}
diff --git a/test/CodeGen/ARM/2013-01-21-PR14992.ll b/test/CodeGen/ARM/2013-01-21-PR14992.ll
index 05abded..014686f 100644
--- a/test/CodeGen/ARM/2013-01-21-PR14992.ll
+++ b/test/CodeGen/ARM/2013-01-21-PR14992.ll
@@ -2,8 +2,8 @@
 ;RUN: llc -mtriple=thumbv7 < %s  | FileCheck -check-prefix=EXPECTED %s
 ;RUN: llc -mtriple=thumbv7 < %s  | FileCheck %s
 
-;EXPECTED: foo:
-;CHECK: foo:
+;EXPECTED-LABEL: foo:
+;CHECK-LABEL: foo:
 define i32 @foo(i32* %a) nounwind optsize {
 entry:
   %0 = load i32* %a, align 4
diff --git a/test/CodeGen/ARM/2013-02-27-expand-vfma.ll b/test/CodeGen/ARM/2013-02-27-expand-vfma.ll
index 0e3bf23..135b144 100644
--- a/test/CodeGen/ARM/2013-02-27-expand-vfma.ll
+++ b/test/CodeGen/ARM/2013-02-27-expand-vfma.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -mtriple=armv7s-apple-darwin | FileCheck %s -check-prefix=VFP4
 
 define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind {
-; CHECK: muladd:
+; CHECK-LABEL: muladd:
 ; CHECK: fmaf
 ; CHECK: fmaf
 ; CHECK: fmaf
@@ -17,7 +17,7 @@ define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounw
 declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
 
 define <2 x float> @muladd2(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind {
-; CHECK: muladd2:
+; CHECK-LABEL: muladd2:
 ; CHECK: fmaf
 ; CHECK: fmaf
 ; CHECK-NOT: fmaf
diff --git a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
index 80b9d28..127429b 100644
--- a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
+++ b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
@@ -1,7 +1,7 @@
 ;PR15293: ARM codegen ice - expected larger existing stack allocation
 ;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
 
-;CHECK: foo:
+;CHECK-LABEL: foo:
 ;CHECK: 	sub	sp, sp, #8
 ;CHECK: 	push	{r11, lr}
 ;CHECK: 	str	r0, [sp, #8]
@@ -11,7 +11,7 @@
 ;CHECK: 	add	sp, sp, #8
 ;CHECK: 	mov	pc, lr
 
-;CHECK: foo2:
+;CHECK-LABEL: foo2:
 ;CHECK: 	sub	sp, sp, #8
 ;CHECK: 	push	{r11, lr}
 ;CHECK: 	str	r0, [sp, #8]
@@ -24,7 +24,7 @@
 ;CHECK: 	add	sp, sp, #8
 ;CHECK: 	mov	pc, lr
 
-;CHECK: doFoo:
+;CHECK-LABEL: doFoo:
 ;CHECK: 	push	{r11, lr}
 ;CHECK: 	ldr	r0,
 ;CHECK: 	ldr	r0, [r0]
@@ -33,7 +33,7 @@
 ;CHECK: 	mov	pc, lr
 
 
-;CHECK: doFoo2:
+;CHECK-LABEL: doFoo2:
 ;CHECK: 	push	{r11, lr}
 ;CHECK: 	ldr	r0,
 ;CHECK: 	mov	r1, #0
diff --git a/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll b/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll
index 38d515f..08bf99b 100644
--- a/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll
+++ b/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll
@@ -53,11 +53,11 @@
 
 ;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s
 ;
-;CHECK:     foo:
+;CHECK-LABEL:     foo:
 ;CHECK-NOT:     mov r0
 ;CHECK-NOT:     ldr r0
 ;CHECK:         bl fooUseI32
-;CHECK:     doFoo:
+;CHECK-LABEL:     doFoo:
 ;CHECK:         movs    r0, #43
 ;CHECK:         bl      foo
 
diff --git a/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll b/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
index de5fd31..0e0537e 100644
--- a/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
+++ b/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
@@ -9,7 +9,7 @@
 
 @.str = private unnamed_addr constant [13 x i8] c"%d %d %f %i\0A\00", align 1
 
-;CHECK: printfn:
+;CHECK-LABEL: printfn:
 define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) {
 entry:
   %conv = sext i16 %b to i32
diff --git a/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll b/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
index abc6e0d..3f054c6 100644
--- a/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
+++ b/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
@@ -2,7 +2,7 @@
 ; rdar://13782395
 
 define i32 @t1(i32 %a, i32 %b, i8** %retaddr) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: Block address taken
 ; CHECK-NOT: Address of block that was removed by CodeGen
   store i8* blockaddress(@t1, %cond_true), i8** %retaddr
@@ -19,7 +19,7 @@ cond_false:
 }
 
 define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, i8** %retaddr) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: Block address taken
 ; CHECK: %cond_true
 ; CHECK: add
@@ -41,7 +41,7 @@ UnifiedReturnBlock:
 }
 
 define hidden fastcc void @t3(i8** %retaddr) {
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: Block address taken
 ; CHECK-NOT: Address of block that was removed by CodeGen
 bb:
diff --git a/test/CodeGen/ARM/a15-SD-dep.ll b/test/CodeGen/ARM/a15-SD-dep.ll
index a52468e..df921e0 100644
--- a/test/CodeGen/ARM/a15-SD-dep.ll
+++ b/test/CodeGen/ARM/a15-SD-dep.ll
@@ -1,8 +1,8 @@
 ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -disable-a15-sd-optimization -verify-machineinstrs < %s  | FileCheck -check-prefix=DISABLED %s
 ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck -check-prefix=ENABLED %s
 
-; CHECK-ENABLED: t1:
-; CHECK-DISABLED: t1:
+; CHECK-ENABLED-LABEL: t1:
+; CHECK-DISABLED-LABEL: t1:
 define <2 x float> @t1(float %f) {
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
   ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
@@ -11,8 +11,8 @@ define <2 x float> @t1(float %f) {
   ret <2 x float> %i2
 }
 
-; CHECK-ENABLED: t2:
-; CHECK-DISABLED: t2:
+; CHECK-ENABLED-LABEL: t2:
+; CHECK-DISABLED-LABEL: t2:
 define <4 x float> @t2(float %g, float %f) {
   ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d0[0]
   ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
@@ -21,8 +21,8 @@ define <4 x float> @t2(float %g, float %f) {
   ret <4 x float> %i2
 }
 
-; CHECK-ENABLED: t3:
-; CHECK-DISABLED: t3:
+; CHECK-ENABLED-LABEL: t3:
+; CHECK-DISABLED-LABEL: t3:
 define arm_aapcs_vfpcc <2 x float> @t3(float %f) {
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] 
   ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
@@ -31,8 +31,8 @@ define arm_aapcs_vfpcc <2 x float> @t3(float %f) {
   ret <2 x float> %i2
 }
 
-; CHECK-ENABLED: t4:
-; CHECK-DISABLED: t4:
+; CHECK-ENABLED-LABEL: t4:
+; CHECK-DISABLED-LABEL: t4:
 define <2 x float> @t4(float %f) {
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
   ; CHECK-DISABLED-NOT: vdup
@@ -45,8 +45,8 @@ b:
   ret <2 x float> %i2
 }
 
-; CHECK-ENABLED: t5:
-; CHECK-DISABLED: t5:
+; CHECK-ENABLED-LABEL: t5:
+; CHECK-DISABLED-LABEL: t5:
 define arm_aapcs_vfpcc <4 x float> @t5(<4 x float> %q, float %f) {
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
   ; CHECK-ENABLED: vadd.f32
diff --git a/test/CodeGen/ARM/a15-partial-update.ll b/test/CodeGen/ARM/a15-partial-update.ll
index 6306790..5747253 100644
--- a/test/CodeGen/ARM/a15-partial-update.ll
+++ b/test/CodeGen/ARM/a15-partial-update.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s  | FileCheck %s
 
-; CHECK: t1:
+; CHECK-LABEL: t1:
 define <2 x float> @t1(float* %A, <2 x float> %B) {
 ; The generated code for this test uses a vld1.32 instruction
 ; to write the lane 1 of a D register containing the value of
@@ -15,7 +15,7 @@ define <2 x float> @t1(float* %A, <2 x float> %B) {
   ret <2 x float> %tmp3
 }
 
-; CHECK: t2:
+; CHECK-LABEL: t2:
 define void @t2(<4 x i8> *%in, <4 x i8> *%out, i32 %n) {
 entry:
   br label %loop
diff --git a/test/CodeGen/ARM/arguments.ll b/test/CodeGen/ARM/arguments.ll
index a8b42e6..e7fbf9f 100644
--- a/test/CodeGen/ARM/arguments.ll
+++ b/test/CodeGen/ARM/arguments.ll
@@ -2,9 +2,9 @@
 ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+vfp2 | FileCheck %s -check-prefix=DARWIN
 
 define i32 @f1(i32 %a, i64 %b) {
-; ELF: f1:
+; ELF-LABEL: f1:
 ; ELF: mov r0, r2
-; DARWIN: f1:
+; DARWIN-LABEL: f1:
 ; DARWIN: mov r0, r1
         %tmp = call i32 @g1(i64 %b)
         ret i32 %tmp
@@ -12,10 +12,10 @@ define i32 @f1(i32 %a, i64 %b) {
 
 ; test that allocating the double to r2/r3 makes r1 unavailable on gnueabi.
 define i32 @f2() nounwind optsize {
-; ELF: f2:
+; ELF-LABEL: f2:
 ; ELF: mov  [[REGISTER:(r[0-9]+)]], #128
 ; ELF: str  [[REGISTER]], [
-; DARWIN: f2:
+; DARWIN-LABEL: f2:
 ; DARWIN: mov	r3, #128
 entry:
   %0 = tail call i32 (i32, ...)* @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; <i32> [#uses=1]
@@ -26,10 +26,10 @@ entry:
 
 ; test that on gnueabi a 64 bit value at this position will cause r3 to go
 ; unused and the value stored in [sp]
-; ELF: f3:
+; ELF-LABEL: f3:
 ; ELF: ldr r0, [sp]
 ; ELF-NEXT: mov pc, lr
-; DARWIN: f3:
+; DARWIN-LABEL: f3:
 ; DARWIN: mov r0, r3
 ; DARWIN-NEXT: mov pc, lr
 define i32 @f3(i32 %i, i32 %j, i32 %k, i64 %l, ...) {
diff --git a/test/CodeGen/ARM/arm-frameaddr.ll b/test/CodeGen/ARM/arm-frameaddr.ll
index 2cf1422..9c4173e 100644
--- a/test/CodeGen/ARM/arm-frameaddr.ll
+++ b/test/CodeGen/ARM/arm-frameaddr.ll
@@ -5,10 +5,10 @@
 
 define i8* @t() nounwind {
 entry:
-; DARWIN: t:
+; DARWIN-LABEL: t:
 ; DARWIN: mov r0, r7
 
-; LINUX: t:
+; LINUX-LABEL: t:
 ; LINUX: mov r0, r11
 	%0 = call i8* @llvm.frameaddress(i32 0)
         ret i8* %0
diff --git a/test/CodeGen/ARM/arm-returnaddr.ll b/test/CodeGen/ARM/arm-returnaddr.ll
index 1272e8e..4266572 100644
--- a/test/CodeGen/ARM/arm-returnaddr.ll
+++ b/test/CodeGen/ARM/arm-returnaddr.ll
@@ -7,7 +7,7 @@
 
 define i8* @rt0(i32 %x) nounwind readnone {
 entry:
-; CHECK: rt0:
+; CHECK-LABEL: rt0:
 ; CHECK: {r7, lr}
 ; CHECK: mov r0, lr
   %0 = tail call i8* @llvm.returnaddress(i32 0)
@@ -16,7 +16,7 @@ entry:
 
 define i8* @rt2() nounwind readnone {
 entry:
-; CHECK: rt2:
+; CHECK-LABEL: rt2:
 ; CHECK: {r7, lr}
 ; CHECK: ldr r[[R0:[0-9]+]], [r7]
 ; CHECK: ldr r0, [r0]
diff --git a/test/CodeGen/ARM/atomic-64bit.ll b/test/CodeGen/ARM/atomic-64bit.ll
index 93664e3..8ec829c 100644
--- a/test/CodeGen/ARM/atomic-64bit.ll
+++ b/test/CodeGen/ARM/atomic-64bit.ll
@@ -12,7 +12,7 @@ define i64 @test1(i64* %ptr, i64 %val) {
 ; CHECK: bne
 ; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test1:
+; CHECK-THUMB-LABEL: test1:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
@@ -37,7 +37,7 @@ define i64 @test2(i64* %ptr, i64 %val) {
 ; CHECK: bne
 ; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test2:
+; CHECK-THUMB-LABEL: test2:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
@@ -62,7 +62,7 @@ define i64 @test3(i64* %ptr, i64 %val) {
 ; CHECK: bne
 ; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test3:
+; CHECK-THUMB-LABEL: test3:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: and.w [[REG3:[a-z0-9]+]], [[REG1]]
@@ -87,7 +87,7 @@ define i64 @test4(i64* %ptr, i64 %val) {
 ; CHECK: bne
 ; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test4:
+; CHECK-THUMB-LABEL: test4:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
@@ -112,7 +112,7 @@ define i64 @test5(i64* %ptr, i64 %val) {
 ; CHECK: bne
 ; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test5:
+; CHECK-THUMB-LABEL: test5:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
@@ -135,7 +135,7 @@ define i64 @test6(i64* %ptr, i64 %val) {
 ; CHECK: bne
 ; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test6:
+; CHECK-THUMB-LABEL: test6:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
@@ -159,7 +159,7 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
 ; CHECK: bne
 ; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test7:
+; CHECK-THUMB-LABEL: test7:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: cmp [[REG1]]
@@ -188,7 +188,7 @@ define i64 @test8(i64* %ptr) {
 ; CHECK: bne
 ; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test8:
+; CHECK-THUMB-LABEL: test8:
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: cmp [[REG1]]
 ; CHECK-THUMB: it eq
@@ -214,7 +214,7 @@ define void @test9(i64* %ptr, i64 %val) {
 ; CHECK: bne
 ; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test9:
+; CHECK-THUMB-LABEL: test9:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
@@ -238,7 +238,7 @@ define i64 @test10(i64* %ptr, i64 %val) {
 ; CHECK: bne
 ; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test10:
+; CHECK-THUMB-LABEL: test10:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
@@ -266,7 +266,7 @@ define i64 @test11(i64* %ptr, i64 %val) {
 ; CHECK: dmb {{ish$}}
 
 
-; CHECK-THUMB: test11:
+; CHECK-THUMB-LABEL: test11:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
@@ -293,7 +293,7 @@ define i64 @test12(i64* %ptr, i64 %val) {
 ; CHECK: bne
 ; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test12:
+; CHECK-THUMB-LABEL: test12:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
@@ -320,7 +320,7 @@ define i64 @test13(i64* %ptr, i64 %val) {
 ; CHECK: bne
 ; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test13:
+; CHECK-THUMB-LABEL: test13:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
diff --git a/test/CodeGen/ARM/atomic-cmp.ll b/test/CodeGen/ARM/atomic-cmp.ll
index 82726da..51ada69 100644
--- a/test/CodeGen/ARM/atomic-cmp.ll
+++ b/test/CodeGen/ARM/atomic-cmp.ll
@@ -3,11 +3,11 @@
 ; rdar://8964854
 
 define i8 @t(i8* %a, i8 %b, i8 %c) nounwind {
-; ARM: t:
+; ARM-LABEL: t:
 ; ARM: ldrexb
 ; ARM: strexb
 
-; T2: t:
+; T2-LABEL: t:
 ; T2: ldrexb
 ; T2: strexb
   %tmp0 = cmpxchg i8* %a, i8 %b, i8 %c monotonic
diff --git a/test/CodeGen/ARM/atomicrmw_minmax.ll b/test/CodeGen/ARM/atomicrmw_minmax.ll
index 69f1384..5befc22 100644
--- a/test/CodeGen/ARM/atomicrmw_minmax.ll
+++ b/test/CodeGen/ARM/atomicrmw_minmax.ll
@@ -1,6 +1,6 @@
 ;  RUN: llc -march=arm -mcpu=cortex-a9 < %s | FileCheck %s
 
-;  CHECK: max:
+;  CHECK-LABEL: max:
 define i32 @max(i8 %ctx, i32* %ptr, i32 %val)
 {
 ;  CHECK: ldrex
@@ -10,7 +10,7 @@ define i32 @max(i8 %ctx, i32* %ptr, i32 %val)
   ret i32 %old
 }
 
-;  CHECK: min:
+;  CHECK-LABEL: min:
 define i32 @min(i8 %ctx, i32* %ptr, i32 %val)
 {
 ;  CHECK: ldrex
diff --git a/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/test/CodeGen/ARM/avoid-cpsr-rmw.ll
index c14f530..0217a4a 100644
--- a/test/CodeGen/ARM/avoid-cpsr-rmw.ll
+++ b/test/CodeGen/ARM/avoid-cpsr-rmw.ll
@@ -6,7 +6,7 @@
 
 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
  entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: muls [[REG:(r[0-9]+)]], r3, r2
 ; CHECK-NEXT: mul  [[REG2:(r[0-9]+)]], r1, r0
 ; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
@@ -20,7 +20,7 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
 ; rdar://10357570
 define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
   %tobool7 = icmp eq i32* %ptr2, null
   br i1 %tobool7, label %while.end, label %while.body
 
@@ -54,7 +54,7 @@ while.end:
 ; rdar://12878928
 define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
   %tobool7 = icmp eq i32* %ptr2, null
   br i1 %tobool7, label %while.end, label %while.body
 
diff --git a/test/CodeGen/ARM/bfc.ll b/test/CodeGen/ARM/bfc.ll
index c4a44b4..3a17d2b 100644
--- a/test/CodeGen/ARM/bfc.ll
+++ b/test/CodeGen/ARM/bfc.ll
@@ -2,7 +2,7 @@
 
 ; 4278190095 = 0xff00000f
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: bfc
     %tmp = and i32 %a, 4278190095
     ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
 
 ; 4286578688 = 0xff800000
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: bfc
     %tmp = and i32 %a, 4286578688
     ret i32 %tmp
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a) {
 
 ; 4095 = 0x00000fff
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: bfc
     %tmp = and i32 %a, 4095
     ret i32 %tmp
diff --git a/test/CodeGen/ARM/bfi.ll b/test/CodeGen/ARM/bfi.ll
index 84f3813..72a4678 100644
--- a/test/CodeGen/ARM/bfi.ll
+++ b/test/CodeGen/ARM/bfi.ll
@@ -52,7 +52,7 @@ define i32 @f4(i32 %a) nounwind {
 ; rdar://8458663
 define i32 @f5(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: bfc
 ; CHECK: bfi r0, r1, #20, #4
   %0 = and i32 %a, -15728641
@@ -65,7 +65,7 @@ entry:
 ; rdar://9609030
 define i32 @f6(i32 %a, i32 %b) nounwind readnone {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: bic
 ; CHECK: bfi r0, r1, #8, #9
   %and = and i32 %a, -130817
diff --git a/test/CodeGen/ARM/bswap-inline-asm.ll b/test/CodeGen/ARM/bswap-inline-asm.ll
index 472213d..31f9d72 100644
--- a/test/CodeGen/ARM/bswap-inline-asm.ll
+++ b/test/CodeGen/ARM/bswap-inline-asm.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 | FileCheck %s
 
 define i32 @t1(i32 %x) nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK-NOT: InlineAsm
 ; CHECK: rev
   %asmtmp = tail call i32 asm "rev $0, $1\0A", "=l,l"(i32 %x) nounwind
diff --git a/test/CodeGen/ARM/call-noret-minsize.ll b/test/CodeGen/ARM/call-noret-minsize.ll
index df3c19e..e610d29 100644
--- a/test/CodeGen/ARM/call-noret-minsize.ll
+++ b/test/CodeGen/ARM/call-noret-minsize.ll
@@ -4,10 +4,10 @@
 
 define void @t1() noreturn minsize nounwind ssp {
 entry:
-; ARM: t1:
+; ARM-LABEL: t1:
 ; ARM: bl _bar
 
-; SWIFT: t1:
+; SWIFT-LABEL: t1:
 ; SWIFT: bl _bar
   tail call void @bar() noreturn nounwind
   unreachable
@@ -15,10 +15,10 @@ entry:
 
 define void @t2() noreturn minsize nounwind ssp {
 entry:
-; ARM: t2:
+; ARM-LABEL: t2:
 ; ARM: bl _t1
 
-; SWIFT: t2:
+; SWIFT-LABEL: t2:
 ; SWIFT: bl _t1
   tail call void @t1() noreturn nounwind
   unreachable
diff --git a/test/CodeGen/ARM/call-noret.ll b/test/CodeGen/ARM/call-noret.ll
index 27062dc..bb56e8b 100644
--- a/test/CodeGen/ARM/call-noret.ll
+++ b/test/CodeGen/ARM/call-noret.ll
@@ -4,11 +4,11 @@
 
 define void @t1() noreturn nounwind ssp {
 entry:
-; ARM: t1:
+; ARM-LABEL: t1:
 ; ARM: mov lr, pc
 ; ARM: b _bar
 
-; SWIFT: t1:
+; SWIFT-LABEL: t1:
 ; SWIFT: mov lr, pc
 ; SWIFT: b _bar
   tail call void @bar() noreturn nounwind
@@ -17,11 +17,11 @@ entry:
 
 define void @t2() noreturn nounwind ssp {
 entry:
-; ARM: t2:
+; ARM-LABEL: t2:
 ; ARM: mov lr, pc
 ; ARM: b _t1
 
-; SWIFT: t2:
+; SWIFT-LABEL: t2:
 ; SWIFT: mov lr, pc
 ; SWIFT: b _t1
   tail call void @t1() noreturn nounwind
diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll
index c7e17ea..d463602 100644
--- a/test/CodeGen/ARM/call-tc.ll
+++ b/test/CodeGen/ARM/call-tc.ll
@@ -11,16 +11,16 @@
 declare void @g(i32, i32, i32, i32)
 
 define void @t1() {
-; CHECKELF: t1:
+; CHECKELF-LABEL: t1:
 ; CHECKELF: bl g(PLT)
         call void @g( i32 1, i32 2, i32 3, i32 4 )
         ret void
 }
 
 define void @t2() {
-; CHECKV6: t2:
+; CHECKV6-LABEL: t2:
 ; CHECKV6: bx r0
-; CHECKT2D: t2:
+; CHECKT2D-LABEL: t2:
 ; CHECKT2D: ldr
 ; CHECKT2D-NEXT: ldr
 ; CHECKT2D-NEXT: bx r0
@@ -30,11 +30,11 @@ define void @t2() {
 }
 
 define void @t3() {
-; CHECKV6: t3:
+; CHECKV6-LABEL: t3:
 ; CHECKV6: b _t2
-; CHECKELF: t3:
+; CHECKELF-LABEL: t3:
 ; CHECKELF: b t2(PLT)
-; CHECKT2D: t3:
+; CHECKT2D-LABEL: t3:
 ; CHECKT2D: b.w _t2
 
         tail call void @t2( )            ; <i32> [#uses=0]
@@ -44,9 +44,9 @@ define void @t3() {
 ; Sibcall optimization of expanded libcalls. rdar://8707777
 define double @t4(double %a) nounwind readonly ssp {
 entry:
-; CHECKV6: t4:
+; CHECKV6-LABEL: t4:
 ; CHECKV6: b _sin
-; CHECKELF: t4:
+; CHECKELF-LABEL: t4:
 ; CHECKELF: b sin(PLT)
   %0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1]
   ret double %0
@@ -54,9 +54,9 @@ entry:
 
 define float @t5(float %a) nounwind readonly ssp {
 entry:
-; CHECKV6: t5:
+; CHECKV6-LABEL: t5:
 ; CHECKV6: b _sinf
-; CHECKELF: t5:
+; CHECKELF-LABEL: t5:
 ; CHECKELF: b sinf(PLT)
   %0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1]
   ret float %0
@@ -68,9 +68,9 @@ declare double @sin(double) nounwind readonly
 
 define i32 @t6(i32 %a, i32 %b) nounwind readnone {
 entry:
-; CHECKV6: t6:
+; CHECKV6-LABEL: t6:
 ; CHECKV6: b ___divsi3
-; CHECKELF: t6:
+; CHECKELF-LABEL: t6:
 ; CHECKELF: b __aeabi_idiv(PLT)
   %0 = sdiv i32 %a, %b
   ret i32 %0
@@ -82,7 +82,7 @@ declare void @foo() nounwind
 
 define void @t7() nounwind {
 entry:
-; CHECKT2D: t7:
+; CHECKT2D-LABEL: t7:
 ; CHECKT2D: blxeq _foo
 ; CHECKT2D-NEXT: pop.w
 ; CHECKT2D-NEXT: b.w _foo
@@ -101,7 +101,7 @@ bb:
 ; rdar://11140249
 define i32 @t8(i32 %x) nounwind ssp {
 entry:
-; CHECKT2D: t8:
+; CHECKT2D-LABEL: t8:
 ; CHECKT2D-NOT: push
   %and = and i32 %x, 1
   %tobool = icmp eq i32 %and, 0
@@ -147,7 +147,7 @@ declare i32 @c(i32)
 @x = external global i32, align 4
 
 define i32 @t9() nounwind {
-; CHECKT2D: t9:
+; CHECKT2D-LABEL: t9:
 ; CHECKT2D: blx __ZN9MutexLockC1Ev
 ; CHECKT2D: blx __ZN9MutexLockD1Ev
 ; CHECKT2D: b.w ___divsi3
@@ -167,7 +167,7 @@ declare %class.MutexLock* @_ZN9MutexLockD1Ev(%class.MutexLock*) unnamed_addr nou
 ; Correctly preserve the input chain for the tailcall node in the bitcast case,
 ; otherwise the call to floorf is lost.
 define float @libcall_tc_test2(float* nocapture %a, float %b) {
-; CHECKT2D: libcall_tc_test2:
+; CHECKT2D-LABEL: libcall_tc_test2:
 ; CHECKT2D: blx _floorf
 ; CHECKT2D: b.w _truncf
   %1 = load float* %a, align 4
diff --git a/test/CodeGen/ARM/call_nolink.ll b/test/CodeGen/ARM/call_nolink.ll
index 5ec7f74..48fa3a6 100644
--- a/test/CodeGen/ARM/call_nolink.ll
+++ b/test/CodeGen/ARM/call_nolink.ll
@@ -7,7 +7,7 @@
 @numi = external global i32		; <i32*> [#uses=1]
 @counter = external global [2 x i32]		; <[2 x i32]*> [#uses=1]
 
-; CHECK: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i:
+; CHECK-LABEL: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i:
 ; CHECK-NOT: bx lr
 
 define void @main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i() {
@@ -56,7 +56,7 @@ define void @PR15520(void ()* %fn) {
   call void %fn()
   ret void
 
-; CHECK: PR15520:
+; CHECK-LABEL: PR15520:
 ; CHECK: mov lr, pc
 ; CHECK: mov pc, r0
 }
diff --git a/test/CodeGen/ARM/carry.ll b/test/CodeGen/ARM/carry.ll
index bf51cd6..f67987f 100644
--- a/test/CodeGen/ARM/carry.ll
+++ b/test/CodeGen/ARM/carry.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: subs r
 ; CHECK: sbc r
 entry:
@@ -10,7 +10,7 @@ entry:
 }
 
 define i64 @f2(i64 %a, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: adc r
 ; CHECK: subs r
 ; CHECK: sbc r
@@ -22,7 +22,7 @@ entry:
 
 ; add with live carry
 define i64 @f3(i32 %al, i32 %bl) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: adds r
 ; CHECK: adc r
 entry:
@@ -39,7 +39,7 @@ entry:
 ; rdar://10073745
 define i64 @f4(i64 %x) nounwind readnone {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: rsbs r
 ; CHECK: rsc r
   %0 = sub nsw i64 0, %x
@@ -49,7 +49,7 @@ entry:
 ; rdar://12559385
 define i64 @f5(i32 %vi) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: movw [[REG:r[0-9]+]], #36102
 ; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
     %v0 = zext i32 %vi to i64
diff --git a/test/CodeGen/ARM/code-placement.ll b/test/CodeGen/ARM/code-placement.ll
index 487ec69..70d85c9 100644
--- a/test/CodeGen/ARM/code-placement.ll
+++ b/test/CodeGen/ARM/code-placement.ll
@@ -7,7 +7,7 @@
 
 define arm_apcscc %struct.list_head* @t1(%struct.list_head* %list) nounwind {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
   %0 = icmp eq %struct.list_head* %list, null
   br i1 %0, label %bb2, label %bb
 
@@ -33,7 +33,7 @@ bb2:
 ; rdar://8117827
 define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: beq LBB1_[[RET:.]]
   %0 = icmp eq i32 %passes, 0                     ; <i1> [#uses=1]
   br i1 %0, label %bb5, label %bb.nph15
diff --git a/test/CodeGen/ARM/ctz.ll b/test/CodeGen/ARM/ctz.ll
index 5ebca53..2c7efc7 100644
--- a/test/CodeGen/ARM/ctz.ll
+++ b/test/CodeGen/ARM/ctz.ll
@@ -3,7 +3,7 @@
 declare i32 @llvm.cttz.i32(i32, i1)
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: rbit
 ; CHECK: clz
   %tmp = call i32 @llvm.cttz.i32( i32 %a, i1 true )
diff --git a/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll b/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
index 18f57ea..8950abd 100644
--- a/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
+++ b/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
 
-; CHECK: f:
+; CHECK-LABEL: f:
 define float @f(<4 x i16>* nocapture %in) {
   ; CHECK: vldr
   ; CHECK: vmovl.u16
diff --git a/test/CodeGen/ARM/data-in-code-annotations.ll b/test/CodeGen/ARM/data-in-code-annotations.ll
index a66a9d1..da70178 100644
--- a/test/CodeGen/ARM/data-in-code-annotations.ll
+++ b/test/CodeGen/ARM/data-in-code-annotations.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
 
 define double @f1() nounwind {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .data_region
 ; CHECK: .long 1413754129
 ; CHECK: .long 1074340347
@@ -11,7 +11,7 @@ define double @f1() nounwind {
 
 
 define i32 @f2()  {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .data_region jt32
 ; CHECK: .end_data_region
 
diff --git a/test/CodeGen/ARM/divmod.ll b/test/CodeGen/ARM/divmod.ll
index 577f8aa..06d6172 100644
--- a/test/CodeGen/ARM/divmod.ll
+++ b/test/CodeGen/ARM/divmod.ll
@@ -5,11 +5,11 @@
 
 define void @foo(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
 entry:
-; A8: foo:
+; A8-LABEL: foo:
 ; A8: bl ___divmodsi4
 ; A8-NOT: bl ___divmodsi4
 
-; SWIFT: foo:
+; SWIFT-LABEL: foo:
 ; SWIFT: sdiv
 ; SWIFT: mls
 ; SWIFT-NOT: bl __divmodsi4
@@ -23,11 +23,11 @@ entry:
 
 define void @bar(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
 entry:
-; A8: bar:
+; A8-LABEL: bar:
 ; A8: bl ___udivmodsi4
 ; A8-NOT: bl ___udivmodsi4
 
-; SWIFT: bar:
+; SWIFT-LABEL: bar:
 ; SWIFT: udiv
 ; SWIFT: mls
 ; SWIFT-NOT: bl __udivmodsi4
@@ -45,8 +45,8 @@ entry:
 
 define void @do_indent(i32 %cols) nounwind {
 entry:
-; A8: do_indent:
-; SWIFT: do_indent:
+; A8-LABEL: do_indent:
+; SWIFT-LABEL: do_indent:
   %0 = load i32* @flags, align 4
   %1 = and i32 %0, 67108864
   %2 = icmp eq i32 %1, 0
@@ -77,11 +77,11 @@ declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind
 ; rdar://11714607
 define i32 @howmany(i32 %x, i32 %y) nounwind {
 entry:
-; A8: howmany:
+; A8-LABEL: howmany:
 ; A8: bl ___udivmodsi4
 ; A8-NOT: ___udivsi3
 
-; SWIFT: howmany:
+; SWIFT-LABEL: howmany:
 ; SWIFT: udiv
 ; SWIFT: mls
 ; SWIFT-NOT: bl __udivmodsi4
diff --git a/test/CodeGen/ARM/ehabi-filters.ll b/test/CodeGen/ARM/ehabi-filters.ll
index 4c92a29..cb5291b 100644
--- a/test/CodeGen/ARM/ehabi-filters.ll
+++ b/test/CodeGen/ARM/ehabi-filters.ll
@@ -15,7 +15,7 @@ declare void @__cxa_throw(i8*, i8*, i8*)
 declare void @__cxa_call_unexpected(i8*)
 
 define i32 @main() {
-; CHECK: main:
+; CHECK-LABEL: main:
 entry:
   %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind
   %0 = bitcast i8* %exception.i to i32*
diff --git a/test/CodeGen/ARM/ehabi.ll b/test/CodeGen/ARM/ehabi.ll
index b05d4be..6644652 100644
--- a/test/CodeGen/ARM/ehabi.ll
+++ b/test/CodeGen/ARM/ehabi.ll
@@ -112,7 +112,7 @@ declare void @__cxa_end_catch()
 
 declare void @_ZSt9terminatev()
 
-; CHECK-FP: _Z4testiiiiiddddd:
+; CHECK-FP-LABEL: _Z4testiiiiiddddd:
 ; CHECK-FP:   .fnstart
 ; CHECK-FP:   .save  {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; CHECK-FP:   push   {r4, r5, r6, r7, r8, r9, r10, r11, lr}
@@ -124,7 +124,7 @@ declare void @_ZSt9terminatev()
 ; CHECK-FP:   .handlerdata
 ; CHECK-FP:   .fnend
 
-; CHECK-FP-ELIM: _Z4testiiiiiddddd:
+; CHECK-FP-ELIM-LABEL: _Z4testiiiiiddddd:
 ; CHECK-FP-ELIM:   .fnstart
 ; CHECK-FP-ELIM:   .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; CHECK-FP-ELIM:   push  {r4, r5, r6, r7, r8, r9, r10, r11, lr}
@@ -134,7 +134,7 @@ declare void @_ZSt9terminatev()
 ; CHECK-FP-ELIM:   .handlerdata
 ; CHECK-FP-ELIM:   .fnend
 
-; CHECK-V7-FP: _Z4testiiiiiddddd:
+; CHECK-V7-FP-LABEL: _Z4testiiiiiddddd:
 ; CHECK-V7-FP:   .fnstart
 ; CHECK-V7-FP:   .save  {r4, r11, lr}
 ; CHECK-V7-FP:   push   {r4, r11, lr}
@@ -148,7 +148,7 @@ declare void @_ZSt9terminatev()
 ; CHECK-V7-FP:   .handlerdata
 ; CHECK-V7-FP:   .fnend
 
-; CHECK-V7-FP-ELIM: _Z4testiiiiiddddd:
+; CHECK-V7-FP-ELIM-LABEL: _Z4testiiiiiddddd:
 ; CHECK-V7-FP-ELIM:   .fnstart
 ; CHECK-V7-FP-ELIM:   .save  {r4, lr}
 ; CHECK-V7-FP-ELIM:   push   {r4, lr}
@@ -173,7 +173,7 @@ entry:
   ret void
 }
 
-; CHECK-FP: test2:
+; CHECK-FP-LABEL: test2:
 ; CHECK-FP:   .fnstart
 ; CHECK-FP:   .save  {r11, lr}
 ; CHECK-FP:   push   {r11, lr}
@@ -183,7 +183,7 @@ entry:
 ; CHECK-FP:   mov    pc, lr
 ; CHECK-FP:   .fnend
 
-; CHECK-FP-ELIM: test2:
+; CHECK-FP-ELIM-LABEL: test2:
 ; CHECK-FP-ELIM:   .fnstart
 ; CHECK-FP-ELIM:   .save {r11, lr}
 ; CHECK-FP-ELIM:   push  {r11, lr}
@@ -191,7 +191,7 @@ entry:
 ; CHECK-FP-ELIM:   mov   pc, lr
 ; CHECK-FP-ELIM:   .fnend
 
-; CHECK-V7-FP: test2:
+; CHECK-V7-FP-LABEL: test2:
 ; CHECK-V7-FP:   .fnstart
 ; CHECK-V7-FP:   .save  {r11, lr}
 ; CHECK-V7-FP:   push   {r11, lr}
@@ -200,7 +200,7 @@ entry:
 ; CHECK-V7-FP:   pop    {r11, pc}
 ; CHECK-V7-FP:   .fnend
 
-; CHECK-V7-FP-ELIM: test2:
+; CHECK-V7-FP-ELIM-LABEL: test2:
 ; CHECK-V7-FP-ELIM:   .fnstart
 ; CHECK-V7-FP-ELIM:   .save {r11, lr}
 ; CHECK-V7-FP-ELIM:   push  {r11, lr}
@@ -229,7 +229,7 @@ entry:
   ret i32 %add6
 }
 
-; CHECK-FP: test3:
+; CHECK-FP-LABEL: test3:
 ; CHECK-FP:   .fnstart
 ; CHECK-FP:   .save  {r4, r5, r11, lr}
 ; CHECK-FP:   push   {r4, r5, r11, lr}
@@ -239,7 +239,7 @@ entry:
 ; CHECK-FP:   mov    pc, lr
 ; CHECK-FP:   .fnend
 
-; CHECK-FP-ELIM: test3:
+; CHECK-FP-ELIM-LABEL: test3:
 ; CHECK-FP-ELIM:   .fnstart
 ; CHECK-FP-ELIM:   .save {r4, r5, r11, lr}
 ; CHECK-FP-ELIM:   push  {r4, r5, r11, lr}
@@ -247,7 +247,7 @@ entry:
 ; CHECK-FP-ELIM:   mov   pc, lr
 ; CHECK-FP-ELIM:   .fnend
 
-; CHECK-V7-FP: test3:
+; CHECK-V7-FP-LABEL: test3:
 ; CHECK-V7-FP:   .fnstart
 ; CHECK-V7-FP:   .save  {r4, r5, r11, lr}
 ; CHECK-V7-FP:   push   {r4, r5, r11, lr}
@@ -256,7 +256,7 @@ entry:
 ; CHECK-V7-FP:   pop    {r4, r5, r11, pc}
 ; CHECK-V7-FP:   .fnend
 
-; CHECK-V7-FP-ELIM: test3:
+; CHECK-V7-FP-ELIM-LABEL: test3:
 ; CHECK-V7-FP-ELIM:   .fnstart
 ; CHECK-V7-FP-ELIM:   .save {r4, r5, r11, lr}
 ; CHECK-V7-FP-ELIM:   push  {r4, r5, r11, lr}
@@ -273,25 +273,25 @@ entry:
   ret void
 }
 
-; CHECK-FP: test4:
+; CHECK-FP-LABEL: test4:
 ; CHECK-FP:   .fnstart
 ; CHECK-FP:   mov pc, lr
 ; CHECK-FP:   .cantunwind
 ; CHECK-FP:   .fnend
 
-; CHECK-FP-ELIM: test4:
+; CHECK-FP-ELIM-LABEL: test4:
 ; CHECK-FP-ELIM:   .fnstart
 ; CHECK-FP-ELIM:   mov pc, lr
 ; CHECK-FP-ELIM:   .cantunwind
 ; CHECK-FP-ELIM:   .fnend
 
-; CHECK-V7-FP: test4:
+; CHECK-V7-FP-LABEL: test4:
 ; CHECK-V7-FP:   .fnstart
 ; CHECK-V7-FP:   bx lr
 ; CHECK-V7-FP:   .cantunwind
 ; CHECK-V7-FP:   .fnend
 
-; CHECK-V7-FP-ELIM: test4:
+; CHECK-V7-FP-ELIM-LABEL: test4:
 ; CHECK-V7-FP-ELIM:   .fnstart
 ; CHECK-V7-FP-ELIM:   bx lr
 ; CHECK-V7-FP-ELIM:   .cantunwind
diff --git a/test/CodeGen/ARM/extload-knownzero.ll b/test/CodeGen/ARM/extload-knownzero.ll
index 8fd6b6b..8ccf58c 100644
--- a/test/CodeGen/ARM/extload-knownzero.ll
+++ b/test/CodeGen/ARM/extload-knownzero.ll
@@ -3,7 +3,7 @@
 
 define void @foo(i16* %ptr, i32 %a) nounwind {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
   %tmp1 = icmp ult i32 %a, 100
   br i1 %tmp1, label %bb1, label %bb2
 bb1:
diff --git a/test/CodeGen/ARM/fast-isel-br-const.ll b/test/CodeGen/ARM/fast-isel-br-const.ll
index 293302f..2e28b08 100644
--- a/test/CodeGen/ARM/fast-isel-br-const.ll
+++ b/test/CodeGen/ARM/fast-isel-br-const.ll
@@ -4,8 +4,8 @@
 
 define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp {
 entry:
-; THUMB: t1:
-; ARM: t1:
+; THUMB-LABEL: t1:
+; ARM-LABEL: t1:
   %x = add i32 %a, %b  
   br i1 1, label %if.then, label %if.else
 ; THUMB-NOT: b {{\.?}}LBB0_1
diff --git a/test/CodeGen/ARM/fast-isel-ext.ll b/test/CodeGen/ARM/fast-isel-ext.ll
index 38ce481..15d0d3c 100644
--- a/test/CodeGen/ARM/fast-isel-ext.ll
+++ b/test/CodeGen/ARM/fast-isel-ext.ll
@@ -17,54 +17,54 @@
 ; zext
 
 define i8 @zext_1_8(i1 %a) nounwind ssp {
-; v7: zext_1_8:
+; v7-LABEL: zext_1_8:
 ; v7: and r0, r0, #1
-; prev6: zext_1_8:
+; prev6-LABEL: zext_1_8:
 ; prev6: and r0, r0, #1
   %r = zext i1 %a to i8
   ret i8 %r
 }
 
 define i16 @zext_1_16(i1 %a) nounwind ssp {
-; v7: zext_1_16:
+; v7-LABEL: zext_1_16:
 ; v7: and r0, r0, #1
-; prev6: zext_1_16:
+; prev6-LABEL: zext_1_16:
 ; prev6: and r0, r0, #1
   %r = zext i1 %a to i16
   ret i16 %r
 }
 
 define i32 @zext_1_32(i1 %a) nounwind ssp {
-; v7: zext_1_32:
+; v7-LABEL: zext_1_32:
 ; v7: and r0, r0, #1
-; prev6: zext_1_32:
+; prev6-LABEL: zext_1_32:
 ; prev6: and r0, r0, #1
   %r = zext i1 %a to i32
   ret i32 %r
 }
 
 define i16 @zext_8_16(i8 %a) nounwind ssp {
-; v7: zext_8_16:
+; v7-LABEL: zext_8_16:
 ; v7: and r0, r0, #255
-; prev6: zext_8_16:
+; prev6-LABEL: zext_8_16:
 ; prev6: and r0, r0, #255
   %r = zext i8 %a to i16
   ret i16 %r
 }
 
 define i32 @zext_8_32(i8 %a) nounwind ssp {
-; v7: zext_8_32:
+; v7-LABEL: zext_8_32:
 ; v7: and r0, r0, #255
-; prev6: zext_8_32:
+; prev6-LABEL: zext_8_32:
 ; prev6: and r0, r0, #255
   %r = zext i8 %a to i32
   ret i32 %r
 }
 
 define i32 @zext_16_32(i16 %a) nounwind ssp {
-; v7: zext_16_32:
+; v7-LABEL: zext_16_32:
 ; v7: uxth r0, r0
-; prev6: zext_16_32:
+; prev6-LABEL: zext_16_32:
 ; prev6: lsl{{s?}} r0, r0, #16
 ; prev6: lsr{{s?}} r0, r0, #16
   %r = zext i16 %a to i32
@@ -74,10 +74,10 @@ define i32 @zext_16_32(i16 %a) nounwind ssp {
 ; sext
 
 define i8 @sext_1_8(i1 %a) nounwind ssp {
-; v7: sext_1_8:
+; v7-LABEL: sext_1_8:
 ; v7: lsl{{s?}} r0, r0, #31
 ; v7: asr{{s?}} r0, r0, #31
-; prev6: sext_1_8:
+; prev6-LABEL: sext_1_8:
 ; prev6: lsl{{s?}} r0, r0, #31
 ; prev6: asr{{s?}} r0, r0, #31
   %r = sext i1 %a to i8
@@ -85,10 +85,10 @@ define i8 @sext_1_8(i1 %a) nounwind ssp {
 }
 
 define i16 @sext_1_16(i1 %a) nounwind ssp {
-; v7: sext_1_16:
+; v7-LABEL: sext_1_16:
 ; v7: lsl{{s?}} r0, r0, #31
 ; v7: asr{{s?}} r0, r0, #31
-; prev6: sext_1_16:
+; prev6-LABEL: sext_1_16:
 ; prev6: lsl{{s?}} r0, r0, #31
 ; prev6: asr{{s?}} r0, r0, #31
   %r = sext i1 %a to i16
@@ -96,10 +96,10 @@ define i16 @sext_1_16(i1 %a) nounwind ssp {
 }
 
 define i32 @sext_1_32(i1 %a) nounwind ssp {
-; v7: sext_1_32:
+; v7-LABEL: sext_1_32:
 ; v7: lsl{{s?}} r0, r0, #31
 ; v7: asr{{s?}} r0, r0, #31
-; prev6: sext_1_32:
+; prev6-LABEL: sext_1_32:
 ; prev6: lsl{{s?}} r0, r0, #31
 ; prev6: asr{{s?}} r0, r0, #31
   %r = sext i1 %a to i32
@@ -107,9 +107,9 @@ define i32 @sext_1_32(i1 %a) nounwind ssp {
 }
 
 define i16 @sext_8_16(i8 %a) nounwind ssp {
-; v7: sext_8_16:
+; v7-LABEL: sext_8_16:
 ; v7: sxtb r0, r0
-; prev6: sext_8_16:
+; prev6-LABEL: sext_8_16:
 ; prev6: lsl{{s?}} r0, r0, #24
 ; prev6: asr{{s?}} r0, r0, #24
   %r = sext i8 %a to i16
@@ -117,9 +117,9 @@ define i16 @sext_8_16(i8 %a) nounwind ssp {
 }
 
 define i32 @sext_8_32(i8 %a) nounwind ssp {
-; v7: sext_8_32:
+; v7-LABEL: sext_8_32:
 ; v7: sxtb r0, r0
-; prev6: sext_8_32:
+; prev6-LABEL: sext_8_32:
 ; prev6: lsl{{s?}} r0, r0, #24
 ; prev6: asr{{s?}} r0, r0, #24
   %r = sext i8 %a to i32
@@ -127,9 +127,9 @@ define i32 @sext_8_32(i8 %a) nounwind ssp {
 }
 
 define i32 @sext_16_32(i16 %a) nounwind ssp {
-; v7: sext_16_32:
+; v7-LABEL: sext_16_32:
 ; v7: sxth r0, r0
-; prev6: sext_16_32:
+; prev6-LABEL: sext_16_32:
 ; prev6: lsl{{s?}} r0, r0, #16
 ; prev6: asr{{s?}} r0, r0, #16
   %r = sext i16 %a to i32
diff --git a/test/CodeGen/ARM/fast-isel-frameaddr.ll b/test/CodeGen/ARM/fast-isel-frameaddr.ll
index 5ae7ad7..8542bb5 100644
--- a/test/CodeGen/ARM/fast-isel-frameaddr.ll
+++ b/test/CodeGen/ARM/fast-isel-frameaddr.ll
@@ -5,22 +5,22 @@
 
 define i8* @frameaddr_index0() nounwind {
 entry:
-; DARWIN-ARM: frameaddr_index0:
+; DARWIN-ARM-LABEL: frameaddr_index0:
 ; DARWIN-ARM: push {r7}
 ; DARWIN-ARM: mov r7, sp
 ; DARWIN-ARM: mov r0, r7
 
-; DARWIN-THUMB2: frameaddr_index0:
+; DARWIN-THUMB2-LABEL: frameaddr_index0:
 ; DARWIN-THUMB2: str r7, [sp, #-4]!
 ; DARWIN-THUMB2: mov r7, sp
 ; DARWIN-THUMB2: mov r0, r7
 
-; LINUX-ARM: frameaddr_index0:
+; LINUX-ARM-LABEL: frameaddr_index0:
 ; LINUX-ARM: push {r11}
 ; LINUX-ARM: mov r11, sp
 ; LINUX-ARM: mov r0, r11
 
-; LINUX-THUMB2: frameaddr_index0:
+; LINUX-THUMB2-LABEL: frameaddr_index0:
 ; LINUX-THUMB2: str r7, [sp, #-4]!
 ; LINUX-THUMB2: mov r7, sp
 ; LINUX-THUMB2: mov r0, r7
@@ -31,24 +31,24 @@ entry:
 
 define i8* @frameaddr_index1() nounwind {
 entry:
-; DARWIN-ARM: frameaddr_index1:
+; DARWIN-ARM-LABEL: frameaddr_index1:
 ; DARWIN-ARM: push {r7}
 ; DARWIN-ARM: mov r7, sp
 ; DARWIN-ARM: mov r0, r7
 ; DARWIN-ARM: ldr r0, [r0]
 
-; DARWIN-THUMB2: frameaddr_index1:
+; DARWIN-THUMB2-LABEL: frameaddr_index1:
 ; DARWIN-THUMB2: str r7, [sp, #-4]!
 ; DARWIN-THUMB2: mov r7, sp
 ; DARWIN-THUMB2: mov r0, r7
 ; DARWIN-THUMB2: ldr r0, [r0]
 
-; LINUX-ARM: frameaddr_index1:
+; LINUX-ARM-LABEL: frameaddr_index1:
 ; LINUX-ARM: push {r11}
 ; LINUX-ARM: mov r11, sp
 ; LINUX-ARM: ldr r0, [r11]
 
-; LINUX-THUMB2: frameaddr_index1:
+; LINUX-THUMB2-LABEL: frameaddr_index1:
 ; LINUX-THUMB2: str r7, [sp, #-4]!
 ; LINUX-THUMB2: mov r7, sp
 ; LINUX-THUMB2: mov r0, r7
@@ -60,7 +60,7 @@ entry:
 
 define i8* @frameaddr_index3() nounwind {
 entry:
-; DARWIN-ARM: frameaddr_index3:
+; DARWIN-ARM-LABEL: frameaddr_index3:
 ; DARWIN-ARM: push {r7}
 ; DARWIN-ARM: mov r7, sp
 ; DARWIN-ARM: mov r0, r7
@@ -68,7 +68,7 @@ entry:
 ; DARWIN-ARM: ldr r0, [r0]
 ; DARWIN-ARM: ldr r0, [r0]
 
-; DARWIN-THUMB2: frameaddr_index3:
+; DARWIN-THUMB2-LABEL: frameaddr_index3:
 ; DARWIN-THUMB2: str r7, [sp, #-4]!
 ; DARWIN-THUMB2: mov r7, sp
 ; DARWIN-THUMB2: mov r0, r7
@@ -76,14 +76,14 @@ entry:
 ; DARWIN-THUMB2: ldr r0, [r0]
 ; DARWIN-THUMB2: ldr r0, [r0]
 
-; LINUX-ARM: frameaddr_index3:
+; LINUX-ARM-LABEL: frameaddr_index3:
 ; LINUX-ARM: push {r11}
 ; LINUX-ARM: mov r11, sp
 ; LINUX-ARM: ldr r0, [r11]
 ; LINUX-ARM: ldr r0, [r0]
 ; LINUX-ARM: ldr r0, [r0]
 
-; LINUX-THUMB2: frameaddr_index3:
+; LINUX-THUMB2-LABEL: frameaddr_index3:
 ; LINUX-THUMB2: str r7, [sp, #-4]!
 ; LINUX-THUMB2: mov r7, sp
 ; LINUX-THUMB2: mov r0, r7
diff --git a/test/CodeGen/ARM/fmacs.ll b/test/CodeGen/ARM/fmacs.ll
index b63f609..f2486c6 100644
--- a/test/CodeGen/ARM/fmacs.ll
+++ b/test/CodeGen/ARM/fmacs.ll
@@ -6,13 +6,13 @@
 
 define float @t1(float %acc, float %a, float %b) {
 entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
 ; VFP2: vmla.f32
 
-; NEON: t1:
+; NEON-LABEL: t1:
 ; NEON: vmla.f32
 
-; A8: t1:
+; A8-LABEL: t1:
 ; A8: vmul.f32
 ; A8: vadd.f32
 	%0 = fmul float %a, %b
@@ -22,13 +22,13 @@ entry:
 
 define double @t2(double %acc, double %a, double %b) {
 entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
 ; VFP2: vmla.f64
 
-; NEON: t2:
+; NEON-LABEL: t2:
 ; NEON: vmla.f64
 
-; A8: t2:
+; A8-LABEL: t2:
 ; A8: vmul.f64
 ; A8: vadd.f64
 	%0 = fmul double %a, %b
@@ -38,13 +38,13 @@ entry:
 
 define float @t3(float %acc, float %a, float %b) {
 entry:
-; VFP2: t3:
+; VFP2-LABEL: t3:
 ; VFP2: vmla.f32
 
-; NEON: t3:
+; NEON-LABEL: t3:
 ; NEON: vmla.f32
 
-; A8: t3:
+; A8-LABEL: t3:
 ; A8: vmul.f32
 ; A8: vadd.f32
 	%0 = fmul float %a, %b
@@ -56,18 +56,18 @@ entry:
 ; rdar://8659675
 define void @t4(float %acc1, float %a, float %b, float %acc2, float %c, float* %P1, float* %P2) {
 entry:
-; A8: t4:
+; A8-LABEL: t4:
 ; A8: vmul.f32
 ; A8: vmul.f32
 ; A8: vadd.f32
 ; A8: vadd.f32
 
 ; Two vmla with now RAW hazard
-; A9: t4:
+; A9-LABEL: t4:
 ; A9: vmla.f32
 ; A9: vmla.f32
 
-; HARD: t4:
+; HARD-LABEL: t4:
 ; HARD: vmla.f32 s0, s1, s2
 ; HARD: vmla.f32 s3, s1, s4
   %0 = fmul float %a, %b
@@ -81,18 +81,18 @@ entry:
 
 define float @t5(float %a, float %b, float %c, float %d, float %e) {
 entry:
-; A8: t5:
+; A8-LABEL: t5:
 ; A8: vmul.f32
 ; A8: vmul.f32
 ; A8: vadd.f32
 ; A8: vadd.f32
 
-; A9: t5:
+; A9-LABEL: t5:
 ; A9: vmla.f32
 ; A9: vmul.f32
 ; A9: vadd.f32
 
-; HARD: t5:
+; HARD-LABEL: t5:
 ; HARD: vmla.f32 s4, s0, s1
 ; HARD: vmul.f32 s0, s2, s3
 ; HARD: vadd.f32 s0, s4, s0
diff --git a/test/CodeGen/ARM/fmscs.ll b/test/CodeGen/ARM/fmscs.ll
index a182833..f16ec17 100644
--- a/test/CodeGen/ARM/fmscs.ll
+++ b/test/CodeGen/ARM/fmscs.ll
@@ -4,13 +4,13 @@
 
 define float @t1(float %acc, float %a, float %b) {
 entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
 ; VFP2: vnmls.f32
 
-; NEON: t1:
+; NEON-LABEL: t1:
 ; NEON: vnmls.f32
 
-; A8: t1:
+; A8-LABEL: t1:
 ; A8: vmul.f32
 ; A8: vsub.f32
 	%0 = fmul float %a, %b
@@ -20,13 +20,13 @@ entry:
 
 define double @t2(double %acc, double %a, double %b) {
 entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
 ; VFP2: vnmls.f64
 
-; NEON: t2:
+; NEON-LABEL: t2:
 ; NEON: vnmls.f64
 
-; A8: t2:
+; A8-LABEL: t2:
 ; A8: vmul.f64
 ; A8: vsub.f64
 	%0 = fmul double %a, %b
diff --git a/test/CodeGen/ARM/fnmacs.ll b/test/CodeGen/ARM/fnmacs.ll
index 1763d46..825feaa 100644
--- a/test/CodeGen/ARM/fnmacs.ll
+++ b/test/CodeGen/ARM/fnmacs.ll
@@ -4,13 +4,13 @@
 
 define float @t1(float %acc, float %a, float %b) {
 entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
 ; VFP2: vmls.f32
 
-; NEON: t1:
+; NEON-LABEL: t1:
 ; NEON: vmls.f32
 
-; A8: t1:
+; A8-LABEL: t1:
 ; A8: vmul.f32
 ; A8: vsub.f32
 	%0 = fmul float %a, %b
@@ -20,13 +20,13 @@ entry:
 
 define double @t2(double %acc, double %a, double %b) {
 entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
 ; VFP2: vmls.f64
 
-; NEON: t2:
+; NEON-LABEL: t2:
 ; NEON: vmls.f64
 
-; A8: t2:
+; A8-LABEL: t2:
 ; A8: vmul.f64
 ; A8: vsub.f64
 	%0 = fmul double %a, %b
diff --git a/test/CodeGen/ARM/fnmscs.ll b/test/CodeGen/ARM/fnmscs.ll
index c308061..78ccb60 100644
--- a/test/CodeGen/ARM/fnmscs.ll
+++ b/test/CodeGen/ARM/fnmscs.ll
@@ -7,17 +7,17 @@
 
 define float @t1(float %acc, float %a, float %b) nounwind {
 entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
 ; VFP2: vnmla.f32
 
-; NEON: t1:
+; NEON-LABEL: t1:
 ; NEON: vnmla.f32
 
-; A8U: t1:
+; A8U-LABEL: t1:
 ; A8U: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
 ; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
 
-; A8: t1:
+; A8-LABEL: t1:
 ; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
 ; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
 	%0 = fmul float %a, %b
@@ -28,17 +28,17 @@ entry:
 
 define float @t2(float %acc, float %a, float %b) nounwind {
 entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
 ; VFP2: vnmla.f32
 
-; NEON: t2:
+; NEON-LABEL: t2:
 ; NEON: vnmla.f32
 
-; A8U: t2:
+; A8U-LABEL: t2:
 ; A8U: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
 ; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
 
-; A8: t2:
+; A8-LABEL: t2:
 ; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
 ; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
 	%0 = fmul float %a, %b
@@ -49,17 +49,17 @@ entry:
 
 define double @t3(double %acc, double %a, double %b) nounwind {
 entry:
-; VFP2: t3:
+; VFP2-LABEL: t3:
 ; VFP2: vnmla.f64
 
-; NEON: t3:
+; NEON-LABEL: t3:
 ; NEON: vnmla.f64
 
-; A8U: t3:
+; A8U-LABEL: t3:
 ; A8U: vnmul.f64 d
 ; A8U: vsub.f64 d
 
-; A8: t3:
+; A8-LABEL: t3:
 ; A8: vnmul.f64 d
 ; A8: vsub.f64 d
 	%0 = fmul double %a, %b
@@ -70,17 +70,17 @@ entry:
 
 define double @t4(double %acc, double %a, double %b) nounwind {
 entry:
-; VFP2: t4:
+; VFP2-LABEL: t4:
 ; VFP2: vnmla.f64
 
-; NEON: t4:
+; NEON-LABEL: t4:
 ; NEON: vnmla.f64
 
-; A8U: t4:
+; A8U-LABEL: t4:
 ; A8U: vnmul.f64 d
 ; A8U: vsub.f64 d
 
-; A8: t4:
+; A8-LABEL: t4:
 ; A8: vnmul.f64 d
 ; A8: vsub.f64 d
 	%0 = fmul double %a, %b
diff --git a/test/CodeGen/ARM/fp.ll b/test/CodeGen/ARM/fp.ll
index 93601cf..fbf3a4a 100644
--- a/test/CodeGen/ARM/fp.ll
+++ b/test/CodeGen/ARM/fp.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
 
 define float @f(i32 %a) {
-;CHECK: f:
+;CHECK-LABEL: f:
 ;CHECK: vmov
 ;CHECK-NEXT: vcvt.f32.s32
 ;CHECK-NEXT: vmov
@@ -11,7 +11,7 @@ entry:
 }
 
 define double @g(i32 %a) {
-;CHECK: g:
+;CHECK-LABEL: g:
 ;CHECK: vmov
 ;CHECK-NEXT: vcvt.f64.s32
 ;CHECK-NEXT: vmov
@@ -21,7 +21,7 @@ entry:
 }
 
 define double @uint_to_double(i32 %a) {
-;CHECK: uint_to_double:
+;CHECK-LABEL: uint_to_double:
 ;CHECK: vmov
 ;CHECK-NEXT: vcvt.f64.u32
 ;CHECK-NEXT: vmov
@@ -31,7 +31,7 @@ entry:
 }
 
 define float @uint_to_float(i32 %a) {
-;CHECK: uint_to_float:
+;CHECK-LABEL: uint_to_float:
 ;CHECK: vmov
 ;CHECK-NEXT: vcvt.f32.u32
 ;CHECK-NEXT: vmov
@@ -41,7 +41,7 @@ entry:
 }
 
 define double @h(double* %v) {
-;CHECK: h:
+;CHECK-LABEL: h:
 ;CHECK: vldr
 ;CHECK-NEXT: vmov
 entry:
@@ -50,20 +50,20 @@ entry:
 }
 
 define float @h2() {
-;CHECK: h2:
+;CHECK-LABEL: h2:
 ;CHECK: mov r0, #1065353216
 entry:
         ret float 1.000000e+00
 }
 
 define double @f2(double %a) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
 ;CHECK-NOT: vmov
         ret double %a
 }
 
 define void @f3() {
-;CHECK: f3:
+;CHECK-LABEL: f3:
 ;CHECK-NOT: vmov
 ;CHECK: f4
 entry:
diff --git a/test/CodeGen/ARM/fp16.ll b/test/CodeGen/ARM/fp16.ll
index 1261ea5..a5c1aed 100644
--- a/test/CodeGen/ARM/fp16.ll
+++ b/test/CodeGen/ARM/fp16.ll
@@ -8,8 +8,8 @@ target triple = "armv7-eabi"
 @z = common global i16 0
 
 define arm_aapcs_vfpcc void @foo() nounwind {
-; CHECK: foo:
-; CHECK-FP6: foo:
+; CHECK-LABEL: foo:
+; CHECK-FP6-LABEL: foo:
 entry:
   %0 = load i16* @x, align 2
   %1 = load i16* @y, align 2
diff --git a/test/CodeGen/ARM/fparith.ll b/test/CodeGen/ARM/fparith.ll
index 40ea33b..cc88014 100644
--- a/test/CodeGen/ARM/fparith.ll
+++ b/test/CodeGen/ARM/fparith.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+vfp2 | FileCheck %s
 
 define float @f1(float %a, float %b) {
-;CHECK: f1:
+;CHECK-LABEL: f1:
 ;CHECK: vadd.f32
 entry:
 	%tmp = fadd float %a, %b		; <float> [#uses=1]
@@ -9,7 +9,7 @@ entry:
 }
 
 define double @f2(double %a, double %b) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
 ;CHECK: vadd.f64
 entry:
 	%tmp = fadd double %a, %b		; <double> [#uses=1]
@@ -17,7 +17,7 @@ entry:
 }
 
 define float @f3(float %a, float %b) {
-;CHECK: f3:
+;CHECK-LABEL: f3:
 ;CHECK: vmul.f32
 entry:
 	%tmp = fmul float %a, %b		; <float> [#uses=1]
@@ -25,7 +25,7 @@ entry:
 }
 
 define double @f4(double %a, double %b) {
-;CHECK: f4:
+;CHECK-LABEL: f4:
 ;CHECK: vmul.f64
 entry:
 	%tmp = fmul double %a, %b		; <double> [#uses=1]
@@ -33,7 +33,7 @@ entry:
 }
 
 define float @f5(float %a, float %b) {
-;CHECK: f5:
+;CHECK-LABEL: f5:
 ;CHECK: vsub.f32
 entry:
 	%tmp = fsub float %a, %b		; <float> [#uses=1]
@@ -41,7 +41,7 @@ entry:
 }
 
 define double @f6(double %a, double %b) {
-;CHECK: f6:
+;CHECK-LABEL: f6:
 ;CHECK: vsub.f64
 entry:
 	%tmp = fsub double %a, %b		; <double> [#uses=1]
@@ -49,7 +49,7 @@ entry:
 }
 
 define float @f7(float %a) {
-;CHECK: f7:
+;CHECK-LABEL: f7:
 ;CHECK: eor
 entry:
 	%tmp1 = fsub float -0.000000e+00, %a		; <float> [#uses=1]
@@ -57,7 +57,7 @@ entry:
 }
 
 define double @f8(double %a) {
-;CHECK: f8:
+;CHECK-LABEL: f8:
 ;CHECK: vneg.f64
 entry:
 	%tmp1 = fsub double -0.000000e+00, %a		; <double> [#uses=1]
@@ -65,7 +65,7 @@ entry:
 }
 
 define float @f9(float %a, float %b) {
-;CHECK: f9:
+;CHECK-LABEL: f9:
 ;CHECK: vdiv.f32
 entry:
 	%tmp1 = fdiv float %a, %b		; <float> [#uses=1]
@@ -73,7 +73,7 @@ entry:
 }
 
 define double @f10(double %a, double %b) {
-;CHECK: f10:
+;CHECK-LABEL: f10:
 ;CHECK: vdiv.f64
 entry:
 	%tmp1 = fdiv double %a, %b		; <double> [#uses=1]
@@ -81,7 +81,7 @@ entry:
 }
 
 define float @f11(float %a) {
-;CHECK: f11:
+;CHECK-LABEL: f11:
 ;CHECK: bic
 entry:
 	%tmp1 = call float @fabsf( float %a ) readnone	; <float> [#uses=1]
@@ -91,7 +91,7 @@ entry:
 declare float @fabsf(float)
 
 define double @f12(double %a) {
-;CHECK: f12:
+;CHECK-LABEL: f12:
 ;CHECK: vabs.f64
 entry:
 	%tmp1 = call double @fabs( double %a ) readnone	; <double> [#uses=1]
diff --git a/test/CodeGen/ARM/fpcmp-opt.ll b/test/CodeGen/ARM/fpcmp-opt.ll
index 2d8f710..902dfa2 100644
--- a/test/CodeGen/ARM/fpcmp-opt.ll
+++ b/test/CodeGen/ARM/fpcmp-opt.ll
@@ -5,7 +5,7 @@
 ; Disable this optimization unless we know one of them is zero.
 define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: vldr [[S0:s[0-9]+]],
 ; CHECK: vldr [[S1:s[0-9]+]],
 ; CHECK: vcmpe.f32 [[S1]], [[S0]]
@@ -29,7 +29,7 @@ bb2:
 ; +0.0 == -0.0
 define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK-NOT: vldr
 ; CHECK: ldr [[REG1:(r[0-9]+)]], [r0]
 ; CHECK: ldr [[REG2:(r[0-9]+)]], [r0, #4]
@@ -55,7 +55,7 @@ bb2:
 
 define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK-NOT: vldr
 ; CHECK: ldr [[REG3:(r[0-9]+)]], [r0]
 ; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648
diff --git a/test/CodeGen/ARM/fpcmp.ll b/test/CodeGen/ARM/fpcmp.ll
index 260ec49..916a1ae 100644
--- a/test/CodeGen/ARM/fpcmp.ll
+++ b/test/CodeGen/ARM/fpcmp.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
 
 define i32 @f1(float %a) {
-;CHECK: f1:
+;CHECK-LABEL: f1:
 ;CHECK: vcmpe.f32
 ;CHECK: movmi
 entry:
@@ -11,7 +11,7 @@ entry:
 }
 
 define i32 @f2(float %a) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
 ;CHECK: vcmpe.f32
 ;CHECK: moveq
 entry:
@@ -21,7 +21,7 @@ entry:
 }
 
 define i32 @f3(float %a) {
-;CHECK: f3:
+;CHECK-LABEL: f3:
 ;CHECK: vcmpe.f32
 ;CHECK: movgt
 entry:
@@ -31,7 +31,7 @@ entry:
 }
 
 define i32 @f4(float %a) {
-;CHECK: f4:
+;CHECK-LABEL: f4:
 ;CHECK: vcmpe.f32
 ;CHECK: movge
 entry:
@@ -41,7 +41,7 @@ entry:
 }
 
 define i32 @f5(float %a) {
-;CHECK: f5:
+;CHECK-LABEL: f5:
 ;CHECK: vcmpe.f32
 ;CHECK: movls
 entry:
@@ -51,7 +51,7 @@ entry:
 }
 
 define i32 @f6(float %a) {
-;CHECK: f6:
+;CHECK-LABEL: f6:
 ;CHECK: vcmpe.f32
 ;CHECK: movne
 entry:
@@ -61,7 +61,7 @@ entry:
 }
 
 define i32 @g1(double %a) {
-;CHECK: g1:
+;CHECK-LABEL: g1:
 ;CHECK: vcmpe.f64
 ;CHECK: movmi
 entry:
diff --git a/test/CodeGen/ARM/fpcmp_ueq.ll b/test/CodeGen/ARM/fpcmp_ueq.ll
index 4a4c5b1..d84c7ae 100644
--- a/test/CodeGen/ARM/fpcmp_ueq.ll
+++ b/test/CodeGen/ARM/fpcmp_ueq.ll
@@ -3,7 +3,7 @@
 
 define i32 @f7(float %a, float %b) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: vcmpe.f32
 ; CHECK: vmrs APSR_nzcv, fpscr
 ; CHECK: movweq
diff --git a/test/CodeGen/ARM/fpconsts.ll b/test/CodeGen/ARM/fpconsts.ll
index 638dde9..0679a47 100644
--- a/test/CodeGen/ARM/fpconsts.ll
+++ b/test/CodeGen/ARM/fpconsts.ll
@@ -2,7 +2,7 @@
 
 define float @t1(float %x) nounwind readnone optsize {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: vmov.f32 s{{.*}}, #4.000000e+00
   %0 = fadd float %x, 4.000000e+00
   ret float %0
@@ -10,7 +10,7 @@ entry:
 
 define double @t2(double %x) nounwind readnone optsize {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: vmov.f64 d{{.*}}, #3.000000e+00
   %0 = fadd double %x, 3.000000e+00
   ret double %0
@@ -18,7 +18,7 @@ entry:
 
 define double @t3(double %x) nounwind readnone optsize {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: vmov.f64 d{{.*}}, #-1.300000e+01
   %0 = fmul double %x, -1.300000e+01
   ret double %0
@@ -26,7 +26,7 @@ entry:
 
 define float @t4(float %x) nounwind readnone optsize {
 entry:
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: vmov.f32 s{{.*}}, #-2.400000e+01
   %0 = fmul float %x, -2.400000e+01
   ret float %0
diff --git a/test/CodeGen/ARM/fpconv.ll b/test/CodeGen/ARM/fpconv.ll
index 1b4c008..326e062 100644
--- a/test/CodeGen/ARM/fpconv.ll
+++ b/test/CodeGen/ARM/fpconv.ll
@@ -2,9 +2,9 @@
 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
 
 define float @f1(double %x) {
-;CHECK-VFP: f1:
+;CHECK-VFP-LABEL: f1:
 ;CHECK-VFP: vcvt.f32.f64
-;CHECK: f1:
+;CHECK-LABEL: f1:
 ;CHECK: truncdfsf2
 entry:
 	%tmp1 = fptrunc double %x to float		; <float> [#uses=1]
@@ -12,9 +12,9 @@ entry:
 }
 
 define double @f2(float %x) {
-;CHECK-VFP: f2:
+;CHECK-VFP-LABEL: f2:
 ;CHECK-VFP: vcvt.f64.f32
-;CHECK: f2:
+;CHECK-LABEL: f2:
 ;CHECK: extendsfdf2
 entry:
 	%tmp1 = fpext float %x to double		; <double> [#uses=1]
@@ -22,9 +22,9 @@ entry:
 }
 
 define i32 @f3(float %x) {
-;CHECK-VFP: f3:
+;CHECK-VFP-LABEL: f3:
 ;CHECK-VFP: vcvt.s32.f32
-;CHECK: f3:
+;CHECK-LABEL: f3:
 ;CHECK: fixsfsi
 entry:
 	%tmp = fptosi float %x to i32		; <i32> [#uses=1]
@@ -32,9 +32,9 @@ entry:
 }
 
 define i32 @f4(float %x) {
-;CHECK-VFP: f4:
+;CHECK-VFP-LABEL: f4:
 ;CHECK-VFP: vcvt.u32.f32
-;CHECK: f4:
+;CHECK-LABEL: f4:
 ;CHECK: fixunssfsi
 entry:
 	%tmp = fptoui float %x to i32		; <i32> [#uses=1]
@@ -42,9 +42,9 @@ entry:
 }
 
 define i32 @f5(double %x) {
-;CHECK-VFP: f5:
+;CHECK-VFP-LABEL: f5:
 ;CHECK-VFP: vcvt.s32.f64
-;CHECK: f5:
+;CHECK-LABEL: f5:
 ;CHECK: fixdfsi
 entry:
 	%tmp = fptosi double %x to i32		; <i32> [#uses=1]
@@ -52,9 +52,9 @@ entry:
 }
 
 define i32 @f6(double %x) {
-;CHECK-VFP: f6:
+;CHECK-VFP-LABEL: f6:
 ;CHECK-VFP: vcvt.u32.f64
-;CHECK: f6:
+;CHECK-LABEL: f6:
 ;CHECK: fixunsdfsi
 entry:
 	%tmp = fptoui double %x to i32		; <i32> [#uses=1]
@@ -62,9 +62,9 @@ entry:
 }
 
 define float @f7(i32 %a) {
-;CHECK-VFP: f7:
+;CHECK-VFP-LABEL: f7:
 ;CHECK-VFP: vcvt.f32.s32
-;CHECK: f7:
+;CHECK-LABEL: f7:
 ;CHECK: floatsisf
 entry:
 	%tmp = sitofp i32 %a to float		; <float> [#uses=1]
@@ -72,9 +72,9 @@ entry:
 }
 
 define double @f8(i32 %a) {
-;CHECK-VFP: f8:
+;CHECK-VFP-LABEL: f8:
 ;CHECK-VFP: vcvt.f64.s32
-;CHECK: f8:
+;CHECK-LABEL: f8:
 ;CHECK: floatsidf
 entry:
 	%tmp = sitofp i32 %a to double		; <double> [#uses=1]
@@ -82,9 +82,9 @@ entry:
 }
 
 define float @f9(i32 %a) {
-;CHECK-VFP: f9:
+;CHECK-VFP-LABEL: f9:
 ;CHECK-VFP: vcvt.f32.u32
-;CHECK: f9:
+;CHECK-LABEL: f9:
 ;CHECK: floatunsisf
 entry:
 	%tmp = uitofp i32 %a to float		; <float> [#uses=1]
@@ -92,9 +92,9 @@ entry:
 }
 
 define double @f10(i32 %a) {
-;CHECK-VFP: f10:
+;CHECK-VFP-LABEL: f10:
 ;CHECK-VFP: vcvt.f64.u32
-;CHECK: f10:
+;CHECK-LABEL: f10:
 ;CHECK: floatunsidf
 entry:
 	%tmp = uitofp i32 %a to double		; <double> [#uses=1]
diff --git a/test/CodeGen/ARM/fpmem.ll b/test/CodeGen/ARM/fpmem.ll
index 8faa578..8fbd1d8 100644
--- a/test/CodeGen/ARM/fpmem.ll
+++ b/test/CodeGen/ARM/fpmem.ll
@@ -1,13 +1,13 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
 
 define float @f1(float %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mov r0, #0
         ret float 0.000000e+00
 }
 
 define float @f2(float* %v, float %u) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: vldr{{.*}}[
         %tmp = load float* %v           ; <float> [#uses=1]
         %tmp1 = fadd float %tmp, %u              ; <float> [#uses=1]
@@ -15,7 +15,7 @@ define float @f2(float* %v, float %u) {
 }
 
 define float @f2offset(float* %v, float %u) {
-; CHECK: f2offset:
+; CHECK-LABEL: f2offset:
 ; CHECK: vldr{{.*}}, #4]
         %addr = getelementptr float* %v, i32 1
         %tmp = load float* %addr
@@ -24,7 +24,7 @@ define float @f2offset(float* %v, float %u) {
 }
 
 define float @f2noffset(float* %v, float %u) {
-; CHECK: f2noffset:
+; CHECK-LABEL: f2noffset:
 ; CHECK: vldr{{.*}}, #-4]
         %addr = getelementptr float* %v, i32 -1
         %tmp = load float* %addr
@@ -33,7 +33,7 @@ define float @f2noffset(float* %v, float %u) {
 }
 
 define void @f3(float %a, float %b, float* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: vstr{{.*}}[
         %tmp = fadd float %a, %b         ; <float> [#uses=1]
         store float %tmp, float* %v
diff --git a/test/CodeGen/ARM/fptoint.ll b/test/CodeGen/ARM/fptoint.ll
index 299cb8f81..7408687 100644
--- a/test/CodeGen/ARM/fptoint.ll
+++ b/test/CodeGen/ARM/fptoint.ll
@@ -44,6 +44,6 @@ define void @foo9(double %x) {
 	store i16 %tmp, i16* null
 	ret void
 }
-; CHECK: foo9:
+; CHECK-LABEL: foo9:
 ; CHECK: 	vmov	r0, s0
 
diff --git a/test/CodeGen/ARM/fusedMAC.ll b/test/CodeGen/ARM/fusedMAC.ll
index 303d165..e29f291 100644
--- a/test/CodeGen/ARM/fusedMAC.ll
+++ b/test/CodeGen/ARM/fusedMAC.ll
@@ -2,7 +2,7 @@
 ; Check generated fused MAC and MLS.
 
 define double @fusedMACTest1(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest1:
+;CHECK-LABEL: fusedMACTest1:
 ;CHECK: vfma.f64
   %1 = fmul double %d1, %d2
   %2 = fadd double %1, %d3
@@ -10,7 +10,7 @@ define double @fusedMACTest1(double %d1, double %d2, double %d3) {
 }
 
 define float @fusedMACTest2(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest2:
+;CHECK-LABEL: fusedMACTest2:
 ;CHECK: vfma.f32
   %1 = fmul float %f1, %f2
   %2 = fadd float %1, %f3
@@ -18,7 +18,7 @@ define float @fusedMACTest2(float %f1, float %f2, float %f3) {
 }
 
 define double @fusedMACTest3(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest3:
+;CHECK-LABEL: fusedMACTest3:
 ;CHECK: vfms.f64
   %1 = fmul double %d2, %d3
   %2 = fsub double %d1, %1
@@ -26,7 +26,7 @@ define double @fusedMACTest3(double %d1, double %d2, double %d3) {
 }
 
 define float @fusedMACTest4(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest4:
+;CHECK-LABEL: fusedMACTest4:
 ;CHECK: vfms.f32
   %1 = fmul float %f2, %f3
   %2 = fsub float %f1, %1
@@ -34,7 +34,7 @@ define float @fusedMACTest4(float %f1, float %f2, float %f3) {
 }
 
 define double @fusedMACTest5(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest5:
+;CHECK-LABEL: fusedMACTest5:
 ;CHECK: vfnma.f64
   %1 = fmul double %d1, %d2
   %2 = fsub double -0.0, %1
@@ -43,7 +43,7 @@ define double @fusedMACTest5(double %d1, double %d2, double %d3) {
 }
 
 define float @fusedMACTest6(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest6:
+;CHECK-LABEL: fusedMACTest6:
 ;CHECK: vfnma.f32
   %1 = fmul float %f1, %f2
   %2 = fsub float -0.0, %1
@@ -52,7 +52,7 @@ define float @fusedMACTest6(float %f1, float %f2, float %f3) {
 }
 
 define double @fusedMACTest7(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest7:
+;CHECK-LABEL: fusedMACTest7:
 ;CHECK: vfnms.f64
   %1 = fmul double %d1, %d2
   %2 = fsub double %1, %d3
@@ -60,7 +60,7 @@ define double @fusedMACTest7(double %d1, double %d2, double %d3) {
 }
 
 define float @fusedMACTest8(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest8:
+;CHECK-LABEL: fusedMACTest8:
 ;CHECK: vfnms.f32
   %1 = fmul float %f1, %f2
   %2 = fsub float %1, %f3
@@ -68,7 +68,7 @@ define float @fusedMACTest8(float %f1, float %f2, float %f3) {
 }
 
 define <2 x float> @fusedMACTest9(<2 x float> %a, <2 x float> %b) {
-;CHECK: fusedMACTest9:
+;CHECK-LABEL: fusedMACTest9:
 ;CHECK: vfma.f32
   %mul = fmul <2 x float> %a, %b
   %add = fadd <2 x float> %mul, %a
@@ -76,7 +76,7 @@ define <2 x float> @fusedMACTest9(<2 x float> %a, <2 x float> %b) {
 }
 
 define <2 x float> @fusedMACTest10(<2 x float> %a, <2 x float> %b) {
-;CHECK: fusedMACTest10:
+;CHECK-LABEL: fusedMACTest10:
 ;CHECK: vfms.f32
   %mul = fmul <2 x float> %a, %b
   %sub = fsub <2 x float> %a, %mul
@@ -84,7 +84,7 @@ define <2 x float> @fusedMACTest10(<2 x float> %a, <2 x float> %b) {
 }
 
 define <4 x float> @fusedMACTest11(<4 x float> %a, <4 x float> %b) {
-;CHECK: fusedMACTest11:
+;CHECK-LABEL: fusedMACTest11:
 ;CHECK: vfma.f32
   %mul = fmul <4 x float> %a, %b
   %add = fadd <4 x float> %mul, %a
@@ -92,7 +92,7 @@ define <4 x float> @fusedMACTest11(<4 x float> %a, <4 x float> %b) {
 }
 
 define <4 x float> @fusedMACTest12(<4 x float> %a, <4 x float> %b) {
-;CHECK: fusedMACTest12:
+;CHECK-LABEL: fusedMACTest12:
 ;CHECK: vfms.f32
   %mul = fmul <4 x float> %a, %b
   %sub = fsub <4 x float> %a, %mul
diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll
index eb71149..3101500 100644
--- a/test/CodeGen/ARM/globals.ll
+++ b/test/CodeGen/ARM/globals.ll
@@ -57,7 +57,7 @@ define i32 @test1() {
 
 
 
-; LinuxPIC: test1:
+; LinuxPIC-LABEL: test1:
 ; LinuxPIC: 	ldr r0, .LCPI0_0
 ; LinuxPIC: 	ldr r1, .LCPI0_1
 	
diff --git a/test/CodeGen/ARM/hidden-vis-2.ll b/test/CodeGen/ARM/hidden-vis-2.ll
index 8bb2c6e..18d38d4 100644
--- a/test/CodeGen/ARM/hidden-vis-2.ll
+++ b/test/CodeGen/ARM/hidden-vis-2.ll
@@ -4,7 +4,7 @@
 
 define i32 @t() nounwind readonly {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: ldr
 ; CHECK-NEXT: ldr
 	%0 = load i32* @x, align 4		; <i32> [#uses=1]
diff --git a/test/CodeGen/ARM/hidden-vis.ll b/test/CodeGen/ARM/hidden-vis.ll
index 3544ae8..ce2ce2c 100644
--- a/test/CodeGen/ARM/hidden-vis.ll
+++ b/test/CodeGen/ARM/hidden-vis.ll
@@ -6,18 +6,18 @@
 
 define weak hidden void @t1() nounwind {
 ; LINUX: .hidden t1
-; LINUX: t1:
+; LINUX-LABEL: t1:
 
 ; DARWIN: .private_extern _t1
-; DARWIN: t1:
+; DARWIN-LABEL: t1:
   ret void
 }
 
 define weak void @t2() nounwind {
-; LINUX: t2:
+; LINUX-LABEL: t2:
 ; LINUX: .hidden a
 
-; DARWIN: t2:
+; DARWIN-LABEL: t2:
 ; DARWIN: .private_extern _a
   ret void
 }
diff --git a/test/CodeGen/ARM/ifcvt1.ll b/test/CodeGen/ARM/ifcvt1.ll
index fd83144..5a55653 100644
--- a/test/CodeGen/ARM/ifcvt1.ll
+++ b/test/CodeGen/ARM/ifcvt1.ll
@@ -2,8 +2,8 @@
 ; RUN: llc < %s -march=arm -mcpu=swift     | FileCheck %s -check-prefix=SWIFT
 
 define i32 @t1(i32 %a, i32 %b) {
-; A8: t1:
-; SWIFT: t1:
+; A8-LABEL: t1:
+; SWIFT-LABEL: t1:
 	%tmp2 = icmp eq i32 %a, 0
 	br i1 %tmp2, label %cond_false, label %cond_true
 
diff --git a/test/CodeGen/ARM/ifcvt10.ll b/test/CodeGen/ARM/ifcvt10.ll
index a5082d8..26c7272 100644
--- a/test/CodeGen/ARM/ifcvt10.ll
+++ b/test/CodeGen/ARM/ifcvt10.ll
@@ -6,7 +6,7 @@
 
 define void @t(double %a, double %b, double %c, double %d, i32* nocapture %solutions, double* nocapture %x) nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: vpop {d8}
 ; CHECK-NOT: vpopne
 ; CHECK: pop {r7, pc}
diff --git a/test/CodeGen/ARM/ifcvt11.ll b/test/CodeGen/ARM/ifcvt11.ll
index 0f142ee..dba8a3f 100644
--- a/test/CodeGen/ARM/ifcvt11.ll
+++ b/test/CodeGen/ARM/ifcvt11.ll
@@ -6,7 +6,7 @@
 %struct.xyz_t = type { double, double, double }
 
 define i32 @effie(i32 %tsets, %struct.xyz_t* nocapture %p, i32 %a, i32 %b, i32 %c) nounwind readonly noinline {
-; CHECK: effie:
+; CHECK-LABEL: effie:
 entry:
   %0 = icmp sgt i32 %tsets, 0
   br i1 %0, label %bb.nph, label %bb6
diff --git a/test/CodeGen/ARM/ifcvt12.ll b/test/CodeGen/ARM/ifcvt12.ll
index 77bdca5..b61f4e1 100644
--- a/test/CodeGen/ARM/ifcvt12.ll
+++ b/test/CodeGen/ARM/ifcvt12.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s
 define i32 @f1(i32 %a, i32 %b, i32 %c) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mlsne r0, r0, r1, r2
     %tmp1 = icmp eq i32 %a, 0
     br i1 %tmp1, label %cond_false, label %cond_true
diff --git a/test/CodeGen/ARM/ifcvt2.ll b/test/CodeGen/ARM/ifcvt2.ll
index 1bca10a..e34edec 100644
--- a/test/CodeGen/ARM/ifcvt2.ll
+++ b/test/CodeGen/ARM/ifcvt2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s
 
 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: bxlt lr
 	%tmp2 = icmp sgt i32 %c, 10
 	%tmp5 = icmp slt i32 %d, 4
@@ -19,7 +19,7 @@ UnifiedReturnBlock:
 }
 
 define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: bxgt lr
 ; CHECK: cmp
 ; CHECK: addge
diff --git a/test/CodeGen/ARM/ifcvt3.ll b/test/CodeGen/ARM/ifcvt3.ll
index eef4de0..fa7d618 100644
--- a/test/CodeGen/ARM/ifcvt3.ll
+++ b/test/CodeGen/ARM/ifcvt3.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 2
 
 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: cmp r2, #1
 ; CHECK: cmpne r2, #7
 	switch i32 %c, label %cond_next [
diff --git a/test/CodeGen/ARM/ifcvt4.ll b/test/CodeGen/ARM/ifcvt4.ll
index d247f14..53c789d 100644
--- a/test/CodeGen/ARM/ifcvt4.ll
+++ b/test/CodeGen/ARM/ifcvt4.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 
 ; Do not if-convert when branches go to the different loops.
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK-NOT: subgt
 ; CHECK-NOT: suble
 ; Don't use
diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll
index 5081791..31e3e00 100644
--- a/test/CodeGen/ARM/ifcvt5.ll
+++ b/test/CodeGen/ARM/ifcvt5.ll
@@ -12,10 +12,10 @@ entry:
 }
 
 define i32 @t1(i32 %a, i32 %b) {
-; A8: t1:
+; A8-LABEL: t1:
 ; A8: poplt {r7, pc}
 
-; SWIFT: t1:
+; SWIFT-LABEL: t1:
 ; SWIFT: pop {r7, pc}
 ; SWIFT: pop {r7, pc}
 entry:
diff --git a/test/CodeGen/ARM/indirectbr-2.ll b/test/CodeGen/ARM/indirectbr-2.ll
index 084f520..0c41da6 100644
--- a/test/CodeGen/ARM/indirectbr-2.ll
+++ b/test/CodeGen/ARM/indirectbr-2.ll
@@ -8,7 +8,7 @@
 ; The indirect branch has the two destinations as successors. The lone PHI
 ; statement shouldn't be implicitly defined.
 
-; CHECK:      func:
+; CHECK-LABEL:      func:
 ; CHECK:      Ltmp1:    @ Block address taken
 ; CHECK-NOT:            @ implicit-def: R0
 ; CHECK:                @ 4-byte Reload
diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll
index 341c33f..6fed8c4 100644
--- a/test/CodeGen/ARM/indirectbr.ll
+++ b/test/CodeGen/ARM/indirectbr.ll
@@ -6,9 +6,9 @@
 @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
 
 define internal i32 @foo(i32 %i) nounwind {
-; ARM: foo:
-; THUMB: foo:
-; THUMB2: foo:
+; ARM-LABEL: foo:
+; THUMB-LABEL: foo:
+; THUMB2-LABEL: foo:
 entry:
   %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2]
   %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1]
diff --git a/test/CodeGen/ARM/inlineasm-64bit.ll b/test/CodeGen/ARM/inlineasm-64bit.ll
index ade0154..b23db10 100644
--- a/test/CodeGen/ARM/inlineasm-64bit.ll
+++ b/test/CodeGen/ARM/inlineasm-64bit.ll
@@ -2,7 +2,7 @@
 ; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s
 ; check if regs are passing correctly
 define void @i64_write(i64* %p, i64 %val) nounwind {
-; CHECK: i64_write:
+; CHECK-LABEL: i64_write:
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
 ; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
   %1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A teq $0, #0\0A bne 1b", "=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %val) nounwind
@@ -12,7 +12,7 @@ define void @i64_write(i64* %p, i64 %val) nounwind {
 ; check if register allocation can reuse the registers
 define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind {
 entry:
-; CHECK: multi_writes:
+; CHECK-LABEL: multi_writes:
 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
@@ -44,7 +44,7 @@ entry:
 
 ; check if callee-saved registers used by inline asm are saved/restored
 define void @foo(i64* %p, i64 %i) nounwind {
-; CHECK:foo:
+; CHECK-LABEL:foo:
 ; CHECK: {{push|push.w}} {{{r[4-9]|r10|r11}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
 ; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
@@ -55,20 +55,20 @@ define void @foo(i64* %p, i64 %i) nounwind {
 
 ; return *p;
 define i64 @ldrd_test(i64* %p) nounwind {
-; CHECK: ldrd_test:
+; CHECK-LABEL: ldrd_test:
   %1 = tail call i64 asm "ldrd $0, ${0:H}, [$1]", "=r,r"(i64* %p) nounwind
   ret i64 %1
 }
 
 define i64 @QR_test(i64* %p) nounwind {
-; CHECK: QR_test:
+; CHECK-LABEL: QR_test:
 ; CHECK: ldrd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
   %1 = tail call i64 asm "ldrd ${0:Q}, ${0:R}, [$1]", "=r,r"(i64* %p) nounwind
   ret i64 %1
 }
 
 define i64 @defuse_test(i64 %p) nounwind {
-; CHECK: defuse_test:
+; CHECK-LABEL: defuse_test:
 ; CHECK: add {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, #1
   %1 = tail call i64 asm "add $0, ${0:H}, #1", "=r,0"(i64 %p) nounwind
   ret i64 %1
@@ -76,7 +76,7 @@ define i64 @defuse_test(i64 %p) nounwind {
 
 ; *p = (hi << 32) | lo;
 define void @strd_test(i64* %p, i32 %lo, i32 %hi) nounwind {
-; CHECK: strd_test:
+; CHECK-LABEL: strd_test:
 ; CHECK: strd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
   %1 = zext i32 %hi to i64
   %2 = shl nuw i64 %1, 32
diff --git a/test/CodeGen/ARM/inlineasm4.ll b/test/CodeGen/ARM/inlineasm4.ll
index 9ed4b99..4a1bcca 100644
--- a/test/CodeGen/ARM/inlineasm4.ll
+++ b/test/CodeGen/ARM/inlineasm4.ll
@@ -4,7 +4,7 @@ define double @f(double %x) {
 entry:
   %0 = tail call double asm "mov     ${0:R}, #4\0A", "=&r"()
   ret double %0
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK:	mov     r1, #4
 }
 
@@ -12,6 +12,6 @@ define double @g(double %x) {
 entry:
   %0 = tail call double asm "mov     ${0:Q}, #4\0A", "=&r"()
   ret double %0
-; CHECK: g:
+; CHECK-LABEL: g:
 ; CHECK:	mov     r0, #4
 }
diff --git a/test/CodeGen/ARM/ldm.ll b/test/CodeGen/ARM/ldm.ll
index db78fd0..d5b805c 100644
--- a/test/CodeGen/ARM/ldm.ll
+++ b/test/CodeGen/ARM/ldm.ll
@@ -4,9 +4,9 @@
 @X = external global [0 x i32]          ; <[0 x i32]*> [#uses=5]
 
 define i32 @t1() {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: pop
-; V4T: t1:
+; V4T-LABEL: t1:
 ; V4T: pop
         %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0)            ; <i32> [#uses=1]
         %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1)           ; <i32> [#uses=1]
@@ -15,9 +15,9 @@ define i32 @t1() {
 }
 
 define i32 @t2() {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: pop
-; V4T: t2:
+; V4T-LABEL: t2:
 ; V4T: pop
         %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2)            ; <i32> [#uses=1]
         %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]
@@ -27,10 +27,10 @@ define i32 @t2() {
 }
 
 define i32 @t3() {
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: ldmib
 ; CHECK: pop
-; V4T: t3:
+; V4T-LABEL: t3:
 ; V4T: ldmib
 ; V4T: pop
 ; V4T-NEXT: bx lr
diff --git a/test/CodeGen/ARM/ldr.ll b/test/CodeGen/ARM/ldr.ll
index 011e61c..e4c695b 100644
--- a/test/CodeGen/ARM/ldr.ll
+++ b/test/CodeGen/ARM/ldr.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 
 define i32 @f1(i32* %v) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldr r0
 entry:
         %tmp = load i32* %v
@@ -9,7 +9,7 @@ entry:
 }
 
 define i32 @f2(i32* %v) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldr r0
 entry:
         %tmp2 = getelementptr i32* %v, i32 1023
@@ -18,7 +18,7 @@ entry:
 }
 
 define i32 @f3(i32* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov
 ; CHECK: ldr r0
 entry:
@@ -28,7 +28,7 @@ entry:
 }
 
 define i32 @f4(i32 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: mvn
 ; CHECK: ldr r0
 entry:
@@ -39,7 +39,7 @@ entry:
 }
 
 define i32 @f5(i32 %base, i32 %offset) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldr r0
 entry:
         %tmp1 = add i32 %base, %offset
@@ -49,7 +49,7 @@ entry:
 }
 
 define i32 @f6(i32 %base, i32 %offset) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ldr r0{{.*}}lsl{{.*}}
 entry:
         %tmp1 = shl i32 %offset, 2
@@ -60,7 +60,7 @@ entry:
 }
 
 define i32 @f7(i32 %base, i32 %offset) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ldr r0{{.*}}lsr{{.*}}
 entry:
         %tmp1 = lshr i32 %offset, 2
diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll
index 4abf6e6..864d18a 100644
--- a/test/CodeGen/ARM/ldrd.ll
+++ b/test/CodeGen/ARM/ldrd.ll
@@ -13,10 +13,10 @@
 
 define i64 @t(i64 %a) nounwind readonly {
 entry:
-; A8: t:
+; A8-LABEL: t:
 ; A8:   ldrd r2, r3, [r2]
 
-; M3: t:
+; M3-LABEL: t:
 ; M3-NOT: ldrd
 
 	%0 = load i64** @b, align 4
diff --git a/test/CodeGen/ARM/ldst-f32-2-i32.ll b/test/CodeGen/ARM/ldst-f32-2-i32.ll
index 1c69e15..61c459c 100644
--- a/test/CodeGen/ARM/ldst-f32-2-i32.ll
+++ b/test/CodeGen/ARM/ldst-f32-2-i32.ll
@@ -3,7 +3,7 @@
 ; rdar://8944252
 
 define void @t(i32 %width, float* nocapture %src, float* nocapture %dst, i32 %index) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 entry:
   %src6 = bitcast float* %src to i8*
   %0 = icmp eq i32 %width, 0
diff --git a/test/CodeGen/ARM/ldstrexd.ll b/test/CodeGen/ARM/ldstrexd.ll
index 0c0911a..bb60e1e 100644
--- a/test/CodeGen/ARM/ldstrexd.ll
+++ b/test/CodeGen/ARM/ldstrexd.ll
@@ -3,7 +3,7 @@
 
 %0 = type { i32, i32 }
 
-; CHECK: f0:
+; CHECK-LABEL: f0:
 ; CHECK: ldrexd
 define i64 @f0(i8* %p) nounwind readonly {
 entry:
@@ -17,7 +17,7 @@ entry:
   ret i64 %4
 }
 
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: strexd
 define i32 @f1(i8* %ptr, i64 %val) nounwind {
 entry:
diff --git a/test/CodeGen/ARM/load-address-masked.ll b/test/CodeGen/ARM/load-address-masked.ll
index 43c98e4..65cc311 100644
--- a/test/CodeGen/ARM/load-address-masked.ll
+++ b/test/CodeGen/ARM/load-address-masked.ll
@@ -10,5 +10,5 @@ entry:
   ret i32 and (i32 ptrtoint (i32* @a to i32), i32 255)
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: ldrb    r0, .LCPI0_0
diff --git a/test/CodeGen/ARM/load_i1_select.ll b/test/CodeGen/ARM/load_i1_select.ll
index bdd4081..7a208ea 100644
--- a/test/CodeGen/ARM/load_i1_select.ll
+++ b/test/CodeGen/ARM/load_i1_select.ll
@@ -6,7 +6,7 @@ target triple = "thumbv7-apple-ios0.0.0"
 ; Codegen should only compare one bit of the loaded value.
 ; rdar://10887484
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: ldrb r[[R0:[0-9]+]], [r0]
 ; CHECK: tst.w r[[R0]], #1
 define void @foo(i8* %call, double* %p) nounwind {
diff --git a/test/CodeGen/ARM/long.ll b/test/CodeGen/ARM/long.ll
index 0f1c7be..7fffc81 100644
--- a/test/CodeGen/ARM/long.ll
+++ b/test/CodeGen/ARM/long.ll
@@ -1,33 +1,33 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 entry:
         ret i64 0
 }
 
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 entry:
         ret i64 1
 }
 
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvn r0, #-2147483648
 entry:
         ret i64 2147483647
 }
 
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mov r0, #-2147483648
 entry:
         ret i64 2147483648
 }
 
 define i64 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvn r0, #0
 ; CHECK: mvn r1, #-2147483648
 entry:
@@ -35,7 +35,7 @@ entry:
 }
 
 define i64 @f6(i64 %x, i64 %y) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: adds
 ; CHECK: adc
 entry:
@@ -44,7 +44,7 @@ entry:
 }
 
 define void @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 entry:
         %tmp = call i64 @f8( )          ; <i64> [#uses=0]
         ret void
@@ -53,7 +53,7 @@ entry:
 declare i64 @f8()
 
 define i64 @f9(i64 %a, i64 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: subs r
 ; CHECK: sbc
 entry:
@@ -62,7 +62,7 @@ entry:
 }
 
 define i64 @f(i32 %a, i32 %b) {
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: smull
 entry:
         %tmp = sext i32 %a to i64               ; <i64> [#uses=1]
@@ -72,7 +72,7 @@ entry:
 }
 
 define i64 @g(i32 %a, i32 %b) {
-; CHECK: g:
+; CHECK-LABEL: g:
 ; CHECK: umull
 entry:
         %tmp = zext i32 %a to i64               ; <i64> [#uses=1]
@@ -82,7 +82,7 @@ entry:
 }
 
 define i64 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 entry:
         %a = alloca i64, align 8                ; <i64*> [#uses=1]
         %retval = load i64* %a          ; <i64> [#uses=1]
diff --git a/test/CodeGen/ARM/longMAC.ll b/test/CodeGen/ARM/longMAC.ll
index e4a00e9..2cf91c3 100644
--- a/test/CodeGen/ARM/longMAC.ll
+++ b/test/CodeGen/ARM/longMAC.ll
@@ -2,7 +2,7 @@
 ; Check generated signed and unsigned multiply accumulate long.
 
 define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
-;CHECK: MACLongTest1:
+;CHECK-LABEL: MACLongTest1:
 ;CHECK: umlal
   %conv = zext i32 %a to i64
   %conv1 = zext i32 %b to i64
@@ -12,7 +12,7 @@ define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
 }
 
 define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c)  {
-;CHECK: MACLongTest2:
+;CHECK-LABEL: MACLongTest2:
 ;CHECK: smlal
   %conv = sext i32 %a to i64
   %conv1 = sext i32 %b to i64
@@ -22,7 +22,7 @@ define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c)  {
 }
 
 define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {
-;CHECK: MACLongTest3:
+;CHECK-LABEL: MACLongTest3:
 ;CHECK: umlal
   %conv = zext i32 %b to i64
   %conv1 = zext i32 %a to i64
@@ -33,7 +33,7 @@ define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {
 }
 
 define i64 @MACLongTest4(i32 %a, i32 %b, i32 %c) {
-;CHECK: MACLongTest4:
+;CHECK-LABEL: MACLongTest4:
 ;CHECK: smlal
   %conv = sext i32 %b to i64
   %conv1 = sext i32 %a to i64
diff --git a/test/CodeGen/ARM/lsr-icmp-imm.ll b/test/CodeGen/ARM/lsr-icmp-imm.ll
index 248c4bd..103642b 100644
--- a/test/CodeGen/ARM/lsr-icmp-imm.ll
+++ b/test/CodeGen/ARM/lsr-icmp-imm.ll
@@ -4,7 +4,7 @@
 ; LSR should compare against the post-incremented induction variable.
 ; In this case, the immediate value is -2 which requires a cmn instruction.
 ;
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: %for.body
 ; CHECK: sub{{.*}}[[IV:r[0-9]+]], #2
 ; CHECK: cmn{{.*}}[[IV]], #2
diff --git a/test/CodeGen/ARM/machine-cse-cmp.ll b/test/CodeGen/ARM/machine-cse-cmp.ll
index 03abd76..7e4b309 100644
--- a/test/CodeGen/ARM/machine-cse-cmp.ll
+++ b/test/CodeGen/ARM/machine-cse-cmp.ll
@@ -6,7 +6,7 @@
 
 define i32 @f1(i32 %cond1, i32 %x1, i32 %x2, i32 %x3) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cmp
 ; CHECK: moveq
 ; CHECK-NOT: cmp
@@ -25,7 +25,7 @@ entry:
 ; rdar://10660865
 define void @f2() nounwind ssp {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cmp
 ; CHECK: poplt
 ; CHECK-NOT: cmp
@@ -49,7 +49,7 @@ declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
 ; rdar://12462006
 define i8* @f3(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: sub
 ; CHECK: cmp
 ; CHECK: blt
diff --git a/test/CodeGen/ARM/machine-licm.ll b/test/CodeGen/ARM/machine-licm.ll
index 8656c5b..87aaacf 100644
--- a/test/CodeGen/ARM/machine-licm.ll
+++ b/test/CodeGen/ARM/machine-licm.ll
@@ -12,7 +12,7 @@
 
 define void @t(i32* nocapture %vals, i32 %c) nounwind {
 entry:
-; ARM: t:
+; ARM-LABEL: t:
 ; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0
 ; Unfortunately currently ARM codegen doesn't cse the ldr from constantpool.
 ; The issue is it can be read by an "add pc" or a "ldr [pc]" so it's messy
@@ -23,14 +23,14 @@ entry:
 ; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]]
 ; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
 
-; MOVT: t:
+; MOVT-LABEL: t:
 ; MOVT: movw [[REGISTER_2:r[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+8))
 ; MOVT: movt [[REGISTER_2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+8))
 ; MOVT: LPC0_0:
 ; MOVT: ldr r{{[0-9]+}}, [pc, [[REGISTER_2]]]
 ; MOVT: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
 
-; THUMB: t:
+; THUMB-LABEL: t:
   %0 = icmp eq i32 %c, 0                          ; <i1> [#uses=1]
   br i1 %0, label %return, label %bb.nph
 
diff --git a/test/CodeGen/ARM/memcpy-inline.ll b/test/CodeGen/ARM/memcpy-inline.ll
index d846e5c..946c63e 100644
--- a/test/CodeGen/ARM/memcpy-inline.ll
+++ b/test/CodeGen/ARM/memcpy-inline.ll
@@ -15,7 +15,7 @@
 
 define i32 @t0() {
 entry:
-; CHECK: t0:
+; CHECK-LABEL: t0:
 ; CHECK: vldr [[REG1:d[0-9]+]],
 ; CHECK: vstr [[REG1]], 
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false)
@@ -24,7 +24,7 @@ entry:
 
 define void @t1(i8* nocapture %C) nounwind {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
 ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
 ; CHECK: adds r0, #15
@@ -37,7 +37,7 @@ entry:
 
 define void @t2(i8* nocapture %C) nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: ldr [[REG2:r[0-9]+]], [r1, #32]
 ; CHECK: str [[REG2]], [r0, #32]
 ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
@@ -52,7 +52,7 @@ entry:
 
 define void @t3(i8* nocapture %C) nounwind {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
 ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
 ; CHECK: adds r0, #16
@@ -65,7 +65,7 @@ entry:
 
 define void @t4(i8* nocapture %C) nounwind {
 entry:
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: vld1.8 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1]
 ; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
@@ -74,7 +74,7 @@ entry:
 
 define void @t5(i8* nocapture %C) nounwind {
 entry:
-; CHECK: t5:
+; CHECK-LABEL: t5:
 ; CHECK: movs [[REG5:r[0-9]+]], #0
 ; CHECK: strb [[REG5]], [r0, #6]
 ; CHECK: movw [[REG6:r[0-9]+]], #21587
@@ -87,7 +87,7 @@ entry:
 
 define void @t6() nounwind {
 entry:
-; CHECK: t6:
+; CHECK-LABEL: t6:
 ; CHECK: vld1.8 {[[REG8:d[0-9]+]]}, [r0]
 ; CHECK: vstr [[REG8]], [r1]
 ; CHECK: adds r1, #6
diff --git a/test/CodeGen/ARM/memset-inline.ll b/test/CodeGen/ARM/memset-inline.ll
index ee8c364..4e86d05 100644
--- a/test/CodeGen/ARM/memset-inline.ll
+++ b/test/CodeGen/ARM/memset-inline.ll
@@ -2,7 +2,7 @@
 
 define void @t1(i8* nocapture %c) nounwind optsize {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: movs r1, #0
 ; CHECK: str r1, [r0]
 ; CHECK: str r1, [r0, #4]
@@ -13,7 +13,7 @@ entry:
 
 define void @t2() nounwind ssp {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: add.w r1, r0, #10
 ; CHECK: vmov.i32 {{q[0-9]+}}, #0x0
 ; CHECK: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
diff --git a/test/CodeGen/ARM/mls.ll b/test/CodeGen/ARM/mls.ll
index 066bf98..8f0d3a8 100644
--- a/test/CodeGen/ARM/mls.ll
+++ b/test/CodeGen/ARM/mls.ll
@@ -14,15 +14,15 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) {
     ret i32 %tmp2
 }
 
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mls	r0, r0, r1, r2
-; NO_MULOPS: f1:
+; NO_MULOPS-LABEL: f1:
 ; NO_MULOPS: mul r0, r0, r1
 ; NO_MULOPS-NEXT: sub r0, r2, r0
 
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mul r0, r0, r1
 ; CHECK-NEXT: sub r0, r0, r2
-; NO_MULOPS: f2:
+; NO_MULOPS-LABEL: f2:
 ; NO_MULOPS: mul r0, r0, r1
 ; NO_MULOPS-NEXT: sub r0, r0, r2
diff --git a/test/CodeGen/ARM/movt.ll b/test/CodeGen/ARM/movt.ll
index e82aca0..25c1bfe 100644
--- a/test/CodeGen/ARM/movt.ll
+++ b/test/CodeGen/ARM/movt.ll
@@ -2,7 +2,7 @@
 ; rdar://7317664
 
 define i32 @t(i32 %X) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movt r0, #65535
 entry:
 	%0 = or i32 %X, -65536
@@ -10,7 +10,7 @@ entry:
 }
 
 define i32 @t2(i32 %X) nounwind {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: movt r0, #65534
 entry:
 	%0 = or i32 %X, -131072
diff --git a/test/CodeGen/ARM/mul_const.ll b/test/CodeGen/ARM/mul_const.ll
index c50a233..482d8f2 100644
--- a/test/CodeGen/ARM/mul_const.ll
+++ b/test/CodeGen/ARM/mul_const.ll
@@ -2,7 +2,7 @@
 
 define i32 @t9(i32 %v) nounwind readnone {
 entry:
-; CHECK: t9:
+; CHECK-LABEL: t9:
 ; CHECK: add r0, r0, r0, lsl #3
 	%0 = mul i32 %v, 9
 	ret i32 %0
@@ -10,7 +10,7 @@ entry:
 
 define i32 @t7(i32 %v) nounwind readnone {
 entry:
-; CHECK: t7:
+; CHECK-LABEL: t7:
 ; CHECK: rsb r0, r0, r0, lsl #3
 	%0 = mul i32 %v, 7
 	ret i32 %0
@@ -18,7 +18,7 @@ entry:
 
 define i32 @t5(i32 %v) nounwind readnone {
 entry:
-; CHECK: t5:
+; CHECK-LABEL: t5:
 ; CHECK: add r0, r0, r0, lsl #2
         %0 = mul i32 %v, 5
         ret i32 %0
@@ -26,7 +26,7 @@ entry:
 
 define i32 @t3(i32 %v) nounwind readnone {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: add r0, r0, r0, lsl #1
         %0 = mul i32 %v, 3
         ret i32 %0
@@ -34,7 +34,7 @@ entry:
 
 define i32 @t12288(i32 %v) nounwind readnone {
 entry:
-; CHECK: t12288:
+; CHECK-LABEL: t12288:
 ; CHECK: add r0, r0, r0, lsl #1
 ; CHECK: lsl{{.*}}#12
         %0 = mul i32 %v, 12288
@@ -43,7 +43,7 @@ entry:
 
 define i32 @tn9(i32 %v) nounwind readnone {
 entry:
-; CHECK: tn9:
+; CHECK-LABEL: tn9:
 ; CHECK: add	r0, r0, r0, lsl #3
 ; CHECK: rsb	r0, r0, #0
         %0 = mul i32 %v, -9
@@ -52,7 +52,7 @@ entry:
 
 define i32 @tn7(i32 %v) nounwind readnone {
 entry:
-; CHECK: tn7:
+; CHECK-LABEL: tn7:
 ; CHECK: sub r0, r0, r0, lsl #3
 	%0 = mul i32 %v, -7
 	ret i32 %0
@@ -60,7 +60,7 @@ entry:
 
 define i32 @tn5(i32 %v) nounwind readnone {
 entry:
-; CHECK: tn5:
+; CHECK-LABEL: tn5:
 ; CHECK: add r0, r0, r0, lsl #2
 ; CHECK: rsb r0, r0, #0
         %0 = mul i32 %v, -5
@@ -69,7 +69,7 @@ entry:
 
 define i32 @tn3(i32 %v) nounwind readnone {
 entry:
-; CHECK: tn3:
+; CHECK-LABEL: tn3:
 ; CHECK: sub r0, r0, r0, lsl #2
         %0 = mul i32 %v, -3
         ret i32 %0
@@ -77,7 +77,7 @@ entry:
 
 define i32 @tn12288(i32 %v) nounwind readnone {
 entry:
-; CHECK: tn12288:
+; CHECK-LABEL: tn12288:
 ; CHECK: sub r0, r0, r0, lsl #2
 ; CHECK: lsl{{.*}}#12
         %0 = mul i32 %v, -12288
diff --git a/test/CodeGen/ARM/mulhi.ll b/test/CodeGen/ARM/mulhi.ll
index 932004c..63705c5 100644
--- a/test/CodeGen/ARM/mulhi.ll
+++ b/test/CodeGen/ARM/mulhi.ll
@@ -3,13 +3,13 @@
 ; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=M3
 
 define i32 @smulhi(i32 %x, i32 %y) nounwind {
-; V6: smulhi:
+; V6-LABEL: smulhi:
 ; V6: smmul
 
-; V4: smulhi:
+; V4-LABEL: smulhi:
 ; V4: smull
 
-; M3: smulhi:
+; M3-LABEL: smulhi:
 ; M3: smull
         %tmp = sext i32 %x to i64               ; <i64> [#uses=1]
         %tmp1 = sext i32 %y to i64              ; <i64> [#uses=1]
@@ -20,13 +20,13 @@ define i32 @smulhi(i32 %x, i32 %y) nounwind {
 }
 
 define i32 @umulhi(i32 %x, i32 %y) nounwind {
-; V6: umulhi:
+; V6-LABEL: umulhi:
 ; V6: umull
 
-; V4: umulhi:
+; V4-LABEL: umulhi:
 ; V4: umull
 
-; M3: umulhi:
+; M3-LABEL: umulhi:
 ; M3: umull
         %tmp = zext i32 %x to i64               ; <i64> [#uses=1]
         %tmp1 = zext i32 %y to i64              ; <i64> [#uses=1]
@@ -38,13 +38,13 @@ define i32 @umulhi(i32 %x, i32 %y) nounwind {
 
 ; rdar://r10152911
 define i32 @t3(i32 %a) nounwind {
-; V6: t3:
+; V6-LABEL: t3:
 ; V6: smmla
 
-; V4: t3:
+; V4-LABEL: t3:
 ; V4: smull
 
-; M3: t3:
+; M3-LABEL: t3:
 ; M3-NOT: smmla
 ; M3: smull
 entry:
diff --git a/test/CodeGen/ARM/neon-spfp.ll b/test/CodeGen/ARM/neon-spfp.ll
index c00f0d1..5385668 100644
--- a/test/CodeGen/ARM/neon-spfp.ll
+++ b/test/CodeGen/ARM/neon-spfp.ll
@@ -21,21 +21,21 @@
 
 @.str = private unnamed_addr constant [12 x i8] c"S317\09%.5g \0A\00", align 1
 
-; CHECK-LINUXA5: main:
-; CHECK-LINUXA8: main:
-; CHECK-LINUXA9: main:
-; CHECK-LINUXA15: main:
-; CHECK-LINUXSWIFT: main:
-; CHECK-UNSAFEA5: main:
-; CHECK-UNSAFEA8: main:
-; CHECK-UNSAFEA9: main:
-; CHECK-UNSAFEA15: main:
-; CHECK-UNSAFESWIFT: main:
-; CHECK-DARWINA5: main:
-; CHECK-DARWINA8: main:
-; CHECK-DARWINA9: main:
-; CHECK-DARWINA15: main:
-; CHECK-DARWINSWIFT: main:
+; CHECK-LINUXA5-LABEL: main:
+; CHECK-LINUXA8-LABEL: main:
+; CHECK-LINUXA9-LABEL: main:
+; CHECK-LINUXA15-LABEL: main:
+; CHECK-LINUXSWIFT-LABEL: main:
+; CHECK-UNSAFEA5-LABEL: main:
+; CHECK-UNSAFEA8-LABEL: main:
+; CHECK-UNSAFEA9-LABEL: main:
+; CHECK-UNSAFEA15-LABEL: main:
+; CHECK-UNSAFESWIFT-LABEL: main:
+; CHECK-DARWINA5-LABEL: main:
+; CHECK-DARWINA8-LABEL: main:
+; CHECK-DARWINA9-LABEL: main:
+; CHECK-DARWINA15-LABEL: main:
+; CHECK-DARWINSWIFT-LABEL: main:
 define i32 @main() {
 entry:
   br label %for.body
diff --git a/test/CodeGen/ARM/neon_minmax.ll b/test/CodeGen/ARM/neon_minmax.ll
index 0a7c8b2..2e45919 100644
--- a/test/CodeGen/ARM/neon_minmax.ll
+++ b/test/CodeGen/ARM/neon_minmax.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
 
 define float @fmin_ole(float %x) nounwind {
-;CHECK: fmin_ole:
+;CHECK-LABEL: fmin_ole:
 ;CHECK: vmin.f32
   %cond = fcmp ole float 1.0, %x
   %min1 = select i1 %cond, float 1.0, float %x
@@ -9,7 +9,7 @@ define float @fmin_ole(float %x) nounwind {
 }
 
 define float @fmin_ole_zero(float %x) nounwind {
-;CHECK: fmin_ole_zero:
+;CHECK-LABEL: fmin_ole_zero:
 ;CHECK-NOT: vmin.f32
   %cond = fcmp ole float 0.0, %x
   %min1 = select i1 %cond, float 0.0, float %x
@@ -17,7 +17,7 @@ define float @fmin_ole_zero(float %x) nounwind {
 }
 
 define float @fmin_ult(float %x) nounwind {
-;CHECK: fmin_ult:
+;CHECK-LABEL: fmin_ult:
 ;CHECK: vmin.f32
   %cond = fcmp ult float %x, 1.0
   %min1 = select i1 %cond, float %x, float 1.0
@@ -25,7 +25,7 @@ define float @fmin_ult(float %x) nounwind {
 }
 
 define float @fmax_ogt(float %x) nounwind {
-;CHECK: fmax_ogt:
+;CHECK-LABEL: fmax_ogt:
 ;CHECK: vmax.f32
   %cond = fcmp ogt float 1.0, %x
   %max1 = select i1 %cond, float 1.0, float %x
@@ -33,7 +33,7 @@ define float @fmax_ogt(float %x) nounwind {
 }
 
 define float @fmax_uge(float %x) nounwind {
-;CHECK: fmax_uge:
+;CHECK-LABEL: fmax_uge:
 ;CHECK: vmax.f32
   %cond = fcmp uge float %x, 1.0
   %max1 = select i1 %cond, float %x, float 1.0
@@ -41,7 +41,7 @@ define float @fmax_uge(float %x) nounwind {
 }
 
 define float @fmax_uge_zero(float %x) nounwind {
-;CHECK: fmax_uge_zero:
+;CHECK-LABEL: fmax_uge_zero:
 ;CHECK-NOT: vmax.f32
   %cond = fcmp uge float %x, 0.0
   %max1 = select i1 %cond, float %x, float 0.0
@@ -49,7 +49,7 @@ define float @fmax_uge_zero(float %x) nounwind {
 }
 
 define float @fmax_olt_reverse(float %x) nounwind {
-;CHECK: fmax_olt_reverse:
+;CHECK-LABEL: fmax_olt_reverse:
 ;CHECK: vmax.f32
   %cond = fcmp olt float %x, 1.0
   %max1 = select i1 %cond, float 1.0, float %x
@@ -57,7 +57,7 @@ define float @fmax_olt_reverse(float %x) nounwind {
 }
 
 define float @fmax_ule_reverse(float %x) nounwind {
-;CHECK: fmax_ule_reverse:
+;CHECK-LABEL: fmax_ule_reverse:
 ;CHECK: vmax.f32
   %cond = fcmp ult float 1.0, %x
   %max1 = select i1 %cond, float %x, float 1.0
@@ -65,7 +65,7 @@ define float @fmax_ule_reverse(float %x) nounwind {
 }
 
 define float @fmin_oge_reverse(float %x) nounwind {
-;CHECK: fmin_oge_reverse:
+;CHECK-LABEL: fmin_oge_reverse:
 ;CHECK: vmin.f32
   %cond = fcmp oge float %x, 1.0
   %min1 = select i1 %cond, float 1.0, float %x
@@ -73,7 +73,7 @@ define float @fmin_oge_reverse(float %x) nounwind {
 }
 
 define float @fmin_ugt_reverse(float %x) nounwind {
-;CHECK: fmin_ugt_reverse:
+;CHECK-LABEL: fmin_ugt_reverse:
 ;CHECK: vmin.f32
   %cond = fcmp ugt float 1.0, %x
   %min1 = select i1 %cond, float %x, float 1.0
diff --git a/test/CodeGen/ARM/peephole-bitcast.ll b/test/CodeGen/ARM/peephole-bitcast.ll
index e72d51f..3c6a187 100644
--- a/test/CodeGen/ARM/peephole-bitcast.ll
+++ b/test/CodeGen/ARM/peephole-bitcast.ll
@@ -10,7 +10,7 @@
 
 define void @t(float %x) nounwind ssp {
 entry:
-; CHECK:     t:
+; CHECK-LABEL:     t:
 ; CHECK-NOT: vmov
 ; CHECK:     bl
   %0 = bitcast float %x to i32
diff --git a/test/CodeGen/ARM/popcnt.ll b/test/CodeGen/ARM/popcnt.ll
index 0b9c946..bdf793d 100644
--- a/test/CodeGen/ARM/popcnt.ll
+++ b/test/CodeGen/ARM/popcnt.ll
@@ -2,7 +2,7 @@
 ; Implement ctpop with vcnt
 
 define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
-;CHECK: vcnt8:
+;CHECK-LABEL: vcnt8:
 ;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
@@ -10,7 +10,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
 }
 
 define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
-;CHECK: vcntQ8:
+;CHECK-LABEL: vcntQ8:
 ;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
@@ -18,7 +18,7 @@ define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vcnt16(<4 x i16>* %A) nounwind {
-; CHECK: vcnt16:
+; CHECK-LABEL: vcnt16:
 ; CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
 ; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
 ; CHECK: vadd.i8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@@ -30,7 +30,7 @@ define <4 x i16> @vcnt16(<4 x i16>* %A) nounwind {
 }
 
 define <8 x i16> @vcntQ16(<8 x i16>* %A) nounwind {
-; CHECK: vcntQ16:
+; CHECK-LABEL: vcntQ16:
 ; CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
 ; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
 ; CHECK: vadd.i8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
@@ -42,7 +42,7 @@ define <8 x i16> @vcntQ16(<8 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vcnt32(<2 x i32>* %A) nounwind {
-; CHECK: vcnt32:
+; CHECK-LABEL: vcnt32:
 ; CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
 ; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
 ; CHECK: vadd.i8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@@ -57,7 +57,7 @@ define <2 x i32> @vcnt32(<2 x i32>* %A) nounwind {
 }
 
 define <4 x i32> @vcntQ32(<4 x i32>* %A) nounwind {
-; CHECK: vcntQ32:
+; CHECK-LABEL: vcntQ32:
 ; CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
 ; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
 ; CHECK: vadd.i8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
@@ -79,7 +79,7 @@ declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone
 declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
 
 define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
-;CHECK: vclz8:
+;CHECK-LABEL: vclz8:
 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
@@ -87,7 +87,7 @@ define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
-;CHECK: vclz16:
+;CHECK-LABEL: vclz16:
 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
@@ -95,7 +95,7 @@ define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
-;CHECK: vclz32:
+;CHECK-LABEL: vclz32:
 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
@@ -103,7 +103,7 @@ define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
 }
 
 define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
-;CHECK: vclzQ8:
+;CHECK-LABEL: vclzQ8:
 ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
@@ -111,7 +111,7 @@ define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
-;CHECK: vclzQ16:
+;CHECK-LABEL: vclzQ16:
 ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
@@ -119,7 +119,7 @@ define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
-;CHECK: vclzQ32:
+;CHECK-LABEL: vclzQ32:
 ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
@@ -135,7 +135,7 @@ declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
 
 define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
-;CHECK: vclss8:
+;CHECK-LABEL: vclss8:
 ;CHECK: vcls.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
@@ -143,7 +143,7 @@ define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
-;CHECK: vclss16:
+;CHECK-LABEL: vclss16:
 ;CHECK: vcls.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
@@ -151,7 +151,7 @@ define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
-;CHECK: vclss32:
+;CHECK-LABEL: vclss32:
 ;CHECK: vcls.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
@@ -159,7 +159,7 @@ define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
 }
 
 define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vclsQs8:
+;CHECK-LABEL: vclsQs8:
 ;CHECK: vcls.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
@@ -167,7 +167,7 @@ define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vclsQs16:
+;CHECK-LABEL: vclsQs16:
 ;CHECK: vcls.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
@@ -175,7 +175,7 @@ define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vclsQs32:
+;CHECK-LABEL: vclsQs32:
 ;CHECK: vcls.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
diff --git a/test/CodeGen/ARM/prefetch.ll b/test/CodeGen/ARM/prefetch.ll
index 9c8ff2b..5badb31 100644
--- a/test/CodeGen/ARM/prefetch.ll
+++ b/test/CodeGen/ARM/prefetch.ll
@@ -6,15 +6,15 @@
 
 define void @t1(i8* %ptr) nounwind  {
 entry:
-; ARM: t1:
+; ARM-LABEL: t1:
 ; ARM-NOT: pldw [r0]
 ; ARM: pld [r0]
 
-; ARM-MP: t1:
+; ARM-MP-LABEL: t1:
 ; ARM-MP: pldw [r0]
 ; ARM-MP: pld [r0]
 
-; THUMB2: t1:
+; THUMB2-LABEL: t1:
 ; THUMB2-NOT: pldw [r0]
 ; THUMB2: pld [r0]
   tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
@@ -24,10 +24,10 @@ entry:
 
 define void @t2(i8* %ptr) nounwind  {
 entry:
-; ARM: t2:
+; ARM-LABEL: t2:
 ; ARM: pld [r0, #1023]
 
-; THUMB2: t2:
+; THUMB2-LABEL: t2:
 ; THUMB2: pld [r0, #1023]
   %tmp = getelementptr i8* %ptr, i32 1023
   tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3, i32 1 )
@@ -36,10 +36,10 @@ entry:
 
 define void @t3(i32 %base, i32 %offset) nounwind  {
 entry:
-; ARM: t3:
+; ARM-LABEL: t3:
 ; ARM: pld [r0, r1, lsr #2]
 
-; THUMB2: t3:
+; THUMB2-LABEL: t3:
 ; THUMB2: lsrs r1, r1, #2
 ; THUMB2: pld [r0, r1]
   %tmp1 = lshr i32 %offset, 2
@@ -51,10 +51,10 @@ entry:
 
 define void @t4(i32 %base, i32 %offset) nounwind  {
 entry:
-; ARM: t4:
+; ARM-LABEL: t4:
 ; ARM: pld [r0, r1, lsl #2]
 
-; THUMB2: t4:
+; THUMB2-LABEL: t4:
 ; THUMB2: pld [r0, r1, lsl #2]
   %tmp1 = shl i32 %offset, 2
   %tmp2 = add i32 %base, %tmp1
@@ -67,10 +67,10 @@ declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
 
 define void @t5(i8* %ptr) nounwind  {
 entry:
-; ARM: t5:
+; ARM-LABEL: t5:
 ; ARM: pli [r0]
 
-; THUMB2: t5:
+; THUMB2-LABEL: t5:
 ; THUMB2: pli [r0]
   tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 0 )
   ret void
diff --git a/test/CodeGen/ARM/private.ll b/test/CodeGen/ARM/private.ll
index 94578d8..e48c292 100644
--- a/test/CodeGen/ARM/private.ll
+++ b/test/CodeGen/ARM/private.ll
@@ -2,7 +2,7 @@
 ;
 ; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
 ; CHECK: .Lfoo:
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: bl .Lfoo
 ; CHECK: .long .Lbaz
 ; CHECK: .Lbaz:
diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll
index fd2083c..3fe2bb8 100644
--- a/test/CodeGen/ARM/reg_sequence.ll
+++ b/test/CodeGen/ARM/reg_sequence.ll
@@ -11,7 +11,7 @@
 
 define void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind {
 entry:
-; CHECK:        t1:
+; CHECK-LABEL:        t1:
 ; CHECK:        vld1.16
 ; CHECK-NOT:    vmov d
 ; CHECK:        vmovl.s16
@@ -44,7 +44,7 @@ entry:
 
 define void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind {
 entry:
-; CHECK:        t2:
+; CHECK-LABEL:        t2:
 ; CHECK:        vld1.16
 ; CHECK-NOT:    vmov
 ; CHECK:        vmul.i16
@@ -73,7 +73,7 @@ entry:
 }
 
 define <8 x i8> @t3(i8* %A, i8* %B) nounwind {
-; CHECK:        t3:
+; CHECK-LABEL:        t3:
 ; CHECK:        vld3.8
 ; CHECK:        vmul.i8
 ; CHECK:        vmov r
@@ -92,7 +92,7 @@ define <8 x i8> @t3(i8* %A, i8* %B) nounwind {
 
 define void @t4(i32* %in, i32* %out) nounwind {
 entry:
-; CHECK:        t4:
+; CHECK-LABEL:        t4:
 ; CHECK:        vld2.32
 ; CHECK-NOT:    vmov
 ; CHECK:        vld2.32
@@ -135,7 +135,7 @@ return2:
 }
 
 define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind {
-; CHECK:        t5:
+; CHECK-LABEL:        t5:
 ; CHECK:        vld1.32
 ; How can FileCheck match Q and D registers? We need a lisp interpreter.
 ; CHECK:        vorr {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
@@ -153,7 +153,7 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind {
-; CHECK:        t6:
+; CHECK-LABEL:        t6:
 ; CHECK:        vldr
 ; CHECK:        vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]]
 ; CHECK-NEXT:   vld2.8 {d[[D1]][1], d[[D0]][1]}
@@ -167,7 +167,7 @@ define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind {
 
 define void @t7(i32* %iptr, i32* %optr) nounwind {
 entry:
-; CHECK:        t7:
+; CHECK-LABEL:        t7:
 ; CHECK:        vld2.32
 ; CHECK:        vst2.32
 ; CHECK:        vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}},
@@ -189,7 +189,7 @@ entry:
 
 ; PR7156
 define arm_aapcs_vfpcc i32 @t8() nounwind {
-; CHECK: t8:
+; CHECK-LABEL: t8:
 ; CHECK: vrsqrte.f32 q8, q8
 bb.nph55.bb.nph55.split_crit_edge:
   br label %bb3
@@ -238,7 +238,7 @@ bb14:                                             ; preds = %bb6
 
 ; PR7157
 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
-; CHECK:        t9:
+; CHECK-LABEL:        t9:
 ; CHECK:        vldr
 ; CHECK-NOT:    vmov d{{.*}}, d16
 ; CHECK:        vmov.i32 d17
@@ -270,7 +270,7 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
 ; PR7162
 define arm_aapcs_vfpcc i32 @t10() nounwind {
 entry:
-; CHECK: t10:
+; CHECK-LABEL: t10:
 ; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3f000000
 ; CHECK: vmul.f32 q8, q8, d[[DREG:[0-1]+]]
 ; CHECK: vadd.f32 q8, q8, q8
diff --git a/test/CodeGen/ARM/ret_sret_vector.ll b/test/CodeGen/ARM/ret_sret_vector.ll
index 9bb3519..f9c4626 100644
--- a/test/CodeGen/ARM/ret_sret_vector.ll
+++ b/test/CodeGen/ARM/ret_sret_vector.ll
@@ -6,7 +6,7 @@ target triple = "thumbv7-apple-ios3.0.0"
 define <4 x double> @PR14337(<4 x double> %a, <4 x double> %b) {
   %foo = fadd <4 x double>  %a, %b
   ret <4 x double> %foo
-; CHECK: PR14337:
+; CHECK-LABEL: PR14337:
 ; CHECK: vst1.64
 ; CHECK: vst1.64
 }
diff --git a/test/CodeGen/ARM/sbfx.ll b/test/CodeGen/ARM/sbfx.ll
index d29693e..36fbd19 100644
--- a/test/CodeGen/ARM/sbfx.ll
+++ b/test/CodeGen/ARM/sbfx.ll
@@ -2,7 +2,7 @@
 
 define i32 @f1(i32 %a) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sbfx r0, r0, #0, #20
     %tmp = shl i32 %a, 12
     %tmp2 = ashr i32 %tmp, 12
@@ -11,7 +11,7 @@ entry:
 
 define i32 @f2(i32 %a) {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: bfc	r0, #20, #12
     %tmp = shl i32 %a, 12
     %tmp2 = lshr i32 %tmp, 12
@@ -20,7 +20,7 @@ entry:
 
 define i32 @f3(i32 %a) {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sbfx r0, r0, #5, #3
     %tmp = shl i32 %a, 24
     %tmp2 = ashr i32 %tmp, 29
@@ -29,7 +29,7 @@ entry:
 
 define i32 @f4(i32 %a) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ubfx r0, r0, #5, #3
     %tmp = shl i32 %a, 24
     %tmp2 = lshr i32 %tmp, 29
@@ -38,7 +38,7 @@ entry:
 
 define i32 @f5(i32 %a) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: sbfx
 ; CHECK: bx
     %tmp = shl i32 %a, 3
diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll
index c9ac66a..765437a 100644
--- a/test/CodeGen/ARM/select-imm.ll
+++ b/test/CodeGen/ARM/select-imm.ll
@@ -4,16 +4,16 @@
 
 define i32 @t1(i32 %c) nounwind readnone {
 entry:
-; ARM: t1:
+; ARM-LABEL: t1:
 ; ARM: mov [[R1:r[0-9]+]], #101
 ; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256
 ; ARM: movgt r0, #123
 
-; ARMT2: t1:
+; ARMT2-LABEL: t1:
 ; ARMT2: movw r0, #357
 ; ARMT2: movgt r0, #123
 
-; THUMB2: t1:
+; THUMB2-LABEL: t1:
 ; THUMB2: movw r0, #357
 ; THUMB2: movgt r0, #123
 
@@ -24,16 +24,16 @@ entry:
 
 define i32 @t2(i32 %c) nounwind readnone {
 entry:
-; ARM: t2:
+; ARM-LABEL: t2:
 ; ARM: mov r0, #123
 ; ARM: movgt r0, #101
 ; ARM: orrgt r0, r0, #256
 
-; ARMT2: t2:
+; ARMT2-LABEL: t2:
 ; ARMT2: mov r0, #123
 ; ARMT2: movwgt r0, #357
 
-; THUMB2: t2:
+; THUMB2-LABEL: t2:
 ; THUMB2: mov{{(s|\.w)}} r0, #123
 ; THUMB2: movwgt r0, #357
 
@@ -44,15 +44,15 @@ entry:
 
 define i32 @t3(i32 %a) nounwind readnone {
 entry:
-; ARM: t3:
+; ARM-LABEL: t3:
 ; ARM: mov r0, #0
 ; ARM: moveq r0, #1
 
-; ARMT2: t3:
+; ARMT2-LABEL: t3:
 ; ARMT2: mov r0, #0
 ; ARMT2: moveq r0, #1
 
-; THUMB2: t3:
+; THUMB2-LABEL: t3:
 ; THUMB2: mov{{(s|\.w)}} r0, #0
 ; THUMB2: moveq r0, #1
   %0 = icmp eq i32 %a, 160
@@ -62,15 +62,15 @@ entry:
 
 define i32 @t4(i32 %a, i32 %b, i32 %x) nounwind {
 entry:
-; ARM: t4:
+; ARM-LABEL: t4:
 ; ARM: ldr
 ; ARM: mov{{lt|ge}}
 
-; ARMT2: t4:
+; ARMT2-LABEL: t4:
 ; ARMT2: movwlt [[R0:r[0-9]+]], #65365
 ; ARMT2: movtlt [[R0]], #65365
 
-; THUMB2: t4:
+; THUMB2-LABEL: t4:
 ; THUMB2: mvnlt [[R0:r[0-9]+]], #11141290
   %0 = icmp slt i32 %a, %b
   %1 = select i1 %0, i32 4283826005, i32 %x
@@ -80,13 +80,13 @@ entry:
 ; rdar://9758317
 define i32 @t5(i32 %a) nounwind {
 entry:
-; ARM: t5:
+; ARM-LABEL: t5:
 ; ARM-NOT: mov
 ; ARM: cmp r0, #1
 ; ARM-NOT: mov
 ; ARM: movne r0, #0
 
-; THUMB2: t5:
+; THUMB2-LABEL: t5:
 ; THUMB2-NOT: mov
 ; THUMB2: cmp r0, #1
 ; THUMB2: it ne
@@ -98,12 +98,12 @@ entry:
 
 define i32 @t6(i32 %a) nounwind {
 entry:
-; ARM: t6:
+; ARM-LABEL: t6:
 ; ARM-NOT: mov
 ; ARM: cmp r0, #0
 ; ARM: movne r0, #1
 
-; THUMB2: t6:
+; THUMB2-LABEL: t6:
 ; THUMB2-NOT: mov
 ; THUMB2: cmp r0, #0
 ; THUMB2: it ne
diff --git a/test/CodeGen/ARM/select.ll b/test/CodeGen/ARM/select.ll
index 62708ed..d5c3a27 100644
--- a/test/CodeGen/ARM/select.ll
+++ b/test/CodeGen/ARM/select.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mattr=+neon,+thumb2 -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=CHECK-NEON
 
 define i32 @f1(i32 %a.s) {
-;CHECK: f1:
+;CHECK-LABEL: f1:
 ;CHECK: moveq
 entry:
     %tmp = icmp eq i32 %a.s, 4
@@ -12,7 +12,7 @@ entry:
 }
 
 define i32 @f2(i32 %a.s) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
 ;CHECK: movgt
 entry:
     %tmp = icmp sgt i32 %a.s, 4
@@ -21,7 +21,7 @@ entry:
 }
 
 define i32 @f3(i32 %a.s, i32 %b.s) {
-;CHECK: f3:
+;CHECK-LABEL: f3:
 ;CHECK: movlt
 entry:
     %tmp = icmp slt i32 %a.s, %b.s
@@ -30,7 +30,7 @@ entry:
 }
 
 define i32 @f4(i32 %a.s, i32 %b.s) {
-;CHECK: f4:
+;CHECK-LABEL: f4:
 ;CHECK: movle
 entry:
     %tmp = icmp sle i32 %a.s, %b.s
@@ -39,7 +39,7 @@ entry:
 }
 
 define i32 @f5(i32 %a.u, i32 %b.u) {
-;CHECK: f5:
+;CHECK-LABEL: f5:
 ;CHECK: movls
 entry:
     %tmp = icmp ule i32 %a.u, %b.u
@@ -48,7 +48,7 @@ entry:
 }
 
 define i32 @f6(i32 %a.u, i32 %b.u) {
-;CHECK: f6:
+;CHECK-LABEL: f6:
 ;CHECK: movhi
 entry:
     %tmp = icmp ugt i32 %a.u, %b.u
@@ -57,10 +57,10 @@ entry:
 }
 
 define double @f7(double %a, double %b) {
-;CHECK: f7:
+;CHECK-LABEL: f7:
 ;CHECK: movlt
 ;CHECK: movlt
-;CHECK-VFP: f7:
+;CHECK-VFP-LABEL: f7:
 ;CHECK-VFP: vmovmi
     %tmp = fcmp olt double %a, 1.234e+00
     %tmp1 = select i1 %tmp, double -1.000e+00, double %b
@@ -94,7 +94,7 @@ define arm_apcscc float @f8(i32 %a) nounwind {
 ; Glue values can only have a single use, but the following test exposed a
 ; case where a SELECT was lowered with 2 uses of a comparison, causing the
 ; scheduler to assert.
-; CHECK-VFP: f9:
+; CHECK-VFP-LABEL: f9:
 
 declare i8* @objc_msgSend(i8*, i8*, ...)
 define void @f9() optsize {
diff --git a/test/CodeGen/ARM/select_xform.ll b/test/CodeGen/ARM/select_xform.ll
index 7507808..e13504a 100644
--- a/test/CodeGen/ARM/select_xform.ll
+++ b/test/CodeGen/ARM/select_xform.ll
@@ -3,11 +3,11 @@
 ; rdar://8662825
 
 define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
-; ARM: t1:
+; ARM-LABEL: t1:
 ; ARM: suble r1, r1, #-2147483647
 ; ARM: mov r0, r1
 
-; T2: t1:
+; T2-LABEL: t1:
 ; T2: mvn r0, #-2147483648
 ; T2: addle r1, r0
 ; T2: mov r0, r1
@@ -18,11 +18,11 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
 }
 
 define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; ARM: t2:
+; ARM-LABEL: t2:
 ; ARM: suble r1, r1, #10
 ; ARM: mov r0, r1
 
-; T2: t2:
+; T2-LABEL: t2:
 ; T2: suble r1, #10
 ; T2: mov r0, r1
   %tmp1 = icmp sgt i32 %c, 10
@@ -32,11 +32,11 @@ define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
 }
 
 define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
-; ARM: t3:
+; ARM-LABEL: t3:
 ; ARM: andge r3, r3, r2
 ; ARM: mov r0, r3
 
-; T2: t3:
+; T2-LABEL: t3:
 ; T2: andge r3, r2
 ; T2: mov r0, r3
   %cond = icmp slt i32 %a, %b
@@ -46,11 +46,11 @@ define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
 }
 
 define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
-; ARM: t4:
+; ARM-LABEL: t4:
 ; ARM: orrge r3, r3, r2
 ; ARM: mov r0, r3
 
-; T2: t4:
+; T2-LABEL: t4:
 ; T2: orrge r3, r2
 ; T2: mov r0, r3
   %cond = icmp slt i32 %a, %b
@@ -61,11 +61,11 @@ define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
 
 define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind {
 entry:
-; ARM: t5:
+; ARM-LABEL: t5:
 ; ARM-NOT: moveq
 ; ARM: orreq r2, r2, #1
 
-; T2: t5:
+; T2-LABEL: t5:
 ; T2-NOT: moveq
 ; T2: orreq r2, r2, #1
   %tmp1 = icmp eq i32 %a, %b
@@ -75,11 +75,11 @@ entry:
 }
 
 define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; ARM: t6:
+; ARM-LABEL: t6:
 ; ARM-NOT: movge
 ; ARM: eorlt r3, r3, r2
 
-; T2: t6:
+; T2-LABEL: t6:
 ; T2-NOT: movge
 ; T2: eorlt r3, r2
   %cond = icmp slt i32 %a, %b
@@ -90,11 +90,11 @@ define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
 
 define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind {
 entry:
-; ARM: t7:
+; ARM-LABEL: t7:
 ; ARM-NOT: lsleq
 ; ARM: andeq r2, r2, r2, lsl #1
 
-; T2: t7:
+; T2-LABEL: t7:
 ; T2-NOT: lsleq.w
 ; T2: andeq.w r2, r2, r2, lsl #1
   %tmp1 = shl i32 %c, 1
@@ -106,11 +106,11 @@ entry:
 
 ; Fold ORRri into movcc.
 define i32 @t8(i32 %a, i32 %b) nounwind {
-; ARM: t8:
+; ARM-LABEL: t8:
 ; ARM: cmp r0, r1
 ; ARM: orrge r0, r1, #1
 
-; T2: t8:
+; T2-LABEL: t8:
 ; T2: cmp r0, r1
 ; T2: orrge r0, r1, #1
   %x = or i32 %b, 1
@@ -121,11 +121,11 @@ define i32 @t8(i32 %a, i32 %b) nounwind {
 
 ; Fold ANDrr into movcc.
 define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind {
-; ARM: t9:
+; ARM-LABEL: t9:
 ; ARM: cmp r0, r1
 ; ARM: andge r0, r1, r2
 
-; T2: t9:
+; T2-LABEL: t9:
 ; T2: cmp r0, r1
 ; T2: andge.w r0, r1, r2
   %x = and i32 %b, %c
@@ -136,11 +136,11 @@ define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind {
 
 ; Fold EORrs into movcc.
 define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; ARM: t10:
+; ARM-LABEL: t10:
 ; ARM: cmp r0, r1
 ; ARM: eorge r0, r1, r2, lsl #7
 
-; T2: t10:
+; T2-LABEL: t10:
 ; T2: cmp r0, r1
 ; T2: eorge.w r0, r1, r2, lsl #7
   %s = shl i32 %c, 7
@@ -152,11 +152,11 @@ define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
 
 ; Fold ORRri into movcc, reversing the condition.
 define i32 @t11(i32 %a, i32 %b) nounwind {
-; ARM: t11:
+; ARM-LABEL: t11:
 ; ARM: cmp r0, r1
 ; ARM: orrlt r0, r1, #1
 
-; T2: t11:
+; T2-LABEL: t11:
 ; T2: cmp r0, r1
 ; T2: orrlt r0, r1, #1
   %x = or i32 %b, 1
@@ -167,11 +167,11 @@ define i32 @t11(i32 %a, i32 %b) nounwind {
 
 ; Fold ADDri12 into movcc
 define i32 @t12(i32 %a, i32 %b) nounwind {
-; ARM: t12:
+; ARM-LABEL: t12:
 ; ARM: cmp r0, r1
 ; ARM: addge r0, r1,
 
-; T2: t12:
+; T2-LABEL: t12:
 ; T2: cmp r0, r1
 ; T2: addwge r0, r1, #3000
   %x = add i32 %b, 3000
diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll
index e93cdbc..b924663 100644
--- a/test/CodeGen/ARM/spill-q.ll
+++ b/test/CodeGen/ARM/spill-q.ll
@@ -10,7 +10,7 @@
 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
 
 define void @aaa(%quuz* %this, i8* %block) {
-; CHECK: aaa:
+; CHECK-LABEL: aaa:
 ; CHECK: bic {{.*}}, #15
 ; CHECK: vst1.64 {{.*}}sp:128
 ; CHECK: vld1.64 {{.*}}sp:128
diff --git a/test/CodeGen/ARM/struct_byval.ll b/test/CodeGen/ARM/struct_byval.ll
index e9541c2..012b994 100644
--- a/test/CodeGen/ARM/struct_byval.ll
+++ b/test/CodeGen/ARM/struct_byval.ll
@@ -6,7 +6,7 @@
 
 define i32 @f() nounwind ssp {
 entry:
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: ldr
 ; CHECK: str
 ; CHECK-NOT:bne
@@ -18,7 +18,7 @@ entry:
 ; Generate a loop for large struct byval
 define i32 @g() nounwind ssp {
 entry:
-; CHECK: g:
+; CHECK-LABEL: g:
 ; CHECK: ldr
 ; CHECK: sub
 ; CHECK: str
@@ -31,7 +31,7 @@ entry:
 ; Generate a loop using NEON instructions
 define i32 @h() nounwind ssp {
 entry:
-; CHECK: h:
+; CHECK-LABEL: h:
 ; CHECK: vld1
 ; CHECK: sub
 ; CHECK: vst1
diff --git a/test/CodeGen/ARM/sub-cmp-peephole.ll b/test/CodeGen/ARM/sub-cmp-peephole.ll
index 2961b94..1b411e3 100644
--- a/test/CodeGen/ARM/sub-cmp-peephole.ll
+++ b/test/CodeGen/ARM/sub-cmp-peephole.ll
@@ -2,7 +2,7 @@
 
 define i32 @f(i32 %a, i32 %b) nounwind ssp {
 entry:
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: subs
 ; CHECK-NOT: cmp
   %cmp = icmp sgt i32 %a, %b
@@ -13,7 +13,7 @@ entry:
 
 define i32 @g(i32 %a, i32 %b) nounwind ssp {
 entry:
-; CHECK: g:
+; CHECK-LABEL: g:
 ; CHECK: subs
 ; CHECK-NOT: cmp
   %cmp = icmp slt i32 %a, %b
@@ -24,7 +24,7 @@ entry:
 
 define i32 @h(i32 %a, i32 %b) nounwind ssp {
 entry:
-; CHECK: h:
+; CHECK-LABEL: h:
 ; CHECK: subs
 ; CHECK-NOT: cmp
   %cmp = icmp sgt i32 %a, 3
@@ -36,7 +36,7 @@ entry:
 ; rdar://11725965
 define i32 @i(i32 %a, i32 %b) nounwind readnone ssp {
 entry:
-; CHECK: i:
+; CHECK-LABEL: i:
 ; CHECK: subs
 ; CHECK-NOT: cmp
   %cmp = icmp ult i32 %a, %b
@@ -48,7 +48,7 @@ entry:
 ; a swapped sub.
 define i32 @j(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: j:
+; CHECK-LABEL: j:
 ; CHECK: sub
 ; CHECK: cmp
   %cmp = icmp eq i32 %b, %a
diff --git a/test/CodeGen/ARM/tail-dup.ll b/test/CodeGen/ARM/tail-dup.ll
index eb4d0ba..d654056 100644
--- a/test/CodeGen/ARM/tail-dup.ll
+++ b/test/CodeGen/ARM/tail-dup.ll
@@ -2,7 +2,7 @@
 
 ; We should be able to tail-duplicate the basic block containing the indirectbr
 ; into all of its predecessors.
-; CHECK: fn:
+; CHECK-LABEL: fn:
 ; CHECK: mov pc
 ; CHECK: mov pc
 ; CHECK: mov pc
diff --git a/test/CodeGen/ARM/tail-opts.ll b/test/CodeGen/ARM/tail-opts.ll
index 220b0f1..37e9a4a 100644
--- a/test/CodeGen/ARM/tail-opts.ll
+++ b/test/CodeGen/ARM/tail-opts.ll
@@ -14,7 +14,7 @@ declare i8* @choose(i8*, i8*)
 ; BranchFolding should tail-duplicate the indirect jump to avoid
 ; redundant branching.
 
-; CHECK: tail_duplicate_me:
+; CHECK-LABEL: tail_duplicate_me:
 ; CHECK:      qux
 ; CHECK:      movw r{{[0-9]+}}, :lower16:_GHJK
 ; CHECK:      movt r{{[0-9]+}}, :upper16:_GHJK
diff --git a/test/CodeGen/ARM/test-sharedidx.ll b/test/CodeGen/ARM/test-sharedidx.ll
index 93340c3..9203f16 100644
--- a/test/CodeGen/ARM/test-sharedidx.ll
+++ b/test/CodeGen/ARM/test-sharedidx.ll
@@ -14,7 +14,7 @@
 ; rdar://10674430
 define void @sharedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c, i32 %s, i32 %len) nounwind ssp {
 entry:
-; CHECK: sharedidx:
+; CHECK-LABEL: sharedidx:
   %cmp8 = icmp eq i32 %len, 0
   br i1 %cmp8, label %for.end, label %for.body
 
diff --git a/test/CodeGen/ARM/tls-models.ll b/test/CodeGen/ARM/tls-models.ll
index a5f3c90..ccc9032 100644
--- a/test/CodeGen/ARM/tls-models.ll
+++ b/test/CodeGen/ARM/tls-models.ll
@@ -21,9 +21,9 @@ entry:
   ret i32* @external_gd
 
   ; Non-PIC code can use initial-exec, PIC code has to use general dynamic.
-  ; CHECK-NONPIC:   f1:
+  ; CHECK-NONPIC-LABEL:   f1:
   ; CHECK-NONPIC:   external_gd(gottpoff)
-  ; CHECK-PIC:      f1:
+  ; CHECK-PIC-LABEL:      f1:
   ; CHECK-PIC:      external_gd(tlsgd)
 }
 
@@ -33,9 +33,9 @@ entry:
 
   ; Non-PIC code can use local exec, PIC code can use local dynamic,
   ; but that is not implemented, so falls back to general dynamic.
-  ; CHECK-NONPIC:   f2:
+  ; CHECK-NONPIC-LABEL:   f2:
   ; CHECK-NONPIC:   internal_gd(tpoff)
-  ; CHECK-PIC:      f2:
+  ; CHECK-PIC-LABEL:      f2:
   ; CHECK-PIC:      internal_gd(tlsgd)
 }
 
@@ -48,9 +48,9 @@ entry:
 
   ; Non-PIC code can use initial exec, PIC should use local dynamic,
   ; but that is not implemented, so falls back to general dynamic.
-  ; CHECK-NONPIC:   f3:
+  ; CHECK-NONPIC-LABEL:   f3:
   ; CHECK-NONPIC:   external_ld(gottpoff)
-  ; CHECK-PIC:      f3:
+  ; CHECK-PIC-LABEL:      f3:
   ; CHECK-PIC:      external_ld(tlsgd)
 }
 
@@ -60,9 +60,9 @@ entry:
 
   ; Non-PIC code can use local exec, PIC code can use local dynamic,
   ; but that is not implemented, so it falls back to general dynamic.
-  ; CHECK-NONPIC:   f4:
+  ; CHECK-NONPIC-LABEL:   f4:
   ; CHECK-NONPIC:   internal_ld(tpoff)
-  ; CHECK-PIC:      f4:
+  ; CHECK-PIC-LABEL:      f4:
   ; CHECK-PIC:      internal_ld(tlsgd)
 }
 
@@ -74,9 +74,9 @@ entry:
   ret i32* @external_ie
 
   ; Non-PIC and PIC code will use initial exec as specified.
-  ; CHECK-NONPIC:   f5:
+  ; CHECK-NONPIC-LABEL:   f5:
   ; CHECK-NONPIC:   external_ie(gottpoff)
-  ; CHECK-PIC:      f5:
+  ; CHECK-PIC-LABEL:      f5:
   ; CHECK-PIC:      external_ie(gottpoff)
 }
 
@@ -85,9 +85,9 @@ entry:
   ret i32* @internal_ie
 
   ; Non-PIC code can use local exec, PIC code use initial exec as specified.
-  ; CHECK-NONPIC:   f6:
+  ; CHECK-NONPIC-LABEL:   f6:
   ; CHECK-NONPIC:   internal_ie(tpoff)
-  ; CHECK-PIC:      f6:
+  ; CHECK-PIC-LABEL:      f6:
   ; CHECK-PIC:      internal_ie(gottpoff)
 }
 
@@ -99,9 +99,9 @@ entry:
   ret i32* @external_le
 
   ; Non-PIC and PIC code will use local exec as specified.
-  ; CHECK-NONPIC:   f7:
+  ; CHECK-NONPIC-LABEL:   f7:
   ; CHECK-NONPIC:   external_le(tpoff)
-  ; CHECK-PIC:      f7:
+  ; CHECK-PIC-LABEL:      f7:
   ; CHECK-PIC:      external_le(tpoff)
 }
 
@@ -110,8 +110,8 @@ entry:
   ret i32* @internal_le
 
   ; Non-PIC and PIC code will use local exec as specified.
-  ; CHECK-NONPIC:   f8:
+  ; CHECK-NONPIC-LABEL:   f8:
   ; CHECK-NONPIC:   internal_le(tpoff)
-  ; CHECK-PIC:      f8:
+  ; CHECK-PIC-LABEL:      f8:
   ; CHECK-PIC:      internal_le(tpoff)
 }
diff --git a/test/CodeGen/ARM/tls2.ll b/test/CodeGen/ARM/tls2.ll
index 57370c4..f048125 100644
--- a/test/CodeGen/ARM/tls2.ll
+++ b/test/CodeGen/ARM/tls2.ll
@@ -6,10 +6,10 @@
 @i = external thread_local global i32		; <i32*> [#uses=2]
 
 define i32 @f() {
-; CHECK-NONPIC: f:
+; CHECK-NONPIC-LABEL: f:
 ; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}]
 ; CHECK-NONPIC: i(gottpoff)
-; CHECK-PIC: f:
+; CHECK-PIC-LABEL: f:
 ; CHECK-PIC: __tls_get_addr
 entry:
 	%tmp1 = load i32* @i		; <i32> [#uses=1]
@@ -17,10 +17,10 @@ entry:
 }
 
 define i32* @g() {
-; CHECK-NONPIC: g:
+; CHECK-NONPIC-LABEL: g:
 ; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}]
 ; CHECK-NONPIC: i(gottpoff)
-; CHECK-PIC: g:
+; CHECK-PIC-LABEL: g:
 ; CHECK-PIC: __tls_get_addr
 entry:
 	ret i32* @i
diff --git a/test/CodeGen/ARM/trap.ll b/test/CodeGen/ARM/trap.ll
index a4e3c3c..db88a03 100644
--- a/test/CodeGen/ARM/trap.ll
+++ b/test/CodeGen/ARM/trap.ll
@@ -23,10 +23,10 @@
 
 define void @t() nounwind {
 entry:
-; INSTR: t:
+; INSTR-LABEL: t:
 ; INSTR: trap
 
-; FUNC: t:
+; FUNC-LABEL: t:
 ; FUNC: bl __trap
 
 ; ENCODING-NACL: f0 de fe e7
@@ -39,10 +39,10 @@ entry:
 
 define void @t2() nounwind {
 entry:
-; INSTR: t2:
+; INSTR-LABEL: t2:
 ; INSTR: trap
 
-; FUNC: t2:
+; FUNC-LABEL: t2:
 ; FUNC: bl __trap
 
 ; ENCODING-NACL: f0 de fe e7
diff --git a/test/CodeGen/ARM/twoaddrinstr.ll b/test/CodeGen/ARM/twoaddrinstr.ll
index fc2aa1e..2172f6b 100644
--- a/test/CodeGen/ARM/twoaddrinstr.ll
+++ b/test/CodeGen/ARM/twoaddrinstr.ll
@@ -3,7 +3,7 @@
 
 define void @PR13378() nounwind {
 ; This was orriginally a crasher trying to schedule the instructions.
-; CHECK:      PR13378:
+; CHECK-LABEL:      PR13378:
 ; CHECK:        vld1.32
 ; CHECK-NEXT:   vst1.32
 ; CHECK-NEXT:   vst1.32
diff --git a/test/CodeGen/ARM/unaligned_load_store.ll b/test/CodeGen/ARM/unaligned_load_store.ll
index 3064202..e7ff63f 100644
--- a/test/CodeGen/ARM/unaligned_load_store.ll
+++ b/test/CodeGen/ARM/unaligned_load_store.ll
@@ -7,7 +7,7 @@
 
 define void @t(i8* nocapture %a, i8* nocapture %b) nounwind {
 entry:
-; EXPANDED: t:
+; EXPANDED-LABEL: t:
 ; EXPANDED: ldrb [[R2:r[0-9]+]]
 ; EXPANDED: ldrb [[R3:r[0-9]+]]
 ; EXPANDED: ldrb [[R12:r[0-9]+]]
@@ -17,7 +17,7 @@ entry:
 ; EXPANDED: strb [[R3]]
 ; EXPANDED: strb [[R2]]
 
-; UNALIGNED: t:
+; UNALIGNED-LABEL: t:
 ; UNALIGNED: ldr r1
 ; UNALIGNED: str r1
 
@@ -30,13 +30,13 @@ entry:
 
 define void @hword(double* %a, double* %b) nounwind {
 entry:
-; EXPANDED: hword:
+; EXPANDED-LABEL: hword:
 ; EXPANDED-NOT: vld1
 ; EXPANDED: ldrh
 ; EXPANDED-NOT: str1
 ; EXPANDED: strh
 
-; UNALIGNED: hword:
+; UNALIGNED-LABEL: hword:
 ; UNALIGNED: vld1.16
 ; UNALIGNED: vst1.16
   %tmp = load double* %a, align 2
@@ -46,13 +46,13 @@ entry:
 
 define void @byte(double* %a, double* %b) nounwind {
 entry:
-; EXPANDED: byte:
+; EXPANDED-LABEL: byte:
 ; EXPANDED-NOT: vld1
 ; EXPANDED: ldrb
 ; EXPANDED-NOT: str1
 ; EXPANDED: strb
 
-; UNALIGNED: byte:
+; UNALIGNED-LABEL: byte:
 ; UNALIGNED: vld1.8
 ; UNALIGNED: vst1.8
   %tmp = load double* %a, align 1
@@ -62,11 +62,11 @@ entry:
 
 define void @byte_word_ops(i32* %a, i32* %b) nounwind {
 entry:
-; EXPANDED: byte_word_ops:
+; EXPANDED-LABEL: byte_word_ops:
 ; EXPANDED: ldrb
 ; EXPANDED: strb
 
-; UNALIGNED: byte_word_ops:
+; UNALIGNED-LABEL: byte_word_ops:
 ; UNALIGNED-NOT: ldrb
 ; UNALIGNED: ldr
 ; UNALIGNED-NOT: strb
diff --git a/test/CodeGen/ARM/unaligned_load_store_vector.ll b/test/CodeGen/ARM/unaligned_load_store_vector.ll
index 25ae651..968a2c7 100644
--- a/test/CodeGen/ARM/unaligned_load_store_vector.ll
+++ b/test/CodeGen/ARM/unaligned_load_store_vector.ll
@@ -4,7 +4,7 @@
 ;SIZE  = 64
 ;TYPE  = <8 x i8>
 define void @v64_v8i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v8i8_1:
+;CHECK-LABEL: v64_v8i8_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -22,7 +22,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <4 x i16>
 define void @v64_v4i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v4i16_1:
+;CHECK-LABEL: v64_v4i16_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -40,7 +40,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <2 x i32>
 define void @v64_v2i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2i32_1:
+;CHECK-LABEL: v64_v2i32_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -58,7 +58,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <2 x float>
 define void @v64_v2f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2f32_1:
+;CHECK-LABEL: v64_v2f32_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -76,7 +76,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <16 x i8>
 define void @v128_v16i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v16i8_1:
+;CHECK-LABEL: v128_v16i8_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -94,7 +94,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <8 x i16>
 define void @v128_v8i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v8i16_1:
+;CHECK-LABEL: v128_v8i16_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -112,7 +112,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <4 x i32>
 define void @v128_v4i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4i32_1:
+;CHECK-LABEL: v128_v4i32_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -130,7 +130,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <2 x i64>
 define void @v128_v2i64_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v2i64_1:
+;CHECK-LABEL: v128_v2i64_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -148,7 +148,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <4 x float>
 define void @v128_v4f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4f32_1:
+;CHECK-LABEL: v128_v4f32_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -166,7 +166,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <8 x i8>
 define void @v64_v8i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v8i8_2:
+;CHECK-LABEL: v64_v8i8_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -184,7 +184,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <4 x i16>
 define void @v64_v4i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v4i16_2:
+;CHECK-LABEL: v64_v4i16_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -202,7 +202,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <2 x i32>
 define void @v64_v2i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2i32_2:
+;CHECK-LABEL: v64_v2i32_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -220,7 +220,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <2 x float>
 define void @v64_v2f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2f32_2:
+;CHECK-LABEL: v64_v2f32_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -238,7 +238,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <16 x i8>
 define void @v128_v16i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v16i8_2:
+;CHECK-LABEL: v128_v16i8_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -256,7 +256,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <8 x i16>
 define void @v128_v8i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v8i16_2:
+;CHECK-LABEL: v128_v8i16_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -274,7 +274,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <4 x i32>
 define void @v128_v4i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4i32_2:
+;CHECK-LABEL: v128_v4i32_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -292,7 +292,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <2 x i64>
 define void @v128_v2i64_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v2i64_2:
+;CHECK-LABEL: v128_v2i64_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -310,7 +310,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <4 x float>
 define void @v128_v4f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4f32_2:
+;CHECK-LABEL: v128_v4f32_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -328,7 +328,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <8 x i8>
 define void @v64_v8i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v8i8_4:
+;CHECK-LABEL: v64_v8i8_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -346,7 +346,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <4 x i16>
 define void @v64_v4i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v4i16_4:
+;CHECK-LABEL: v64_v4i16_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -364,7 +364,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <2 x i32>
 define void @v64_v2i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2i32_4:
+;CHECK-LABEL: v64_v2i32_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -382,7 +382,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <2 x float>
 define void @v64_v2f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2f32_4:
+;CHECK-LABEL: v64_v2f32_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -400,7 +400,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <16 x i8>
 define void @v128_v16i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v16i8_4:
+;CHECK-LABEL: v128_v16i8_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -418,7 +418,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <8 x i16>
 define void @v128_v8i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v8i16_4:
+;CHECK-LABEL: v128_v8i16_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -436,7 +436,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <4 x i32>
 define void @v128_v4i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4i32_4:
+;CHECK-LABEL: v128_v4i32_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -454,7 +454,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <2 x i64>
 define void @v128_v2i64_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v2i64_4:
+;CHECK-LABEL: v128_v2i64_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -472,7 +472,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <4 x float>
 define void @v128_v4f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4f32_4:
+;CHECK-LABEL: v128_v4f32_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
diff --git a/test/CodeGen/ARM/undef-sext.ll b/test/CodeGen/ARM/undef-sext.ll
index 2c28da3..c6d76d0 100644
--- a/test/CodeGen/ARM/undef-sext.ll
+++ b/test/CodeGen/ARM/undef-sext.ll
@@ -4,7 +4,7 @@
 
 define i32 @t(i32* %a) nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: ldr r0, [r0]
 ; CHECK: bx lr
   %0 = sext i16 undef to i32
diff --git a/test/CodeGen/ARM/unwind-init.ll b/test/CodeGen/ARM/unwind-init.ll
index 11683d5..1e12f55 100644
--- a/test/CodeGen/ARM/unwind-init.ll
+++ b/test/CodeGen/ARM/unwind-init.ll
@@ -11,7 +11,7 @@ define void @calls_unwind_init() {
   ret void
 }
 
-; CHECK: calls_unwind_init:
+; CHECK-LABEL: calls_unwind_init:
 ; CHECK: push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; CHECK: vpush   {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK: vpop    {d8, d9, d10, d11, d12, d13, d14, d15}
diff --git a/test/CodeGen/ARM/v1-constant-fold.ll b/test/CodeGen/ARM/v1-constant-fold.ll
index b86d5db..eb49a81 100644
--- a/test/CodeGen/ARM/v1-constant-fold.ll
+++ b/test/CodeGen/ARM/v1-constant-fold.ll
@@ -2,7 +2,7 @@
 
 ; PR15611. Check that we don't crash when constant folding v1i32 types.
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 define void @foo(i32 %arg) {
 bb:
   %tmp = insertelement <4 x i32> undef, i32 %arg, i32 0
diff --git a/test/CodeGen/ARM/vaba.ll b/test/CodeGen/ARM/vaba.ll
index 4fe1c43..97139e9 100644
--- a/test/CodeGen/ARM/vaba.ll
+++ b/test/CodeGen/ARM/vaba.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabas8:
+;CHECK-LABEL: vabas8:
 ;CHECK: vaba.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabas16:
+;CHECK-LABEL: vabas16:
 ;CHECK: vaba.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -23,7 +23,7 @@ define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabas32:
+;CHECK-LABEL: vabas32:
 ;CHECK: vaba.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -34,7 +34,7 @@ define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabau8:
+;CHECK-LABEL: vabau8:
 ;CHECK: vaba.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -45,7 +45,7 @@ define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabau16:
+;CHECK-LABEL: vabau16:
 ;CHECK: vaba.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -56,7 +56,7 @@ define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabau32:
+;CHECK-LABEL: vabau32:
 ;CHECK: vaba.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -67,7 +67,7 @@ define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: vabaQs8:
+;CHECK-LABEL: vabaQs8:
 ;CHECK: vaba.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -78,7 +78,7 @@ define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 }
 
 define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vabaQs16:
+;CHECK-LABEL: vabaQs16:
 ;CHECK: vaba.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -89,7 +89,7 @@ define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
 }
 
 define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vabaQs32:
+;CHECK-LABEL: vabaQs32:
 ;CHECK: vaba.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind
 }
 
 define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: vabaQu8:
+;CHECK-LABEL: vabaQu8:
 ;CHECK: vaba.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -111,7 +111,7 @@ define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 }
 
 define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vabaQu16:
+;CHECK-LABEL: vabaQu16:
 ;CHECK: vaba.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -122,7 +122,7 @@ define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
 }
 
 define <4 x i32> @vabaQu32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vabaQu32:
+;CHECK-LABEL: vabaQu32:
 ;CHECK: vaba.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -149,7 +149,7 @@ declare <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16>, <8 x i16>) nounwind read
 declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabals8:
+;CHECK-LABEL: vabals8:
 ;CHECK: vabal.s8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -161,7 +161,7 @@ define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabals16:
+;CHECK-LABEL: vabals16:
 ;CHECK: vabal.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -173,7 +173,7 @@ define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabals32:
+;CHECK-LABEL: vabals32:
 ;CHECK: vabal.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -185,7 +185,7 @@ define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabalu8:
+;CHECK-LABEL: vabalu8:
 ;CHECK: vabal.u8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -197,7 +197,7 @@ define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabalu16:
+;CHECK-LABEL: vabalu16:
 ;CHECK: vabal.u16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -209,7 +209,7 @@ define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i64> @vabalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabalu32:
+;CHECK-LABEL: vabalu32:
 ;CHECK: vabal.u32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
diff --git a/test/CodeGen/ARM/vabd.ll b/test/CodeGen/ARM/vabd.ll
index 9ec734f..2eb6d93 100644
--- a/test/CodeGen/ARM/vabd.ll
+++ b/test/CodeGen/ARM/vabd.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabds8:
+;CHECK-LABEL: vabds8:
 ;CHECK: vabd.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabds16:
+;CHECK-LABEL: vabds16:
 ;CHECK: vabd.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabds32:
+;CHECK-LABEL: vabds32:
 ;CHECK: vabd.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabdu8:
+;CHECK-LABEL: vabdu8:
 ;CHECK: vabd.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabdu16:
+;CHECK-LABEL: vabdu16:
 ;CHECK: vabd.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabdu32:
+;CHECK-LABEL: vabdu32:
 ;CHECK: vabd.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vabdf32:
+;CHECK-LABEL: vabdf32:
 ;CHECK: vabd.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -64,7 +64,7 @@ define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vabdQs8:
+;CHECK-LABEL: vabdQs8:
 ;CHECK: vabd.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -73,7 +73,7 @@ define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vabdQs16:
+;CHECK-LABEL: vabdQs16:
 ;CHECK: vabd.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -82,7 +82,7 @@ define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vabdQs32:
+;CHECK-LABEL: vabdQs32:
 ;CHECK: vabd.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -91,7 +91,7 @@ define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vabdQu8:
+;CHECK-LABEL: vabdQu8:
 ;CHECK: vabd.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -100,7 +100,7 @@ define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vabdQu16:
+;CHECK-LABEL: vabdQu16:
 ;CHECK: vabd.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -109,7 +109,7 @@ define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vabdQu32:
+;CHECK-LABEL: vabdQu32:
 ;CHECK: vabd.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -118,7 +118,7 @@ define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vabdQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vabdQf32:
+;CHECK-LABEL: vabdQf32:
 ;CHECK: vabd.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -147,7 +147,7 @@ declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind read
 declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>) nounwind readnone
 
 define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabdls8:
+;CHECK-LABEL: vabdls8:
 ;CHECK: vabdl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -157,7 +157,7 @@ define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabdls16:
+;CHECK-LABEL: vabdls16:
 ;CHECK: vabdl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -167,7 +167,7 @@ define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabdls32:
+;CHECK-LABEL: vabdls32:
 ;CHECK: vabdl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -177,7 +177,7 @@ define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabdlu8:
+;CHECK-LABEL: vabdlu8:
 ;CHECK: vabdl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -187,7 +187,7 @@ define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabdlu16:
+;CHECK-LABEL: vabdlu16:
 ;CHECK: vabdl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -197,7 +197,7 @@ define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vabdlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabdlu32:
+;CHECK-LABEL: vabdlu32:
 ;CHECK: vabdl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
diff --git a/test/CodeGen/ARM/vabs.ll b/test/CodeGen/ARM/vabs.ll
index 18ba61f..96dd38e 100644
--- a/test/CodeGen/ARM/vabs.ll
+++ b/test/CodeGen/ARM/vabs.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
-;CHECK: vabss8:
+;CHECK-LABEL: vabss8:
 ;CHECK: vabs.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)
@@ -9,7 +9,7 @@ define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
-;CHECK: vabss16:
+;CHECK-LABEL: vabss16:
 ;CHECK: vabs.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)
@@ -17,7 +17,7 @@ define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
-;CHECK: vabss32:
+;CHECK-LABEL: vabss32:
 ;CHECK: vabs.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)
@@ -25,7 +25,7 @@ define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
-;CHECK: vabsf32:
+;CHECK-LABEL: vabsf32:
 ;CHECK: vabs.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = call <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float> %tmp1)
@@ -33,7 +33,7 @@ define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
 }
 
 define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vabsQs8:
+;CHECK-LABEL: vabsQs8:
 ;CHECK: vabs.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1)
@@ -41,7 +41,7 @@ define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vabsQs16:
+;CHECK-LABEL: vabsQs16:
 ;CHECK: vabs.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1)
@@ -49,7 +49,7 @@ define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vabsQs32:
+;CHECK-LABEL: vabsQs32:
 ;CHECK: vabs.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1)
@@ -57,7 +57,7 @@ define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind {
 }
 
 define <4 x float> @vabsQf32(<4 x float>* %A) nounwind {
-;CHECK: vabsQf32:
+;CHECK-LABEL: vabsQf32:
 ;CHECK: vabs.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float> %tmp1)
@@ -75,7 +75,7 @@ declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) nounwind readnone
 declare <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float>) nounwind readnone
 
 define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind {
-;CHECK: vqabss8:
+;CHECK-LABEL: vqabss8:
 ;CHECK: vqabs.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1)
@@ -83,7 +83,7 @@ define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind {
-;CHECK: vqabss16:
+;CHECK-LABEL: vqabss16:
 ;CHECK: vqabs.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1)
@@ -91,7 +91,7 @@ define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind {
-;CHECK: vqabss32:
+;CHECK-LABEL: vqabss32:
 ;CHECK: vqabs.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1)
@@ -99,7 +99,7 @@ define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind {
 }
 
 define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vqabsQs8:
+;CHECK-LABEL: vqabsQs8:
 ;CHECK: vqabs.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1)
@@ -107,7 +107,7 @@ define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vqabsQs16:
+;CHECK-LABEL: vqabsQs16:
 ;CHECK: vqabs.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1)
@@ -115,7 +115,7 @@ define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vqabsQs32:
+;CHECK-LABEL: vqabsQs32:
 ;CHECK: vqabs.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1)
diff --git a/test/CodeGen/ARM/vadd.ll b/test/CodeGen/ARM/vadd.ll
index a830e96..a1ad37b 100644
--- a/test/CodeGen/ARM/vadd.ll
+++ b/test/CodeGen/ARM/vadd.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddi8:
+;CHECK-LABEL: vaddi8:
 ;CHECK: vadd.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddi16:
+;CHECK-LABEL: vaddi16:
 ;CHECK: vadd.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddi32:
+;CHECK-LABEL: vaddi32:
 ;CHECK: vadd.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vaddi64:
+;CHECK-LABEL: vaddi64:
 ;CHECK: vadd.i64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vaddf32:
+;CHECK-LABEL: vaddf32:
 ;CHECK: vadd.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -46,7 +46,7 @@ define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vaddQi8:
+;CHECK-LABEL: vaddQi8:
 ;CHECK: vadd.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -55,7 +55,7 @@ define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vaddQi16:
+;CHECK-LABEL: vaddQi16:
 ;CHECK: vadd.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -64,7 +64,7 @@ define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vaddQi32:
+;CHECK-LABEL: vaddQi32:
 ;CHECK: vadd.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -73,7 +73,7 @@ define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vaddQi64:
+;CHECK-LABEL: vaddQi64:
 ;CHECK: vadd.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -82,7 +82,7 @@ define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vaddQf32:
+;CHECK-LABEL: vaddQf32:
 ;CHECK: vadd.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -91,7 +91,7 @@ define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 }
 
 define <8 x i8> @vaddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vaddhni16:
+;CHECK-LABEL: vaddhni16:
 ;CHECK: vaddhn.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <8 x i8> @vaddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i16> @vaddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vaddhni32:
+;CHECK-LABEL: vaddhni32:
 ;CHECK: vaddhn.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -109,7 +109,7 @@ define <4 x i16> @vaddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vaddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vaddhni64:
+;CHECK-LABEL: vaddhni64:
 ;CHECK: vaddhn.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -122,7 +122,7 @@ declare <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32>, <4 x i32>) nounwind rea
 declare <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vraddhni16:
+;CHECK-LABEL: vraddhni16:
 ;CHECK: vraddhn.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -131,7 +131,7 @@ define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vraddhni32:
+;CHECK-LABEL: vraddhni32:
 ;CHECK: vraddhn.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -140,7 +140,7 @@ define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vraddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vraddhni64:
+;CHECK-LABEL: vraddhni64:
 ;CHECK: vraddhn.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -153,7 +153,7 @@ declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) nounwind re
 declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddls8:
+;CHECK-LABEL: vaddls8:
 ;CHECK: vaddl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -164,7 +164,7 @@ define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddls16:
+;CHECK-LABEL: vaddls16:
 ;CHECK: vaddl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -175,7 +175,7 @@ define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddls32:
+;CHECK-LABEL: vaddls32:
 ;CHECK: vaddl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -186,7 +186,7 @@ define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddlu8:
+;CHECK-LABEL: vaddlu8:
 ;CHECK: vaddl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -197,7 +197,7 @@ define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddlu16:
+;CHECK-LABEL: vaddlu16:
 ;CHECK: vaddl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -208,7 +208,7 @@ define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddlu32:
+;CHECK-LABEL: vaddlu32:
 ;CHECK: vaddl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -219,7 +219,7 @@ define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddws8:
+;CHECK-LABEL: vaddws8:
 ;CHECK: vaddw.s8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -229,7 +229,7 @@ define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddws16:
+;CHECK-LABEL: vaddws16:
 ;CHECK: vaddw.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -239,7 +239,7 @@ define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddws32:
+;CHECK-LABEL: vaddws32:
 ;CHECK: vaddw.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -249,7 +249,7 @@ define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddwu8:
+;CHECK-LABEL: vaddwu8:
 ;CHECK: vaddw.u8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -259,7 +259,7 @@ define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddwu16:
+;CHECK-LABEL: vaddwu16:
 ;CHECK: vaddw.u16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -269,7 +269,7 @@ define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddwu32:
+;CHECK-LABEL: vaddwu32:
 ;CHECK: vaddw.u32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
diff --git a/test/CodeGen/ARM/vbits.ll b/test/CodeGen/ARM/vbits.ll
index 51f9bdf..7b48441 100644
--- a/test/CodeGen/ARM/vbits.ll
+++ b/test/CodeGen/ARM/vbits.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a8 | FileCheck %s
 
 define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_andi8:
+;CHECK-LABEL: v_andi8:
 ;CHECK: vand
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_andi16:
+;CHECK-LABEL: v_andi16:
 ;CHECK: vand
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_andi32:
+;CHECK-LABEL: v_andi32:
 ;CHECK: vand
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_andi64:
+;CHECK-LABEL: v_andi64:
 ;CHECK: vand
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_andQi8:
+;CHECK-LABEL: v_andQi8:
 ;CHECK: vand
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -46,7 +46,7 @@ define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_andQi16:
+;CHECK-LABEL: v_andQi16:
 ;CHECK: vand
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -55,7 +55,7 @@ define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_andQi32:
+;CHECK-LABEL: v_andQi32:
 ;CHECK: vand
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -64,7 +64,7 @@ define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_andQi64:
+;CHECK-LABEL: v_andQi64:
 ;CHECK: vand
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -73,7 +73,7 @@ define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_bici8:
+;CHECK-LABEL: v_bici8:
 ;CHECK: vbic
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -83,7 +83,7 @@ define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_bici16:
+;CHECK-LABEL: v_bici16:
 ;CHECK: vbic
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -93,7 +93,7 @@ define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_bici32:
+;CHECK-LABEL: v_bici32:
 ;CHECK: vbic
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -103,7 +103,7 @@ define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_bici64:
+;CHECK-LABEL: v_bici64:
 ;CHECK: vbic
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -113,7 +113,7 @@ define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_bicQi8:
+;CHECK-LABEL: v_bicQi8:
 ;CHECK: vbic
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -123,7 +123,7 @@ define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_bicQi16:
+;CHECK-LABEL: v_bicQi16:
 ;CHECK: vbic
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -133,7 +133,7 @@ define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_bicQi32:
+;CHECK-LABEL: v_bicQi32:
 ;CHECK: vbic
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -143,7 +143,7 @@ define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_bicQi64:
+;CHECK-LABEL: v_bicQi64:
 ;CHECK: vbic
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -153,7 +153,7 @@ define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_eori8:
+;CHECK-LABEL: v_eori8:
 ;CHECK: veor
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -162,7 +162,7 @@ define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_eori16:
+;CHECK-LABEL: v_eori16:
 ;CHECK: veor
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -171,7 +171,7 @@ define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_eori32:
+;CHECK-LABEL: v_eori32:
 ;CHECK: veor
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -180,7 +180,7 @@ define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_eori64:
+;CHECK-LABEL: v_eori64:
 ;CHECK: veor
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -189,7 +189,7 @@ define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_eorQi8:
+;CHECK-LABEL: v_eorQi8:
 ;CHECK: veor
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -198,7 +198,7 @@ define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_eorQi16:
+;CHECK-LABEL: v_eorQi16:
 ;CHECK: veor
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -207,7 +207,7 @@ define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_eorQi32:
+;CHECK-LABEL: v_eorQi32:
 ;CHECK: veor
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -216,7 +216,7 @@ define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_eorQi64:
+;CHECK-LABEL: v_eorQi64:
 ;CHECK: veor
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -225,7 +225,7 @@ define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind {
-;CHECK: v_mvni8:
+;CHECK-LABEL: v_mvni8:
 ;CHECK: vmvn
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
@@ -233,7 +233,7 @@ define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind {
-;CHECK: v_mvni16:
+;CHECK-LABEL: v_mvni16:
 ;CHECK: vmvn
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 >
@@ -241,7 +241,7 @@ define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind {
-;CHECK: v_mvni32:
+;CHECK-LABEL: v_mvni32:
 ;CHECK: vmvn
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 >
@@ -249,7 +249,7 @@ define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind {
-;CHECK: v_mvni64:
+;CHECK-LABEL: v_mvni64:
 ;CHECK: vmvn
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = xor <1 x i64> %tmp1, < i64 -1 >
@@ -257,7 +257,7 @@ define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind {
-;CHECK: v_mvnQi8:
+;CHECK-LABEL: v_mvnQi8:
 ;CHECK: vmvn
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
@@ -265,7 +265,7 @@ define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind {
-;CHECK: v_mvnQi16:
+;CHECK-LABEL: v_mvnQi16:
 ;CHECK: vmvn
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
@@ -273,7 +273,7 @@ define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind {
-;CHECK: v_mvnQi32:
+;CHECK-LABEL: v_mvnQi32:
 ;CHECK: vmvn
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 >
@@ -281,7 +281,7 @@ define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind {
-;CHECK: v_mvnQi64:
+;CHECK-LABEL: v_mvnQi64:
 ;CHECK: vmvn
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 >
@@ -289,7 +289,7 @@ define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_orri8:
+;CHECK-LABEL: v_orri8:
 ;CHECK: vorr
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -298,7 +298,7 @@ define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_orri16:
+;CHECK-LABEL: v_orri16:
 ;CHECK: vorr
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -307,7 +307,7 @@ define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_orri32:
+;CHECK-LABEL: v_orri32:
 ;CHECK: vorr
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -316,7 +316,7 @@ define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_orri64:
+;CHECK-LABEL: v_orri64:
 ;CHECK: vorr
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -325,7 +325,7 @@ define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_orrQi8:
+;CHECK-LABEL: v_orrQi8:
 ;CHECK: vorr
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -334,7 +334,7 @@ define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_orrQi16:
+;CHECK-LABEL: v_orrQi16:
 ;CHECK: vorr
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -343,7 +343,7 @@ define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_orrQi32:
+;CHECK-LABEL: v_orrQi32:
 ;CHECK: vorr
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -352,7 +352,7 @@ define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_orrQi64:
+;CHECK-LABEL: v_orrQi64:
 ;CHECK: vorr
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -361,7 +361,7 @@ define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_orni8:
+;CHECK-LABEL: v_orni8:
 ;CHECK: vorn
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -371,7 +371,7 @@ define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_orni16:
+;CHECK-LABEL: v_orni16:
 ;CHECK: vorn
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -381,7 +381,7 @@ define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_orni32:
+;CHECK-LABEL: v_orni32:
 ;CHECK: vorn
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -391,7 +391,7 @@ define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_orni64:
+;CHECK-LABEL: v_orni64:
 ;CHECK: vorn
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -401,7 +401,7 @@ define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_ornQi8:
+;CHECK-LABEL: v_ornQi8:
 ;CHECK: vorn
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -411,7 +411,7 @@ define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_ornQi16:
+;CHECK-LABEL: v_ornQi16:
 ;CHECK: vorn
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -421,7 +421,7 @@ define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_ornQi32:
+;CHECK-LABEL: v_ornQi32:
 ;CHECK: vorn
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -431,7 +431,7 @@ define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_ornQi64:
+;CHECK-LABEL: v_ornQi64:
 ;CHECK: vorn
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -441,7 +441,7 @@ define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtsti8:
+;CHECK-LABEL: vtsti8:
 ;CHECK: vtst.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -452,7 +452,7 @@ define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vtsti16:
+;CHECK-LABEL: vtsti16:
 ;CHECK: vtst.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -463,7 +463,7 @@ define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vtsti32:
+;CHECK-LABEL: vtsti32:
 ;CHECK: vtst.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -474,7 +474,7 @@ define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vtstQi8:
+;CHECK-LABEL: vtstQi8:
 ;CHECK: vtst.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -485,7 +485,7 @@ define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vtstQi16:
+;CHECK-LABEL: vtstQi16:
 ;CHECK: vtst.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -496,7 +496,7 @@ define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vtstQi32:
+;CHECK-LABEL: vtstQi32:
 ;CHECK: vtst.32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -507,7 +507,7 @@ define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
-; CHECK: v_orrimm:
+; CHECK-LABEL: v_orrimm:
 ; CHECK-NOT: vmov
 ; CHECK-NOT: vmvn
 ; CHECK: vorr
@@ -527,7 +527,7 @@ define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
-; CHECK: v_bicimm:
+; CHECK-LABEL: v_bicimm:
 ; CHECK-NOT: vmov
 ; CHECK-NOT: vmvn
 ; CHECK: vbic
@@ -537,7 +537,7 @@ define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
 }
 
 define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
-; CHECK: v_bicimmQ:
+; CHECK-LABEL: v_bicimmQ:
 ; CHECK-NOT: vmov
 ; CHECK-NOT: vmvn
 ; CHECK: vbic
diff --git a/test/CodeGen/ARM/vbsl-constant.ll b/test/CodeGen/ARM/vbsl-constant.ll
index ffda0a5..5e033fe 100644
--- a/test/CodeGen/ARM/vbsl-constant.ll
+++ b/test/CodeGen/ARM/vbsl-constant.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+neon | FileCheck %s
 
 define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: v_bsli8:
+;CHECK-LABEL: v_bsli8:
 ;CHECK: vldr
 ;CHECK: vldr
 ;CHECK: vbsl
@@ -15,7 +15,7 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: v_bsli16:
+;CHECK-LABEL: v_bsli16:
 ;CHECK: vldr
 ;CHECK: vldr
 ;CHECK: vbsl
@@ -29,7 +29,7 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: v_bsli32:
+;CHECK-LABEL: v_bsli32:
 ;CHECK: vldr
 ;CHECK: vldr
 ;CHECK: vbsl
@@ -43,7 +43,7 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
-;CHECK: v_bsli64:
+;CHECK-LABEL: v_bsli64:
 ;CHECK: vldr
 ;CHECK: vldr
 ;CHECK: vldr
@@ -58,7 +58,7 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind
 }
 
 define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: v_bslQi8:
+;CHECK-LABEL: v_bslQi8:
 ;CHECK: vld1.32
 ;CHECK: vld1.32
 ;CHECK: vbsl
@@ -72,7 +72,7 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 }
 
 define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: v_bslQi16:
+;CHECK-LABEL: v_bslQi16:
 ;CHECK: vld1.32
 ;CHECK: vld1.32
 ;CHECK: vbsl
@@ -86,7 +86,7 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin
 }
 
 define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: v_bslQi32:
+;CHECK-LABEL: v_bslQi32:
 ;CHECK: vld1.32
 ;CHECK: vld1.32
 ;CHECK: vbsl
@@ -100,7 +100,7 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin
 }
 
 define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
-;CHECK: v_bslQi64:
+;CHECK-LABEL: v_bslQi64:
 ;CHECK: vld1.32
 ;CHECK: vld1.32
 ;CHECK: vld1.64
diff --git a/test/CodeGen/ARM/vbsl.ll b/test/CodeGen/ARM/vbsl.ll
index 56e40eb..1e53e51 100644
--- a/test/CodeGen/ARM/vbsl.ll
+++ b/test/CodeGen/ARM/vbsl.ll
@@ -3,7 +3,7 @@
 ; rdar://12471808
 
 define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: v_bsli8:
+;CHECK-LABEL: v_bsli8:
 ;CHECK: vbsl
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -16,7 +16,7 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: v_bsli16:
+;CHECK-LABEL: v_bsli16:
 ;CHECK: vbsl
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -29,7 +29,7 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: v_bsli32:
+;CHECK-LABEL: v_bsli32:
 ;CHECK: vbsl
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -42,7 +42,7 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
-;CHECK: v_bsli64:
+;CHECK-LABEL: v_bsli64:
 ;CHECK: vbsl
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -55,7 +55,7 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind
 }
 
 define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: v_bslQi8:
+;CHECK-LABEL: v_bslQi8:
 ;CHECK: vbsl
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -68,7 +68,7 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 }
 
 define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: v_bslQi16:
+;CHECK-LABEL: v_bslQi16:
 ;CHECK: vbsl
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -81,7 +81,7 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin
 }
 
 define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: v_bslQi32:
+;CHECK-LABEL: v_bslQi32:
 ;CHECK: vbsl
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -94,7 +94,7 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin
 }
 
 define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
-;CHECK: v_bslQi64:
+;CHECK-LABEL: v_bslQi64:
 ;CHECK: vbsl
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -107,56 +107,56 @@ define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwin
 }
 
 define <8 x i8> @f1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind readnone optsize ssp {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: vbsl
   %vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind
   ret <8 x i8> %vbsl.i
 }
 
 define <4 x i16> @f2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: vbsl
   %vbsl3.i = tail call <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind
   ret <4 x i16> %vbsl3.i
 }
 
 define <2 x i32> @f3(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: vbsl
   %vbsl3.i = tail call <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind
   ret <2 x i32> %vbsl3.i
 }
 
 define <2 x float> @f4(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone optsize ssp {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: vbsl
   %vbsl4.i = tail call <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind
   ret <2 x float> %vbsl4.i
 }
 
 define <16 x i8> @g1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind readnone optsize ssp {
-; CHECK: g1:
+; CHECK-LABEL: g1:
 ; CHECK: vbsl
   %vbsl.i = tail call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind
   ret <16 x i8> %vbsl.i
 }
 
 define <8 x i16> @g2(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind readnone optsize ssp {
-; CHECK: g2:
+; CHECK-LABEL: g2:
 ; CHECK: vbsl
   %vbsl3.i = tail call <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind
   ret <8 x i16> %vbsl3.i
 }
 
 define <4 x i32> @g3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
-; CHECK: g3:
+; CHECK-LABEL: g3:
 ; CHECK: vbsl
   %vbsl3.i = tail call <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind
   ret <4 x i32> %vbsl3.i
 }
 
 define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone optsize ssp {
-; CHECK: g4:
+; CHECK-LABEL: g4:
 ; CHECK: vbsl
   %vbsl4.i = tail call <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind
   ret <4 x float> %vbsl4.i
diff --git a/test/CodeGen/ARM/vceq.ll b/test/CodeGen/ARM/vceq.ll
index 051c349..0a1f2eb 100644
--- a/test/CodeGen/ARM/vceq.ll
+++ b/test/CodeGen/ARM/vceq.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vceqi8:
+;CHECK-LABEL: vceqi8:
 ;CHECK: vceq.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vceqi16:
+;CHECK-LABEL: vceqi16:
 ;CHECK: vceq.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -21,7 +21,7 @@ define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vceqi32:
+;CHECK-LABEL: vceqi32:
 ;CHECK: vceq.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -31,7 +31,7 @@ define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vceqf32:
+;CHECK-LABEL: vceqf32:
 ;CHECK: vceq.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -41,7 +41,7 @@ define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vceqQi8:
+;CHECK-LABEL: vceqQi8:
 ;CHECK: vceq.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -51,7 +51,7 @@ define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vceqQi16:
+;CHECK-LABEL: vceqQi16:
 ;CHECK: vceq.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -61,7 +61,7 @@ define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vceqQi32:
+;CHECK-LABEL: vceqQi32:
 ;CHECK: vceq.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -71,7 +71,7 @@ define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vceqQf32:
+;CHECK-LABEL: vceqQf32:
 ;CHECK: vceq.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -81,7 +81,7 @@ define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 }
 
 define <8 x i8> @vceqi8Z(<8 x i8>* %A) nounwind {
-;CHECK: vceqi8Z:
+;CHECK-LABEL: vceqi8Z:
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vceq.i8
diff --git a/test/CodeGen/ARM/vcge.ll b/test/CodeGen/ARM/vcge.ll
index bf5f0b9..13c895c 100644
--- a/test/CodeGen/ARM/vcge.ll
+++ b/test/CodeGen/ARM/vcge.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcges8:
+;CHECK-LABEL: vcges8:
 ;CHECK: vcge.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcges16:
+;CHECK-LABEL: vcges16:
 ;CHECK: vcge.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -21,7 +21,7 @@ define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcges32:
+;CHECK-LABEL: vcges32:
 ;CHECK: vcge.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -31,7 +31,7 @@ define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcgeu8:
+;CHECK-LABEL: vcgeu8:
 ;CHECK: vcge.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -41,7 +41,7 @@ define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcgeu16:
+;CHECK-LABEL: vcgeu16:
 ;CHECK: vcge.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -51,7 +51,7 @@ define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcgeu32:
+;CHECK-LABEL: vcgeu32:
 ;CHECK: vcge.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -61,7 +61,7 @@ define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcgef32:
+;CHECK-LABEL: vcgef32:
 ;CHECK: vcge.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -71,7 +71,7 @@ define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgeQs8:
+;CHECK-LABEL: vcgeQs8:
 ;CHECK: vcge.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -81,7 +81,7 @@ define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgeQs16:
+;CHECK-LABEL: vcgeQs16:
 ;CHECK: vcge.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgeQs32:
+;CHECK-LABEL: vcgeQs32:
 ;CHECK: vcge.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -101,7 +101,7 @@ define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgeQu8:
+;CHECK-LABEL: vcgeQu8:
 ;CHECK: vcge.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -111,7 +111,7 @@ define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgeQu16:
+;CHECK-LABEL: vcgeQu16:
 ;CHECK: vcge.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -121,7 +121,7 @@ define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgeQu32:
+;CHECK-LABEL: vcgeQu32:
 ;CHECK: vcge.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -131,7 +131,7 @@ define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vcgeQf32:
+;CHECK-LABEL: vcgeQf32:
 ;CHECK: vcge.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -141,7 +141,7 @@ define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 }
 
 define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vacgef32:
+;CHECK-LABEL: vacgef32:
 ;CHECK: vacge.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -150,7 +150,7 @@ define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vacgeQf32:
+;CHECK-LABEL: vacgeQf32:
 ;CHECK: vacge.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -162,7 +162,7 @@ declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>) nounwind readn
 declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>) nounwind readnone
 
 define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind {
-;CHECK: vcgei8Z:
+;CHECK-LABEL: vcgei8Z:
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vcge.s8
@@ -173,7 +173,7 @@ define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind {
 }
 
 define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind {
-;CHECK: vclei8Z:
+;CHECK-LABEL: vclei8Z:
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vcle.s8
diff --git a/test/CodeGen/ARM/vcgt.ll b/test/CodeGen/ARM/vcgt.ll
index 2243bac..056866f 100644
--- a/test/CodeGen/ARM/vcgt.ll
+++ b/test/CodeGen/ARM/vcgt.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
 
 define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcgts8:
+;CHECK-LABEL: vcgts8:
 ;CHECK: vcgt.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcgts16:
+;CHECK-LABEL: vcgts16:
 ;CHECK: vcgt.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -22,7 +22,7 @@ define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcgts32:
+;CHECK-LABEL: vcgts32:
 ;CHECK: vcgt.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -32,7 +32,7 @@ define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcgtu8:
+;CHECK-LABEL: vcgtu8:
 ;CHECK: vcgt.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -42,7 +42,7 @@ define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcgtu16:
+;CHECK-LABEL: vcgtu16:
 ;CHECK: vcgt.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -52,7 +52,7 @@ define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcgtu32:
+;CHECK-LABEL: vcgtu32:
 ;CHECK: vcgt.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -62,7 +62,7 @@ define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcgtf32:
+;CHECK-LABEL: vcgtf32:
 ;CHECK: vcgt.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -72,7 +72,7 @@ define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgtQs8:
+;CHECK-LABEL: vcgtQs8:
 ;CHECK: vcgt.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgtQs16:
+;CHECK-LABEL: vcgtQs16:
 ;CHECK: vcgt.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -92,7 +92,7 @@ define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgtQs32:
+;CHECK-LABEL: vcgtQs32:
 ;CHECK: vcgt.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -102,7 +102,7 @@ define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgtQu8:
+;CHECK-LABEL: vcgtQu8:
 ;CHECK: vcgt.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -112,7 +112,7 @@ define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgtQu16:
+;CHECK-LABEL: vcgtQu16:
 ;CHECK: vcgt.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -122,7 +122,7 @@ define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgtQu32:
+;CHECK-LABEL: vcgtQu32:
 ;CHECK: vcgt.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -132,7 +132,7 @@ define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vcgtQf32:
+;CHECK-LABEL: vcgtQf32:
 ;CHECK: vcgt.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -142,7 +142,7 @@ define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 }
 
 define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vacgtf32:
+;CHECK-LABEL: vacgtf32:
 ;CHECK: vacgt.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -151,7 +151,7 @@ define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vacgtQf32:
+;CHECK-LABEL: vacgtQf32:
 ;CHECK: vacgt.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -161,7 +161,7 @@ define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 
 ; rdar://7923010
 define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vcgt_zext:
+;CHECK-LABEL: vcgt_zext:
 ;CHECK: vmov.i32 [[Q0:q[0-9]+]], #0x1
 ;CHECK: vcgt.f32 [[Q1:q[0-9]+]]
 ;CHECK: vand [[Q2:q[0-9]+]], [[Q1]], [[Q0]]
@@ -176,7 +176,7 @@ declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) nounwind readn
 declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone
 
 define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind {
-;CHECK: vcgti8Z:
+;CHECK-LABEL: vcgti8Z:
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vcgt.s8
@@ -187,7 +187,7 @@ define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind {
 }
 
 define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind {
-;CHECK: vclti8Z:
+;CHECK-LABEL: vclti8Z:
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vclt.s8
diff --git a/test/CodeGen/ARM/vcnt.ll b/test/CodeGen/ARM/vcnt.ll
index 9f55c24..0b53979 100644
--- a/test/CodeGen/ARM/vcnt.ll
+++ b/test/CodeGen/ARM/vcnt.ll
@@ -2,7 +2,7 @@
 ; NB: this tests vcnt, vclz, and vcls
 
 define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
-;CHECK: vcnt8:
+;CHECK-LABEL: vcnt8:
 ;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
@@ -10,7 +10,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
 }
 
 define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
-;CHECK: vcntQ8:
+;CHECK-LABEL: vcntQ8:
 ;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
@@ -21,7 +21,7 @@ declare <8 x i8>  @llvm.ctpop.v8i8(<8 x i8>) nounwind readnone
 declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
 
 define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
-;CHECK: vclz8:
+;CHECK-LABEL: vclz8:
 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
@@ -29,7 +29,7 @@ define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
-;CHECK: vclz16:
+;CHECK-LABEL: vclz16:
 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
@@ -37,7 +37,7 @@ define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
-;CHECK: vclz32:
+;CHECK-LABEL: vclz32:
 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
@@ -45,7 +45,7 @@ define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
 }
 
 define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
-;CHECK: vclzQ8:
+;CHECK-LABEL: vclzQ8:
 ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
@@ -53,7 +53,7 @@ define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
-;CHECK: vclzQ16:
+;CHECK-LABEL: vclzQ16:
 ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
@@ -61,7 +61,7 @@ define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
-;CHECK: vclzQ32:
+;CHECK-LABEL: vclzQ32:
 ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
@@ -77,7 +77,7 @@ declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
 
 define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
-;CHECK: vclss8:
+;CHECK-LABEL: vclss8:
 ;CHECK: vcls.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
@@ -85,7 +85,7 @@ define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
-;CHECK: vclss16:
+;CHECK-LABEL: vclss16:
 ;CHECK: vcls.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
@@ -93,7 +93,7 @@ define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
-;CHECK: vclss32:
+;CHECK-LABEL: vclss32:
 ;CHECK: vcls.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
@@ -101,7 +101,7 @@ define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
 }
 
 define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vclsQs8:
+;CHECK-LABEL: vclsQs8:
 ;CHECK: vcls.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
@@ -109,7 +109,7 @@ define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vclsQs16:
+;CHECK-LABEL: vclsQs16:
 ;CHECK: vcls.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
@@ -117,7 +117,7 @@ define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vclsQs32:
+;CHECK-LABEL: vclsQs32:
 ;CHECK: vcls.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
diff --git a/test/CodeGen/ARM/vcvt-cost.ll b/test/CodeGen/ARM/vcvt-cost.ll
index 0d45c40..5e56a5b 100644
--- a/test/CodeGen/ARM/vcvt-cost.ll
+++ b/test/CodeGen/ARM/vcvt-cost.ll
@@ -4,7 +4,7 @@
 ; RUN: opt < %s  -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST
 %T0_5 = type <8 x i8>
 %T1_5 = type <8 x i32>
-; CHECK: func_cvt5:
+; CHECK-LABEL: func_cvt5:
 define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
 ; CHECK: vmovl.s8
 ; CHECK: vmovl.s16
@@ -20,7 +20,7 @@ define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
 ;; is improved the cost needs to change.
 %TA0_5 = type <8 x i8>
 %TA1_5 = type <8 x i32>
-; CHECK: func_cvt1:
+; CHECK-LABEL: func_cvt1:
 define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
 ; CHECK: vmovl.u8
 ; CHECK: vmovl.u16
@@ -35,7 +35,7 @@ define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
 
 %T0_51 = type <8 x i32>
 %T1_51 = type <8 x i8>
-; CHECK: func_cvt51:
+; CHECK-LABEL: func_cvt51:
 define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
 ; CHECK: vmovn.i32
 ; CHECK: vmovn.i32
@@ -50,7 +50,7 @@ define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
 
 %TT0_5 = type <16 x i8>
 %TT1_5 = type <16 x i32>
-; CHECK: func_cvt52:
+; CHECK-LABEL: func_cvt52:
 define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
 ; CHECK: vmovl.s16
 ; CHECK: vmovl.s16
@@ -67,7 +67,7 @@ define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
 ;; is improved the cost needs to change.
 %TTA0_5 = type <16 x i8>
 %TTA1_5 = type <16 x i32>
-; CHECK: func_cvt12:
+; CHECK-LABEL: func_cvt12:
 define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
 ; CHECK: vmovl.u16
 ; CHECK: vmovl.u16
@@ -83,7 +83,7 @@ define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
 
 %TT0_51 = type <16 x i32>
 %TT1_51 = type <16 x i8>
-; CHECK: func_cvt512:
+; CHECK-LABEL: func_cvt512:
 define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) {
 ; CHECK: vmovn.i32
 ; CHECK: vmovn.i32
@@ -99,7 +99,7 @@ define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) {
   ret void
 }
 
-; CHECK: sext_v4i16_v4i64:
+; CHECK-LABEL: sext_v4i16_v4i64:
 define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
 ; CHECK: vmovl.s32
 ; CHECK: vmovl.s32
@@ -111,7 +111,7 @@ define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
   ret void
 }
 
-; CHECK: zext_v4i16_v4i64:
+; CHECK-LABEL: zext_v4i16_v4i64:
 define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
 ; CHECK: vmovl.u32
 ; CHECK: vmovl.u32
@@ -123,7 +123,7 @@ define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
   ret void
 }
 
-; CHECK: sext_v8i16_v8i64:
+; CHECK-LABEL: sext_v8i16_v8i64:
 define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
 ; CHECK: vmovl.s32
 ; CHECK: vmovl.s32
@@ -137,7 +137,7 @@ define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
   ret void
 }
 
-; CHECK: zext_v8i16_v8i64:
+; CHECK-LABEL: zext_v8i16_v8i64:
 define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
 ; CHECK: vmovl.u32
 ; CHECK: vmovl.u32
diff --git a/test/CodeGen/ARM/vcvt.ll b/test/CodeGen/ARM/vcvt.ll
index 9b315b1..4f17dc5 100644
--- a/test/CodeGen/ARM/vcvt.ll
+++ b/test/CodeGen/ARM/vcvt.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon,+fp16 | FileCheck %s
 
 define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_f32tos32:
+;CHECK-LABEL: vcvt_f32tos32:
 ;CHECK: vcvt.s32.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = fptosi <2 x float> %tmp1 to <2 x i32>
@@ -9,7 +9,7 @@ define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
 }
 
 define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_f32tou32:
+;CHECK-LABEL: vcvt_f32tou32:
 ;CHECK: vcvt.u32.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = fptoui <2 x float> %tmp1 to <2 x i32>
@@ -17,7 +17,7 @@ define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
 }
 
 define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_s32tof32:
+;CHECK-LABEL: vcvt_s32tof32:
 ;CHECK: vcvt.f32.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = sitofp <2 x i32> %tmp1 to <2 x float>
@@ -25,7 +25,7 @@ define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_u32tof32:
+;CHECK-LABEL: vcvt_u32tof32:
 ;CHECK: vcvt.f32.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = uitofp <2 x i32> %tmp1 to <2 x float>
@@ -33,7 +33,7 @@ define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
 }
 
 define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_f32tos32:
+;CHECK-LABEL: vcvtQ_f32tos32:
 ;CHECK: vcvt.s32.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = fptosi <4 x float> %tmp1 to <4 x i32>
@@ -41,7 +41,7 @@ define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
 }
 
 define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_f32tou32:
+;CHECK-LABEL: vcvtQ_f32tou32:
 ;CHECK: vcvt.u32.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = fptoui <4 x float> %tmp1 to <4 x i32>
@@ -49,7 +49,7 @@ define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
 }
 
 define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_s32tof32:
+;CHECK-LABEL: vcvtQ_s32tof32:
 ;CHECK: vcvt.f32.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = sitofp <4 x i32> %tmp1 to <4 x float>
@@ -57,7 +57,7 @@ define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
 }
 
 define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_u32tof32:
+;CHECK-LABEL: vcvtQ_u32tof32:
 ;CHECK: vcvt.f32.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = uitofp <4 x i32> %tmp1 to <4 x float>
@@ -65,7 +65,7 @@ define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_n_f32tos32:
+;CHECK-LABEL: vcvt_n_f32tos32:
 ;CHECK: vcvt.s32.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
@@ -73,7 +73,7 @@ define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
 }
 
 define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_n_f32tou32:
+;CHECK-LABEL: vcvt_n_f32tou32:
 ;CHECK: vcvt.u32.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
@@ -81,7 +81,7 @@ define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
 }
 
 define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_n_s32tof32:
+;CHECK-LABEL: vcvt_n_s32tof32:
 ;CHECK: vcvt.f32.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
@@ -89,7 +89,7 @@ define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_n_u32tof32:
+;CHECK-LABEL: vcvt_n_u32tof32:
 ;CHECK: vcvt.f32.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
@@ -102,7 +102,7 @@ declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwi
 declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
 
 define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_n_f32tos32:
+;CHECK-LABEL: vcvtQ_n_f32tos32:
 ;CHECK: vcvt.s32.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
@@ -110,7 +110,7 @@ define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
 }
 
 define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_n_f32tou32:
+;CHECK-LABEL: vcvtQ_n_f32tou32:
 ;CHECK: vcvt.u32.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
@@ -118,7 +118,7 @@ define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
 }
 
 define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_n_s32tof32:
+;CHECK-LABEL: vcvtQ_n_s32tof32:
 ;CHECK: vcvt.f32.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
@@ -126,7 +126,7 @@ define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
 }
 
 define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_n_u32tof32:
+;CHECK-LABEL: vcvtQ_n_u32tof32:
 ;CHECK: vcvt.f32.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
@@ -139,7 +139,7 @@ declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwi
 declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
 
 define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
-;CHECK: vcvt_f16tof32:
+;CHECK-LABEL: vcvt_f16tof32:
 ;CHECK: vcvt.f32.f16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %tmp1)
@@ -147,7 +147,7 @@ define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind {
-;CHECK: vcvt_f32tof16:
+;CHECK-LABEL: vcvt_f32tof16:
 ;CHECK: vcvt.f16.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %tmp1)
@@ -159,7 +159,7 @@ declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone
 
 
 define <4 x i16> @fix_float_to_i16(<4 x float> %in) {
-; CHECK: fix_float_to_i16:
+; CHECK-LABEL: fix_float_to_i16:
 ; CHECK: vcvt.u32.f32 [[TMP:q[0-9]+]], {{q[0-9]+}}, #1
 ; CHECK: vmovn.i32 {{d[0-9]+}}, [[TMP]]
 
@@ -169,7 +169,7 @@ define <4 x i16> @fix_float_to_i16(<4 x float> %in) {
 }
 
 define <2 x i64> @fix_float_to_i64(<2 x float> %in) {
-; CHECK: fix_float_to_i64:
+; CHECK-LABEL: fix_float_to_i64:
 ; CHECK: bl
 ; CHECK: bl
 
@@ -179,7 +179,7 @@ define <2 x i64> @fix_float_to_i64(<2 x float> %in) {
 }
 
 define <4 x i16> @fix_double_to_i16(<4 x double> %in) {
-; CHECK: fix_double_to_i16:
+; CHECK-LABEL: fix_double_to_i16:
 ; CHECK: vcvt.s32.f64
 ; CHECK: vcvt.s32.f64
 
@@ -189,7 +189,7 @@ define <4 x i16> @fix_double_to_i16(<4 x double> %in) {
 }
 
 define <2 x i64> @fix_double_to_i64(<2 x double> %in) {
-; CHECK: fix_double_to_i64:
+; CHECK-LABEL: fix_double_to_i64:
 ; CHECK: bl
 ; CHECK: bl
   %scale = fmul <2 x double> %in, <double 2.0, double 2.0>
diff --git a/test/CodeGen/ARM/vdiv_combine.ll b/test/CodeGen/ARM/vdiv_combine.ll
index 3b43be4..96807f7 100644
--- a/test/CodeGen/ARM/vdiv_combine.ll
+++ b/test/CodeGen/ARM/vdiv_combine.ll
@@ -97,7 +97,7 @@ entry:
 declare void @foo_float32x4_t(<4 x float>)
 
 define <4 x float> @fix_unsigned_i16_to_float(<4 x i16> %in) {
-; CHECK: fix_unsigned_i16_to_float:
+; CHECK-LABEL: fix_unsigned_i16_to_float:
 ; CHECK: vmovl.u16 [[TMP:q[0-9]+]], {{d[0-9]+}}
 ; CHECK: vcvt.f32.u32 {{q[0-9]+}}, [[TMP]], #1
 
@@ -107,7 +107,7 @@ define <4 x float> @fix_unsigned_i16_to_float(<4 x i16> %in) {
 }
 
 define <4 x float> @fix_signed_i16_to_float(<4 x i16> %in) {
-; CHECK: fix_signed_i16_to_float:
+; CHECK-LABEL: fix_signed_i16_to_float:
 ; CHECK: vmovl.s16 [[TMP:q[0-9]+]], {{d[0-9]+}}
 ; CHECK: vcvt.f32.s32 {{q[0-9]+}}, [[TMP]], #1
 
@@ -117,7 +117,7 @@ define <4 x float> @fix_signed_i16_to_float(<4 x i16> %in) {
 }
 
 define <2 x float> @fix_i64_to_float(<2 x i64> %in) {
-; CHECK: fix_i64_to_float:
+; CHECK-LABEL: fix_i64_to_float:
 ; CHECK: bl
 ; CHECK: bl
 
@@ -127,7 +127,7 @@ define <2 x float> @fix_i64_to_float(<2 x i64> %in) {
 }
 
 define <2 x double> @fix_i64_to_double(<2 x i64> %in) {
-; CHECK: fix_i64_to_double:
+; CHECK-LABEL: fix_i64_to_double:
 ; CHECK: bl
 ; CHECK: bl
 
diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll
index 2cf94d6..8805ef7 100644
--- a/test/CodeGen/ARM/vdup.ll
+++ b/test/CodeGen/ARM/vdup.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @v_dup8(i8 %A) nounwind {
-;CHECK: v_dup8:
+;CHECK-LABEL: v_dup8:
 ;CHECK: vdup.8
 	%tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
 	%tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1
@@ -15,7 +15,7 @@ define <8 x i8> @v_dup8(i8 %A) nounwind {
 }
 
 define <4 x i16> @v_dup16(i16 %A) nounwind {
-;CHECK: v_dup16:
+;CHECK-LABEL: v_dup16:
 ;CHECK: vdup.16
 	%tmp1 = insertelement <4 x i16> zeroinitializer, i16 %A, i32 0
 	%tmp2 = insertelement <4 x i16> %tmp1, i16 %A, i32 1
@@ -25,7 +25,7 @@ define <4 x i16> @v_dup16(i16 %A) nounwind {
 }
 
 define <2 x i32> @v_dup32(i32 %A) nounwind {
-;CHECK: v_dup32:
+;CHECK-LABEL: v_dup32:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <2 x i32> zeroinitializer, i32 %A, i32 0
 	%tmp2 = insertelement <2 x i32> %tmp1, i32 %A, i32 1
@@ -33,7 +33,7 @@ define <2 x i32> @v_dup32(i32 %A) nounwind {
 }
 
 define <2 x float> @v_dupfloat(float %A) nounwind {
-;CHECK: v_dupfloat:
+;CHECK-LABEL: v_dupfloat:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <2 x float> zeroinitializer, float %A, i32 0
 	%tmp2 = insertelement <2 x float> %tmp1, float %A, i32 1
@@ -41,7 +41,7 @@ define <2 x float> @v_dupfloat(float %A) nounwind {
 }
 
 define <16 x i8> @v_dupQ8(i8 %A) nounwind {
-;CHECK: v_dupQ8:
+;CHECK-LABEL: v_dupQ8:
 ;CHECK: vdup.8
 	%tmp1 = insertelement <16 x i8> zeroinitializer, i8 %A, i32 0
 	%tmp2 = insertelement <16 x i8> %tmp1, i8 %A, i32 1
@@ -63,7 +63,7 @@ define <16 x i8> @v_dupQ8(i8 %A) nounwind {
 }
 
 define <8 x i16> @v_dupQ16(i16 %A) nounwind {
-;CHECK: v_dupQ16:
+;CHECK-LABEL: v_dupQ16:
 ;CHECK: vdup.16
 	%tmp1 = insertelement <8 x i16> zeroinitializer, i16 %A, i32 0
 	%tmp2 = insertelement <8 x i16> %tmp1, i16 %A, i32 1
@@ -77,7 +77,7 @@ define <8 x i16> @v_dupQ16(i16 %A) nounwind {
 }
 
 define <4 x i32> @v_dupQ32(i32 %A) nounwind {
-;CHECK: v_dupQ32:
+;CHECK-LABEL: v_dupQ32:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %A, i32 0
 	%tmp2 = insertelement <4 x i32> %tmp1, i32 %A, i32 1
@@ -87,7 +87,7 @@ define <4 x i32> @v_dupQ32(i32 %A) nounwind {
 }
 
 define <4 x float> @v_dupQfloat(float %A) nounwind {
-;CHECK: v_dupQfloat:
+;CHECK-LABEL: v_dupQfloat:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <4 x float> zeroinitializer, float %A, i32 0
 	%tmp2 = insertelement <4 x float> %tmp1, float %A, i32 1
@@ -99,7 +99,7 @@ define <4 x float> @v_dupQfloat(float %A) nounwind {
 ; Check to make sure it works with shuffles, too.
 
 define <8 x i8> @v_shuffledup8(i8 %A) nounwind {
-;CHECK: v_shuffledup8:
+;CHECK-LABEL: v_shuffledup8:
 ;CHECK: vdup.8
 	%tmp1 = insertelement <8 x i8> undef, i8 %A, i32 0
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
@@ -107,7 +107,7 @@ define <8 x i8> @v_shuffledup8(i8 %A) nounwind {
 }
 
 define <4 x i16> @v_shuffledup16(i16 %A) nounwind {
-;CHECK: v_shuffledup16:
+;CHECK-LABEL: v_shuffledup16:
 ;CHECK: vdup.16
 	%tmp1 = insertelement <4 x i16> undef, i16 %A, i32 0
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
@@ -115,7 +115,7 @@ define <4 x i16> @v_shuffledup16(i16 %A) nounwind {
 }
 
 define <2 x i32> @v_shuffledup32(i32 %A) nounwind {
-;CHECK: v_shuffledup32:
+;CHECK-LABEL: v_shuffledup32:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <2 x i32> undef, i32 %A, i32 0
 	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
@@ -123,7 +123,7 @@ define <2 x i32> @v_shuffledup32(i32 %A) nounwind {
 }
 
 define <2 x float> @v_shuffledupfloat(float %A) nounwind {
-;CHECK: v_shuffledupfloat:
+;CHECK-LABEL: v_shuffledupfloat:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <2 x float> undef, float %A, i32 0
 	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
@@ -131,7 +131,7 @@ define <2 x float> @v_shuffledupfloat(float %A) nounwind {
 }
 
 define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind {
-;CHECK: v_shuffledupQ8:
+;CHECK-LABEL: v_shuffledupQ8:
 ;CHECK: vdup.8
 	%tmp1 = insertelement <16 x i8> undef, i8 %A, i32 0
 	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> zeroinitializer
@@ -139,7 +139,7 @@ define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind {
 }
 
 define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind {
-;CHECK: v_shuffledupQ16:
+;CHECK-LABEL: v_shuffledupQ16:
 ;CHECK: vdup.16
 	%tmp1 = insertelement <8 x i16> undef, i16 %A, i32 0
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> zeroinitializer
@@ -147,7 +147,7 @@ define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind {
 }
 
 define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind {
-;CHECK: v_shuffledupQ32:
+;CHECK-LABEL: v_shuffledupQ32:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <4 x i32> undef, i32 %A, i32 0
 	%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> zeroinitializer
@@ -155,7 +155,7 @@ define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind {
 }
 
 define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
-;CHECK: v_shuffledupQfloat:
+;CHECK-LABEL: v_shuffledupQfloat:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <4 x float> undef, float %A, i32 0
 	%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
@@ -163,7 +163,7 @@ define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
 }
 
 define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
-;CHECK: vduplane8:
+;CHECK-LABEL: vduplane8:
 ;CHECK: vdup.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
@@ -171,7 +171,7 @@ define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
-;CHECK: vduplane16:
+;CHECK-LABEL: vduplane16:
 ;CHECK: vdup.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
@@ -179,7 +179,7 @@ define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
-;CHECK: vduplane32:
+;CHECK-LABEL: vduplane32:
 ;CHECK: vdup.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
@@ -187,7 +187,7 @@ define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
-;CHECK: vduplanefloat:
+;CHECK-LABEL: vduplanefloat:
 ;CHECK: vdup.32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
@@ -195,7 +195,7 @@ define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
 }
 
 define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
-;CHECK: vduplaneQ8:
+;CHECK-LABEL: vduplaneQ8:
 ;CHECK: vdup.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
@@ -203,7 +203,7 @@ define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
-;CHECK: vduplaneQ16:
+;CHECK-LABEL: vduplaneQ16:
 ;CHECK: vdup.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
@@ -211,7 +211,7 @@ define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
-;CHECK: vduplaneQ32:
+;CHECK-LABEL: vduplaneQ32:
 ;CHECK: vdup.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
@@ -219,7 +219,7 @@ define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
 }
 
 define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
-;CHECK: vduplaneQfloat:
+;CHECK-LABEL: vduplaneQfloat:
 ;CHECK: vdup.32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
@@ -251,7 +251,7 @@ entry:
 }
 
 ; Radar 7373643
-;CHECK: redundantVdup:
+;CHECK-LABEL: redundantVdup:
 ;CHECK: vmov.i8
 ;CHECK-NOT: vdup.8
 ;CHECK: vstr
@@ -297,7 +297,7 @@ define <4 x i32> @tduplane(<4 x i32> %invec) {
 }
 
 define <2 x float> @check_f32(<4 x float> %v) nounwind {
-;CHECK: check_f32:
+;CHECK-LABEL: check_f32:
 ;CHECK: vdup.32 {{.*}}, d{{..}}[1]
   %x = extractelement <4 x float> %v, i32 3
   %1 = insertelement  <2 x float> undef, float %x, i32 0
@@ -306,7 +306,7 @@ define <2 x float> @check_f32(<4 x float> %v) nounwind {
 }
 
 define <2 x i32> @check_i32(<4 x i32> %v) nounwind {
-;CHECK: check_i32:
+;CHECK-LABEL: check_i32:
 ;CHECK: vdup.32 {{.*}}, d{{..}}[1]
   %x = extractelement <4 x i32> %v, i32 3
   %1 = insertelement  <2 x i32> undef, i32 %x, i32 0
@@ -315,7 +315,7 @@ define <2 x i32> @check_i32(<4 x i32> %v) nounwind {
 }
 
 define <4 x i16> @check_i16(<8 x i16> %v) nounwind {
-;CHECK: check_i16:
+;CHECK-LABEL: check_i16:
 ;CHECK: vdup.16 {{.*}}, d{{..}}[3]
   %x = extractelement <8 x i16> %v, i32 3
   %1 = insertelement  <4 x i16> undef, i16 %x, i32 0
@@ -324,7 +324,7 @@ define <4 x i16> @check_i16(<8 x i16> %v) nounwind {
 }
 
 define <8 x i8> @check_i8(<16 x i8> %v) nounwind {
-;CHECK: check_i8:
+;CHECK-LABEL: check_i8:
 ;CHECK: vdup.8 {{.*}}, d{{..}}[3]
   %x = extractelement <16 x i8> %v, i32 3
   %1 = insertelement  <8  x i8> undef, i8 %x, i32 0
diff --git a/test/CodeGen/ARM/vector-extend-narrow.ll b/test/CodeGen/ARM/vector-extend-narrow.ll
index 22af797..f321896 100644
--- a/test/CodeGen/ARM/vector-extend-narrow.ll
+++ b/test/CodeGen/ARM/vector-extend-narrow.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
 
-; CHECK: f:
+; CHECK-LABEL: f:
 define float @f(<4 x i16>* nocapture %in) {
   ; CHECK: vldr
   ; CHECK: vmovl.u16
@@ -18,7 +18,7 @@ define float @f(<4 x i16>* nocapture %in) {
   ret float %7
 }
 
-; CHECK: g:
+; CHECK-LABEL: g:
 define float @g(<4 x i8>* nocapture %in) {
 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
 ; instructions is bad on some cores
@@ -39,7 +39,7 @@ define float @g(<4 x i8>* nocapture %in) {
   ret float %7
 }
 
-; CHECK: h:
+; CHECK-LABEL: h:
 define <4 x i8> @h(<4 x float> %v) {
   ; CHECK: vcvt.{{[us]}}32.f32
   ; CHECK: vmovn.i32
@@ -47,7 +47,7 @@ define <4 x i8> @h(<4 x float> %v) {
   ret <4 x i8> %1
 }
 
-; CHECK: i:
+; CHECK-LABEL: i:
 define <4 x i8> @i(<4 x i8>* %x) {
 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
 ; instructions is bad on some cores
@@ -62,7 +62,7 @@ define <4 x i8> @i(<4 x i8>* %x) {
   %2 = sdiv <4 x i8> zeroinitializer, %1
   ret <4 x i8> %2
 }
-; CHECK: j:
+; CHECK-LABEL: j:
 define <4 x i32> @j(<4 x i8>* %in) nounwind {
   ; CHECK: vld1
   ; CHECK: vmovl.u8
diff --git a/test/CodeGen/ARM/vfcmp.ll b/test/CodeGen/ARM/vfcmp.ll
index 6946d02..a23db7b 100644
--- a/test/CodeGen/ARM/vfcmp.ll
+++ b/test/CodeGen/ARM/vfcmp.ll
@@ -4,7 +4,7 @@
 
 ; une is implemented with VCEQ/VMVN
 define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcunef32:
+;CHECK-LABEL: vcunef32:
 ;CHECK: vceq.f32
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <2 x float>* %A
@@ -16,7 +16,7 @@ define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; olt is implemented with VCGT
 define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcoltf32:
+;CHECK-LABEL: vcoltf32:
 ;CHECK: vcgt.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -27,7 +27,7 @@ define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; ole is implemented with VCGE
 define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcolef32:
+;CHECK-LABEL: vcolef32:
 ;CHECK: vcge.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -38,7 +38,7 @@ define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; uge is implemented with VCGT/VMVN
 define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcugef32:
+;CHECK-LABEL: vcugef32:
 ;CHECK: vcgt.f32
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <2 x float>* %A
@@ -50,7 +50,7 @@ define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; ule is implemented with VCGT/VMVN
 define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vculef32:
+;CHECK-LABEL: vculef32:
 ;CHECK: vcgt.f32
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <2 x float>* %A
@@ -62,7 +62,7 @@ define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; ugt is implemented with VCGE/VMVN
 define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcugtf32:
+;CHECK-LABEL: vcugtf32:
 ;CHECK: vcge.f32
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <2 x float>* %A
@@ -74,7 +74,7 @@ define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; ult is implemented with VCGE/VMVN
 define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcultf32:
+;CHECK-LABEL: vcultf32:
 ;CHECK: vcge.f32
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <2 x float>* %A
@@ -86,7 +86,7 @@ define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; ueq is implemented with VCGT/VCGT/VORR/VMVN
 define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcueqf32:
+;CHECK-LABEL: vcueqf32:
 ;CHECK: vcgt.f32
 ;CHECK-NEXT: vcgt.f32
 ;CHECK-NEXT: vorr
@@ -100,7 +100,7 @@ define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; one is implemented with VCGT/VCGT/VORR
 define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vconef32:
+;CHECK-LABEL: vconef32:
 ;CHECK: vcgt.f32
 ;CHECK-NEXT: vcgt.f32
 ;CHECK-NEXT: vorr
@@ -113,7 +113,7 @@ define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; uno is implemented with VCGT/VCGE/VORR/VMVN
 define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcunof32:
+;CHECK-LABEL: vcunof32:
 ;CHECK: vcge.f32
 ;CHECK-NEXT: vcgt.f32
 ;CHECK-NEXT: vorr
@@ -127,7 +127,7 @@ define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; ord is implemented with VCGT/VCGE/VORR
 define <2 x i32> @vcordf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcordf32:
+;CHECK-LABEL: vcordf32:
 ;CHECK: vcge.f32
 ;CHECK-NEXT: vcgt.f32
 ;CHECK-NEXT: vorr
diff --git a/test/CodeGen/ARM/vget_lane.ll b/test/CodeGen/ARM/vget_lane.ll
index 806ec95..2518ee2 100644
--- a/test/CodeGen/ARM/vget_lane.ll
+++ b/test/CodeGen/ARM/vget_lane.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-
 target triple = "thumbv7-elf"
 
 define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
-;CHECK: vget_lanes8:
+;CHECK-LABEL: vget_lanes8:
 ;CHECK: vmov.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = extractelement <8 x i8> %tmp1, i32 1
@@ -12,7 +12,7 @@ define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
 }
 
 define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
-;CHECK: vget_lanes16:
+;CHECK-LABEL: vget_lanes16:
 ;CHECK: vmov.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = extractelement <4 x i16> %tmp1, i32 1
@@ -21,7 +21,7 @@ define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
 }
 
 define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
-;CHECK: vget_laneu8:
+;CHECK-LABEL: vget_laneu8:
 ;CHECK: vmov.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = extractelement <8 x i8> %tmp1, i32 1
@@ -30,7 +30,7 @@ define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
 }
 
 define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
-;CHECK: vget_laneu16:
+;CHECK-LABEL: vget_laneu16:
 ;CHECK: vmov.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = extractelement <4 x i16> %tmp1, i32 1
@@ -40,7 +40,7 @@ define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
 
 ; Do a vector add to keep the extraction from being done directly from memory.
 define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
-;CHECK: vget_lanei32:
+;CHECK-LABEL: vget_lanei32:
 ;CHECK: vmov.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = add <2 x i32> %tmp1, %tmp1
@@ -49,7 +49,7 @@ define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
 }
 
 define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
-;CHECK: vgetQ_lanes8:
+;CHECK-LABEL: vgetQ_lanes8:
 ;CHECK: vmov.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = extractelement <16 x i8> %tmp1, i32 1
@@ -58,7 +58,7 @@ define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
 }
 
 define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
-;CHECK: vgetQ_lanes16:
+;CHECK-LABEL: vgetQ_lanes16:
 ;CHECK: vmov.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = extractelement <8 x i16> %tmp1, i32 1
@@ -67,7 +67,7 @@ define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
 }
 
 define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
-;CHECK: vgetQ_laneu8:
+;CHECK-LABEL: vgetQ_laneu8:
 ;CHECK: vmov.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = extractelement <16 x i8> %tmp1, i32 1
@@ -76,7 +76,7 @@ define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
 }
 
 define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
-;CHECK: vgetQ_laneu16:
+;CHECK-LABEL: vgetQ_laneu16:
 ;CHECK: vmov.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = extractelement <8 x i16> %tmp1, i32 1
@@ -86,7 +86,7 @@ define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
 
 ; Do a vector add to keep the extraction from being done directly from memory.
 define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind {
-;CHECK: vgetQ_lanei32:
+;CHECK-LABEL: vgetQ_lanei32:
 ;CHECK: vmov.32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = add <4 x i32> %tmp1, %tmp1
@@ -159,7 +159,7 @@ return:                                           ; preds = %entry
 }
 
 define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind {
-;CHECK: vset_lane8:
+;CHECK-LABEL: vset_lane8:
 ;CHECK: vmov.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = insertelement <8 x i8> %tmp1, i8 %B, i32 1
@@ -167,7 +167,7 @@ define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind {
 }
 
 define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind {
-;CHECK: vset_lane16:
+;CHECK-LABEL: vset_lane16:
 ;CHECK: vmov.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = insertelement <4 x i16> %tmp1, i16 %B, i32 1
@@ -175,7 +175,7 @@ define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind {
 }
 
 define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind {
-;CHECK: vset_lane32:
+;CHECK-LABEL: vset_lane32:
 ;CHECK: vmov.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = insertelement <2 x i32> %tmp1, i32 %B, i32 1
@@ -183,7 +183,7 @@ define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind {
 }
 
 define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind {
-;CHECK: vsetQ_lane8:
+;CHECK-LABEL: vsetQ_lane8:
 ;CHECK: vmov.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = insertelement <16 x i8> %tmp1, i8 %B, i32 1
@@ -191,7 +191,7 @@ define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind {
 }
 
 define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
-;CHECK: vsetQ_lane16:
+;CHECK-LABEL: vsetQ_lane16:
 ;CHECK: vmov.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = insertelement <8 x i16> %tmp1, i16 %B, i32 1
@@ -199,7 +199,7 @@ define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
 }
 
 define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
-;CHECK: vsetQ_lane32:
+;CHECK-LABEL: vsetQ_lane32:
 ;CHECK: vmov.32 d{{.*}}[1], r1
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1
diff --git a/test/CodeGen/ARM/vhadd.ll b/test/CodeGen/ARM/vhadd.ll
index 379e062..9c2ed57 100644
--- a/test/CodeGen/ARM/vhadd.ll
+++ b/test/CodeGen/ARM/vhadd.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhadds8:
+;CHECK-LABEL: vhadds8:
 ;CHECK: vhadd.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhadds16:
+;CHECK-LABEL: vhadds16:
 ;CHECK: vhadd.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhadds32:
+;CHECK-LABEL: vhadds32:
 ;CHECK: vhadd.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhaddu8:
+;CHECK-LABEL: vhaddu8:
 ;CHECK: vhadd.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhaddu16:
+;CHECK-LABEL: vhaddu16:
 ;CHECK: vhadd.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhaddu32:
+;CHECK-LABEL: vhaddu32:
 ;CHECK: vhadd.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhaddQs8:
+;CHECK-LABEL: vhaddQs8:
 ;CHECK: vhadd.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -64,7 +64,7 @@ define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhaddQs16:
+;CHECK-LABEL: vhaddQs16:
 ;CHECK: vhadd.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -73,7 +73,7 @@ define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhaddQs32:
+;CHECK-LABEL: vhaddQs32:
 ;CHECK: vhadd.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -82,7 +82,7 @@ define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhaddQu8:
+;CHECK-LABEL: vhaddQu8:
 ;CHECK: vhadd.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -91,7 +91,7 @@ define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhaddQu16:
+;CHECK-LABEL: vhaddQu16:
 ;CHECK: vhadd.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhaddQu32:
+;CHECK-LABEL: vhaddQu32:
 ;CHECK: vhadd.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -125,7 +125,7 @@ declare <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16>, <8 x i16>) nounwind rea
 declare <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrhadds8:
+;CHECK-LABEL: vrhadds8:
 ;CHECK: vrhadd.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -134,7 +134,7 @@ define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrhadds16:
+;CHECK-LABEL: vrhadds16:
 ;CHECK: vrhadd.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -143,7 +143,7 @@ define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrhadds32:
+;CHECK-LABEL: vrhadds32:
 ;CHECK: vrhadd.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -152,7 +152,7 @@ define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrhaddu8:
+;CHECK-LABEL: vrhaddu8:
 ;CHECK: vrhadd.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -161,7 +161,7 @@ define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrhaddu16:
+;CHECK-LABEL: vrhaddu16:
 ;CHECK: vrhadd.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -170,7 +170,7 @@ define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrhaddu32:
+;CHECK-LABEL: vrhaddu32:
 ;CHECK: vrhadd.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -179,7 +179,7 @@ define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrhaddQs8:
+;CHECK-LABEL: vrhaddQs8:
 ;CHECK: vrhadd.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -188,7 +188,7 @@ define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrhaddQs16:
+;CHECK-LABEL: vrhaddQs16:
 ;CHECK: vrhadd.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -197,7 +197,7 @@ define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrhaddQs32:
+;CHECK-LABEL: vrhaddQs32:
 ;CHECK: vrhadd.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -206,7 +206,7 @@ define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrhaddQu8:
+;CHECK-LABEL: vrhaddQu8:
 ;CHECK: vrhadd.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -215,7 +215,7 @@ define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrhaddQu16:
+;CHECK-LABEL: vrhaddQu16:
 ;CHECK: vrhadd.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -224,7 +224,7 @@ define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vrhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrhaddQu32:
+;CHECK-LABEL: vrhaddQu32:
 ;CHECK: vrhadd.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
diff --git a/test/CodeGen/ARM/vhsub.ll b/test/CodeGen/ARM/vhsub.ll
index 0f0d027..4bc2e87 100644
--- a/test/CodeGen/ARM/vhsub.ll
+++ b/test/CodeGen/ARM/vhsub.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhsubs8:
+;CHECK-LABEL: vhsubs8:
 ;CHECK: vhsub.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhsubs16:
+;CHECK-LABEL: vhsubs16:
 ;CHECK: vhsub.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhsubs32:
+;CHECK-LABEL: vhsubs32:
 ;CHECK: vhsub.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhsubu8:
+;CHECK-LABEL: vhsubu8:
 ;CHECK: vhsub.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhsubu16:
+;CHECK-LABEL: vhsubu16:
 ;CHECK: vhsub.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhsubu32:
+;CHECK-LABEL: vhsubu32:
 ;CHECK: vhsub.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhsubQs8:
+;CHECK-LABEL: vhsubQs8:
 ;CHECK: vhsub.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -64,7 +64,7 @@ define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhsubQs16:
+;CHECK-LABEL: vhsubQs16:
 ;CHECK: vhsub.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -73,7 +73,7 @@ define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhsubQs32:
+;CHECK-LABEL: vhsubQs32:
 ;CHECK: vhsub.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -82,7 +82,7 @@ define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhsubQu8:
+;CHECK-LABEL: vhsubQu8:
 ;CHECK: vhsub.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -91,7 +91,7 @@ define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhsubQu16:
+;CHECK-LABEL: vhsubQu16:
 ;CHECK: vhsub.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vhsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhsubQu32:
+;CHECK-LABEL: vhsubQu32:
 ;CHECK: vhsub.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
diff --git a/test/CodeGen/ARM/vicmp.ll b/test/CodeGen/ARM/vicmp.ll
index 2d8cb89..0a8f103 100644
--- a/test/CodeGen/ARM/vicmp.ll
+++ b/test/CodeGen/ARM/vicmp.ll
@@ -7,7 +7,7 @@
 ; the other operations.
 
 define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcnei8:
+;CHECK-LABEL: vcnei8:
 ;CHECK: vceq.i8
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <8 x i8>* %A
@@ -18,7 +18,7 @@ define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcnei16:
+;CHECK-LABEL: vcnei16:
 ;CHECK: vceq.i16
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <4 x i16>* %A
@@ -29,7 +29,7 @@ define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcnei32:
+;CHECK-LABEL: vcnei32:
 ;CHECK: vceq.i32
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <2 x i32>* %A
@@ -40,7 +40,7 @@ define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcneQi8:
+;CHECK-LABEL: vcneQi8:
 ;CHECK: vceq.i8
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <16 x i8>* %A
@@ -51,7 +51,7 @@ define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcneQi16:
+;CHECK-LABEL: vcneQi16:
 ;CHECK: vceq.i16
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <8 x i16>* %A
@@ -62,7 +62,7 @@ define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcneQi32:
+;CHECK-LABEL: vcneQi32:
 ;CHECK: vceq.i32
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <4 x i32>* %A
@@ -73,7 +73,7 @@ define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcltQs8:
+;CHECK-LABEL: vcltQs8:
 ;CHECK: vcgt.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -83,7 +83,7 @@ define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcles16:
+;CHECK-LABEL: vcles16:
 ;CHECK: vcge.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -93,7 +93,7 @@ define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcltu16:
+;CHECK-LABEL: vcltu16:
 ;CHECK: vcgt.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -103,7 +103,7 @@ define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vcleQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcleQu32:
+;CHECK-LABEL: vcleQu32:
 ;CHECK: vcge.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll
index 994f05d..444d0d5 100644
--- a/test/CodeGen/ARM/vld1.ll
+++ b/test/CodeGen/ARM/vld1.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
 
 define <8 x i8> @vld1i8(i8* %A) nounwind {
-;CHECK: vld1i8:
+;CHECK-LABEL: vld1i8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld1.8 {d16}, [r0:64]
 	%tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16)
@@ -10,7 +10,7 @@ define <8 x i8> @vld1i8(i8* %A) nounwind {
 }
 
 define <4 x i16> @vld1i16(i16* %A) nounwind {
-;CHECK: vld1i16:
+;CHECK-LABEL: vld1i16:
 ;CHECK: vld1.16
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1)
@@ -19,7 +19,7 @@ define <4 x i16> @vld1i16(i16* %A) nounwind {
 
 ;Check for a post-increment updating load. 
 define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
-;CHECK: vld1i16_update:
+;CHECK-LABEL: vld1i16_update:
 ;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]!
 	%A = load i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
@@ -30,7 +30,7 @@ define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
 }
 
 define <2 x i32> @vld1i32(i32* %A) nounwind {
-;CHECK: vld1i32:
+;CHECK-LABEL: vld1i32:
 ;CHECK: vld1.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1)
@@ -39,7 +39,7 @@ define <2 x i32> @vld1i32(i32* %A) nounwind {
 
 ;Check for a post-increment updating load with register increment.
 define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind {
-;CHECK: vld1i32_update:
+;CHECK-LABEL: vld1i32_update:
 ;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}}
 	%A = load i32** %ptr
 	%tmp0 = bitcast i32* %A to i8*
@@ -50,7 +50,7 @@ define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind {
 }
 
 define <2 x float> @vld1f(float* %A) nounwind {
-;CHECK: vld1f:
+;CHECK-LABEL: vld1f:
 ;CHECK: vld1.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0, i32 1)
@@ -58,7 +58,7 @@ define <2 x float> @vld1f(float* %A) nounwind {
 }
 
 define <1 x i64> @vld1i64(i64* %A) nounwind {
-;CHECK: vld1i64:
+;CHECK-LABEL: vld1i64:
 ;CHECK: vld1.64
 	%tmp0 = bitcast i64* %A to i8*
 	%tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0, i32 1)
@@ -66,7 +66,7 @@ define <1 x i64> @vld1i64(i64* %A) nounwind {
 }
 
 define <16 x i8> @vld1Qi8(i8* %A) nounwind {
-;CHECK: vld1Qi8:
+;CHECK-LABEL: vld1Qi8:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vld1.8 {d16, d17}, [r0:64]
 	%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
@@ -75,7 +75,7 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwind {
 
 ;Check for a post-increment updating load.
 define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
-;CHECK: vld1Qi8_update:
+;CHECK-LABEL: vld1Qi8_update:
 ;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]!
 	%A = load i8** %ptr
 	%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
@@ -85,7 +85,7 @@ define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
 }
 
 define <8 x i16> @vld1Qi16(i16* %A) nounwind {
-;CHECK: vld1Qi16:
+;CHECK-LABEL: vld1Qi16:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vld1.16 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -94,7 +94,7 @@ define <8 x i16> @vld1Qi16(i16* %A) nounwind {
 }
 
 define <4 x i32> @vld1Qi32(i32* %A) nounwind {
-;CHECK: vld1Qi32:
+;CHECK-LABEL: vld1Qi32:
 ;CHECK: vld1.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %tmp0, i32 1)
@@ -102,7 +102,7 @@ define <4 x i32> @vld1Qi32(i32* %A) nounwind {
 }
 
 define <4 x float> @vld1Qf(float* %A) nounwind {
-;CHECK: vld1Qf:
+;CHECK-LABEL: vld1Qf:
 ;CHECK: vld1.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0, i32 1)
@@ -110,7 +110,7 @@ define <4 x float> @vld1Qf(float* %A) nounwind {
 }
 
 define <2 x i64> @vld1Qi64(i64* %A) nounwind {
-;CHECK: vld1Qi64:
+;CHECK-LABEL: vld1Qi64:
 ;CHECK: vld1.64
 	%tmp0 = bitcast i64* %A to i8*
 	%tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0, i32 1)
diff --git a/test/CodeGen/ARM/vld2.ll b/test/CodeGen/ARM/vld2.ll
index caa016e..fddafea 100644
--- a/test/CodeGen/ARM/vld2.ll
+++ b/test/CodeGen/ARM/vld2.ll
@@ -12,7 +12,7 @@
 %struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
 
 define <8 x i8> @vld2i8(i8* %A) nounwind {
-;CHECK: vld2i8:
+;CHECK-LABEL: vld2i8:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vld2.8 {d16, d17}, [r0:64]
 	%tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 8)
@@ -23,7 +23,7 @@ define <8 x i8> @vld2i8(i8* %A) nounwind {
 }
 
 define <4 x i16> @vld2i16(i16* %A) nounwind {
-;CHECK: vld2i16:
+;CHECK-LABEL: vld2i16:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vld2.16 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -35,7 +35,7 @@ define <4 x i16> @vld2i16(i16* %A) nounwind {
 }
 
 define <2 x i32> @vld2i32(i32* %A) nounwind {
-;CHECK: vld2i32:
+;CHECK-LABEL: vld2i32:
 ;CHECK: vld2.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8* %tmp0, i32 1)
@@ -46,7 +46,7 @@ define <2 x i32> @vld2i32(i32* %A) nounwind {
 }
 
 define <2 x float> @vld2f(float* %A) nounwind {
-;CHECK: vld2f:
+;CHECK-LABEL: vld2f:
 ;CHECK: vld2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 1)
@@ -58,7 +58,7 @@ define <2 x float> @vld2f(float* %A) nounwind {
 
 ;Check for a post-increment updating load. 
 define <2 x float> @vld2f_update(float** %ptr) nounwind {
-;CHECK: vld2f_update:
+;CHECK-LABEL: vld2f_update:
 ;CHECK: vld2.32 {d16, d17}, [r1]!
 	%A = load float** %ptr
 	%tmp0 = bitcast float* %A to i8*
@@ -72,7 +72,7 @@ define <2 x float> @vld2f_update(float** %ptr) nounwind {
 }
 
 define <1 x i64> @vld2i64(i64* %A) nounwind {
-;CHECK: vld2i64:
+;CHECK-LABEL: vld2i64:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vld1.64 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i64* %A to i8*
@@ -84,7 +84,7 @@ define <1 x i64> @vld2i64(i64* %A) nounwind {
 }
 
 define <16 x i8> @vld2Qi8(i8* %A) nounwind {
-;CHECK: vld2Qi8:
+;CHECK-LABEL: vld2Qi8:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64]
 	%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 8)
@@ -96,7 +96,7 @@ define <16 x i8> @vld2Qi8(i8* %A) nounwind {
 
 ;Check for a post-increment updating load with register increment.
 define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind {
-;CHECK: vld2Qi8_update:
+;CHECK-LABEL: vld2Qi8_update:
 ;CHECK: vld2.8 {d16, d17, d18, d19}, [r2:128], r1
 	%A = load i8** %ptr
 	%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 16)
@@ -109,7 +109,7 @@ define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind {
 }
 
 define <8 x i16> @vld2Qi16(i16* %A) nounwind {
-;CHECK: vld2Qi16:
+;CHECK-LABEL: vld2Qi16:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -121,7 +121,7 @@ define <8 x i16> @vld2Qi16(i16* %A) nounwind {
 }
 
 define <4 x i32> @vld2Qi32(i32* %A) nounwind {
-;CHECK: vld2Qi32:
+;CHECK-LABEL: vld2Qi32:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i32* %A to i8*
@@ -133,7 +133,7 @@ define <4 x i32> @vld2Qi32(i32* %A) nounwind {
 }
 
 define <4 x float> @vld2Qf(float* %A) nounwind {
-;CHECK: vld2Qf:
+;CHECK-LABEL: vld2Qf:
 ;CHECK: vld2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(i8* %tmp0, i32 1)
diff --git a/test/CodeGen/ARM/vld3.ll b/test/CodeGen/ARM/vld3.ll
index ad63e1f..400541f 100644
--- a/test/CodeGen/ARM/vld3.ll
+++ b/test/CodeGen/ARM/vld3.ll
@@ -13,7 +13,7 @@
 %struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
 
 define <8 x i8> @vld3i8(i8* %A) nounwind {
-;CHECK: vld3i8:
+;CHECK-LABEL: vld3i8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld3.8 {d16, d17, d18}, [r0:64]
 	%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32)
@@ -24,7 +24,7 @@ define <8 x i8> @vld3i8(i8* %A) nounwind {
 }
 
 define <4 x i16> @vld3i16(i16* %A) nounwind {
-;CHECK: vld3i16:
+;CHECK-LABEL: vld3i16:
 ;CHECK: vld3.16
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1)
@@ -36,7 +36,7 @@ define <4 x i16> @vld3i16(i16* %A) nounwind {
 
 ;Check for a post-increment updating load with register increment.
 define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind {
-;CHECK: vld3i16_update:
+;CHECK-LABEL: vld3i16_update:
 ;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}}
 	%A = load i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
@@ -50,7 +50,7 @@ define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind {
 }
 
 define <2 x i32> @vld3i32(i32* %A) nounwind {
-;CHECK: vld3i32:
+;CHECK-LABEL: vld3i32:
 ;CHECK: vld3.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %tmp0, i32 1)
@@ -61,7 +61,7 @@ define <2 x i32> @vld3i32(i32* %A) nounwind {
 }
 
 define <2 x float> @vld3f(float* %A) nounwind {
-;CHECK: vld3f:
+;CHECK-LABEL: vld3f:
 ;CHECK: vld3.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8* %tmp0, i32 1)
@@ -72,7 +72,7 @@ define <2 x float> @vld3f(float* %A) nounwind {
 }
 
 define <1 x i64> @vld3i64(i64* %A) nounwind {
-;CHECK: vld3i64:
+;CHECK-LABEL: vld3i64:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld1.64 {d16, d17, d18}, [r0:64]
 	%tmp0 = bitcast i64* %A to i8*
@@ -84,7 +84,7 @@ define <1 x i64> @vld3i64(i64* %A) nounwind {
 }
 
 define <16 x i8> @vld3Qi8(i8* %A) nounwind {
-;CHECK: vld3Qi8:
+;CHECK-LABEL: vld3Qi8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld3.8 {d16, d18, d20}, [r0:64]!
 ;CHECK: vld3.8 {d17, d19, d21}, [r0:64]
@@ -96,7 +96,7 @@ define <16 x i8> @vld3Qi8(i8* %A) nounwind {
 }
 
 define <8 x i16> @vld3Qi16(i16* %A) nounwind {
-;CHECK: vld3Qi16:
+;CHECK-LABEL: vld3Qi16:
 ;CHECK: vld3.16
 ;CHECK: vld3.16
 	%tmp0 = bitcast i16* %A to i8*
@@ -108,7 +108,7 @@ define <8 x i16> @vld3Qi16(i16* %A) nounwind {
 }
 
 define <4 x i32> @vld3Qi32(i32* %A) nounwind {
-;CHECK: vld3Qi32:
+;CHECK-LABEL: vld3Qi32:
 ;CHECK: vld3.32
 ;CHECK: vld3.32
 	%tmp0 = bitcast i32* %A to i8*
@@ -121,7 +121,7 @@ define <4 x i32> @vld3Qi32(i32* %A) nounwind {
 
 ;Check for a post-increment updating load. 
 define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind {
-;CHECK: vld3Qi32_update:
+;CHECK-LABEL: vld3Qi32_update:
 ;CHECK: vld3.32 {d16, d18, d20}, [r[[R:[0-9]+]]]!
 ;CHECK: vld3.32 {d17, d19, d21}, [r[[R]]]!
 	%A = load i32** %ptr
@@ -136,7 +136,7 @@ define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind {
 }
 
 define <4 x float> @vld3Qf(float* %A) nounwind {
-;CHECK: vld3Qf:
+;CHECK-LABEL: vld3Qf:
 ;CHECK: vld3.32
 ;CHECK: vld3.32
 	%tmp0 = bitcast float* %A to i8*
diff --git a/test/CodeGen/ARM/vld4.ll b/test/CodeGen/ARM/vld4.ll
index 9ee5fe4..f7376b5 100644
--- a/test/CodeGen/ARM/vld4.ll
+++ b/test/CodeGen/ARM/vld4.ll
@@ -12,7 +12,7 @@
 %struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
 
 define <8 x i8> @vld4i8(i8* %A) nounwind {
-;CHECK: vld4i8:
+;CHECK-LABEL: vld4i8:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64]
 	%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 8)
@@ -24,7 +24,7 @@ define <8 x i8> @vld4i8(i8* %A) nounwind {
 
 ;Check for a post-increment updating load with register increment.
 define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
-;CHECK: vld4i8_update:
+;CHECK-LABEL: vld4i8_update:
 ;CHECK: vld4.8 {d16, d17, d18, d19}, [r2:128], r1
 	%A = load i8** %ptr
 	%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16)
@@ -37,7 +37,7 @@ define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
 }
 
 define <4 x i16> @vld4i16(i16* %A) nounwind {
-;CHECK: vld4i16:
+;CHECK-LABEL: vld4i16:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -49,7 +49,7 @@ define <4 x i16> @vld4i16(i16* %A) nounwind {
 }
 
 define <2 x i32> @vld4i32(i32* %A) nounwind {
-;CHECK: vld4i32:
+;CHECK-LABEL: vld4i32:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i32* %A to i8*
@@ -61,7 +61,7 @@ define <2 x i32> @vld4i32(i32* %A) nounwind {
 }
 
 define <2 x float> @vld4f(float* %A) nounwind {
-;CHECK: vld4f:
+;CHECK-LABEL: vld4f:
 ;CHECK: vld4.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8* %tmp0, i32 1)
@@ -72,7 +72,7 @@ define <2 x float> @vld4f(float* %A) nounwind {
 }
 
 define <1 x i64> @vld4i64(i64* %A) nounwind {
-;CHECK: vld4i64:
+;CHECK-LABEL: vld4i64:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld1.64 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i64* %A to i8*
@@ -84,7 +84,7 @@ define <1 x i64> @vld4i64(i64* %A) nounwind {
 }
 
 define <16 x i8> @vld4Qi8(i8* %A) nounwind {
-;CHECK: vld4Qi8:
+;CHECK-LABEL: vld4Qi8:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]!
 ;CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]
@@ -96,7 +96,7 @@ define <16 x i8> @vld4Qi8(i8* %A) nounwind {
 }
 
 define <8 x i16> @vld4Qi16(i16* %A) nounwind {
-;CHECK: vld4Qi16:
+;CHECK-LABEL: vld4Qi16:
 ;Check for no alignment specifier.
 ;CHECK: vld4.16 {d16, d18, d20, d22}, [r0]!
 ;CHECK: vld4.16 {d17, d19, d21, d23}, [r0]
@@ -110,7 +110,7 @@ define <8 x i16> @vld4Qi16(i16* %A) nounwind {
 
 ;Check for a post-increment updating load. 
 define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind {
-;CHECK: vld4Qi16_update:
+;CHECK-LABEL: vld4Qi16_update:
 ;CHECK: vld4.16 {d16, d18, d20, d22}, [r1:64]!
 ;CHECK: vld4.16 {d17, d19, d21, d23}, [r1:64]!
 	%A = load i16** %ptr
@@ -125,7 +125,7 @@ define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind {
 }
 
 define <4 x i32> @vld4Qi32(i32* %A) nounwind {
-;CHECK: vld4Qi32:
+;CHECK-LABEL: vld4Qi32:
 ;CHECK: vld4.32
 ;CHECK: vld4.32
 	%tmp0 = bitcast i32* %A to i8*
@@ -137,7 +137,7 @@ define <4 x i32> @vld4Qi32(i32* %A) nounwind {
 }
 
 define <4 x float> @vld4Qf(float* %A) nounwind {
-;CHECK: vld4Qf:
+;CHECK-LABEL: vld4Qf:
 ;CHECK: vld4.32
 ;CHECK: vld4.32
 	%tmp0 = bitcast float* %A to i8*
diff --git a/test/CodeGen/ARM/vlddup.ll b/test/CodeGen/ARM/vlddup.ll
index 7c7319c..5509f3e 100644
--- a/test/CodeGen/ARM/vlddup.ll
+++ b/test/CodeGen/ARM/vlddup.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vld1dupi8(i8* %A) nounwind {
-;CHECK: vld1dupi8:
+;CHECK-LABEL: vld1dupi8:
 ;Check the (default) alignment value.
 ;CHECK: vld1.8 {d16[]}, [r0]
 	%tmp1 = load i8* %A, align 8
@@ -11,7 +11,7 @@ define <8 x i8> @vld1dupi8(i8* %A) nounwind {
 }
 
 define <4 x i16> @vld1dupi16(i16* %A) nounwind {
-;CHECK: vld1dupi16:
+;CHECK-LABEL: vld1dupi16:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vld1.16 {d16[]}, [r0:16]
 	%tmp1 = load i16* %A, align 8
@@ -21,7 +21,7 @@ define <4 x i16> @vld1dupi16(i16* %A) nounwind {
 }
 
 define <2 x i32> @vld1dupi32(i32* %A) nounwind {
-;CHECK: vld1dupi32:
+;CHECK-LABEL: vld1dupi32:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vld1.32 {d16[]}, [r0:32]
 	%tmp1 = load i32* %A, align 8
@@ -31,7 +31,7 @@ define <2 x i32> @vld1dupi32(i32* %A) nounwind {
 }
 
 define <2 x float> @vld1dupf(float* %A) nounwind {
-;CHECK: vld1dupf:
+;CHECK-LABEL: vld1dupf:
 ;CHECK: vld1.32 {d16[]}, [r0:32]
 	%tmp0 = load float* %A
         %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
@@ -40,7 +40,7 @@ define <2 x float> @vld1dupf(float* %A) nounwind {
 }
 
 define <16 x i8> @vld1dupQi8(i8* %A) nounwind {
-;CHECK: vld1dupQi8:
+;CHECK-LABEL: vld1dupQi8:
 ;Check the (default) alignment value.
 ;CHECK: vld1.8 {d16[], d17[]}, [r0]
 	%tmp1 = load i8* %A, align 8
@@ -50,7 +50,7 @@ define <16 x i8> @vld1dupQi8(i8* %A) nounwind {
 }
 
 define <4 x float> @vld1dupQf(float* %A) nounwind {
-;CHECK: vld1dupQf:
+;CHECK-LABEL: vld1dupQf:
 ;CHECK: vld1.32 {d16[], d17[]}, [r0:32]
         %tmp0 = load float* %A
         %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
@@ -63,7 +63,7 @@ define <4 x float> @vld1dupQf(float* %A) nounwind {
 %struct.__neon_int2x32x2_t = type { <2 x i32>, <2 x i32> }
 
 define <8 x i8> @vld2dupi8(i8* %A) nounwind {
-;CHECK: vld2dupi8:
+;CHECK-LABEL: vld2dupi8:
 ;Check the (default) alignment value.
 ;CHECK: vld2.8 {d16[], d17[]}, [r0]
 	%tmp0 = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
@@ -76,7 +76,7 @@ define <8 x i8> @vld2dupi8(i8* %A) nounwind {
 }
 
 define <4 x i16> @vld2dupi16(i8* %A) nounwind {
-;CHECK: vld2dupi16:
+;CHECK-LABEL: vld2dupi16:
 ;Check that a power-of-two alignment smaller than the total size of the memory
 ;being loaded is ignored.
 ;CHECK: vld2.16 {d16[], d17[]}, [r0]
@@ -91,7 +91,7 @@ define <4 x i16> @vld2dupi16(i8* %A) nounwind {
 
 ;Check for a post-increment updating load. 
 define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind {
-;CHECK: vld2dupi16_update:
+;CHECK-LABEL: vld2dupi16_update:
 ;CHECK: vld2.16 {d16[], d17[]}, [r1]!
 	%A = load i16** %ptr
         %A2 = bitcast i16* %A to i8*
@@ -107,7 +107,7 @@ define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind {
 }
 
 define <2 x i32> @vld2dupi32(i8* %A) nounwind {
-;CHECK: vld2dupi32:
+;CHECK-LABEL: vld2dupi32:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld2.32 {d16[], d17[]}, [r0:64]
 	%tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16)
@@ -128,7 +128,7 @@ declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8*, <2 x i32>,
 
 ;Check for a post-increment updating load with register increment.
 define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind {
-;CHECK: vld3dupi8_update:
+;CHECK-LABEL: vld3dupi8_update:
 ;CHECK: vld3.8 {d16[], d17[], d18[]}, [r2], r1
 	%A = load i8** %ptr
 	%tmp0 = tail call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 8)
@@ -146,7 +146,7 @@ define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind {
 }
 
 define <4 x i16> @vld3dupi16(i8* %A) nounwind {
-;CHECK: vld3dupi16:
+;CHECK-LABEL: vld3dupi16:
 ;Check the (default) alignment value. VLD3 does not support alignment.
 ;CHECK: vld3.16 {d16[], d17[], d18[]}, [r0]
 	%tmp0 = tail call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 8)
@@ -169,7 +169,7 @@ declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8*, <4 x i16>,
 
 ;Check for a post-increment updating load.
 define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind {
-;CHECK: vld4dupi16_update:
+;CHECK-LABEL: vld4dupi16_update:
 ;CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r1]!
 	%A = load i16** %ptr
         %A2 = bitcast i16* %A to i8*
@@ -191,7 +191,7 @@ define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind {
 }
 
 define <2 x i32> @vld4dupi32(i8* %A) nounwind {
-;CHECK: vld4dupi32:
+;CHECK-LABEL: vld4dupi32:
 ;Check the alignment value.  An 8-byte alignment is allowed here even though
 ;it is smaller than the total size of the memory being loaded.
 ;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r0:64]
diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll
index f35fa92..a378555 100644
--- a/test/CodeGen/ARM/vldlane.ll
+++ b/test/CodeGen/ARM/vldlane.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
 
 define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld1lanei8:
+;CHECK-LABEL: vld1lanei8:
 ;Check the (default) alignment value.
 ;CHECK: vld1.8 {d16[3]}, [r0]
 	%tmp1 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld1lanei16:
+;CHECK-LABEL: vld1lanei16:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vld1.16 {d16[2]}, [r0:16]
 	%tmp1 = load <4 x i16>* %B
@@ -22,7 +22,7 @@ define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld1lanei32:
+;CHECK-LABEL: vld1lanei32:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vld1.32 {d16[1]}, [r0:32]
 	%tmp1 = load <2 x i32>* %B
@@ -32,7 +32,7 @@ define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld1lanei32a32:
+;CHECK-LABEL: vld1lanei32a32:
 ;Check the alignment value.  Legal values are none or :32.
 ;CHECK: vld1.32 {d16[1]}, [r0:32]
 	%tmp1 = load <2 x i32>* %B
@@ -42,7 +42,7 @@ define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld1lanef:
+;CHECK-LABEL: vld1lanef:
 ;CHECK: vld1.32 {d16[1]}, [r0:32]
 	%tmp1 = load <2 x float>* %B
 	%tmp2 = load float* %A, align 4
@@ -51,7 +51,7 @@ define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vld1laneQi8:
+;CHECK-LABEL: vld1laneQi8:
 ;CHECK: vld1.8 {d17[1]}, [r0]
 	%tmp1 = load <16 x i8>* %B
 	%tmp2 = load i8* %A, align 8
@@ -60,7 +60,7 @@ define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld1laneQi16:
+;CHECK-LABEL: vld1laneQi16:
 ;CHECK: vld1.16 {d17[1]}, [r0:16]
 	%tmp1 = load <8 x i16>* %B
 	%tmp2 = load i16* %A, align 8
@@ -69,7 +69,7 @@ define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld1laneQi32:
+;CHECK-LABEL: vld1laneQi32:
 ;CHECK: vld1.32 {d17[1]}, [r0:32]
 	%tmp1 = load <4 x i32>* %B
 	%tmp2 = load i32* %A, align 8
@@ -78,7 +78,7 @@ define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld1laneQf:
+;CHECK-LABEL: vld1laneQf:
 ;CHECK: vld1.32 {d16[0]}, [r0:32]
 	%tmp1 = load <4 x float>* %B
 	%tmp2 = load float* %A
@@ -96,7 +96,7 @@ define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind {
 %struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
 
 define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld2lanei8:
+;CHECK-LABEL: vld2lanei8:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vld2.8 {d16[1], d17[1]}, [r0:16]
 	%tmp1 = load <8 x i8>* %B
@@ -108,7 +108,7 @@ define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld2lanei16:
+;CHECK-LABEL: vld2lanei16:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vld2.16 {d16[1], d17[1]}, [r0:32]
 	%tmp0 = bitcast i16* %A to i8*
@@ -121,7 +121,7 @@ define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld2lanei32:
+;CHECK-LABEL: vld2lanei32:
 ;CHECK: vld2.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
@@ -134,7 +134,7 @@ define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
 
 ;Check for a post-increment updating load.
 define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind {
-;CHECK: vld2lanei32_update:
+;CHECK-LABEL: vld2lanei32_update:
 ;CHECK: vld2.32 {d16[1], d17[1]}, [{{r[0-9]+}}]!
 	%A = load i32** %ptr
 	%tmp0 = bitcast i32* %A to i8*
@@ -149,7 +149,7 @@ define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld2lanef:
+;CHECK-LABEL: vld2lanef:
 ;CHECK: vld2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -161,7 +161,7 @@ define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld2laneQi16:
+;CHECK-LABEL: vld2laneQi16:
 ;Check the (default) alignment.
 ;CHECK: vld2.16 {d17[1], d19[1]}, [{{r[0-9]+}}]
 	%tmp0 = bitcast i16* %A to i8*
@@ -174,7 +174,7 @@ define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld2laneQi32:
+;CHECK-LABEL: vld2laneQi32:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld2.32 {d17[0], d19[0]}, [{{r[0-9]+}}:64]
 	%tmp0 = bitcast i32* %A to i8*
@@ -187,7 +187,7 @@ define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld2laneQf:
+;CHECK-LABEL: vld2laneQf:
 ;CHECK: vld2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
@@ -217,7 +217,7 @@ declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8*, <4 x flo
 %struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
 
 define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld3lanei8:
+;CHECK-LABEL: vld3lanei8:
 ;CHECK: vld3.8
 	%tmp1 = load <8 x i8>* %B
 	%tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
@@ -230,7 +230,7 @@ define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld3lanei16:
+;CHECK-LABEL: vld3lanei16:
 ;Check the (default) alignment value.  VLD3 does not support alignment.
 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}]
 	%tmp0 = bitcast i16* %A to i8*
@@ -245,7 +245,7 @@ define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld3lanei32:
+;CHECK-LABEL: vld3lanei32:
 ;CHECK: vld3.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
@@ -259,7 +259,7 @@ define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld3lanef:
+;CHECK-LABEL: vld3lanef:
 ;CHECK: vld3.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -273,7 +273,7 @@ define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld3laneQi16:
+;CHECK-LABEL: vld3laneQi16:
 ;Check the (default) alignment value.  VLD3 does not support alignment.
 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}]
 	%tmp0 = bitcast i16* %A to i8*
@@ -289,7 +289,7 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 
 ;Check for a post-increment updating load with register increment.
 define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
-;CHECK: vld3laneQi16_update:
+;CHECK-LABEL: vld3laneQi16_update:
 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}], {{r[0-9]+}}
 	%A = load i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
@@ -306,7 +306,7 @@ define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounw
 }
 
 define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld3laneQi32:
+;CHECK-LABEL: vld3laneQi32:
 ;CHECK: vld3.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <4 x i32>* %B
@@ -320,7 +320,7 @@ define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld3laneQf:
+;CHECK-LABEL: vld3laneQf:
 ;CHECK: vld3.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
@@ -352,7 +352,7 @@ declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8*, <4 x flo
 %struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
 
 define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld4lanei8:
+;CHECK-LABEL: vld4lanei8:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vld4.8 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}:32]
 	%tmp1 = load <8 x i8>* %B
@@ -369,7 +369,7 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
 
 ;Check for a post-increment updating load.
 define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
-;CHECK: vld4lanei8_update:
+;CHECK-LABEL: vld4lanei8_update:
 ;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:32]!
 	%A = load i8** %ptr
 	%tmp1 = load <8 x i8>* %B
@@ -387,7 +387,7 @@ define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld4lanei16:
+;CHECK-LABEL: vld4lanei16:
 ;Check that a power-of-two alignment smaller than the total size of the memory
 ;being loaded is ignored.
 ;CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}]
@@ -405,7 +405,7 @@ define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld4lanei32:
+;CHECK-LABEL: vld4lanei32:
 ;Check the alignment value.  An 8-byte alignment is allowed here even though
 ;it is smaller than the total size of the memory being loaded.
 ;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:64]
@@ -423,7 +423,7 @@ define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld4lanef:
+;CHECK-LABEL: vld4lanef:
 ;CHECK: vld4.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -439,7 +439,7 @@ define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld4laneQi16:
+;CHECK-LABEL: vld4laneQi16:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [{{r[0-9]+}}:64]
 	%tmp0 = bitcast i16* %A to i8*
@@ -456,7 +456,7 @@ define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld4laneQi32:
+;CHECK-LABEL: vld4laneQi32:
 ;Check the (default) alignment.
 ;CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [{{r[0-9]+}}]
 	%tmp0 = bitcast i32* %A to i8*
@@ -473,7 +473,7 @@ define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld4laneQf:
+;CHECK-LABEL: vld4laneQf:
 ;CHECK: vld4.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
diff --git a/test/CodeGen/ARM/vminmax.ll b/test/CodeGen/ARM/vminmax.ll
index e3527c1..81f4578 100644
--- a/test/CodeGen/ARM/vminmax.ll
+++ b/test/CodeGen/ARM/vminmax.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmins8:
+;CHECK-LABEL: vmins8:
 ;CHECK: vmin.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmins16:
+;CHECK-LABEL: vmins16:
 ;CHECK: vmin.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmins32:
+;CHECK-LABEL: vmins32:
 ;CHECK: vmin.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vminu8:
+;CHECK-LABEL: vminu8:
 ;CHECK: vmin.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vminu16:
+;CHECK-LABEL: vminu16:
 ;CHECK: vmin.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vminu32:
+;CHECK-LABEL: vminu32:
 ;CHECK: vmin.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vminf32:
+;CHECK-LABEL: vminf32:
 ;CHECK: vmin.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -64,7 +64,7 @@ define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vminQs8:
+;CHECK-LABEL: vminQs8:
 ;CHECK: vmin.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -73,7 +73,7 @@ define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vminQs16:
+;CHECK-LABEL: vminQs16:
 ;CHECK: vmin.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -82,7 +82,7 @@ define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vminQs32:
+;CHECK-LABEL: vminQs32:
 ;CHECK: vmin.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -91,7 +91,7 @@ define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vminQu8:
+;CHECK-LABEL: vminQu8:
 ;CHECK: vmin.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -100,7 +100,7 @@ define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vminQu16:
+;CHECK-LABEL: vminQu16:
 ;CHECK: vmin.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -109,7 +109,7 @@ define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vminQu32:
+;CHECK-LABEL: vminQu32:
 ;CHECK: vmin.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -118,7 +118,7 @@ define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vminQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vminQf32:
+;CHECK-LABEL: vminQf32:
 ;CHECK: vmin.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -147,7 +147,7 @@ declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind read
 declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
 
 define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmaxs8:
+;CHECK-LABEL: vmaxs8:
 ;CHECK: vmax.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -156,7 +156,7 @@ define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmaxs16:
+;CHECK-LABEL: vmaxs16:
 ;CHECK: vmax.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -165,7 +165,7 @@ define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmaxs32:
+;CHECK-LABEL: vmaxs32:
 ;CHECK: vmax.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -174,7 +174,7 @@ define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmaxu8:
+;CHECK-LABEL: vmaxu8:
 ;CHECK: vmax.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -183,7 +183,7 @@ define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmaxu16:
+;CHECK-LABEL: vmaxu16:
 ;CHECK: vmax.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -192,7 +192,7 @@ define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmaxu32:
+;CHECK-LABEL: vmaxu32:
 ;CHECK: vmax.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -201,7 +201,7 @@ define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vmaxf32:
+;CHECK-LABEL: vmaxf32:
 ;CHECK: vmax.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -210,7 +210,7 @@ define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmaxQs8:
+;CHECK-LABEL: vmaxQs8:
 ;CHECK: vmax.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -219,7 +219,7 @@ define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vmaxQs16:
+;CHECK-LABEL: vmaxQs16:
 ;CHECK: vmax.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -228,7 +228,7 @@ define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vmaxQs32:
+;CHECK-LABEL: vmaxQs32:
 ;CHECK: vmax.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -237,7 +237,7 @@ define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmaxQu8:
+;CHECK-LABEL: vmaxQu8:
 ;CHECK: vmax.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -246,7 +246,7 @@ define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vmaxQu16:
+;CHECK-LABEL: vmaxQu16:
 ;CHECK: vmax.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -255,7 +255,7 @@ define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vmaxQu32:
+;CHECK-LABEL: vmaxQu32:
 ;CHECK: vmax.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -264,7 +264,7 @@ define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vmaxQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vmaxQf32:
+;CHECK-LABEL: vmaxQf32:
 ;CHECK: vmax.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
diff --git a/test/CodeGen/ARM/vmla.ll b/test/CodeGen/ARM/vmla.ll
index 9c6b210..caf6556 100644
--- a/test/CodeGen/ARM/vmla.ll
+++ b/test/CodeGen/ARM/vmla.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
-;CHECK: vmlai8:
+;CHECK-LABEL: vmlai8:
 ;CHECK: vmla.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
 }
 
 define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlai16:
+;CHECK-LABEL: vmlai16:
 ;CHECK: vmla.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -23,7 +23,7 @@ define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlai32:
+;CHECK-LABEL: vmlai32:
 ;CHECK: vmla.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -34,7 +34,7 @@ define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK: vmlaf32:
+;CHECK-LABEL: vmlaf32:
 ;CHECK: vmla.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -45,7 +45,7 @@ define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n
 }
 
 define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
-;CHECK: vmlaQi8:
+;CHECK-LABEL: vmlaQi8:
 ;CHECK: vmla.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -56,7 +56,7 @@ define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind
 }
 
 define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vmlaQi16:
+;CHECK-LABEL: vmlaQi16:
 ;CHECK: vmla.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -67,7 +67,7 @@ define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
 }
 
 define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vmlaQi32:
+;CHECK-LABEL: vmlaQi32:
 ;CHECK: vmla.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -78,7 +78,7 @@ define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind
 }
 
 define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK: vmlaQf32:
+;CHECK-LABEL: vmlaQf32:
 ;CHECK: vmla.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -89,7 +89,7 @@ define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C)
 }
 
 define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlals8:
+;CHECK-LABEL: vmlals8:
 ;CHECK: vmlal.s8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -102,7 +102,7 @@ define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlals16:
+;CHECK-LABEL: vmlals16:
 ;CHECK: vmlal.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -115,7 +115,7 @@ define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlals32:
+;CHECK-LABEL: vmlals32:
 ;CHECK: vmlal.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -128,7 +128,7 @@ define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlalu8:
+;CHECK-LABEL: vmlalu8:
 ;CHECK: vmlal.u8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -141,7 +141,7 @@ define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlalu16:
+;CHECK-LABEL: vmlalu16:
 ;CHECK: vmlal.u16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -154,7 +154,7 @@ define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i64> @vmlalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlalu32:
+;CHECK-LABEL: vmlalu32:
 ;CHECK: vmlal.u32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
diff --git a/test/CodeGen/ARM/vmls.ll b/test/CodeGen/ARM/vmls.ll
index 65e7fe4..61f3424 100644
--- a/test/CodeGen/ARM/vmls.ll
+++ b/test/CodeGen/ARM/vmls.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
-;CHECK: vmlsi8:
+;CHECK-LABEL: vmlsi8:
 ;CHECK: vmls.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
 }
 
 define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlsi16:
+;CHECK-LABEL: vmlsi16:
 ;CHECK: vmls.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -23,7 +23,7 @@ define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlsi32:
+;CHECK-LABEL: vmlsi32:
 ;CHECK: vmls.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -34,7 +34,7 @@ define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK: vmlsf32:
+;CHECK-LABEL: vmlsf32:
 ;CHECK: vmls.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -45,7 +45,7 @@ define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n
 }
 
 define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
-;CHECK: vmlsQi8:
+;CHECK-LABEL: vmlsQi8:
 ;CHECK: vmls.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -56,7 +56,7 @@ define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind
 }
 
 define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vmlsQi16:
+;CHECK-LABEL: vmlsQi16:
 ;CHECK: vmls.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -67,7 +67,7 @@ define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
 }
 
 define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vmlsQi32:
+;CHECK-LABEL: vmlsQi32:
 ;CHECK: vmls.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -78,7 +78,7 @@ define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind
 }
 
 define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK: vmlsQf32:
+;CHECK-LABEL: vmlsQf32:
 ;CHECK: vmls.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -89,7 +89,7 @@ define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C)
 }
 
 define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlsls8:
+;CHECK-LABEL: vmlsls8:
 ;CHECK: vmlsl.s8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -102,7 +102,7 @@ define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlsls16:
+;CHECK-LABEL: vmlsls16:
 ;CHECK: vmlsl.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -115,7 +115,7 @@ define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlsls32:
+;CHECK-LABEL: vmlsls32:
 ;CHECK: vmlsl.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -128,7 +128,7 @@ define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlslu8:
+;CHECK-LABEL: vmlslu8:
 ;CHECK: vmlsl.u8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -141,7 +141,7 @@ define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlslu16:
+;CHECK-LABEL: vmlslu16:
 ;CHECK: vmlsl.u16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -154,7 +154,7 @@ define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i64> @vmlslu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlslu32:
+;CHECK-LABEL: vmlslu32:
 ;CHECK: vmlsl.u32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll
index 0c23879..2b277a2 100644
--- a/test/CodeGen/ARM/vmov.ll
+++ b/test/CodeGen/ARM/vmov.ll
@@ -1,169 +1,169 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @v_movi8() nounwind {
-;CHECK: v_movi8:
+;CHECK-LABEL: v_movi8:
 ;CHECK: vmov.i8 d{{.*}}, #0x8
 	ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
 }
 
 define <4 x i16> @v_movi16a() nounwind {
-;CHECK: v_movi16a:
+;CHECK-LABEL: v_movi16a:
 ;CHECK: vmov.i16 d{{.*}}, #0x10
 	ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
 }
 
 define <4 x i16> @v_movi16b() nounwind {
-;CHECK: v_movi16b:
+;CHECK-LABEL: v_movi16b:
 ;CHECK: vmov.i16 d{{.*}}, #0x1000
 	ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
 }
 
 define <4 x i16> @v_mvni16a() nounwind {
-;CHECK: v_mvni16a:
+;CHECK-LABEL: v_mvni16a:
 ;CHECK: vmvn.i16 d{{.*}}, #0x10
 	ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
 }
 
 define <4 x i16> @v_mvni16b() nounwind {
-;CHECK: v_mvni16b:
+;CHECK-LABEL: v_mvni16b:
 ;CHECK: vmvn.i16 d{{.*}}, #0x1000
 	ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
 }
 
 define <2 x i32> @v_movi32a() nounwind {
-;CHECK: v_movi32a:
+;CHECK-LABEL: v_movi32a:
 ;CHECK: vmov.i32 d{{.*}}, #0x20
 	ret <2 x i32> < i32 32, i32 32 >
 }
 
 define <2 x i32> @v_movi32b() nounwind {
-;CHECK: v_movi32b:
+;CHECK-LABEL: v_movi32b:
 ;CHECK: vmov.i32 d{{.*}}, #0x2000
 	ret <2 x i32> < i32 8192, i32 8192 >
 }
 
 define <2 x i32> @v_movi32c() nounwind {
-;CHECK: v_movi32c:
+;CHECK-LABEL: v_movi32c:
 ;CHECK: vmov.i32 d{{.*}}, #0x200000
 	ret <2 x i32> < i32 2097152, i32 2097152 >
 }
 
 define <2 x i32> @v_movi32d() nounwind {
-;CHECK: v_movi32d:
+;CHECK-LABEL: v_movi32d:
 ;CHECK: vmov.i32 d{{.*}}, #0x20000000
 	ret <2 x i32> < i32 536870912, i32 536870912 >
 }
 
 define <2 x i32> @v_movi32e() nounwind {
-;CHECK: v_movi32e:
+;CHECK-LABEL: v_movi32e:
 ;CHECK: vmov.i32 d{{.*}}, #0x20ff
 	ret <2 x i32> < i32 8447, i32 8447 >
 }
 
 define <2 x i32> @v_movi32f() nounwind {
-;CHECK: v_movi32f:
+;CHECK-LABEL: v_movi32f:
 ;CHECK: vmov.i32 d{{.*}}, #0x20ffff
 	ret <2 x i32> < i32 2162687, i32 2162687 >
 }
 
 define <2 x i32> @v_mvni32a() nounwind {
-;CHECK: v_mvni32a:
+;CHECK-LABEL: v_mvni32a:
 ;CHECK: vmvn.i32 d{{.*}}, #0x20
 	ret <2 x i32> < i32 4294967263, i32 4294967263 >
 }
 
 define <2 x i32> @v_mvni32b() nounwind {
-;CHECK: v_mvni32b:
+;CHECK-LABEL: v_mvni32b:
 ;CHECK: vmvn.i32 d{{.*}}, #0x2000
 	ret <2 x i32> < i32 4294959103, i32 4294959103 >
 }
 
 define <2 x i32> @v_mvni32c() nounwind {
-;CHECK: v_mvni32c:
+;CHECK-LABEL: v_mvni32c:
 ;CHECK: vmvn.i32 d{{.*}}, #0x200000
 	ret <2 x i32> < i32 4292870143, i32 4292870143 >
 }
 
 define <2 x i32> @v_mvni32d() nounwind {
-;CHECK: v_mvni32d:
+;CHECK-LABEL: v_mvni32d:
 ;CHECK: vmvn.i32 d{{.*}}, #0x20000000
 	ret <2 x i32> < i32 3758096383, i32 3758096383 >
 }
 
 define <2 x i32> @v_mvni32e() nounwind {
-;CHECK: v_mvni32e:
+;CHECK-LABEL: v_mvni32e:
 ;CHECK: vmvn.i32 d{{.*}}, #0x20ff
 	ret <2 x i32> < i32 4294958848, i32 4294958848 >
 }
 
 define <2 x i32> @v_mvni32f() nounwind {
-;CHECK: v_mvni32f:
+;CHECK-LABEL: v_mvni32f:
 ;CHECK: vmvn.i32 d{{.*}}, #0x20ffff
 	ret <2 x i32> < i32 4292804608, i32 4292804608 >
 }
 
 define <1 x i64> @v_movi64() nounwind {
-;CHECK: v_movi64:
+;CHECK-LABEL: v_movi64:
 ;CHECK: vmov.i64 d{{.*}}, #0xff0000ff0000ffff
 	ret <1 x i64> < i64 18374687574888349695 >
 }
 
 define <16 x i8> @v_movQi8() nounwind {
-;CHECK: v_movQi8:
+;CHECK-LABEL: v_movQi8:
 ;CHECK: vmov.i8 q{{.*}}, #0x8
 	ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
 }
 
 define <8 x i16> @v_movQi16a() nounwind {
-;CHECK: v_movQi16a:
+;CHECK-LABEL: v_movQi16a:
 ;CHECK: vmov.i16 q{{.*}}, #0x10
 	ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
 }
 
 define <8 x i16> @v_movQi16b() nounwind {
-;CHECK: v_movQi16b:
+;CHECK-LABEL: v_movQi16b:
 ;CHECK: vmov.i16 q{{.*}}, #0x1000
 	ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
 }
 
 define <4 x i32> @v_movQi32a() nounwind {
-;CHECK: v_movQi32a:
+;CHECK-LABEL: v_movQi32a:
 ;CHECK: vmov.i32 q{{.*}}, #0x20
 	ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
 }
 
 define <4 x i32> @v_movQi32b() nounwind {
-;CHECK: v_movQi32b:
+;CHECK-LABEL: v_movQi32b:
 ;CHECK: vmov.i32 q{{.*}}, #0x2000
 	ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
 }
 
 define <4 x i32> @v_movQi32c() nounwind {
-;CHECK: v_movQi32c:
+;CHECK-LABEL: v_movQi32c:
 ;CHECK: vmov.i32 q{{.*}}, #0x200000
 	ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
 }
 
 define <4 x i32> @v_movQi32d() nounwind {
-;CHECK: v_movQi32d:
+;CHECK-LABEL: v_movQi32d:
 ;CHECK: vmov.i32 q{{.*}}, #0x20000000
 	ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
 }
 
 define <4 x i32> @v_movQi32e() nounwind {
-;CHECK: v_movQi32e:
+;CHECK-LABEL: v_movQi32e:
 ;CHECK: vmov.i32 q{{.*}}, #0x20ff
 	ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
 }
 
 define <4 x i32> @v_movQi32f() nounwind {
-;CHECK: v_movQi32f:
+;CHECK-LABEL: v_movQi32f:
 ;CHECK: vmov.i32 q{{.*}}, #0x20ffff
 	ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
 }
 
 define <2 x i64> @v_movQi64() nounwind {
-;CHECK: v_movQi64:
+;CHECK-LABEL: v_movQi64:
 ;CHECK: vmov.i64 q{{.*}}, #0xff0000ff0000ffff
 	ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
 }
@@ -172,7 +172,7 @@ define <2 x i64> @v_movQi64() nounwind {
 %struct.int8x8_t = type { <8 x i8> }
 define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
 entry:
-;CHECK: vdupn128:
+;CHECK-LABEL: vdupn128:
 ;CHECK: vmov.i8 d{{.*}}, #0x80
   %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
   store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, <8 x i8>* %0, align 8
@@ -181,7 +181,7 @@ entry:
 
 define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
 entry:
-;CHECK: vdupnneg75:
+;CHECK-LABEL: vdupnneg75:
 ;CHECK: vmov.i8 d{{.*}}, #0xb5
   %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
   store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, <8 x i8>* %0, align 8
@@ -189,7 +189,7 @@ entry:
 }
 
 define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
-;CHECK: vmovls8:
+;CHECK-LABEL: vmovls8:
 ;CHECK: vmovl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
@@ -197,7 +197,7 @@ define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
-;CHECK: vmovls16:
+;CHECK-LABEL: vmovls16:
 ;CHECK: vmovl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
@@ -205,7 +205,7 @@ define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
-;CHECK: vmovls32:
+;CHECK-LABEL: vmovls32:
 ;CHECK: vmovl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
@@ -213,7 +213,7 @@ define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
 }
 
 define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
-;CHECK: vmovlu8:
+;CHECK-LABEL: vmovlu8:
 ;CHECK: vmovl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
@@ -221,7 +221,7 @@ define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
-;CHECK: vmovlu16:
+;CHECK-LABEL: vmovlu16:
 ;CHECK: vmovl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
@@ -229,7 +229,7 @@ define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
-;CHECK: vmovlu32:
+;CHECK-LABEL: vmovlu32:
 ;CHECK: vmovl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
@@ -237,7 +237,7 @@ define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
 }
 
 define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
-;CHECK: vmovni16:
+;CHECK-LABEL: vmovni16:
 ;CHECK: vmovn.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>
@@ -245,7 +245,7 @@ define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
-;CHECK: vmovni32:
+;CHECK-LABEL: vmovni32:
 ;CHECK: vmovn.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
@@ -253,7 +253,7 @@ define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
-;CHECK: vmovni64:
+;CHECK-LABEL: vmovni64:
 ;CHECK: vmovn.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
@@ -261,7 +261,7 @@ define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
-;CHECK: vqmovns16:
+;CHECK-LABEL: vqmovns16:
 ;CHECK: vqmovn.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
@@ -269,7 +269,7 @@ define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
-;CHECK: vqmovns32:
+;CHECK-LABEL: vqmovns32:
 ;CHECK: vqmovn.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
@@ -277,7 +277,7 @@ define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
-;CHECK: vqmovns64:
+;CHECK-LABEL: vqmovns64:
 ;CHECK: vqmovn.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
@@ -285,7 +285,7 @@ define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
-;CHECK: vqmovnu16:
+;CHECK-LABEL: vqmovnu16:
 ;CHECK: vqmovn.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
@@ -293,7 +293,7 @@ define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
-;CHECK: vqmovnu32:
+;CHECK-LABEL: vqmovnu32:
 ;CHECK: vqmovn.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
@@ -301,7 +301,7 @@ define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
-;CHECK: vqmovnu64:
+;CHECK-LABEL: vqmovnu64:
 ;CHECK: vqmovn.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
@@ -309,7 +309,7 @@ define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
-;CHECK: vqmovuns16:
+;CHECK-LABEL: vqmovuns16:
 ;CHECK: vqmovun.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
@@ -317,7 +317,7 @@ define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
-;CHECK: vqmovuns32:
+;CHECK-LABEL: vqmovuns32:
 ;CHECK: vqmovun.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
@@ -325,7 +325,7 @@ define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
-;CHECK: vqmovuns64:
+;CHECK-LABEL: vqmovuns64:
 ;CHECK: vqmovun.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
@@ -358,7 +358,7 @@ define void @noTruncStore(<4 x i32>* %a, <4 x i16>* %b) nounwind {
 ; rdar://10437054
 define void @v_mov_v2f32(<2 x float>* nocapture %p) nounwind {
 entry:
-;CHECK: v_mov_v2f32:
+;CHECK-LABEL: v_mov_v2f32:
 ;CHECK: vmov.f32 d{{.*}}, #-1.600000e+01
   store <2 x float> <float -1.600000e+01, float -1.600000e+01>, <2 x float>* %p, align 4
   ret void
@@ -366,7 +366,7 @@ entry:
 
 define void @v_mov_v4f32(<4 x float>* nocapture %p) nounwind {
 entry:
-;CHECK: v_mov_v4f32:
+;CHECK-LABEL: v_mov_v4f32:
 ;CHECK: vmov.f32 q{{.*}}, #3.100000e+01
   store <4 x float> <float 3.100000e+01, float 3.100000e+01, float 3.100000e+01, float 3.100000e+01>, <4 x float>* %p, align 4
   ret void
@@ -374,7 +374,7 @@ entry:
 
 define void @v_mov_v4f32_undef(<4 x float> * nocapture %p) nounwind {
 entry:
-;CHECK: v_mov_v4f32_undef:
+;CHECK-LABEL: v_mov_v4f32_undef:
 ;CHECK: vmov.f32 q{{.*}}, #1.000000e+00
   %a = load <4 x float> *%p
   %b = fadd <4 x float> %a, <float undef, float 1.0, float 1.0, float 1.0>
diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll
index aa3cda0..6210ad3 100644
--- a/test/CodeGen/ARM/vmul.ll
+++ b/test/CodeGen/ARM/vmul.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
 
 define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmuli8:
+;CHECK-LABEL: vmuli8:
 ;CHECK: vmul.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmuli16:
+;CHECK-LABEL: vmuli16:
 ;CHECK: vmul.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmuli32:
+;CHECK-LABEL: vmuli32:
 ;CHECK: vmul.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vmulf32:
+;CHECK-LABEL: vmulf32:
 ;CHECK: vmul.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -37,7 +37,7 @@ define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmulp8:
+;CHECK-LABEL: vmulp8:
 ;CHECK: vmul.p8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmulQi8:
+;CHECK-LABEL: vmulQi8:
 ;CHECK: vmul.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -55,7 +55,7 @@ define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vmulQi16:
+;CHECK-LABEL: vmulQi16:
 ;CHECK: vmul.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -64,7 +64,7 @@ define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vmulQi32:
+;CHECK-LABEL: vmulQi32:
 ;CHECK: vmul.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -73,7 +73,7 @@ define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vmulQf32:
+;CHECK-LABEL: vmulQf32:
 ;CHECK: vmul.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -82,7 +82,7 @@ define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vmulQp8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmulQp8:
+;CHECK-LABEL: vmulQp8:
 ;CHECK: vmul.p8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -148,7 +148,7 @@ entry:
 }
 
 define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmulls8:
+;CHECK-LABEL: vmulls8:
 ;CHECK: vmull.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -159,7 +159,7 @@ define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmulls8_int:
+;CHECK-LABEL: vmulls8_int:
 ;CHECK: vmull.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -168,7 +168,7 @@ define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmulls16:
+;CHECK-LABEL: vmulls16:
 ;CHECK: vmull.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -179,7 +179,7 @@ define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmulls16_int:
+;CHECK-LABEL: vmulls16_int:
 ;CHECK: vmull.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -188,7 +188,7 @@ define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmulls32:
+;CHECK-LABEL: vmulls32:
 ;CHECK: vmull.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -199,7 +199,7 @@ define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmulls32_int:
+;CHECK-LABEL: vmulls32_int:
 ;CHECK: vmull.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -208,7 +208,7 @@ define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmullu8:
+;CHECK-LABEL: vmullu8:
 ;CHECK: vmull.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -219,7 +219,7 @@ define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmullu8_int:
+;CHECK-LABEL: vmullu8_int:
 ;CHECK: vmull.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -228,7 +228,7 @@ define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmullu16:
+;CHECK-LABEL: vmullu16:
 ;CHECK: vmull.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -239,7 +239,7 @@ define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmullu16_int:
+;CHECK-LABEL: vmullu16_int:
 ;CHECK: vmull.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -248,7 +248,7 @@ define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmullu32:
+;CHECK-LABEL: vmullu32:
 ;CHECK: vmull.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -259,7 +259,7 @@ define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmullu32_int:
+;CHECK-LABEL: vmullu32_int:
 ;CHECK: vmull.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -268,7 +268,7 @@ define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmullp8:
+;CHECK-LABEL: vmullp8:
 ;CHECK: vmull.p8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -441,7 +441,7 @@ define <2 x i64> @vmull_extvec_u32(<2 x i32> %arg) nounwind {
 ; rdar://9197392
 define void @distribute(i16* %dst, i8* %src, i32 %mul) nounwind {
 entry:
-; CHECK: distribute:
+; CHECK-LABEL: distribute:
 ; CHECK: vmull.u8 [[REG1:(q[0-9]+)]], d{{.*}}, [[REG2:(d[0-9]+)]]
 ; CHECK: vmlal.u8 [[REG1]], d{{.*}}, [[REG2]]
   %0 = trunc i32 %mul to i8
diff --git a/test/CodeGen/ARM/vneg.ll b/test/CodeGen/ARM/vneg.ll
index 4a10732..1be4f74 100644
--- a/test/CodeGen/ARM/vneg.ll
+++ b/test/CodeGen/ARM/vneg.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
-;CHECK: vnegs8:
+;CHECK-LABEL: vnegs8:
 ;CHECK: vneg.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = sub <8 x i8> zeroinitializer, %tmp1
@@ -9,7 +9,7 @@ define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
-;CHECK: vnegs16:
+;CHECK-LABEL: vnegs16:
 ;CHECK: vneg.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = sub <4 x i16> zeroinitializer, %tmp1
@@ -17,7 +17,7 @@ define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
-;CHECK: vnegs32:
+;CHECK-LABEL: vnegs32:
 ;CHECK: vneg.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = sub <2 x i32> zeroinitializer, %tmp1
@@ -25,7 +25,7 @@ define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
-;CHECK: vnegf32:
+;CHECK-LABEL: vnegf32:
 ;CHECK: vneg.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
@@ -33,7 +33,7 @@ define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
 }
 
 define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
-;CHECK: vnegQs8:
+;CHECK-LABEL: vnegQs8:
 ;CHECK: vneg.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = sub <16 x i8> zeroinitializer, %tmp1
@@ -41,7 +41,7 @@ define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
-;CHECK: vnegQs16:
+;CHECK-LABEL: vnegQs16:
 ;CHECK: vneg.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = sub <8 x i16> zeroinitializer, %tmp1
@@ -49,7 +49,7 @@ define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
-;CHECK: vnegQs32:
+;CHECK-LABEL: vnegQs32:
 ;CHECK: vneg.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = sub <4 x i32> zeroinitializer, %tmp1
@@ -57,7 +57,7 @@ define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
 }
 
 define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
-;CHECK: vnegQf32:
+;CHECK-LABEL: vnegQf32:
 ;CHECK: vneg.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1
@@ -65,7 +65,7 @@ define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
 }
 
 define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
-;CHECK: vqnegs8:
+;CHECK-LABEL: vqnegs8:
 ;CHECK: vqneg.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)
@@ -73,7 +73,7 @@ define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
-;CHECK: vqnegs16:
+;CHECK-LABEL: vqnegs16:
 ;CHECK: vqneg.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
@@ -81,7 +81,7 @@ define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
-;CHECK: vqnegs32:
+;CHECK-LABEL: vqnegs32:
 ;CHECK: vqneg.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)
@@ -89,7 +89,7 @@ define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
 }
 
 define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
-;CHECK: vqnegQs8:
+;CHECK-LABEL: vqnegQs8:
 ;CHECK: vqneg.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)
@@ -97,7 +97,7 @@ define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
-;CHECK: vqnegQs16:
+;CHECK-LABEL: vqnegQs16:
 ;CHECK: vqneg.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
@@ -105,7 +105,7 @@ define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind {
-;CHECK: vqnegQs32:
+;CHECK-LABEL: vqnegQs32:
 ;CHECK: vqneg.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1)
diff --git a/test/CodeGen/ARM/vpadal.ll b/test/CodeGen/ARM/vpadal.ll
index 7296e936..a616a8d 100644
--- a/test/CodeGen/ARM/vpadal.ll
+++ b/test/CodeGen/ARM/vpadal.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpadals8:
+;CHECK-LABEL: vpadals8:
 ;CHECK: vpadal.s8
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpadals16:
+;CHECK-LABEL: vpadals16:
 ;CHECK: vpadal.s16
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpadals32:
+;CHECK-LABEL: vpadals32:
 ;CHECK: vpadal.s32
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpadalu8:
+;CHECK-LABEL: vpadalu8:
 ;CHECK: vpadal.u8
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpadalu16:
+;CHECK-LABEL: vpadalu16:
 ;CHECK: vpadal.u16
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpadalu32:
+;CHECK-LABEL: vpadalu32:
 ;CHECK: vpadal.u32
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vpadalQs8:
+;CHECK-LABEL: vpadalQs8:
 ;CHECK: vpadal.s8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -64,7 +64,7 @@ define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vpadalQs16:
+;CHECK-LABEL: vpadalQs16:
 ;CHECK: vpadal.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -73,7 +73,7 @@ define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vpadalQs32:
+;CHECK-LABEL: vpadalQs32:
 ;CHECK: vpadal.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -82,7 +82,7 @@ define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vpadalQu8:
+;CHECK-LABEL: vpadalQu8:
 ;CHECK: vpadal.u8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vpadalQu16:
+;CHECK-LABEL: vpadalQu16:
 ;CHECK: vpadal.u16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vpadalQu32:
+;CHECK-LABEL: vpadalQu32:
 ;CHECK: vpadal.u32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <4 x i32>* %B
diff --git a/test/CodeGen/ARM/vpadd.ll b/test/CodeGen/ARM/vpadd.ll
index 1ba68f5..f84721f 100644
--- a/test/CodeGen/ARM/vpadd.ll
+++ b/test/CodeGen/ARM/vpadd.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpaddi8:
+;CHECK-LABEL: vpaddi8:
 ;CHECK: vpadd.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpaddi16:
+;CHECK-LABEL: vpaddi16:
 ;CHECK: vpadd.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpaddi32:
+;CHECK-LABEL: vpaddi32:
 ;CHECK: vpadd.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vpaddf32:
+;CHECK-LABEL: vpaddf32:
 ;CHECK: vpadd.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -43,7 +43,7 @@ declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind read
 declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
 
 define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
-;CHECK: vpaddls8:
+;CHECK-LABEL: vpaddls8:
 ;CHECK: vpaddl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1)
@@ -51,7 +51,7 @@ define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
 }
 
 define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
-;CHECK: vpaddls16:
+;CHECK-LABEL: vpaddls16:
 ;CHECK: vpaddl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1)
@@ -59,7 +59,7 @@ define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
 }
 
 define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
-;CHECK: vpaddls32:
+;CHECK-LABEL: vpaddls32:
 ;CHECK: vpaddl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1)
@@ -67,7 +67,7 @@ define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
 }
 
 define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
-;CHECK: vpaddlu8:
+;CHECK-LABEL: vpaddlu8:
 ;CHECK: vpaddl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1)
@@ -75,7 +75,7 @@ define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
 }
 
 define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
-;CHECK: vpaddlu16:
+;CHECK-LABEL: vpaddlu16:
 ;CHECK: vpaddl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1)
@@ -83,7 +83,7 @@ define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
 }
 
 define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
-;CHECK: vpaddlu32:
+;CHECK-LABEL: vpaddlu32:
 ;CHECK: vpaddl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1)
@@ -91,7 +91,7 @@ define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
 }
 
 define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
-;CHECK: vpaddlQs8:
+;CHECK-LABEL: vpaddlQs8:
 ;CHECK: vpaddl.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1)
@@ -99,7 +99,7 @@ define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
 }
 
 define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
-;CHECK: vpaddlQs16:
+;CHECK-LABEL: vpaddlQs16:
 ;CHECK: vpaddl.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1)
@@ -107,7 +107,7 @@ define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
 }
 
 define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
-;CHECK: vpaddlQs32:
+;CHECK-LABEL: vpaddlQs32:
 ;CHECK: vpaddl.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1)
@@ -115,7 +115,7 @@ define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
 }
 
 define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
-;CHECK: vpaddlQu8:
+;CHECK-LABEL: vpaddlQu8:
 ;CHECK: vpaddl.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1)
@@ -123,7 +123,7 @@ define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
 }
 
 define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
-;CHECK: vpaddlQu16:
+;CHECK-LABEL: vpaddlQu16:
 ;CHECK: vpaddl.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1)
@@ -131,7 +131,7 @@ define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
 }
 
 define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind {
-;CHECK: vpaddlQu32:
+;CHECK-LABEL: vpaddlQu32:
 ;CHECK: vpaddl.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
diff --git a/test/CodeGen/ARM/vpminmax.ll b/test/CodeGen/ARM/vpminmax.ll
index b75bcc9..c68b319 100644
--- a/test/CodeGen/ARM/vpminmax.ll
+++ b/test/CodeGen/ARM/vpminmax.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpmins8:
+;CHECK-LABEL: vpmins8:
 ;CHECK: vpmin.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpmins16:
+;CHECK-LABEL: vpmins16:
 ;CHECK: vpmin.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpmins32:
+;CHECK-LABEL: vpmins32:
 ;CHECK: vpmin.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpminu8:
+;CHECK-LABEL: vpminu8:
 ;CHECK: vpmin.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpminu16:
+;CHECK-LABEL: vpminu16:
 ;CHECK: vpmin.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpminu32:
+;CHECK-LABEL: vpminu32:
 ;CHECK: vpmin.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vpminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vpminf32:
+;CHECK-LABEL: vpminf32:
 ;CHECK: vpmin.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -74,7 +74,7 @@ declare <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32>, <2 x i32>) nounwind rea
 declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
 
 define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpmaxs8:
+;CHECK-LABEL: vpmaxs8:
 ;CHECK: vpmax.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -83,7 +83,7 @@ define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpmaxs16:
+;CHECK-LABEL: vpmaxs16:
 ;CHECK: vpmax.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -92,7 +92,7 @@ define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpmaxs32:
+;CHECK-LABEL: vpmaxs32:
 ;CHECK: vpmax.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -101,7 +101,7 @@ define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpmaxu8:
+;CHECK-LABEL: vpmaxu8:
 ;CHECK: vpmax.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -110,7 +110,7 @@ define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpmaxu16:
+;CHECK-LABEL: vpmaxu16:
 ;CHECK: vpmax.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -119,7 +119,7 @@ define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpmaxu32:
+;CHECK-LABEL: vpmaxu32:
 ;CHECK: vpmax.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -128,7 +128,7 @@ define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vpmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vpmaxf32:
+;CHECK-LABEL: vpmaxf32:
 ;CHECK: vpmax.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
diff --git a/test/CodeGen/ARM/vqadd.ll b/test/CodeGen/ARM/vqadd.ll
index a1669b6..7840766 100644
--- a/test/CodeGen/ARM/vqadd.ll
+++ b/test/CodeGen/ARM/vqadd.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqadds8:
+;CHECK-LABEL: vqadds8:
 ;CHECK: vqadd.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqadds16:
+;CHECK-LABEL: vqadds16:
 ;CHECK: vqadd.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqadds32:
+;CHECK-LABEL: vqadds32:
 ;CHECK: vqadd.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqadds64:
+;CHECK-LABEL: vqadds64:
 ;CHECK: vqadd.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqaddu8:
+;CHECK-LABEL: vqaddu8:
 ;CHECK: vqadd.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqaddu16:
+;CHECK-LABEL: vqaddu16:
 ;CHECK: vqadd.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -55,7 +55,7 @@ define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqaddu32:
+;CHECK-LABEL: vqaddu32:
 ;CHECK: vqadd.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -64,7 +64,7 @@ define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqaddu64:
+;CHECK-LABEL: vqaddu64:
 ;CHECK: vqadd.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -73,7 +73,7 @@ define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqaddQs8:
+;CHECK-LABEL: vqaddQs8:
 ;CHECK: vqadd.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqaddQs16:
+;CHECK-LABEL: vqaddQs16:
 ;CHECK: vqadd.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqaddQs32:
+;CHECK-LABEL: vqaddQs32:
 ;CHECK: vqadd.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqaddQs64:
+;CHECK-LABEL: vqaddQs64:
 ;CHECK: vqadd.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -109,7 +109,7 @@ define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqaddQu8:
+;CHECK-LABEL: vqaddQu8:
 ;CHECK: vqadd.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqaddQu16:
+;CHECK-LABEL: vqaddQu16:
 ;CHECK: vqadd.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqaddQu32:
+;CHECK-LABEL: vqaddQu32:
 ;CHECK: vqadd.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqaddQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqaddQu64:
+;CHECK-LABEL: vqaddQu64:
 ;CHECK: vqadd.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
diff --git a/test/CodeGen/ARM/vqdmul.ll b/test/CodeGen/ARM/vqdmul.ll
index 08e7d2b..a28cae9 100644
--- a/test/CodeGen/ARM/vqdmul.ll
+++ b/test/CodeGen/ARM/vqdmul.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-
 target triple = "thumbv7-elf"
 
 define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqdmulhs16:
+;CHECK-LABEL: vqdmulhs16:
 ;CHECK: vqdmulh.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -12,7 +12,7 @@ define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqdmulhs32:
+;CHECK-LABEL: vqdmulhs32:
 ;CHECK: vqdmulh.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -21,7 +21,7 @@ define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqdmulhQs16:
+;CHECK-LABEL: vqdmulhQs16:
 ;CHECK: vqdmulh.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -30,7 +30,7 @@ define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqdmulhQs32:
+;CHECK-LABEL: vqdmulhQs32:
 ;CHECK: vqdmulh.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -81,7 +81,7 @@ declare <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind re
 declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqrdmulhs16:
+;CHECK-LABEL: vqrdmulhs16:
 ;CHECK: vqrdmulh.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -90,7 +90,7 @@ define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqrdmulhs32:
+;CHECK-LABEL: vqrdmulhs32:
 ;CHECK: vqrdmulh.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -99,7 +99,7 @@ define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqrdmulhQs16:
+;CHECK-LABEL: vqrdmulhQs16:
 ;CHECK: vqrdmulh.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -108,7 +108,7 @@ define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqrdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqrdmulhQs32:
+;CHECK-LABEL: vqrdmulhQs32:
 ;CHECK: vqrdmulh.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -159,7 +159,7 @@ declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind r
 declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqdmulls16:
+;CHECK-LABEL: vqdmulls16:
 ;CHECK: vqdmull.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -168,7 +168,7 @@ define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vqdmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqdmulls32:
+;CHECK-LABEL: vqdmulls32:
 ;CHECK: vqdmull.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -198,7 +198,7 @@ declare <4 x i32>  @llvm.arm.neon.vqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind r
 declare <2 x i64>  @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
 
 define <4 x i32> @vqdmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vqdmlals16:
+;CHECK-LABEL: vqdmlals16:
 ;CHECK: vqdmlal.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -208,7 +208,7 @@ define <4 x i32> @vqdmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwi
 }
 
 define <2 x i64> @vqdmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vqdmlals32:
+;CHECK-LABEL: vqdmlals32:
 ;CHECK: vqdmlal.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -239,7 +239,7 @@ declare <4 x i32>  @llvm.arm.neon.vqdmlal.v4i32(<4 x i32>, <4 x i16>, <4 x i16>)
 declare <2 x i64>  @llvm.arm.neon.vqdmlal.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
 
 define <4 x i32> @vqdmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vqdmlsls16:
+;CHECK-LABEL: vqdmlsls16:
 ;CHECK: vqdmlsl.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -249,7 +249,7 @@ define <4 x i32> @vqdmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwi
 }
 
 define <2 x i64> @vqdmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vqdmlsls32:
+;CHECK-LABEL: vqdmlsls32:
 ;CHECK: vqdmlsl.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
diff --git a/test/CodeGen/ARM/vqshl.ll b/test/CodeGen/ARM/vqshl.ll
index e4d29a3..b5cd716 100644
--- a/test/CodeGen/ARM/vqshl.ll
+++ b/test/CodeGen/ARM/vqshl.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqshls8:
+;CHECK-LABEL: vqshls8:
 ;CHECK: vqshl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqshls16:
+;CHECK-LABEL: vqshls16:
 ;CHECK: vqshl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqshls32:
+;CHECK-LABEL: vqshls32:
 ;CHECK: vqshl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqshls64:
+;CHECK-LABEL: vqshls64:
 ;CHECK: vqshl.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqshlu8:
+;CHECK-LABEL: vqshlu8:
 ;CHECK: vqshl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqshlu16:
+;CHECK-LABEL: vqshlu16:
 ;CHECK: vqshl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -55,7 +55,7 @@ define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqshlu32:
+;CHECK-LABEL: vqshlu32:
 ;CHECK: vqshl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -64,7 +64,7 @@ define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqshlu64:
+;CHECK-LABEL: vqshlu64:
 ;CHECK: vqshl.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -73,7 +73,7 @@ define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqshlQs8:
+;CHECK-LABEL: vqshlQs8:
 ;CHECK: vqshl.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqshlQs16:
+;CHECK-LABEL: vqshlQs16:
 ;CHECK: vqshl.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqshlQs32:
+;CHECK-LABEL: vqshlQs32:
 ;CHECK: vqshl.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqshlQs64:
+;CHECK-LABEL: vqshlQs64:
 ;CHECK: vqshl.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -109,7 +109,7 @@ define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqshlQu8:
+;CHECK-LABEL: vqshlQu8:
 ;CHECK: vqshl.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqshlQu16:
+;CHECK-LABEL: vqshlQu16:
 ;CHECK: vqshl.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqshlQu32:
+;CHECK-LABEL: vqshlQu32:
 ;CHECK: vqshl.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqshlQu64:
+;CHECK-LABEL: vqshlQu64:
 ;CHECK: vqshl.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -145,7 +145,7 @@ define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind {
-;CHECK: vqshls_n8:
+;CHECK-LABEL: vqshls_n8:
 ;CHECK: vqshl.s8{{.*#7}}
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -153,7 +153,7 @@ define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind {
-;CHECK: vqshls_n16:
+;CHECK-LABEL: vqshls_n16:
 ;CHECK: vqshl.s16{{.*#15}}
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -161,7 +161,7 @@ define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind {
-;CHECK: vqshls_n32:
+;CHECK-LABEL: vqshls_n32:
 ;CHECK: vqshl.s32{{.*#31}}
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -169,7 +169,7 @@ define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind {
-;CHECK: vqshls_n64:
+;CHECK-LABEL: vqshls_n64:
 ;CHECK: vqshl.s64{{.*#63}}
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
@@ -177,7 +177,7 @@ define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind {
-;CHECK: vqshlu_n8:
+;CHECK-LABEL: vqshlu_n8:
 ;CHECK: vqshl.u8{{.*#7}}
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -185,7 +185,7 @@ define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind {
-;CHECK: vqshlu_n16:
+;CHECK-LABEL: vqshlu_n16:
 ;CHECK: vqshl.u16{{.*#15}}
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -193,7 +193,7 @@ define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind {
-;CHECK: vqshlu_n32:
+;CHECK-LABEL: vqshlu_n32:
 ;CHECK: vqshl.u32{{.*#31}}
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -201,7 +201,7 @@ define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind {
-;CHECK: vqshlu_n64:
+;CHECK-LABEL: vqshlu_n64:
 ;CHECK: vqshl.u64{{.*#63}}
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
@@ -209,7 +209,7 @@ define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind {
-;CHECK: vqshlsu_n8:
+;CHECK-LABEL: vqshlsu_n8:
 ;CHECK: vqshlu.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -217,7 +217,7 @@ define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind {
-;CHECK: vqshlsu_n16:
+;CHECK-LABEL: vqshlsu_n16:
 ;CHECK: vqshlu.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -225,7 +225,7 @@ define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind {
-;CHECK: vqshlsu_n32:
+;CHECK-LABEL: vqshlsu_n32:
 ;CHECK: vqshlu.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -233,7 +233,7 @@ define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind {
-;CHECK: vqshlsu_n64:
+;CHECK-LABEL: vqshlsu_n64:
 ;CHECK: vqshlu.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
@@ -241,7 +241,7 @@ define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind {
-;CHECK: vqshlQs_n8:
+;CHECK-LABEL: vqshlQs_n8:
 ;CHECK: vqshl.s8{{.*#7}}
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -249,7 +249,7 @@ define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind {
-;CHECK: vqshlQs_n16:
+;CHECK-LABEL: vqshlQs_n16:
 ;CHECK: vqshl.s16{{.*#15}}
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
@@ -257,7 +257,7 @@ define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind {
-;CHECK: vqshlQs_n32:
+;CHECK-LABEL: vqshlQs_n32:
 ;CHECK: vqshl.s32{{.*#31}}
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
@@ -265,7 +265,7 @@ define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind {
-;CHECK: vqshlQs_n64:
+;CHECK-LABEL: vqshlQs_n64:
 ;CHECK: vqshl.s64{{.*#63}}
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
@@ -273,7 +273,7 @@ define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind {
-;CHECK: vqshlQu_n8:
+;CHECK-LABEL: vqshlQu_n8:
 ;CHECK: vqshl.u8{{.*#7}}
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -281,7 +281,7 @@ define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind {
-;CHECK: vqshlQu_n16:
+;CHECK-LABEL: vqshlQu_n16:
 ;CHECK: vqshl.u16{{.*#15}}
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
@@ -289,7 +289,7 @@ define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind {
-;CHECK: vqshlQu_n32:
+;CHECK-LABEL: vqshlQu_n32:
 ;CHECK: vqshl.u32{{.*#31}}
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
@@ -297,7 +297,7 @@ define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind {
-;CHECK: vqshlQu_n64:
+;CHECK-LABEL: vqshlQu_n64:
 ;CHECK: vqshl.u64{{.*#63}}
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
@@ -305,7 +305,7 @@ define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind {
-;CHECK: vqshlQsu_n8:
+;CHECK-LABEL: vqshlQsu_n8:
 ;CHECK: vqshlu.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -313,7 +313,7 @@ define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind {
-;CHECK: vqshlQsu_n16:
+;CHECK-LABEL: vqshlQsu_n16:
 ;CHECK: vqshlu.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
@@ -321,7 +321,7 @@ define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind {
-;CHECK: vqshlQsu_n32:
+;CHECK-LABEL: vqshlQsu_n32:
 ;CHECK: vqshlu.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
@@ -329,7 +329,7 @@ define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vqshlQsu_n64(<2 x i64>* %A) nounwind {
-;CHECK: vqshlQsu_n64:
+;CHECK-LABEL: vqshlQsu_n64:
 ;CHECK: vqshlu.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
@@ -367,7 +367,7 @@ declare <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32>, <4 x i32>) nounwind
 declare <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqrshls8:
+;CHECK-LABEL: vqrshls8:
 ;CHECK: vqrshl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -376,7 +376,7 @@ define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqrshls16:
+;CHECK-LABEL: vqrshls16:
 ;CHECK: vqrshl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -385,7 +385,7 @@ define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqrshls32:
+;CHECK-LABEL: vqrshls32:
 ;CHECK: vqrshl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -394,7 +394,7 @@ define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqrshls64:
+;CHECK-LABEL: vqrshls64:
 ;CHECK: vqrshl.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -403,7 +403,7 @@ define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqrshlu8:
+;CHECK-LABEL: vqrshlu8:
 ;CHECK: vqrshl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -412,7 +412,7 @@ define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqrshlu16:
+;CHECK-LABEL: vqrshlu16:
 ;CHECK: vqrshl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -421,7 +421,7 @@ define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqrshlu32:
+;CHECK-LABEL: vqrshlu32:
 ;CHECK: vqrshl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -430,7 +430,7 @@ define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqrshlu64:
+;CHECK-LABEL: vqrshlu64:
 ;CHECK: vqrshl.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -439,7 +439,7 @@ define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqrshlQs8:
+;CHECK-LABEL: vqrshlQs8:
 ;CHECK: vqrshl.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -448,7 +448,7 @@ define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqrshlQs16:
+;CHECK-LABEL: vqrshlQs16:
 ;CHECK: vqrshl.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -457,7 +457,7 @@ define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqrshlQs32:
+;CHECK-LABEL: vqrshlQs32:
 ;CHECK: vqrshl.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -466,7 +466,7 @@ define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqrshlQs64:
+;CHECK-LABEL: vqrshlQs64:
 ;CHECK: vqrshl.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -475,7 +475,7 @@ define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqrshlQu8:
+;CHECK-LABEL: vqrshlQu8:
 ;CHECK: vqrshl.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -484,7 +484,7 @@ define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqrshlQu16:
+;CHECK-LABEL: vqrshlQu16:
 ;CHECK: vqrshl.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -493,7 +493,7 @@ define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqrshlQu32:
+;CHECK-LABEL: vqrshlQu32:
 ;CHECK: vqrshl.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -502,7 +502,7 @@ define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqrshlQu64:
+;CHECK-LABEL: vqrshlQu64:
 ;CHECK: vqrshl.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
diff --git a/test/CodeGen/ARM/vqshrn.ll b/test/CodeGen/ARM/vqshrn.ll
index 5da7943..4abae70 100644
--- a/test/CodeGen/ARM/vqshrn.ll
+++ b/test/CodeGen/ARM/vqshrn.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vqshrns8:
+;CHECK-LABEL: vqshrns8:
 ;CHECK: vqshrn.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -9,7 +9,7 @@ define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vqshrns16:
+;CHECK-LABEL: vqshrns16:
 ;CHECK: vqshrn.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -17,7 +17,7 @@ define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vqshrns32:
+;CHECK-LABEL: vqshrns32:
 ;CHECK: vqshrn.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -25,7 +25,7 @@ define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
-;CHECK: vqshrnu8:
+;CHECK-LABEL: vqshrnu8:
 ;CHECK: vqshrn.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -33,7 +33,7 @@ define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
-;CHECK: vqshrnu16:
+;CHECK-LABEL: vqshrnu16:
 ;CHECK: vqshrn.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -41,7 +41,7 @@ define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
-;CHECK: vqshrnu32:
+;CHECK-LABEL: vqshrnu32:
 ;CHECK: vqshrn.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -49,7 +49,7 @@ define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
-;CHECK: vqshruns8:
+;CHECK-LABEL: vqshruns8:
 ;CHECK: vqshrun.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -57,7 +57,7 @@ define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
-;CHECK: vqshruns16:
+;CHECK-LABEL: vqshruns16:
 ;CHECK: vqshrun.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -65,7 +65,7 @@ define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind {
-;CHECK: vqshruns32:
+;CHECK-LABEL: vqshruns32:
 ;CHECK: vqshrun.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -85,7 +85,7 @@ declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind
 declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshrns8:
+;CHECK-LABEL: vqrshrns8:
 ;CHECK: vqrshrn.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -93,7 +93,7 @@ define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshrns16:
+;CHECK-LABEL: vqrshrns16:
 ;CHECK: vqrshrn.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -101,7 +101,7 @@ define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshrns32:
+;CHECK-LABEL: vqrshrns32:
 ;CHECK: vqrshrn.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -109,7 +109,7 @@ define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshrnu8:
+;CHECK-LABEL: vqrshrnu8:
 ;CHECK: vqrshrn.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -117,7 +117,7 @@ define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshrnu16:
+;CHECK-LABEL: vqrshrnu16:
 ;CHECK: vqrshrn.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -125,7 +125,7 @@ define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshrnu32:
+;CHECK-LABEL: vqrshrnu32:
 ;CHECK: vqrshrn.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -133,7 +133,7 @@ define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshruns8:
+;CHECK-LABEL: vqrshruns8:
 ;CHECK: vqrshrun.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -141,7 +141,7 @@ define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshruns16:
+;CHECK-LABEL: vqrshruns16:
 ;CHECK: vqrshrun.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -149,7 +149,7 @@ define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshruns32:
+;CHECK-LABEL: vqrshruns32:
 ;CHECK: vqrshrun.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
diff --git a/test/CodeGen/ARM/vqsub.ll b/test/CodeGen/ARM/vqsub.ll
index 4231fca..90bc349 100644
--- a/test/CodeGen/ARM/vqsub.ll
+++ b/test/CodeGen/ARM/vqsub.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqsubs8:
+;CHECK-LABEL: vqsubs8:
 ;CHECK: vqsub.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqsubs16:
+;CHECK-LABEL: vqsubs16:
 ;CHECK: vqsub.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqsubs32:
+;CHECK-LABEL: vqsubs32:
 ;CHECK: vqsub.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqsubs64:
+;CHECK-LABEL: vqsubs64:
 ;CHECK: vqsub.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqsubu8:
+;CHECK-LABEL: vqsubu8:
 ;CHECK: vqsub.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqsubu16:
+;CHECK-LABEL: vqsubu16:
 ;CHECK: vqsub.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -55,7 +55,7 @@ define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqsubu32:
+;CHECK-LABEL: vqsubu32:
 ;CHECK: vqsub.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -64,7 +64,7 @@ define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqsubu64:
+;CHECK-LABEL: vqsubu64:
 ;CHECK: vqsub.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -73,7 +73,7 @@ define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqsubQs8:
+;CHECK-LABEL: vqsubQs8:
 ;CHECK: vqsub.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqsubQs16:
+;CHECK-LABEL: vqsubQs16:
 ;CHECK: vqsub.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqsubQs32:
+;CHECK-LABEL: vqsubQs32:
 ;CHECK: vqsub.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqsubQs64:
+;CHECK-LABEL: vqsubQs64:
 ;CHECK: vqsub.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -109,7 +109,7 @@ define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqsubQu8:
+;CHECK-LABEL: vqsubQu8:
 ;CHECK: vqsub.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqsubQu16:
+;CHECK-LABEL: vqsubQu16:
 ;CHECK: vqsub.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqsubQu32:
+;CHECK-LABEL: vqsubQu32:
 ;CHECK: vqsub.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqsubQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqsubQu64:
+;CHECK-LABEL: vqsubQu64:
 ;CHECK: vqsub.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
diff --git a/test/CodeGen/ARM/vrec.ll b/test/CodeGen/ARM/vrec.ll
index 99989e9..c0deca9 100644
--- a/test/CodeGen/ARM/vrec.ll
+++ b/test/CodeGen/ARM/vrec.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind {
-;CHECK: vrecpei32:
+;CHECK-LABEL: vrecpei32:
 ;CHECK: vrecpe.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
@@ -9,7 +9,7 @@ define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind {
 }
 
 define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind {
-;CHECK: vrecpeQi32:
+;CHECK-LABEL: vrecpeQi32:
 ;CHECK: vrecpe.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
@@ -17,7 +17,7 @@ define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vrecpef32(<2 x float>* %A) nounwind {
-;CHECK: vrecpef32:
+;CHECK-LABEL: vrecpef32:
 ;CHECK: vrecpe.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
@@ -25,7 +25,7 @@ define <2 x float> @vrecpef32(<2 x float>* %A) nounwind {
 }
 
 define <4 x float> @vrecpeQf32(<4 x float>* %A) nounwind {
-;CHECK: vrecpeQf32:
+;CHECK-LABEL: vrecpeQf32:
 ;CHECK: vrecpe.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
@@ -39,7 +39,7 @@ declare <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float>) nounwind readnone
 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
 
 define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vrecpsf32:
+;CHECK-LABEL: vrecpsf32:
 ;CHECK: vrecps.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -48,7 +48,7 @@ define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <4 x float> @vrecpsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vrecpsQf32:
+;CHECK-LABEL: vrecpsQf32:
 ;CHECK: vrecps.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -60,7 +60,7 @@ declare <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float>, <2 x float>) nounwi
 declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
 
 define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
-;CHECK: vrsqrtei32:
+;CHECK-LABEL: vrsqrtei32:
 ;CHECK: vrsqrte.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
@@ -68,7 +68,7 @@ define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
 }
 
 define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
-;CHECK: vrsqrteQi32:
+;CHECK-LABEL: vrsqrteQi32:
 ;CHECK: vrsqrte.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
@@ -76,7 +76,7 @@ define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
-;CHECK: vrsqrtef32:
+;CHECK-LABEL: vrsqrtef32:
 ;CHECK: vrsqrte.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
@@ -84,7 +84,7 @@ define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
 }
 
 define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind {
-;CHECK: vrsqrteQf32:
+;CHECK-LABEL: vrsqrteQf32:
 ;CHECK: vrsqrte.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
@@ -98,7 +98,7 @@ declare <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float>) nounwind readnone
 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
 
 define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vrsqrtsf32:
+;CHECK-LABEL: vrsqrtsf32:
 ;CHECK: vrsqrts.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -107,7 +107,7 @@ define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <4 x float> @vrsqrtsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vrsqrtsQf32:
+;CHECK-LABEL: vrsqrtsQf32:
 ;CHECK: vrsqrts.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
diff --git a/test/CodeGen/ARM/vselect_imax.ll b/test/CodeGen/ARM/vselect_imax.ll
index 9744f4d..9ea56a4 100644
--- a/test/CodeGen/ARM/vselect_imax.ll
+++ b/test/CodeGen/ARM/vselect_imax.ll
@@ -15,7 +15,7 @@ define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) {
 ; lowering we also need to adjust the cost.
 %T0_10 = type <16 x i16>
 %T1_10 = type <16 x i1>
-; CHECK: func_blend10:
+; CHECK-LABEL: func_blend10:
 define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2,
                            %T1_10* %blend, %T0_10* %storeaddr) {
   %v0 = load %T0_10* %loadaddr
@@ -31,7 +31,7 @@ define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2,
 }
 %T0_14 = type <8 x i32>
 %T1_14 = type <8 x i1>
-; CHECK: func_blend14:
+; CHECK-LABEL: func_blend14:
 define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2,
                            %T1_14* %blend, %T0_14* %storeaddr) {
   %v0 = load %T0_14* %loadaddr
@@ -47,7 +47,7 @@ define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2,
 }
 %T0_15 = type <16 x i32>
 %T1_15 = type <16 x i1>
-; CHECK: func_blend15:
+; CHECK-LABEL: func_blend15:
 define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2,
                            %T1_15* %blend, %T0_15* %storeaddr) {
 ; CHECK: vbsl
@@ -63,7 +63,7 @@ define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2,
 }
 %T0_18 = type <4 x i64>
 %T1_18 = type <4 x i1>
-; CHECK: func_blend18:
+; CHECK-LABEL: func_blend18:
 define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2,
                            %T1_18* %blend, %T0_18* %storeaddr) {
 ; CHECK: vbsl
@@ -79,7 +79,7 @@ define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2,
 }
 %T0_19 = type <8 x i64>
 %T1_19 = type <8 x i1>
-; CHECK: func_blend19:
+; CHECK-LABEL: func_blend19:
 define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2,
                            %T1_19* %blend, %T0_19* %storeaddr) {
 ; CHECK: vbsl
@@ -97,7 +97,7 @@ define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2,
 }
 %T0_20 = type <16 x i64>
 %T1_20 = type <16 x i1>
-; CHECK: func_blend20:
+; CHECK-LABEL: func_blend20:
 define void @func_blend20(%T0_20* %loadaddr, %T0_20* %loadaddr2,
                            %T1_20* %blend, %T0_20* %storeaddr) {
 ; CHECK: vbsl
diff --git a/test/CodeGen/ARM/vshift.ll b/test/CodeGen/ARM/vshift.ll
index f3cbec7..de380d3 100644
--- a/test/CodeGen/ARM/vshift.ll
+++ b/test/CodeGen/ARM/vshift.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vshls8:
+;CHECK-LABEL: vshls8:
 ;CHECK: vshl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vshls16:
+;CHECK-LABEL: vshls16:
 ;CHECK: vshl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vshls32:
+;CHECK-LABEL: vshls32:
 ;CHECK: vshl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vshls64:
+;CHECK-LABEL: vshls64:
 ;CHECK: vshl.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
-;CHECK: vshli8:
+;CHECK-LABEL: vshli8:
 ;CHECK: vshl.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
@@ -45,7 +45,7 @@ define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
-;CHECK: vshli16:
+;CHECK-LABEL: vshli16:
 ;CHECK: vshl.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >
@@ -53,7 +53,7 @@ define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
-;CHECK: vshli32:
+;CHECK-LABEL: vshli32:
 ;CHECK: vshl.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 >
@@ -61,7 +61,7 @@ define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
-;CHECK: vshli64:
+;CHECK-LABEL: vshli64:
 ;CHECK: vshl.i64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = shl <1 x i64> %tmp1, < i64 63 >
@@ -69,7 +69,7 @@ define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vshlQs8:
+;CHECK-LABEL: vshlQs8:
 ;CHECK: vshl.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -78,7 +78,7 @@ define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vshlQs16:
+;CHECK-LABEL: vshlQs16:
 ;CHECK: vshl.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -87,7 +87,7 @@ define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vshlQs32:
+;CHECK-LABEL: vshlQs32:
 ;CHECK: vshl.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -96,7 +96,7 @@ define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vshlQs64:
+;CHECK-LABEL: vshlQs64:
 ;CHECK: vshl.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -105,7 +105,7 @@ define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
-;CHECK: vshlQi8:
+;CHECK-LABEL: vshlQi8:
 ;CHECK: vshl.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
@@ -113,7 +113,7 @@ define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
-;CHECK: vshlQi16:
+;CHECK-LABEL: vshlQi16:
 ;CHECK: vshl.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
@@ -121,7 +121,7 @@ define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
-;CHECK: vshlQi32:
+;CHECK-LABEL: vshlQi32:
 ;CHECK: vshl.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >
@@ -129,7 +129,7 @@ define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
-;CHECK: vshlQi64:
+;CHECK-LABEL: vshlQi64:
 ;CHECK: vshl.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 >
@@ -137,7 +137,7 @@ define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vlshru8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vlshru8:
+;CHECK-LABEL: vlshru8:
 ;CHECK: vneg.s8
 ;CHECK: vshl.u8
 	%tmp1 = load <8 x i8>* %A
@@ -147,7 +147,7 @@ define <8 x i8> @vlshru8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vlshru16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vlshru16:
+;CHECK-LABEL: vlshru16:
 ;CHECK: vneg.s16
 ;CHECK: vshl.u16
 	%tmp1 = load <4 x i16>* %A
@@ -157,7 +157,7 @@ define <4 x i16> @vlshru16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vlshru32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vlshru32:
+;CHECK-LABEL: vlshru32:
 ;CHECK: vneg.s32
 ;CHECK: vshl.u32
 	%tmp1 = load <2 x i32>* %A
@@ -167,7 +167,7 @@ define <2 x i32> @vlshru32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vlshru64:
+;CHECK-LABEL: vlshru64:
 ;CHECK: vsub.i64
 ;CHECK: vshl.u64
 	%tmp1 = load <1 x i64>* %A
@@ -177,7 +177,7 @@ define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind {
-;CHECK: vlshri8:
+;CHECK-LABEL: vlshri8:
 ;CHECK: vshr.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = lshr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
@@ -185,7 +185,7 @@ define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind {
-;CHECK: vlshri16:
+;CHECK-LABEL: vlshri16:
 ;CHECK: vshr.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = lshr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
@@ -193,7 +193,7 @@ define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind {
-;CHECK: vlshri32:
+;CHECK-LABEL: vlshri32:
 ;CHECK: vshr.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = lshr <2 x i32> %tmp1, < i32 32, i32 32 >
@@ -201,7 +201,7 @@ define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vlshri64(<1 x i64>* %A) nounwind {
-;CHECK: vlshri64:
+;CHECK-LABEL: vlshri64:
 ;CHECK: vshr.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = lshr <1 x i64> %tmp1, < i64 64 >
@@ -209,7 +209,7 @@ define <1 x i64> @vlshri64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vlshrQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vlshrQu8:
+;CHECK-LABEL: vlshrQu8:
 ;CHECK: vneg.s8
 ;CHECK: vshl.u8
 	%tmp1 = load <16 x i8>* %A
@@ -219,7 +219,7 @@ define <16 x i8> @vlshrQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vlshrQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vlshrQu16:
+;CHECK-LABEL: vlshrQu16:
 ;CHECK: vneg.s16
 ;CHECK: vshl.u16
 	%tmp1 = load <8 x i16>* %A
@@ -229,7 +229,7 @@ define <8 x i16> @vlshrQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vlshrQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vlshrQu32:
+;CHECK-LABEL: vlshrQu32:
 ;CHECK: vneg.s32
 ;CHECK: vshl.u32
 	%tmp1 = load <4 x i32>* %A
@@ -239,7 +239,7 @@ define <4 x i32> @vlshrQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vlshrQu64:
+;CHECK-LABEL: vlshrQu64:
 ;CHECK: vsub.i64
 ;CHECK: vshl.u64
 	%tmp1 = load <2 x i64>* %A
@@ -249,7 +249,7 @@ define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind {
-;CHECK: vlshrQi8:
+;CHECK-LABEL: vlshrQi8:
 ;CHECK: vshr.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = lshr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
@@ -257,7 +257,7 @@ define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind {
-;CHECK: vlshrQi16:
+;CHECK-LABEL: vlshrQi16:
 ;CHECK: vshr.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = lshr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
@@ -265,7 +265,7 @@ define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind {
-;CHECK: vlshrQi32:
+;CHECK-LABEL: vlshrQi32:
 ;CHECK: vshr.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = lshr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
@@ -273,7 +273,7 @@ define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vlshrQi64(<2 x i64>* %A) nounwind {
-;CHECK: vlshrQi64:
+;CHECK-LABEL: vlshrQi64:
 ;CHECK: vshr.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = lshr <2 x i64> %tmp1, < i64 64, i64 64 >
@@ -288,7 +288,7 @@ entry:
 }
 
 define <8 x i8> @vashrs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vashrs8:
+;CHECK-LABEL: vashrs8:
 ;CHECK: vneg.s8
 ;CHECK: vshl.s8
 	%tmp1 = load <8 x i8>* %A
@@ -298,7 +298,7 @@ define <8 x i8> @vashrs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vashrs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vashrs16:
+;CHECK-LABEL: vashrs16:
 ;CHECK: vneg.s16
 ;CHECK: vshl.s16
 	%tmp1 = load <4 x i16>* %A
@@ -308,7 +308,7 @@ define <4 x i16> @vashrs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vashrs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vashrs32:
+;CHECK-LABEL: vashrs32:
 ;CHECK: vneg.s32
 ;CHECK: vshl.s32
 	%tmp1 = load <2 x i32>* %A
@@ -318,7 +318,7 @@ define <2 x i32> @vashrs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vashrs64:
+;CHECK-LABEL: vashrs64:
 ;CHECK: vsub.i64
 ;CHECK: vshl.s64
 	%tmp1 = load <1 x i64>* %A
@@ -328,7 +328,7 @@ define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vashri8(<8 x i8>* %A) nounwind {
-;CHECK: vashri8:
+;CHECK-LABEL: vashri8:
 ;CHECK: vshr.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = ashr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
@@ -336,7 +336,7 @@ define <8 x i8> @vashri8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vashri16(<4 x i16>* %A) nounwind {
-;CHECK: vashri16:
+;CHECK-LABEL: vashri16:
 ;CHECK: vshr.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = ashr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
@@ -344,7 +344,7 @@ define <4 x i16> @vashri16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vashri32(<2 x i32>* %A) nounwind {
-;CHECK: vashri32:
+;CHECK-LABEL: vashri32:
 ;CHECK: vshr.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = ashr <2 x i32> %tmp1, < i32 32, i32 32 >
@@ -352,7 +352,7 @@ define <2 x i32> @vashri32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vashri64(<1 x i64>* %A) nounwind {
-;CHECK: vashri64:
+;CHECK-LABEL: vashri64:
 ;CHECK: vshr.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = ashr <1 x i64> %tmp1, < i64 64 >
@@ -360,7 +360,7 @@ define <1 x i64> @vashri64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vashrQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vashrQs8:
+;CHECK-LABEL: vashrQs8:
 ;CHECK: vneg.s8
 ;CHECK: vshl.s8
 	%tmp1 = load <16 x i8>* %A
@@ -370,7 +370,7 @@ define <16 x i8> @vashrQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vashrQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vashrQs16:
+;CHECK-LABEL: vashrQs16:
 ;CHECK: vneg.s16
 ;CHECK: vshl.s16
 	%tmp1 = load <8 x i16>* %A
@@ -380,7 +380,7 @@ define <8 x i16> @vashrQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vashrQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vashrQs32:
+;CHECK-LABEL: vashrQs32:
 ;CHECK: vneg.s32
 ;CHECK: vshl.s32
 	%tmp1 = load <4 x i32>* %A
@@ -390,7 +390,7 @@ define <4 x i32> @vashrQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vashrQs64:
+;CHECK-LABEL: vashrQs64:
 ;CHECK: vsub.i64
 ;CHECK: vshl.s64
 	%tmp1 = load <2 x i64>* %A
@@ -400,7 +400,7 @@ define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind {
-;CHECK: vashrQi8:
+;CHECK-LABEL: vashrQi8:
 ;CHECK: vshr.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = ashr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
@@ -408,7 +408,7 @@ define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind {
-;CHECK: vashrQi16:
+;CHECK-LABEL: vashrQi16:
 ;CHECK: vshr.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = ashr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
@@ -416,7 +416,7 @@ define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind {
-;CHECK: vashrQi32:
+;CHECK-LABEL: vashrQi32:
 ;CHECK: vshr.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = ashr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
@@ -424,7 +424,7 @@ define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vashrQi64(<2 x i64>* %A) nounwind {
-;CHECK: vashrQi64:
+;CHECK-LABEL: vashrQi64:
 ;CHECK: vshr.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = ashr <2 x i64> %tmp1, < i64 64, i64 64 >
diff --git a/test/CodeGen/ARM/vshiftins.ll b/test/CodeGen/ARM/vshiftins.ll
index 3a4f857..27610bf 100644
--- a/test/CodeGen/ARM/vshiftins.ll
+++ b/test/CodeGen/ARM/vshiftins.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsli8:
+;CHECK-LABEL: vsli8:
 ;CHECK: vsli.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsli16:
+;CHECK-LABEL: vsli16:
 ;CHECK: vsli.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsli32:
+;CHECK-LABEL: vsli32:
 ;CHECK: vsli.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsli64:
+;CHECK-LABEL: vsli64:
 ;CHECK: vsli.64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsliQ8:
+;CHECK-LABEL: vsliQ8:
 ;CHECK: vsli.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -46,7 +46,7 @@ define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsliQ16:
+;CHECK-LABEL: vsliQ16:
 ;CHECK: vsli.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -55,7 +55,7 @@ define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsliQ32:
+;CHECK-LABEL: vsliQ32:
 ;CHECK: vsli.32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -64,7 +64,7 @@ define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsliQ64:
+;CHECK-LABEL: vsliQ64:
 ;CHECK: vsli.64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -73,7 +73,7 @@ define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsri8:
+;CHECK-LABEL: vsri8:
 ;CHECK: vsri.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -82,7 +82,7 @@ define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsri16:
+;CHECK-LABEL: vsri16:
 ;CHECK: vsri.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -91,7 +91,7 @@ define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsri32:
+;CHECK-LABEL: vsri32:
 ;CHECK: vsri.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -100,7 +100,7 @@ define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsri64:
+;CHECK-LABEL: vsri64:
 ;CHECK: vsri.64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -109,7 +109,7 @@ define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsriQ8:
+;CHECK-LABEL: vsriQ8:
 ;CHECK: vsri.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsriQ16:
+;CHECK-LABEL: vsriQ16:
 ;CHECK: vsri.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsriQ32:
+;CHECK-LABEL: vsriQ32:
 ;CHECK: vsri.32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsriQ64:
+;CHECK-LABEL: vsriQ64:
 ;CHECK: vsri.64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
diff --git a/test/CodeGen/ARM/vshl.ll b/test/CodeGen/ARM/vshl.ll
index 818e71b..462f7fe 100644
--- a/test/CodeGen/ARM/vshl.ll
+++ b/test/CodeGen/ARM/vshl.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vshls8:
+;CHECK-LABEL: vshls8:
 ;CHECK: vshl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vshls16:
+;CHECK-LABEL: vshls16:
 ;CHECK: vshl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vshls32:
+;CHECK-LABEL: vshls32:
 ;CHECK: vshl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vshls64:
+;CHECK-LABEL: vshls64:
 ;CHECK: vshl.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vshlu8:
+;CHECK-LABEL: vshlu8:
 ;CHECK: vshl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vshlu16:
+;CHECK-LABEL: vshlu16:
 ;CHECK: vshl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -55,7 +55,7 @@ define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vshlu32:
+;CHECK-LABEL: vshlu32:
 ;CHECK: vshl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -64,7 +64,7 @@ define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vshlu64:
+;CHECK-LABEL: vshlu64:
 ;CHECK: vshl.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -73,7 +73,7 @@ define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vshlQs8:
+;CHECK-LABEL: vshlQs8:
 ;CHECK: vshl.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vshlQs16:
+;CHECK-LABEL: vshlQs16:
 ;CHECK: vshl.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vshlQs32:
+;CHECK-LABEL: vshlQs32:
 ;CHECK: vshl.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vshlQs64:
+;CHECK-LABEL: vshlQs64:
 ;CHECK: vshl.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -109,7 +109,7 @@ define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vshlQu8:
+;CHECK-LABEL: vshlQu8:
 ;CHECK: vshl.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vshlQu16:
+;CHECK-LABEL: vshlQu16:
 ;CHECK: vshl.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vshlQu32:
+;CHECK-LABEL: vshlQu32:
 ;CHECK: vshl.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vshlQu64:
+;CHECK-LABEL: vshlQu64:
 ;CHECK: vshl.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -148,7 +148,7 @@ define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ; Test a mix of both signed and unsigned intrinsics.
 
 define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
-;CHECK: vshli8:
+;CHECK-LABEL: vshli8:
 ;CHECK: vshl.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -156,7 +156,7 @@ define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
-;CHECK: vshli16:
+;CHECK-LABEL: vshli16:
 ;CHECK: vshl.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -164,7 +164,7 @@ define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
-;CHECK: vshli32:
+;CHECK-LABEL: vshli32:
 ;CHECK: vshl.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -172,7 +172,7 @@ define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
-;CHECK: vshli64:
+;CHECK-LABEL: vshli64:
 ;CHECK: vshl.i64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
@@ -180,7 +180,7 @@ define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
-;CHECK: vshlQi8:
+;CHECK-LABEL: vshlQi8:
 ;CHECK: vshl.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -188,7 +188,7 @@ define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
-;CHECK: vshlQi16:
+;CHECK-LABEL: vshlQi16:
 ;CHECK: vshl.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
@@ -196,7 +196,7 @@ define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
-;CHECK: vshlQi32:
+;CHECK-LABEL: vshlQi32:
 ;CHECK: vshl.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
@@ -204,7 +204,7 @@ define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
-;CHECK: vshlQi64:
+;CHECK-LABEL: vshlQi64:
 ;CHECK: vshl.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
@@ -214,7 +214,7 @@ define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
 ; Right shift by immediate:
 
 define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind {
-;CHECK: vshrs8:
+;CHECK-LABEL: vshrs8:
 ;CHECK: vshr.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -222,7 +222,7 @@ define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind {
-;CHECK: vshrs16:
+;CHECK-LABEL: vshrs16:
 ;CHECK: vshr.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -230,7 +230,7 @@ define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind {
-;CHECK: vshrs32:
+;CHECK-LABEL: vshrs32:
 ;CHECK: vshr.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
@@ -238,7 +238,7 @@ define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind {
-;CHECK: vshrs64:
+;CHECK-LABEL: vshrs64:
 ;CHECK: vshr.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
@@ -246,7 +246,7 @@ define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vshru8(<8 x i8>* %A) nounwind {
-;CHECK: vshru8:
+;CHECK-LABEL: vshru8:
 ;CHECK: vshr.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -254,7 +254,7 @@ define <8 x i8> @vshru8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vshru16(<4 x i16>* %A) nounwind {
-;CHECK: vshru16:
+;CHECK-LABEL: vshru16:
 ;CHECK: vshr.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -262,7 +262,7 @@ define <4 x i16> @vshru16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vshru32(<2 x i32>* %A) nounwind {
-;CHECK: vshru32:
+;CHECK-LABEL: vshru32:
 ;CHECK: vshr.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
@@ -270,7 +270,7 @@ define <2 x i32> @vshru32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vshru64(<1 x i64>* %A) nounwind {
-;CHECK: vshru64:
+;CHECK-LABEL: vshru64:
 ;CHECK: vshr.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
@@ -278,7 +278,7 @@ define <1 x i64> @vshru64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind {
-;CHECK: vshrQs8:
+;CHECK-LABEL: vshrQs8:
 ;CHECK: vshr.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -286,7 +286,7 @@ define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind {
-;CHECK: vshrQs16:
+;CHECK-LABEL: vshrQs16:
 ;CHECK: vshr.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -294,7 +294,7 @@ define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind {
-;CHECK: vshrQs32:
+;CHECK-LABEL: vshrQs32:
 ;CHECK: vshr.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
@@ -302,7 +302,7 @@ define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind {
-;CHECK: vshrQs64:
+;CHECK-LABEL: vshrQs64:
 ;CHECK: vshr.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
@@ -310,7 +310,7 @@ define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind {
-;CHECK: vshrQu8:
+;CHECK-LABEL: vshrQu8:
 ;CHECK: vshr.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -318,7 +318,7 @@ define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind {
-;CHECK: vshrQu16:
+;CHECK-LABEL: vshrQu16:
 ;CHECK: vshr.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -326,7 +326,7 @@ define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind {
-;CHECK: vshrQu32:
+;CHECK-LABEL: vshrQu32:
 ;CHECK: vshr.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
@@ -334,7 +334,7 @@ define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vshrQu64(<2 x i64>* %A) nounwind {
-;CHECK: vshrQu64:
+;CHECK-LABEL: vshrQu64:
 ;CHECK: vshr.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
@@ -362,7 +362,7 @@ declare <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind re
 declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrshls8:
+;CHECK-LABEL: vrshls8:
 ;CHECK: vrshl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -371,7 +371,7 @@ define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrshls16:
+;CHECK-LABEL: vrshls16:
 ;CHECK: vrshl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -380,7 +380,7 @@ define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrshls32:
+;CHECK-LABEL: vrshls32:
 ;CHECK: vrshl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -389,7 +389,7 @@ define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrshls64:
+;CHECK-LABEL: vrshls64:
 ;CHECK: vrshl.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -398,7 +398,7 @@ define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrshlu8:
+;CHECK-LABEL: vrshlu8:
 ;CHECK: vrshl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -407,7 +407,7 @@ define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrshlu16:
+;CHECK-LABEL: vrshlu16:
 ;CHECK: vrshl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -416,7 +416,7 @@ define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrshlu32:
+;CHECK-LABEL: vrshlu32:
 ;CHECK: vrshl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -425,7 +425,7 @@ define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrshlu64:
+;CHECK-LABEL: vrshlu64:
 ;CHECK: vrshl.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -434,7 +434,7 @@ define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrshlQs8:
+;CHECK-LABEL: vrshlQs8:
 ;CHECK: vrshl.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -443,7 +443,7 @@ define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrshlQs16:
+;CHECK-LABEL: vrshlQs16:
 ;CHECK: vrshl.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -452,7 +452,7 @@ define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrshlQs32:
+;CHECK-LABEL: vrshlQs32:
 ;CHECK: vrshl.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -461,7 +461,7 @@ define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrshlQs64:
+;CHECK-LABEL: vrshlQs64:
 ;CHECK: vrshl.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -470,7 +470,7 @@ define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrshlQu8:
+;CHECK-LABEL: vrshlQu8:
 ;CHECK: vrshl.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -479,7 +479,7 @@ define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrshlQu16:
+;CHECK-LABEL: vrshlQu16:
 ;CHECK: vrshl.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -488,7 +488,7 @@ define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrshlQu32:
+;CHECK-LABEL: vrshlQu32:
 ;CHECK: vrshl.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -497,7 +497,7 @@ define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrshlQu64:
+;CHECK-LABEL: vrshlQu64:
 ;CHECK: vrshl.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -506,7 +506,7 @@ define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind {
-;CHECK: vrshrs8:
+;CHECK-LABEL: vrshrs8:
 ;CHECK: vrshr.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -514,7 +514,7 @@ define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind {
-;CHECK: vrshrs16:
+;CHECK-LABEL: vrshrs16:
 ;CHECK: vrshr.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -522,7 +522,7 @@ define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind {
-;CHECK: vrshrs32:
+;CHECK-LABEL: vrshrs32:
 ;CHECK: vrshr.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
@@ -530,7 +530,7 @@ define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind {
-;CHECK: vrshrs64:
+;CHECK-LABEL: vrshrs64:
 ;CHECK: vrshr.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
@@ -538,7 +538,7 @@ define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind {
-;CHECK: vrshru8:
+;CHECK-LABEL: vrshru8:
 ;CHECK: vrshr.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -546,7 +546,7 @@ define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind {
-;CHECK: vrshru16:
+;CHECK-LABEL: vrshru16:
 ;CHECK: vrshr.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -554,7 +554,7 @@ define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind {
-;CHECK: vrshru32:
+;CHECK-LABEL: vrshru32:
 ;CHECK: vrshr.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
@@ -562,7 +562,7 @@ define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind {
-;CHECK: vrshru64:
+;CHECK-LABEL: vrshru64:
 ;CHECK: vrshr.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
@@ -570,7 +570,7 @@ define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind {
-;CHECK: vrshrQs8:
+;CHECK-LABEL: vrshrQs8:
 ;CHECK: vrshr.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -578,7 +578,7 @@ define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind {
-;CHECK: vrshrQs16:
+;CHECK-LABEL: vrshrQs16:
 ;CHECK: vrshr.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -586,7 +586,7 @@ define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind {
-;CHECK: vrshrQs32:
+;CHECK-LABEL: vrshrQs32:
 ;CHECK: vrshr.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
@@ -594,7 +594,7 @@ define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind {
-;CHECK: vrshrQs64:
+;CHECK-LABEL: vrshrQs64:
 ;CHECK: vrshr.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
@@ -602,7 +602,7 @@ define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind {
-;CHECK: vrshrQu8:
+;CHECK-LABEL: vrshrQu8:
 ;CHECK: vrshr.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -610,7 +610,7 @@ define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind {
-;CHECK: vrshrQu16:
+;CHECK-LABEL: vrshrQu16:
 ;CHECK: vrshr.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -618,7 +618,7 @@ define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind {
-;CHECK: vrshrQu32:
+;CHECK-LABEL: vrshrQu32:
 ;CHECK: vrshr.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
@@ -626,7 +626,7 @@ define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vrshrQu64(<2 x i64>* %A) nounwind {
-;CHECK: vrshrQu64:
+;CHECK-LABEL: vrshrQu64:
 ;CHECK: vrshr.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
diff --git a/test/CodeGen/ARM/vshll.ll b/test/CodeGen/ARM/vshll.ll
index 8e85b98..ae80664 100644
--- a/test/CodeGen/ARM/vshll.ll
+++ b/test/CodeGen/ARM/vshll.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind {
-;CHECK: vshlls8:
+;CHECK-LABEL: vshlls8:
 ;CHECK: vshll.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -9,7 +9,7 @@ define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind {
-;CHECK: vshlls16:
+;CHECK-LABEL: vshlls16:
 ;CHECK: vshll.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -17,7 +17,7 @@ define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind {
-;CHECK: vshlls32:
+;CHECK-LABEL: vshlls32:
 ;CHECK: vshll.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -25,7 +25,7 @@ define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind {
 }
 
 define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind {
-;CHECK: vshllu8:
+;CHECK-LABEL: vshllu8:
 ;CHECK: vshll.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -33,7 +33,7 @@ define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind {
-;CHECK: vshllu16:
+;CHECK-LABEL: vshllu16:
 ;CHECK: vshll.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -41,7 +41,7 @@ define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
-;CHECK: vshllu32:
+;CHECK-LABEL: vshllu32:
 ;CHECK: vshll.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -51,7 +51,7 @@ define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
 ; The following tests use the maximum shift count, so the signedness is
 ; irrelevant.  Test both signed and unsigned versions.
 define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind {
-;CHECK: vshlli8:
+;CHECK-LABEL: vshlli8:
 ;CHECK: vshll.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >)
@@ -59,7 +59,7 @@ define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind {
-;CHECK: vshlli16:
+;CHECK-LABEL: vshlli16:
 ;CHECK: vshll.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 16, i16 16, i16 16, i16 16 >)
@@ -67,7 +67,7 @@ define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind {
-;CHECK: vshlli32:
+;CHECK-LABEL: vshlli32:
 ;CHECK: vshll.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >)
diff --git a/test/CodeGen/ARM/vshrn.ll b/test/CodeGen/ARM/vshrn.ll
index e2544f4..40a94fe 100644
--- a/test/CodeGen/ARM/vshrn.ll
+++ b/test/CodeGen/ARM/vshrn.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vshrns8:
+;CHECK-LABEL: vshrns8:
 ;CHECK: vshrn.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -9,7 +9,7 @@ define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vshrns16:
+;CHECK-LABEL: vshrns16:
 ;CHECK: vshrn.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -17,7 +17,7 @@ define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vshrns32:
+;CHECK-LABEL: vshrns32:
 ;CHECK: vshrn.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -29,7 +29,7 @@ declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind re
 declare <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vrshrns8:
+;CHECK-LABEL: vrshrns8:
 ;CHECK: vrshrn.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -37,7 +37,7 @@ define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vrshrns16:
+;CHECK-LABEL: vrshrns16:
 ;CHECK: vrshrn.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -45,7 +45,7 @@ define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vrshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vrshrns32:
+;CHECK-LABEL: vrshrns32:
 ;CHECK: vrshrn.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
diff --git a/test/CodeGen/ARM/vsra.ll b/test/CodeGen/ARM/vsra.ll
index acb672d..7a211c3 100644
--- a/test/CodeGen/ARM/vsra.ll
+++ b/test/CodeGen/ARM/vsra.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsras8:
+;CHECK-LABEL: vsras8:
 ;CHECK: vsra.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsras16:
+;CHECK-LABEL: vsras16:
 ;CHECK: vsra.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -21,7 +21,7 @@ define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsras32:
+;CHECK-LABEL: vsras32:
 ;CHECK: vsra.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -31,7 +31,7 @@ define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsras64:
+;CHECK-LABEL: vsras64:
 ;CHECK: vsra.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -41,7 +41,7 @@ define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsraQs8:
+;CHECK-LABEL: vsraQs8:
 ;CHECK: vsra.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -51,7 +51,7 @@ define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsraQs16:
+;CHECK-LABEL: vsraQs16:
 ;CHECK: vsra.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -61,7 +61,7 @@ define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsraQs32:
+;CHECK-LABEL: vsraQs32:
 ;CHECK: vsra.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -71,7 +71,7 @@ define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsraQs64:
+;CHECK-LABEL: vsraQs64:
 ;CHECK: vsra.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -81,7 +81,7 @@ define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsrau8:
+;CHECK-LABEL: vsrau8:
 ;CHECK: vsra.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -91,7 +91,7 @@ define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsrau16:
+;CHECK-LABEL: vsrau16:
 ;CHECK: vsra.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -101,7 +101,7 @@ define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsrau32:
+;CHECK-LABEL: vsrau32:
 ;CHECK: vsra.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -111,7 +111,7 @@ define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsrau64:
+;CHECK-LABEL: vsrau64:
 ;CHECK: vsra.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -121,7 +121,7 @@ define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsraQu8:
+;CHECK-LABEL: vsraQu8:
 ;CHECK: vsra.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -131,7 +131,7 @@ define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsraQu16:
+;CHECK-LABEL: vsraQu16:
 ;CHECK: vsra.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -141,7 +141,7 @@ define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsraQu32:
+;CHECK-LABEL: vsraQu32:
 ;CHECK: vsra.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -151,7 +151,7 @@ define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsraQu64:
+;CHECK-LABEL: vsraQu64:
 ;CHECK: vsra.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -161,7 +161,7 @@ define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrsras8:
+;CHECK-LABEL: vrsras8:
 ;CHECK: vrsra.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -171,7 +171,7 @@ define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrsras16:
+;CHECK-LABEL: vrsras16:
 ;CHECK: vrsra.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -181,7 +181,7 @@ define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrsras32:
+;CHECK-LABEL: vrsras32:
 ;CHECK: vrsra.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -191,7 +191,7 @@ define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrsras64:
+;CHECK-LABEL: vrsras64:
 ;CHECK: vrsra.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -201,7 +201,7 @@ define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrsrau8:
+;CHECK-LABEL: vrsrau8:
 ;CHECK: vrsra.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -211,7 +211,7 @@ define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrsrau16:
+;CHECK-LABEL: vrsrau16:
 ;CHECK: vrsra.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -221,7 +221,7 @@ define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrsrau32:
+;CHECK-LABEL: vrsrau32:
 ;CHECK: vrsra.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -231,7 +231,7 @@ define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrsrau64:
+;CHECK-LABEL: vrsrau64:
 ;CHECK: vrsra.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -241,7 +241,7 @@ define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrsraQs8:
+;CHECK-LABEL: vrsraQs8:
 ;CHECK: vrsra.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -251,7 +251,7 @@ define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrsraQs16:
+;CHECK-LABEL: vrsraQs16:
 ;CHECK: vrsra.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -261,7 +261,7 @@ define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrsraQs32:
+;CHECK-LABEL: vrsraQs32:
 ;CHECK: vrsra.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -271,7 +271,7 @@ define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrsraQs64:
+;CHECK-LABEL: vrsraQs64:
 ;CHECK: vrsra.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -281,7 +281,7 @@ define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrsraQu8:
+;CHECK-LABEL: vrsraQu8:
 ;CHECK: vrsra.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -291,7 +291,7 @@ define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrsraQu16:
+;CHECK-LABEL: vrsraQu16:
 ;CHECK: vrsra.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -301,7 +301,7 @@ define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrsraQu32:
+;CHECK-LABEL: vrsraQu32:
 ;CHECK: vrsra.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -311,7 +311,7 @@ define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vrsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrsraQu64:
+;CHECK-LABEL: vrsraQu64:
 ;CHECK: vrsra.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
diff --git a/test/CodeGen/ARM/vst1.ll b/test/CodeGen/ARM/vst1.ll
index e1f3e88..36439fd 100644
--- a/test/CodeGen/ARM/vst1.ll
+++ b/test/CodeGen/ARM/vst1.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst1i8:
+;CHECK-LABEL: vst1i8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vst1.8 {d16}, [r0:64]
 	%tmp1 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
 }
 
 define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst1i16:
+;CHECK-LABEL: vst1i16:
 ;CHECK: vst1.16
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst1i32:
+;CHECK-LABEL: vst1i32:
 ;CHECK: vst1.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define void @vst1f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst1f:
+;CHECK-LABEL: vst1f:
 ;CHECK: vst1.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -38,7 +38,7 @@ define void @vst1f(float* %A, <2 x float>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind {
-;CHECK: vst1f_update:
+;CHECK-LABEL: vst1f_update:
 ;CHECK: vst1.32 {d16}, [r1]!
 	%A = load float** %ptr
 	%tmp0 = bitcast float* %A to i8*
@@ -50,7 +50,7 @@ define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind {
 }
 
 define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst1i64:
+;CHECK-LABEL: vst1i64:
 ;CHECK: vst1.64
 	%tmp0 = bitcast i64* %A to i8*
 	%tmp1 = load <1 x i64>* %B
@@ -59,7 +59,7 @@ define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind {
 }
 
 define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst1Qi8:
+;CHECK-LABEL: vst1Qi8:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst1.8 {d16, d17}, [r0:64]
 	%tmp1 = load <16 x i8>* %B
@@ -68,7 +68,7 @@ define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
 }
 
 define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst1Qi16:
+;CHECK-LABEL: vst1Qi16:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst1.16 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -79,7 +79,7 @@ define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
 
 ;Check for a post-increment updating store with register increment.
 define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
-;CHECK: vst1Qi16_update:
+;CHECK-LABEL: vst1Qi16_update:
 ;CHECK: vst1.16 {d16, d17}, [r1:64], r2
 	%A = load i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
@@ -91,7 +91,7 @@ define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
 }
 
 define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst1Qi32:
+;CHECK-LABEL: vst1Qi32:
 ;CHECK: vst1.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define void @vst1Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst1Qf:
+;CHECK-LABEL: vst1Qf:
 ;CHECK: vst1.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
@@ -109,7 +109,7 @@ define void @vst1Qf(float* %A, <4 x float>* %B) nounwind {
 }
 
 define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind {
-;CHECK: vst1Qi64:
+;CHECK-LABEL: vst1Qi64:
 ;CHECK: vst1.64
 	%tmp0 = bitcast i64* %A to i8*
 	%tmp1 = load <2 x i64>* %B
diff --git a/test/CodeGen/ARM/vst2.ll b/test/CodeGen/ARM/vst2.ll
index a31f863..af82463 100644
--- a/test/CodeGen/ARM/vst2.ll
+++ b/test/CodeGen/ARM/vst2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst2i8:
+;CHECK-LABEL: vst2i8:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst2.8 {d16, d17}, [r0:64]
 	%tmp1 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
 
 ;Check for a post-increment updating store with register increment.
 define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
-;CHECK: vst2i8_update:
+;CHECK-LABEL: vst2i8_update:
 ;CHECK: vst2.8 {d16, d17}, [r1], r2
 	%A = load i8** %ptr
 	%tmp1 = load <8 x i8>* %B
@@ -22,7 +22,7 @@ define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
 }
 
 define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst2i16:
+;CHECK-LABEL: vst2i16:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst2.16 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -32,7 +32,7 @@ define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst2i32:
+;CHECK-LABEL: vst2i32:
 ;CHECK: vst2.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
@@ -41,7 +41,7 @@ define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define void @vst2f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst2f:
+;CHECK-LABEL: vst2f:
 ;CHECK: vst2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -50,7 +50,7 @@ define void @vst2f(float* %A, <2 x float>* %B) nounwind {
 }
 
 define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst2i64:
+;CHECK-LABEL: vst2i64:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst1.64 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i64* %A to i8*
@@ -61,7 +61,7 @@ define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
-;CHECK: vst2i64_update:
+;CHECK-LABEL: vst2i64_update:
 ;CHECK: vst1.64 {d16, d17}, [r1:64]!
 	%A = load i64** %ptr
 	%tmp0 = bitcast i64* %A to i8*
@@ -73,7 +73,7 @@ define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
 }
 
 define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst2Qi8:
+;CHECK-LABEL: vst2Qi8:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64]
 	%tmp1 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind {
 }
 
 define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst2Qi16:
+;CHECK-LABEL: vst2Qi16:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -92,7 +92,7 @@ define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst2Qi32:
+;CHECK-LABEL: vst2Qi32:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i32* %A to i8*
@@ -102,7 +102,7 @@ define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define void @vst2Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst2Qf:
+;CHECK-LABEL: vst2Qf:
 ;CHECK: vst2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
diff --git a/test/CodeGen/ARM/vst3.ll b/test/CodeGen/ARM/vst3.ll
index 281bb73..91eb7fc 100644
--- a/test/CodeGen/ARM/vst3.ll
+++ b/test/CodeGen/ARM/vst3.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon -fast-isel=0 -O0 | FileCheck %s
 
 define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst3i8:
+;CHECK-LABEL: vst3i8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;This test runs at -O0 so do not check for specific register numbers.
 ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
@@ -11,7 +11,7 @@ define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
 }
 
 define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst3i16:
+;CHECK-LABEL: vst3i16:
 ;CHECK: vst3.16
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = load <4 x i16>* %B
@@ -20,7 +20,7 @@ define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst3i32:
+;CHECK-LABEL: vst3i32:
 ;CHECK: vst3.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
@@ -30,7 +30,7 @@ define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst3i32_update(i32** %ptr, <2 x i32>* %B) nounwind {
-;CHECK: vst3i32_update:
+;CHECK-LABEL: vst3i32_update:
 ;CHECK: vst3.32 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
 	%A = load i32** %ptr
 	%tmp0 = bitcast i32* %A to i8*
@@ -42,7 +42,7 @@ define void @vst3i32_update(i32** %ptr, <2 x i32>* %B) nounwind {
 }
 
 define void @vst3f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst3f:
+;CHECK-LABEL: vst3f:
 ;CHECK: vst3.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -51,7 +51,7 @@ define void @vst3f(float* %A, <2 x float>* %B) nounwind {
 }
 
 define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst3i64:
+;CHECK-LABEL: vst3i64:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;This test runs at -O0 so do not check for specific register numbers.
 ;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
@@ -62,7 +62,7 @@ define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind {
 }
 
 define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst3Qi8:
+;CHECK-LABEL: vst3Qi8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;This test runs at -O0 so do not check for specific register numbers.
 ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]!
@@ -73,7 +73,7 @@ define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind {
 }
 
 define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst3Qi16:
+;CHECK-LABEL: vst3Qi16:
 ;CHECK: vst3.16
 ;CHECK: vst3.16
 	%tmp0 = bitcast i16* %A to i8*
@@ -84,7 +84,7 @@ define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst3Qi16_update(i16** %ptr, <8 x i16>* %B) nounwind {
-;CHECK: vst3Qi16_update:
+;CHECK-LABEL: vst3Qi16_update:
 ;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
 ;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
 	%A = load i16** %ptr
@@ -97,7 +97,7 @@ define void @vst3Qi16_update(i16** %ptr, <8 x i16>* %B) nounwind {
 }
 
 define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst3Qi32:
+;CHECK-LABEL: vst3Qi32:
 ;CHECK: vst3.32
 ;CHECK: vst3.32
 	%tmp0 = bitcast i32* %A to i8*
@@ -107,7 +107,7 @@ define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define void @vst3Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst3Qf:
+;CHECK-LABEL: vst3Qf:
 ;CHECK: vst3.32
 ;CHECK: vst3.32
 	%tmp0 = bitcast float* %A to i8*
diff --git a/test/CodeGen/ARM/vst4.ll b/test/CodeGen/ARM/vst4.ll
index 7dedb2f..ef5c83a 100644
--- a/test/CodeGen/ARM/vst4.ll
+++ b/test/CodeGen/ARM/vst4.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst4i8:
+;CHECK-LABEL: vst4i8:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64]
 	%tmp1 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
 
 ;Check for a post-increment updating store with register increment.
 define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
-;CHECK: vst4i8_update:
+;CHECK-LABEL: vst4i8_update:
 ;CHECK: vst4.8 {d16, d17, d18, d19}, [r1:128], r2
 	%A = load i8** %ptr
 	%tmp1 = load <8 x i8>* %B
@@ -22,7 +22,7 @@ define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
 }
 
 define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst4i16:
+;CHECK-LABEL: vst4i16:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -32,7 +32,7 @@ define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst4i32:
+;CHECK-LABEL: vst4i32:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst4.32 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i32* %A to i8*
@@ -42,7 +42,7 @@ define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define void @vst4f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst4f:
+;CHECK-LABEL: vst4f:
 ;CHECK: vst4.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -51,7 +51,7 @@ define void @vst4f(float* %A, <2 x float>* %B) nounwind {
 }
 
 define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst4i64:
+;CHECK-LABEL: vst4i64:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst1.64 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i64* %A to i8*
@@ -61,7 +61,7 @@ define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind {
 }
 
 define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst4Qi8:
+;CHECK-LABEL: vst4Qi8:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]!
 ;CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]
@@ -71,7 +71,7 @@ define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind {
 }
 
 define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst4Qi16:
+;CHECK-LABEL: vst4Qi16:
 ;Check for no alignment specifier.
 ;CHECK: vst4.16 {d16, d18, d20, d22}, [r0]!
 ;CHECK: vst4.16 {d17, d19, d21, d23}, [r0]
@@ -82,7 +82,7 @@ define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst4Qi32:
+;CHECK-LABEL: vst4Qi32:
 ;CHECK: vst4.32
 ;CHECK: vst4.32
 	%tmp0 = bitcast i32* %A to i8*
@@ -92,7 +92,7 @@ define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define void @vst4Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst4Qf:
+;CHECK-LABEL: vst4Qf:
 ;CHECK: vst4.32
 ;CHECK: vst4.32
 	%tmp0 = bitcast float* %A to i8*
@@ -103,7 +103,7 @@ define void @vst4Qf(float* %A, <4 x float>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst4Qf_update(float** %ptr, <4 x float>* %B) nounwind {
-;CHECK: vst4Qf_update:
+;CHECK-LABEL: vst4Qf_update:
 ;CHECK: vst4.32 {d16, d18, d20, d22}, [r1]!
 ;CHECK: vst4.32 {d17, d19, d21, d23}, [r1]!
 	%A = load float** %ptr
diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll
index 67f251f..651b6d5 100644
--- a/test/CodeGen/ARM/vstlane.ll
+++ b/test/CodeGen/ARM/vstlane.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst1lanei8:
+;CHECK-LABEL: vst1lanei8:
 ;Check the (default) alignment.
 ;CHECK: vst1.8 {d16[3]}, [r0]
 	%tmp1 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
-;CHECK: vst1lanei8_update:
+;CHECK-LABEL: vst1lanei8_update:
 ;CHECK: vst1.8 {d16[3]}, [r2]!
 	%A = load i8** %ptr
 	%tmp1 = load <8 x i8>* %B
@@ -24,7 +24,7 @@ define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
 }
 
 define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst1lanei16:
+;CHECK-LABEL: vst1lanei16:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vst1.16 {d16[2]}, [r0:16]
 	%tmp1 = load <4 x i16>* %B
@@ -34,7 +34,7 @@ define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst1lanei32:
+;CHECK-LABEL: vst1lanei32:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vst1.32 {d16[1]}, [r0:32]
 	%tmp1 = load <2 x i32>* %B
@@ -44,7 +44,7 @@ define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define void @vst1lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst1lanef:
+;CHECK-LABEL: vst1lanef:
 ;CHECK: vst1.32 {d16[1]}, [r0:32]
 	%tmp1 = load <2 x float>* %B
         %tmp2 = extractelement <2 x float> %tmp1, i32 1
@@ -53,7 +53,7 @@ define void @vst1lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst1laneQi8:
+;CHECK-LABEL: vst1laneQi8:
 ; // Can use scalar load. No need to use vectors.
 ; // CHE-CK: vst1.8 {d17[1]}, [r0]
 	%tmp1 = load <16 x i8>* %B
@@ -63,7 +63,7 @@ define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
 }
 
 define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst1laneQi16:
+;CHECK-LABEL: vst1laneQi16:
 ;CHECK: vst1.16 {d17[1]}, [r0:16]
 	%tmp1 = load <8 x i16>* %B
         %tmp2 = extractelement <8 x i16> %tmp1, i32 5
@@ -72,7 +72,7 @@ define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst1laneQi32:
+;CHECK-LABEL: vst1laneQi32:
 ; // Can use scalar load. No need to use vectors.
 ; // CHE-CK: vst1.32 {d17[1]}, [r0:32]
 	%tmp1 = load <4 x i32>* %B
@@ -83,7 +83,7 @@ define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
-;CHECK: vst1laneQi32_update:
+;CHECK-LABEL: vst1laneQi32_update:
 ; // Can use scalar load. No need to use vectors.
 ; // CHE-CK: vst1.32 {d17[1]}, [r1:32]!
 	%A = load i32** %ptr
@@ -96,7 +96,7 @@ define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
 }
 
 define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst1laneQf:
+;CHECK-LABEL: vst1laneQf:
 ; // Can use scalar load. No need to use vectors.
 ; // CHE-CK: vst1.32 {d17[1]}, [r0]
 	%tmp1 = load <4 x float>* %B
@@ -106,7 +106,7 @@ define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind {
 }
 
 define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst2lanei8:
+;CHECK-LABEL: vst2lanei8:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vst2.8 {d16[1], d17[1]}, [r0:16]
 	%tmp1 = load <8 x i8>* %B
@@ -115,7 +115,7 @@ define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
 }
 
 define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst2lanei16:
+;CHECK-LABEL: vst2lanei16:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vst2.16 {d16[1], d17[1]}, [r0:32]
 	%tmp0 = bitcast i16* %A to i8*
@@ -126,7 +126,7 @@ define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
 
 ;Check for a post-increment updating store with register increment.
 define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind {
-;CHECK: vst2lanei16_update:
+;CHECK-LABEL: vst2lanei16_update:
 ;CHECK: vst2.16 {d16[1], d17[1]}, [r1], r2
 	%A = load i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
@@ -138,7 +138,7 @@ define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind {
 }
 
 define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst2lanei32:
+;CHECK-LABEL: vst2lanei32:
 ;CHECK: vst2.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
@@ -147,7 +147,7 @@ define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define void @vst2lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst2lanef:
+;CHECK-LABEL: vst2lanef:
 ;CHECK: vst2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -156,7 +156,7 @@ define void @vst2lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst2laneQi16:
+;CHECK-LABEL: vst2laneQi16:
 ;Check the (default) alignment.
 ;CHECK: vst2.16 {d17[1], d19[1]}, [r0]
 	%tmp0 = bitcast i16* %A to i8*
@@ -166,7 +166,7 @@ define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst2laneQi32:
+;CHECK-LABEL: vst2laneQi32:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vst2.32 {d17[0], d19[0]}, [r0:64]
 	%tmp0 = bitcast i32* %A to i8*
@@ -176,7 +176,7 @@ define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define void @vst2laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst2laneQf:
+;CHECK-LABEL: vst2laneQf:
 ;CHECK: vst2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
@@ -194,7 +194,7 @@ declare void @llvm.arm.neon.vst2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32)
 declare void @llvm.arm.neon.vst2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind
 
 define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst3lanei8:
+;CHECK-LABEL: vst3lanei8:
 ;CHECK: vst3.8
 	%tmp1 = load <8 x i8>* %B
 	call void @llvm.arm.neon.vst3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
@@ -202,7 +202,7 @@ define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
 }
 
 define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst3lanei16:
+;CHECK-LABEL: vst3lanei16:
 ;Check the (default) alignment value.  VST3 does not support alignment.
 ;CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0]
 	%tmp0 = bitcast i16* %A to i8*
@@ -212,7 +212,7 @@ define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst3lanei32:
+;CHECK-LABEL: vst3lanei32:
 ;CHECK: vst3.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
@@ -221,7 +221,7 @@ define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst3lanef:
+;CHECK-LABEL: vst3lanef:
 ;CHECK: vst3.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -230,7 +230,7 @@ define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst3laneQi16:
+;CHECK-LABEL: vst3laneQi16:
 ;Check the (default) alignment value.  VST3 does not support alignment.
 ;CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0]
 	%tmp0 = bitcast i16* %A to i8*
@@ -240,7 +240,7 @@ define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst3laneQi32:
+;CHECK-LABEL: vst3laneQi32:
 ;CHECK: vst3.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <4 x i32>* %B
@@ -250,7 +250,7 @@ define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
-;CHECK: vst3laneQi32_update:
+;CHECK-LABEL: vst3laneQi32_update:
 ;CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r1]!
 	%A = load i32** %ptr
 	%tmp0 = bitcast i32* %A to i8*
@@ -262,7 +262,7 @@ define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
 }
 
 define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst3laneQf:
+;CHECK-LABEL: vst3laneQf:
 ;CHECK: vst3.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
@@ -281,7 +281,7 @@ declare void @llvm.arm.neon.vst3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x f
 
 
 define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst4lanei8:
+;CHECK-LABEL: vst4lanei8:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
 	%tmp1 = load <8 x i8>* %B
@@ -291,7 +291,7 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
-;CHECK: vst4lanei8_update:
+;CHECK-LABEL: vst4lanei8_update:
 ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!
 	%A = load i8** %ptr
 	%tmp1 = load <8 x i8>* %B
@@ -302,7 +302,7 @@ define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
 }
 
 define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst4lanei16:
+;CHECK-LABEL: vst4lanei16:
 ;CHECK: vst4.16
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = load <4 x i16>* %B
@@ -311,7 +311,7 @@ define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst4lanei32:
+;CHECK-LABEL: vst4lanei32:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
 	%tmp0 = bitcast i32* %A to i8*
@@ -321,7 +321,7 @@ define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define void @vst4lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst4lanef:
+;CHECK-LABEL: vst4lanef:
 ;CHECK: vst4.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -330,7 +330,7 @@ define void @vst4lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst4laneQi16:
+;CHECK-LABEL: vst4laneQi16:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]
 	%tmp0 = bitcast i16* %A to i8*
@@ -340,7 +340,7 @@ define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst4laneQi32:
+;CHECK-LABEL: vst4laneQi32:
 ;Check the (default) alignment.
 ;CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
 	%tmp0 = bitcast i32* %A to i8*
@@ -350,7 +350,7 @@ define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst4laneQf:
+;CHECK-LABEL: vst4laneQf:
 ;CHECK: vst4.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
@@ -360,7 +360,7 @@ define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind {
 
 ; Make sure this doesn't crash; PR10258
 define <8 x i16> @variable_insertelement(<8 x i16> %a, i16 %b, i32 %c) nounwind readnone {
-;CHECK: variable_insertelement:
+;CHECK-LABEL: variable_insertelement:
     %r = insertelement <8 x i16> %a, i16 %b, i32 %c
     ret <8 x i16> %r
 }
diff --git a/test/CodeGen/ARM/vsub.ll b/test/CodeGen/ARM/vsub.ll
index df77bb3..89c3095 100644
--- a/test/CodeGen/ARM/vsub.ll
+++ b/test/CodeGen/ARM/vsub.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubi8:
+;CHECK-LABEL: vsubi8:
 ;CHECK: vsub.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubi16:
+;CHECK-LABEL: vsubi16:
 ;CHECK: vsub.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubi32:
+;CHECK-LABEL: vsubi32:
 ;CHECK: vsub.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsubi64:
+;CHECK-LABEL: vsubi64:
 ;CHECK: vsub.i64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vsubf32:
+;CHECK-LABEL: vsubf32:
 ;CHECK: vsub.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -46,7 +46,7 @@ define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsubQi8:
+;CHECK-LABEL: vsubQi8:
 ;CHECK: vsub.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -55,7 +55,7 @@ define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsubQi16:
+;CHECK-LABEL: vsubQi16:
 ;CHECK: vsub.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -64,7 +64,7 @@ define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsubQi32:
+;CHECK-LABEL: vsubQi32:
 ;CHECK: vsub.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -73,7 +73,7 @@ define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsubQi64:
+;CHECK-LABEL: vsubQi64:
 ;CHECK: vsub.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -82,7 +82,7 @@ define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vsubQf32:
+;CHECK-LABEL: vsubQf32:
 ;CHECK: vsub.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -91,7 +91,7 @@ define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 }
 
 define <8 x i8> @vsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsubhni16:
+;CHECK-LABEL: vsubhni16:
 ;CHECK: vsubhn.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <8 x i8> @vsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i16> @vsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsubhni32:
+;CHECK-LABEL: vsubhni32:
 ;CHECK: vsubhn.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -109,7 +109,7 @@ define <4 x i16> @vsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsubhni64:
+;CHECK-LABEL: vsubhni64:
 ;CHECK: vsubhn.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -122,7 +122,7 @@ declare <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind rea
 declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrsubhni16:
+;CHECK-LABEL: vrsubhni16:
 ;CHECK: vrsubhn.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -131,7 +131,7 @@ define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrsubhni32:
+;CHECK-LABEL: vrsubhni32:
 ;CHECK: vrsubhn.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -140,7 +140,7 @@ define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vrsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrsubhni64:
+;CHECK-LABEL: vrsubhni64:
 ;CHECK: vrsubhn.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -153,7 +153,7 @@ declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind re
 declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubls8:
+;CHECK-LABEL: vsubls8:
 ;CHECK: vsubl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -164,7 +164,7 @@ define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubls16:
+;CHECK-LABEL: vsubls16:
 ;CHECK: vsubl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -175,7 +175,7 @@ define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubls32:
+;CHECK-LABEL: vsubls32:
 ;CHECK: vsubl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -186,7 +186,7 @@ define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsublu8:
+;CHECK-LABEL: vsublu8:
 ;CHECK: vsubl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -197,7 +197,7 @@ define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsublu16:
+;CHECK-LABEL: vsublu16:
 ;CHECK: vsubl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -208,7 +208,7 @@ define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsublu32:
+;CHECK-LABEL: vsublu32:
 ;CHECK: vsubl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -219,7 +219,7 @@ define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubws8:
+;CHECK-LABEL: vsubws8:
 ;CHECK: vsubw.s8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -229,7 +229,7 @@ define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubws16:
+;CHECK-LABEL: vsubws16:
 ;CHECK: vsubw.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -239,7 +239,7 @@ define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubws32:
+;CHECK-LABEL: vsubws32:
 ;CHECK: vsubw.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -249,7 +249,7 @@ define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubwu8:
+;CHECK-LABEL: vsubwu8:
 ;CHECK: vsubw.u8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -259,7 +259,7 @@ define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubwu16:
+;CHECK-LABEL: vsubwu16:
 ;CHECK: vsubw.u16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -269,7 +269,7 @@ define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubwu32:
+;CHECK-LABEL: vsubwu32:
 ;CHECK: vsubw.u32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
diff --git a/test/CodeGen/ARM/vtbl.ll b/test/CodeGen/ARM/vtbl.ll
index 9264987..21614b0 100644
--- a/test/CodeGen/ARM/vtbl.ll
+++ b/test/CodeGen/ARM/vtbl.ll
@@ -5,7 +5,7 @@
 %struct.__neon_int8x8x4_t = type { <8 x i8>,  <8 x i8>,  <8 x i8>, <8 x i8> }
 
 define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtbl1:
+;CHECK-LABEL: vtbl1:
 ;CHECK: vtbl.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -14,7 +14,7 @@ define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind {
-;CHECK: vtbl2:
+;CHECK-LABEL: vtbl2:
 ;CHECK: vtbl.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load %struct.__neon_int8x8x2_t* %B
@@ -25,7 +25,7 @@ define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind {
 }
 
 define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind {
-;CHECK: vtbl3:
+;CHECK-LABEL: vtbl3:
 ;CHECK: vtbl.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load %struct.__neon_int8x8x3_t* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind {
 }
 
 define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind {
-;CHECK: vtbl4:
+;CHECK-LABEL: vtbl4:
 ;CHECK: vtbl.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load %struct.__neon_int8x8x4_t* %B
@@ -50,7 +50,7 @@ define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind {
 }
 
 define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx1:
+;CHECK-LABEL: vtbx1:
 ;CHECK: vtbx.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -60,7 +60,7 @@ define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx2:
+;CHECK-LABEL: vtbx2:
 ;CHECK: vtbx.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load %struct.__neon_int8x8x2_t* %B
@@ -72,7 +72,7 @@ define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C
 }
 
 define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx3:
+;CHECK-LABEL: vtbx3:
 ;CHECK: vtbx.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load %struct.__neon_int8x8x3_t* %B
@@ -85,7 +85,7 @@ define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C
 }
 
 define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx4:
+;CHECK-LABEL: vtbx4:
 ;CHECK: vtbx.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load %struct.__neon_int8x8x4_t* %B
diff --git a/test/CodeGen/ARM/vtrn.ll b/test/CodeGen/ARM/vtrn.ll
index b1c2f93..7d101bc 100644
--- a/test/CodeGen/ARM/vtrn.ll
+++ b/test/CodeGen/ARM/vtrn.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtrni8:
+;CHECK-LABEL: vtrni8:
 ;CHECK: vtrn.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <8 x i8>* %A
@@ -13,7 +13,7 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vtrni16:
+;CHECK-LABEL: vtrni16:
 ;CHECK: vtrn.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <4 x i16>* %A
@@ -25,7 +25,7 @@ define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vtrni32:
+;CHECK-LABEL: vtrni32:
 ;CHECK: vtrn.32
 ;CHECK-NEXT: vadd.i32
 	%tmp1 = load <2 x i32>* %A
@@ -37,7 +37,7 @@ define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vtrnf:
+;CHECK-LABEL: vtrnf:
 ;CHECK: vtrn.32
 ;CHECK-NEXT: vadd.f32
 	%tmp1 = load <2 x float>* %A
@@ -49,7 +49,7 @@ define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vtrnQi8:
+;CHECK-LABEL: vtrnQi8:
 ;CHECK: vtrn.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <16 x i8>* %A
@@ -61,7 +61,7 @@ define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vtrnQi16:
+;CHECK-LABEL: vtrnQi16:
 ;CHECK: vtrn.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <8 x i16>* %A
@@ -73,7 +73,7 @@ define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vtrnQi32:
+;CHECK-LABEL: vtrnQi32:
 ;CHECK: vtrn.32
 ;CHECK-NEXT: vadd.i32
 	%tmp1 = load <4 x i32>* %A
@@ -85,7 +85,7 @@ define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vtrnQf:
+;CHECK-LABEL: vtrnQf:
 ;CHECK: vtrn.32
 ;CHECK-NEXT: vadd.f32
 	%tmp1 = load <4 x float>* %A
@@ -99,7 +99,7 @@ define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
 ; Undef shuffle indices should not prevent matching to VTRN:
 
 define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtrni8_undef:
+;CHECK-LABEL: vtrni8_undef:
 ;CHECK: vtrn.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <8 x i8>* %A
@@ -111,7 +111,7 @@ define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vtrnQi16_undef:
+;CHECK-LABEL: vtrnQi16_undef:
 ;CHECK: vtrn.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <8 x i16>* %A
diff --git a/test/CodeGen/ARM/vuzp.ll b/test/CodeGen/ARM/vuzp.ll
index 9130f62..2d193c1 100644
--- a/test/CodeGen/ARM/vuzp.ll
+++ b/test/CodeGen/ARM/vuzp.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vuzpi8:
+;CHECK-LABEL: vuzpi8:
 ;CHECK: vuzp.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <8 x i8>* %A
@@ -13,7 +13,7 @@ define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vuzpi16:
+;CHECK-LABEL: vuzpi16:
 ;CHECK: vuzp.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <4 x i16>* %A
@@ -27,7 +27,7 @@ define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
 
 define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vuzpQi8:
+;CHECK-LABEL: vuzpQi8:
 ;CHECK: vuzp.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <16 x i8>* %A
@@ -39,7 +39,7 @@ define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vuzpQi16:
+;CHECK-LABEL: vuzpQi16:
 ;CHECK: vuzp.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <8 x i16>* %A
@@ -51,7 +51,7 @@ define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vuzpQi32:
+;CHECK-LABEL: vuzpQi32:
 ;CHECK: vuzp.32
 ;CHECK-NEXT: vadd.i32
 	%tmp1 = load <4 x i32>* %A
@@ -63,7 +63,7 @@ define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vuzpQf:
+;CHECK-LABEL: vuzpQf:
 ;CHECK: vuzp.32
 ;CHECK-NEXT: vadd.f32
 	%tmp1 = load <4 x float>* %A
@@ -77,7 +77,7 @@ define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
 ; Undef shuffle indices should not prevent matching to VUZP:
 
 define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vuzpi8_undef:
+;CHECK-LABEL: vuzpi8_undef:
 ;CHECK: vuzp.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <8 x i8>* %A
@@ -89,7 +89,7 @@ define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vuzpQi16_undef:
+;CHECK-LABEL: vuzpQi16_undef:
 ;CHECK: vuzp.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <8 x i16>* %A
diff --git a/test/CodeGen/ARM/vzip.ll b/test/CodeGen/ARM/vzip.ll
index 926970a..f71aef7 100644
--- a/test/CodeGen/ARM/vzip.ll
+++ b/test/CodeGen/ARM/vzip.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vzipi8:
+;CHECK-LABEL: vzipi8:
 ;CHECK: vzip.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <8 x i8>* %A
@@ -13,7 +13,7 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vzipi16:
+;CHECK-LABEL: vzipi16:
 ;CHECK: vzip.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <4 x i16>* %A
@@ -27,7 +27,7 @@ define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
 
 define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vzipQi8:
+;CHECK-LABEL: vzipQi8:
 ;CHECK: vzip.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <16 x i8>* %A
@@ -39,7 +39,7 @@ define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vzipQi16:
+;CHECK-LABEL: vzipQi16:
 ;CHECK: vzip.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <8 x i16>* %A
@@ -51,7 +51,7 @@ define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vzipQi32:
+;CHECK-LABEL: vzipQi32:
 ;CHECK: vzip.32
 ;CHECK-NEXT: vadd.i32
 	%tmp1 = load <4 x i32>* %A
@@ -63,7 +63,7 @@ define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vzipQf:
+;CHECK-LABEL: vzipQf:
 ;CHECK: vzip.32
 ;CHECK-NEXT: vadd.f32
 	%tmp1 = load <4 x float>* %A
@@ -77,7 +77,7 @@ define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
 ; Undef shuffle indices should not prevent matching to VZIP:
 
 define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vzipi8_undef:
+;CHECK-LABEL: vzipi8_undef:
 ;CHECK: vzip.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <8 x i8>* %A
@@ -89,7 +89,7 @@ define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vzipQi8_undef:
+;CHECK-LABEL: vzipQi8_undef:
 ;CHECK: vzip.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <16 x i8>* %A
diff --git a/test/CodeGen/MBlaze/brind.ll b/test/CodeGen/MBlaze/brind.ll
index 2229a87..8aa1ae9 100644
--- a/test/CodeGen/MBlaze/brind.ll
+++ b/test/CodeGen/MBlaze/brind.ll
@@ -15,7 +15,7 @@ declare i32 @printf(i8*, ...)
 
 define i32 @brind(i32 %a, i32 %b)
 {
-    ; CHECK:        brind:
+    ; CHECK-LABEL:        brind:
 entry:
     br label %loop
 
diff --git a/test/CodeGen/MBlaze/callind.ll b/test/CodeGen/MBlaze/callind.ll
index bfc8d00..8265a6e 100644
--- a/test/CodeGen/MBlaze/callind.ll
+++ b/test/CodeGen/MBlaze/callind.ll
@@ -15,7 +15,7 @@ declare i32 @printf(i8*, ...)
 
 define i32 @doadd(i32 %a, i32 %b)
 {
-    ; CHECK:        doadd:
+    ; CHECK-LABEL:        doadd:
     %tmp.0 = add i32 %a, %b
     ret i32 %tmp.0
     ; CHECK:        rtsd
@@ -23,7 +23,7 @@ define i32 @doadd(i32 %a, i32 %b)
 
 define i32 @dosub(i32 %a, i32 %b)
 {
-    ; CHECK:        dosub:
+    ; CHECK-LABEL:        dosub:
     %tmp.0 = sub i32 %a, %b
     ret i32 %tmp.0
     ; CHECK:        rtsd
@@ -31,7 +31,7 @@ define i32 @dosub(i32 %a, i32 %b)
 
 define i32 @domul(i32 %a, i32 %b)
 {
-    ; CHECK:        domul:
+    ; CHECK-LABEL:        domul:
     %tmp.0 = mul i32 %a, %b
     ret i32 %tmp.0
     ; CHECK:        rtsd
@@ -39,7 +39,7 @@ define i32 @domul(i32 %a, i32 %b)
 
 define i32 @dodiv(i32 %a, i32 %b)
 {
-    ; CHECK:        dodiv:
+    ; CHECK-LABEL:        dodiv:
     %tmp.0 = sdiv i32 %a, %b
     ret i32 %tmp.0
     ; CHECK:        rtsd
@@ -47,7 +47,7 @@ define i32 @dodiv(i32 %a, i32 %b)
 
 define i32 @dorem(i32 %a, i32 %b)
 {
-    ; CHECK:        dorem:
+    ; CHECK-LABEL:        dorem:
     %tmp.0 = srem i32 %a, %b
     ret i32 %tmp.0
     ; CHECK:        rtsd
@@ -55,7 +55,7 @@ define i32 @dorem(i32 %a, i32 %b)
 
 define i32 @callind(i32 %a, i32 %b)
 {
-    ; CHECK:        callind:
+    ; CHECK-LABEL:        callind:
 entry:
     br label %loop
 
diff --git a/test/CodeGen/MBlaze/cc.ll b/test/CodeGen/MBlaze/cc.ll
index 827fd32..e12f3b4 100644
--- a/test/CodeGen/MBlaze/cc.ll
+++ b/test/CodeGen/MBlaze/cc.ll
@@ -10,7 +10,7 @@ declare i32 @printf(i8*, ...)
 @MSG = internal constant [13 x i8] c"Message: %d\0A\00"
 
 define void @params0_noret() {
-    ; CHECK:        params0_noret:
+    ; CHECK-LABEL:        params0_noret:
     ret void
     ; CHECK-NOT:    {{.* r3, .*, .*}}
     ; CHECK-NOT:    {{.* r4, .*, .*}}
@@ -18,7 +18,7 @@ define void @params0_noret() {
 }
 
 define i8 @params0_8bitret() {
-    ; CHECK:        params0_8bitret:
+    ; CHECK-LABEL:        params0_8bitret:
     ret i8 1
     ; CHECK-NOT:    {{.* r3, .*, .*}}
     ; CHECK-NOT:    {{.* r4, .*, .*}}
@@ -27,7 +27,7 @@ define i8 @params0_8bitret() {
 }
 
 define i16 @params0_16bitret() {
-    ; CHECK:        params0_16bitret:
+    ; CHECK-LABEL:        params0_16bitret:
     ret i16 1
     ; CHECK:        rtsd
     ; CHECK:        {{.* r3, r0, 1}}
@@ -35,7 +35,7 @@ define i16 @params0_16bitret() {
 }
 
 define i32 @params0_32bitret() {
-    ; CHECK:        params0_32bitret:
+    ; CHECK-LABEL:        params0_32bitret:
     ret i32 1
     ; CHECK-NOT:    {{.* r4, .*, .*}}
     ; CHECK:        rtsd
@@ -43,7 +43,7 @@ define i32 @params0_32bitret() {
 }
 
 define i64 @params0_64bitret() {
-    ; CHECK:        params0_64bitret:
+    ; CHECK-LABEL:        params0_64bitret:
     ret i64 1
     ; CHECK:        {{.* r3, r0, .*}}
     ; CHECK:        rtsd
@@ -51,7 +51,7 @@ define i64 @params0_64bitret() {
 }
 
 define i32 @params1_32bitret(i32 %a) {
-    ; CHECK:        params1_32bitret:
+    ; CHECK-LABEL:        params1_32bitret:
     ret i32 %a
     ; CHECK-NOT:    {{.* r3, .*, .*}}
     ; CHECK-NOT:    {{.* r4, .*, .*}}
@@ -60,7 +60,7 @@ define i32 @params1_32bitret(i32 %a) {
 }
 
 define i32 @params2_32bitret(i32 %a, i32 %b) {
-    ; CHECK:        params2_32bitret:
+    ; CHECK-LABEL:        params2_32bitret:
     ret i32 %b
     ; CHECK-NOT:    {{.* r3, .*, .*}}
     ; CHECK-NOT:    {{.* r4, .*, .*}}
@@ -69,7 +69,7 @@ define i32 @params2_32bitret(i32 %a, i32 %b) {
 }
 
 define i32 @params3_32bitret(i32 %a, i32 %b, i32 %c) {
-    ; CHECK:        params3_32bitret:
+    ; CHECK-LABEL:        params3_32bitret:
     ret i32 %c
     ; CHECK-NOT:    {{.* r3, .*, .*}}
     ; CHECK-NOT:    {{.* r4, .*, .*}}
@@ -78,7 +78,7 @@ define i32 @params3_32bitret(i32 %a, i32 %b, i32 %c) {
 }
 
 define i32 @params4_32bitret(i32 %a, i32 %b, i32 %c, i32 %d) {
-    ; CHECK:        params4_32bitret:
+    ; CHECK-LABEL:        params4_32bitret:
     ret i32 %d
     ; CHECK-NOT:    {{.* r3, .*, .*}}
     ; CHECK-NOT:    {{.* r4, .*, .*}}
@@ -87,7 +87,7 @@ define i32 @params4_32bitret(i32 %a, i32 %b, i32 %c, i32 %d) {
 }
 
 define i32 @params5_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
-    ; CHECK:        params5_32bitret:
+    ; CHECK-LABEL:        params5_32bitret:
     ret i32 %e
     ; CHECK-NOT:    {{.* r3, .*, .*}}
     ; CHECK-NOT:    {{.* r4, .*, .*}}
@@ -96,7 +96,7 @@ define i32 @params5_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
 }
 
 define i32 @params6_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) {
-    ; CHECK:        params6_32bitret:
+    ; CHECK-LABEL:        params6_32bitret:
     ret i32 %f
     ; CHECK-NOT:    {{.* r3, .*, .*}}
     ; CHECK-NOT:    {{.* r4, .*, .*}}
@@ -106,7 +106,7 @@ define i32 @params6_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) {
 
 define i32 @params7_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
                              i32 %g) {
-    ; CHECK:        params7_32bitret:
+    ; CHECK-LABEL:        params7_32bitret:
     ret i32 %g
     ; CHECK:        {{lwi? r3, r1, 32}}
     ; CHECK-NOT:    {{.* r4, .*, .*}}
@@ -115,7 +115,7 @@ define i32 @params7_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
 
 define i32 @params8_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
                              i32 %g, i32 %h) {
-    ; CHECK:        params8_32bitret:
+    ; CHECK-LABEL:        params8_32bitret:
     ret i32 %h
     ; CHECK:        {{lwi? r3, r1, 36}}
     ; CHECK-NOT:    {{.* r4, .*, .*}}
@@ -124,7 +124,7 @@ define i32 @params8_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
 
 define i32 @params9_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
                              i32 %g, i32 %h, i32 %i) {
-    ; CHECK:        params9_32bitret:
+    ; CHECK-LABEL:        params9_32bitret:
     ret i32 %i
     ; CHECK:        {{lwi? r3, r1, 40}}
     ; CHECK-NOT:    {{.* r4, .*, .*}}
@@ -133,7 +133,7 @@ define i32 @params9_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
 
 define i32 @params10_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
                               i32 %g, i32 %h, i32 %i, i32 %j) {
-    ; CHECK:        params10_32bitret:
+    ; CHECK-LABEL:        params10_32bitret:
     ret i32 %j
     ; CHECK:        {{lwi? r3, r1, 44}}
     ; CHECK-NOT:    {{.* r4, .*, .*}}
diff --git a/test/CodeGen/MBlaze/div.ll b/test/CodeGen/MBlaze/div.ll
index 621784a..60753aa 100644
--- a/test/CodeGen/MBlaze/div.ll
+++ b/test/CodeGen/MBlaze/div.ll
@@ -6,8 +6,8 @@
 ; RUN: llc < %s -march=mblaze -mattr=+div | FileCheck -check-prefix=DIV %s
 
 define i8 @test_i8(i8 %a, i8 %b) {
-    ; FUN:        test_i8:
-    ; DIV:        test_i8:
+    ; FUN-LABEL:        test_i8:
+    ; DIV-LABEL:        test_i8:
 
     %tmp.1 = udiv i8 %a, %b
     ; FUN-NOT:    idiv
@@ -29,8 +29,8 @@ define i8 @test_i8(i8 %a, i8 %b) {
 }
 
 define i16 @test_i16(i16 %a, i16 %b) {
-    ; FUN:        test_i16:
-    ; DIV:        test_i16:
+    ; FUN-LABEL:        test_i16:
+    ; DIV-LABEL:        test_i16:
 
     %tmp.1 = udiv i16 %a, %b
     ; FUN-NOT:    idiv
@@ -52,8 +52,8 @@ define i16 @test_i16(i16 %a, i16 %b) {
 }
 
 define i32 @test_i32(i32 %a, i32 %b) {
-    ; FUN:        test_i32:
-    ; DIV:        test_i32:
+    ; FUN-LABEL:        test_i32:
+    ; DIV-LABEL:        test_i32:
 
     %tmp.1 = udiv i32 %a, %b
     ; FUN-NOT:    idiv
diff --git a/test/CodeGen/MBlaze/fpu.ll b/test/CodeGen/MBlaze/fpu.ll
index 2aef4fd..5078d7d 100644
--- a/test/CodeGen/MBlaze/fpu.ll
+++ b/test/CodeGen/MBlaze/fpu.ll
@@ -6,8 +6,8 @@
 ; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
 
 define float @test_add(float %a, float %b) {
-    ; FUN:        test_add:
-    ; FPU:        test_add:
+    ; FUN-LABEL:        test_add:
+    ; FPU-LABEL:        test_add:
 
     %tmp.1 = fadd float %a, %b
     ; FUN:        brlid
@@ -21,8 +21,8 @@ define float @test_add(float %a, float %b) {
 }
 
 define float @test_sub(float %a, float %b) {
-    ; FUN:        test_sub:
-    ; FPU:        test_sub:
+    ; FUN-LABEL:        test_sub:
+    ; FPU-LABEL:        test_sub:
 
     %tmp.1 = fsub float %a, %b
     ; FUN:        brlid
@@ -36,8 +36,8 @@ define float @test_sub(float %a, float %b) {
 }
 
 define float @test_mul(float %a, float %b) {
-    ; FUN:        test_mul:
-    ; FPU:        test_mul:
+    ; FUN-LABEL:        test_mul:
+    ; FPU-LABEL:        test_mul:
 
     %tmp.1 = fmul float %a, %b
     ; FUN:        brlid
@@ -51,8 +51,8 @@ define float @test_mul(float %a, float %b) {
 }
 
 define float @test_div(float %a, float %b) {
-    ; FUN:        test_div:
-    ; FPU:        test_div:
+    ; FUN-LABEL:        test_div:
+    ; FPU-LABEL:        test_div:
 
     %tmp.1 = fdiv float %a, %b
     ; FUN:        brlid
diff --git a/test/CodeGen/MBlaze/fsl.ll b/test/CodeGen/MBlaze/fsl.ll
index 5444f82..936e6cf 100644
--- a/test/CodeGen/MBlaze/fsl.ll
+++ b/test/CodeGen/MBlaze/fsl.ll
@@ -56,7 +56,7 @@ declare void @llvm.mblaze.fsl.tncput(i32 %port)
 declare void @llvm.mblaze.fsl.tncaput(i32 %port)
 
 define void @fsl_get(i32 %port) {
-    ; CHECK:        fsl_get:
+    ; CHECK-LABEL:        fsl_get:
     %v0  = call i32 @llvm.mblaze.fsl.get(i32 %port)
     ; CHECK:        getd
     %v1  = call i32 @llvm.mblaze.fsl.aget(i32 %port)
@@ -126,7 +126,7 @@ define void @fsl_get(i32 %port) {
 }
 
 define void @fslc_get() {
-    ; CHECK:        fslc_get:
+    ; CHECK-LABEL:        fslc_get:
     %v0  = call i32 @llvm.mblaze.fsl.get(i32 1)
     ; CHECK:        get
     %v1  = call i32 @llvm.mblaze.fsl.aget(i32 1)
@@ -227,7 +227,7 @@ define void @fslc_get() {
 }
 
 define void @putfsl(i32 %value, i32 %port) {
-    ; CHECK:        putfsl:
+    ; CHECK-LABEL:        putfsl:
     call void @llvm.mblaze.fsl.put(i32 %value, i32 %port)
     ; CHECK:        putd
     call void @llvm.mblaze.fsl.aput(i32 %value, i32 %port)
@@ -265,7 +265,7 @@ define void @putfsl(i32 %value, i32 %port) {
 }
 
 define void @putfsl_const(i32 %value) {
-    ; CHECK:        putfsl_const:
+    ; CHECK-LABEL:        putfsl_const:
     call void @llvm.mblaze.fsl.put(i32 %value, i32 1)
     ; CHECK-NOT:    putd
     ; CHECK:        put
diff --git a/test/CodeGen/MBlaze/imm.ll b/test/CodeGen/MBlaze/imm.ll
index 6effd3e..406b659 100644
--- a/test/CodeGen/MBlaze/imm.ll
+++ b/test/CodeGen/MBlaze/imm.ll
@@ -6,41 +6,41 @@
 ; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
 
 define i8 @retimm_i8() {
-    ; CHECK:        retimm_i8:
+    ; CHECK-LABEL:        retimm_i8:
     ; CHECK:        rtsd
     ; CHECK-NEXT:   add
-    ; FPU:          retimm_i8:
+    ; FPU-LABEL:          retimm_i8:
     ; FPU:          rtsd
     ; FPU-NEXT:     add
     ret i8 123
 }
 
 define i16 @retimm_i16() {
-    ; CHECK:        retimm_i16:
+    ; CHECK-LABEL:        retimm_i16:
     ; CHECK:        rtsd
     ; CHECK-NEXT:   add
-    ; FPU:          retimm_i16:
+    ; FPU-LABEL:          retimm_i16:
     ; FPU:          rtsd
     ; FPU-NEXT:     add
     ret i16 31212
 }
 
 define i32 @retimm_i32() {
-    ; CHECK:        retimm_i32:
+    ; CHECK-LABEL:        retimm_i32:
     ; CHECK:        add
     ; CHECK-NEXT:   rtsd
-    ; FPU:          retimm_i32:
+    ; FPU-LABEL:          retimm_i32:
     ; FPU:          add
     ; FPU-NEXT:     rtsd
     ret i32 2938128
 }
 
 define i64 @retimm_i64() {
-    ; CHECK:        retimm_i64:
+    ; CHECK-LABEL:        retimm_i64:
     ; CHECK:        add
     ; CHECK-NEXT:   rtsd
     ; CHECK-NEXT:   add
-    ; FPU:          retimm_i64:
+    ; FPU-LABEL:          retimm_i64:
     ; FPU:          add
     ; FPU-NEXT:     rtsd
     ; FPU-NEXT:     add
@@ -48,21 +48,21 @@ define i64 @retimm_i64() {
 }
 
 define float @retimm_float() {
-    ; CHECK:        retimm_float:
+    ; CHECK-LABEL:        retimm_float:
     ; CHECK:        add
     ; CHECK-NEXT:   rtsd
-    ; FPU:          retimm_float:
+    ; FPU-LABEL:          retimm_float:
     ; FPU:          or
     ; FPU-NEXT:     rtsd
     ret float 12.0
 }
 
 define double @retimm_double() {
-    ; CHECK:        retimm_double:
+    ; CHECK-LABEL:        retimm_double:
     ; CHECK:        add
     ; CHECK-NEXT:   add
     ; CHECK-NEXT:   rtsd
-    ; FPU:          retimm_double:
+    ; FPU-LABEL:          retimm_double:
     ; FPU:          add
     ; FPU-NEXT:     add
     ; FPU-NEXT:     rtsd
diff --git a/test/CodeGen/MBlaze/intr.ll b/test/CodeGen/MBlaze/intr.ll
index 79c6bff..fb2c66e 100644
--- a/test/CodeGen/MBlaze/intr.ll
+++ b/test/CodeGen/MBlaze/intr.ll
@@ -7,7 +7,7 @@
 @_interrupt_handler = alias void ()* @myintr
 
 define cc73 void @myintr() nounwind noinline {
-  ; CHECK:        myintr:
+  ; CHECK-LABEL:        myintr:
   ; CHECK:        swi   r3, r1
   ; CHECK:        swi   r4, r1
   ; CHECK:        swi   r5, r1
diff --git a/test/CodeGen/MBlaze/jumptable.ll b/test/CodeGen/MBlaze/jumptable.ll
index 299084d..81b85c9 100644
--- a/test/CodeGen/MBlaze/jumptable.ll
+++ b/test/CodeGen/MBlaze/jumptable.ll
@@ -6,7 +6,7 @@
 
 define i32 @jmptable(i32 %arg)
 {
-    ; CHECK:        jmptable:
+    ; CHECK-LABEL:        jmptable:
     switch i32 %arg, label %DEFAULT [ i32 0, label %L0
                                       i32 1, label %L1
                                       i32 2, label %L2
diff --git a/test/CodeGen/MBlaze/loop.ll b/test/CodeGen/MBlaze/loop.ll
index 7439d0b..966a0fc 100644
--- a/test/CodeGen/MBlaze/loop.ll
+++ b/test/CodeGen/MBlaze/loop.ll
@@ -9,7 +9,7 @@ declare i32 @printf(i8*, ...)
 
 define i32 @loop(i32 %a, i32 %b)
 {
-    ; CHECK:        loop:
+    ; CHECK-LABEL:        loop:
 entry:
     br label %loop_outer
 
diff --git a/test/CodeGen/MBlaze/mul.ll b/test/CodeGen/MBlaze/mul.ll
index cefdb8d..c09d430 100644
--- a/test/CodeGen/MBlaze/mul.ll
+++ b/test/CodeGen/MBlaze/mul.ll
@@ -6,8 +6,8 @@
 ; RUN: llc < %s -march=mblaze -mattr=+mul | FileCheck -check-prefix=MUL %s
 
 define i8 @test_i8(i8 %a, i8 %b) {
-    ; FUN:        test_i8:
-    ; MUL:        test_i8:
+    ; FUN-LABEL:        test_i8:
+    ; MUL-LABEL:        test_i8:
 
     %tmp.1 = mul i8 %a, %b
     ; FUN-NOT:    mul
@@ -21,8 +21,8 @@ define i8 @test_i8(i8 %a, i8 %b) {
 }
 
 define i16 @test_i16(i16 %a, i16 %b) {
-    ; FUN:        test_i16:
-    ; MUL:        test_i16:
+    ; FUN-LABEL:        test_i16:
+    ; MUL-LABEL:        test_i16:
 
     %tmp.1 = mul i16 %a, %b
     ; FUN-NOT:    mul
@@ -36,8 +36,8 @@ define i16 @test_i16(i16 %a, i16 %b) {
 }
 
 define i32 @test_i32(i32 %a, i32 %b) {
-    ; FUN:        test_i32:
-    ; MUL:        test_i32:
+    ; FUN-LABEL:        test_i32:
+    ; MUL-LABEL:        test_i32:
 
     %tmp.1 = mul i32 %a, %b
     ; FUN-NOT:    mul
diff --git a/test/CodeGen/MBlaze/mul64.ll b/test/CodeGen/MBlaze/mul64.ll
index e0ef413..60ccf04 100644
--- a/test/CodeGen/MBlaze/mul64.ll
+++ b/test/CodeGen/MBlaze/mul64.ll
@@ -7,8 +7,8 @@
 ; RUN:      FileCheck -check-prefix=MUL %s
 
 define i64 @test_i64(i64 %a, i64 %b) {
-    ; FUN:        test_i64:
-    ; MUL:        test_i64:
+    ; FUN-LABEL:        test_i64:
+    ; MUL-LABEL:        test_i64:
 
     %tmp.1 = mul i64 %a, %b
     ; FUN-NOT:    mul
diff --git a/test/CodeGen/MBlaze/select.ll b/test/CodeGen/MBlaze/select.ll
index 47a88a1..c4bdbc4 100644
--- a/test/CodeGen/MBlaze/select.ll
+++ b/test/CodeGen/MBlaze/select.ll
@@ -5,7 +5,7 @@
 
 define i32 @testsel(i32 %a, i32 %b)
 {
-    ; CHECK:        testsel:
+    ; CHECK-LABEL:        testsel:
     %tmp.1 = icmp eq i32 %a, %b
     ; CHECK:        cmp
     %tmp.2 = select i1 %tmp.1, i32 %a, i32 %b
diff --git a/test/CodeGen/MBlaze/shift.ll b/test/CodeGen/MBlaze/shift.ll
index 99f0519..c1c890d 100644
--- a/test/CodeGen/MBlaze/shift.ll
+++ b/test/CodeGen/MBlaze/shift.ll
@@ -6,8 +6,8 @@
 ; RUN: llc < %s -march=mblaze -mattr=+barrel | FileCheck -check-prefix=SHT %s
 
 define i8 @test_i8(i8 %a, i8 %b) {
-    ; FUN:        test_i8:
-    ; SHT:        test_i8:
+    ; FUN-LABEL:        test_i8:
+    ; SHT-LABEL:        test_i8:
 
     %tmp.1 = shl i8 %a, %b
     ; FUN:        andi
@@ -23,8 +23,8 @@ define i8 @test_i8(i8 %a, i8 %b) {
 }
 
 define i8 @testc_i8(i8 %a, i8 %b) {
-    ; FUN:        testc_i8:
-    ; SHT:        testc_i8:
+    ; FUN-LABEL:        testc_i8:
+    ; SHT-LABEL:        testc_i8:
 
     %tmp.1 = shl i8 %a, 5
     ; FUN:        andi
@@ -42,8 +42,8 @@ define i8 @testc_i8(i8 %a, i8 %b) {
 }
 
 define i16 @test_i16(i16 %a, i16 %b) {
-    ; FUN:        test_i16:
-    ; SHT:        test_i16:
+    ; FUN-LABEL:        test_i16:
+    ; SHT-LABEL:        test_i16:
 
     %tmp.1 = shl i16 %a, %b
     ; FUN:        andi
@@ -59,8 +59,8 @@ define i16 @test_i16(i16 %a, i16 %b) {
 }
 
 define i16 @testc_i16(i16 %a, i16 %b) {
-    ; FUN:        testc_i16:
-    ; SHT:        testc_i16:
+    ; FUN-LABEL:        testc_i16:
+    ; SHT-LABEL:        testc_i16:
 
     %tmp.1 = shl i16 %a, 5
     ; FUN:        andi
@@ -78,8 +78,8 @@ define i16 @testc_i16(i16 %a, i16 %b) {
 }
 
 define i32 @test_i32(i32 %a, i32 %b) {
-    ; FUN:        test_i32:
-    ; SHT:        test_i32:
+    ; FUN-LABEL:        test_i32:
+    ; SHT-LABEL:        test_i32:
 
     %tmp.1 = shl i32 %a, %b
     ; FUN:        andi
@@ -96,8 +96,8 @@ define i32 @test_i32(i32 %a, i32 %b) {
 }
 
 define i32 @testc_i32(i32 %a, i32 %b) {
-    ; FUN:        testc_i32:
-    ; SHT:        testc_i32:
+    ; FUN-LABEL:        testc_i32:
+    ; SHT-LABEL:        testc_i32:
 
     %tmp.1 = shl i32 %a, 5
     ; FUN:        andi
diff --git a/test/CodeGen/MBlaze/svol.ll b/test/CodeGen/MBlaze/svol.ll
index c1e9620..f5d5464 100644
--- a/test/CodeGen/MBlaze/svol.ll
+++ b/test/CodeGen/MBlaze/svol.ll
@@ -6,7 +6,7 @@
 @.str = private constant [28 x i8] c"The interrupt has gone off\0A\00"
 
 define cc74 void @mysvol() nounwind noinline {
-  ; CHECK:        mysvol:
+  ; CHECK-LABEL:        mysvol:
   ; CHECK:        swi   r3, r1
   ; CHECK:        swi   r4, r1
   ; CHECK:        swi   r5, r1
@@ -41,7 +41,7 @@ define cc74 void @mysvol() nounwind noinline {
 }
 
 define cc74 void @mysvol2() nounwind noinline {
-  ; CHECK:        mysvol2:
+  ; CHECK-LABEL:        mysvol2:
   ; CHECK-NOT:    swi   r3, r1
   ; CHECK-NOT:    swi   r4, r1
   ; CHECK-NOT:    swi   r5, r1
diff --git a/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll b/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll
index 94fe5c7..dce9d25 100644
--- a/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll
+++ b/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll
@@ -7,7 +7,7 @@ target triple = "msp430-elf"
 
 define signext i8 @foo(i8 signext %_si1, i8 signext %_si2) nounwind readnone {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: call #__mulqi3
   %mul = mul i8 %_si2, %_si1                      ; <i8> [#uses=1]
   ret i8 %mul
diff --git a/test/CodeGen/MSP430/AddrMode-bis-rx.ll b/test/CodeGen/MSP430/AddrMode-bis-rx.ll
index c7ecb5a..44c92eb 100644
--- a/test/CodeGen/MSP430/AddrMode-bis-rx.ll
+++ b/test/CodeGen/MSP430/AddrMode-bis-rx.ll
@@ -7,7 +7,7 @@ define i16 @am1(i16 %x, i16* %a) nounwind {
 	%2 = or i16 %1,%x
 	ret i16 %2
 }
-; CHECK: am1:
+; CHECK-LABEL: am1:
 ; CHECK:		bis.w	0(r14), r15
 
 @foo = external global i16
@@ -17,7 +17,7 @@ define i16 @am2(i16 %x) nounwind {
 	%2 = or i16 %1,%x
 	ret i16 %2
 }
-; CHECK: am2:
+; CHECK-LABEL: am2:
 ; CHECK:		bis.w	&foo, r15
 
 @bar = internal constant [2 x i8] [ i8 32, i8 64 ]
@@ -28,7 +28,7 @@ define i8 @am3(i8 %x, i16 %n) nounwind {
 	%3 = or i8 %2,%x
 	ret i8 %3
 }
-; CHECK: am3:
+; CHECK-LABEL: am3:
 ; CHECK:		bis.b	bar(r14), r15
 
 define i16 @am4(i16 %x) nounwind {
@@ -36,7 +36,7 @@ define i16 @am4(i16 %x) nounwind {
 	%2 = or i16 %1,%x
 	ret i16 %2
 }
-; CHECK: am4:
+; CHECK-LABEL: am4:
 ; CHECK:		bis.w	&32, r15
 
 define i16 @am5(i16 %x, i16* %a) nounwind {
@@ -45,7 +45,7 @@ define i16 @am5(i16 %x, i16* %a) nounwind {
 	%3 = or i16 %2,%x
 	ret i16 %3
 }
-; CHECK: am5:
+; CHECK-LABEL: am5:
 ; CHECK:		bis.w	4(r14), r15
 
 %S = type { i16, i16 }
@@ -56,7 +56,7 @@ define i16 @am6(i16 %x) nounwind {
 	%2 = or i16 %1,%x
 	ret i16 %2
 }
-; CHECK: am6:
+; CHECK-LABEL: am6:
 ; CHECK:		bis.w	&baz+2, r15
 
 %T = type { i16, [2 x i8] }
@@ -69,6 +69,6 @@ define i8 @am7(i8 %x, i16 %n) nounwind {
 	%4 = or i8 %3,%x
 	ret i8 %4
 }
-; CHECK: am7:
+; CHECK-LABEL: am7:
 ; CHECK:		bis.b	duh+2(r14), r15
 
diff --git a/test/CodeGen/MSP430/AddrMode-bis-xr.ll b/test/CodeGen/MSP430/AddrMode-bis-xr.ll
index 727c29f..06a3d32 100644
--- a/test/CodeGen/MSP430/AddrMode-bis-xr.ll
+++ b/test/CodeGen/MSP430/AddrMode-bis-xr.ll
@@ -8,7 +8,7 @@ define void @am1(i16* %a, i16 %x) nounwind {
 	store i16 %2, i16* %a
 	ret void
 }
-; CHECK: am1:
+; CHECK-LABEL: am1:
 ; CHECK:		bis.w	r14, 0(r15)
 
 @foo = external global i16
@@ -19,7 +19,7 @@ define void @am2(i16 %x) nounwind {
 	store i16 %2, i16* @foo
 	ret void
 }
-; CHECK: am2:
+; CHECK-LABEL: am2:
 ; CHECK:		bis.w	r15, &foo
 
 @bar = external global [2 x i8]
@@ -31,7 +31,7 @@ define void @am3(i16 %i, i8 %x) nounwind {
 	store i8 %3, i8* %1
 	ret void
 }
-; CHECK: am3:
+; CHECK-LABEL: am3:
 ; CHECK:		bis.b	r14, bar(r15)
 
 define void @am4(i16 %x) nounwind {
@@ -40,7 +40,7 @@ define void @am4(i16 %x) nounwind {
 	store volatile i16 %2, i16* inttoptr(i16 32 to i16*)
 	ret void
 }
-; CHECK: am4:
+; CHECK-LABEL: am4:
 ; CHECK:		bis.w	r15, &32
 
 define void @am5(i16* %a, i16 %x) readonly {
@@ -50,7 +50,7 @@ define void @am5(i16* %a, i16 %x) readonly {
 	store i16 %3, i16* %1
 	ret void
 }
-; CHECK: am5:
+; CHECK-LABEL: am5:
 ; CHECK:		bis.w	r14, 4(r15)
 
 %S = type { i16, i16 }
@@ -62,7 +62,7 @@ define void @am6(i16 %x) nounwind {
 	store i16 %2, i16* getelementptr (%S* @baz, i32 0, i32 1)
 	ret void
 }
-; CHECK: am6:
+; CHECK-LABEL: am6:
 ; CHECK:		bis.w	r15, &baz+2
 
 %T = type { i16, [2 x i8] }
@@ -76,6 +76,6 @@ define void @am7(i16 %n, i8 %x) nounwind {
 	store i8 %4, i8* %2
 	ret void
 }
-; CHECK: am7:
+; CHECK-LABEL: am7:
 ; CHECK:		bis.b	r14, duh+2(r15)
 
diff --git a/test/CodeGen/MSP430/AddrMode-mov-rx.ll b/test/CodeGen/MSP430/AddrMode-mov-rx.ll
index 7cd345b..378b7ae 100644
--- a/test/CodeGen/MSP430/AddrMode-mov-rx.ll
+++ b/test/CodeGen/MSP430/AddrMode-mov-rx.ll
@@ -6,7 +6,7 @@ define i16 @am1(i16* %a) nounwind {
 	%1 = load i16* %a
 	ret i16 %1
 }
-; CHECK: am1:
+; CHECK-LABEL: am1:
 ; CHECK:		mov.w	0(r15), r15
 
 @foo = external global i16
@@ -15,7 +15,7 @@ define i16 @am2() nounwind {
 	%1 = load i16* @foo
 	ret i16 %1
 }
-; CHECK: am2:
+; CHECK-LABEL: am2:
 ; CHECK:		mov.w	&foo, r15
 
 @bar = internal constant [2 x i8] [ i8 32, i8 64 ]
@@ -25,14 +25,14 @@ define i8 @am3(i16 %n) nounwind {
 	%2 = load i8* %1
 	ret i8 %2
 }
-; CHECK: am3:
+; CHECK-LABEL: am3:
 ; CHECK:		mov.b	bar(r15), r15
 
 define i16 @am4() nounwind {
 	%1 = load volatile i16* inttoptr(i16 32 to i16*)
 	ret i16 %1
 }
-; CHECK: am4:
+; CHECK-LABEL: am4:
 ; CHECK:		mov.w	&32, r15
 
 define i16 @am5(i16* %a) nounwind {
@@ -40,7 +40,7 @@ define i16 @am5(i16* %a) nounwind {
 	%2 = load i16* %1
 	ret i16 %2
 }
-; CHECK: am5:
+; CHECK-LABEL: am5:
 ; CHECK:		mov.w	4(r15), r15
 
 %S = type { i16, i16 }
@@ -50,7 +50,7 @@ define i16 @am6() nounwind {
 	%1 = load i16* getelementptr (%S* @baz, i32 0, i32 1)
 	ret i16 %1
 }
-; CHECK: am6:
+; CHECK-LABEL: am6:
 ; CHECK:		mov.w	&baz+2, r15
 
 %T = type { i16, [2 x i8] }
@@ -62,6 +62,6 @@ define i8 @am7(i16 %n) nounwind {
 	%3= load i8* %2
 	ret i8 %3
 }
-; CHECK: am7:
+; CHECK-LABEL: am7:
 ; CHECK:		mov.b	duh+2(r15), r15
 
diff --git a/test/CodeGen/MSP430/AddrMode-mov-xr.ll b/test/CodeGen/MSP430/AddrMode-mov-xr.ll
index 5eeb02f..f55fd54 100644
--- a/test/CodeGen/MSP430/AddrMode-mov-xr.ll
+++ b/test/CodeGen/MSP430/AddrMode-mov-xr.ll
@@ -6,7 +6,7 @@ define void @am1(i16* %a, i16 %b) nounwind {
 	store i16 %b, i16* %a
 	ret void
 }
-; CHECK: am1:
+; CHECK-LABEL: am1:
 ; CHECK:		mov.w	r14, 0(r15)
 
 @foo = external global i16
@@ -15,7 +15,7 @@ define void @am2(i16 %a) nounwind {
 	store i16 %a, i16* @foo
 	ret void
 }
-; CHECK: am2:
+; CHECK-LABEL: am2:
 ; CHECK:		mov.w	r15, &foo
 
 @bar = external global [2 x i8]
@@ -25,14 +25,14 @@ define void @am3(i16 %i, i8 %a) nounwind {
 	store i8 %a, i8* %1
 	ret void
 }
-; CHECK: am3:
+; CHECK-LABEL: am3:
 ; CHECK:		mov.b	r14, bar(r15)
 
 define void @am4(i16 %a) nounwind {
 	store volatile i16 %a, i16* inttoptr(i16 32 to i16*)
 	ret void
 }
-; CHECK: am4:
+; CHECK-LABEL: am4:
 ; CHECK:		mov.w	r15, &32
 
 define void @am5(i16* nocapture %p, i16 %a) nounwind readonly {
@@ -40,7 +40,7 @@ define void @am5(i16* nocapture %p, i16 %a) nounwind readonly {
 	store i16 %a, i16* %1
 	ret void
 }
-; CHECK: am5:
+; CHECK-LABEL: am5:
 ; CHECK:		mov.w	r14, 4(r15)
 
 %S = type { i16, i16 }
@@ -50,7 +50,7 @@ define void @am6(i16 %a) nounwind {
 	store i16 %a, i16* getelementptr (%S* @baz, i32 0, i32 1)
 	ret void
 }
-; CHECK: am6:
+; CHECK-LABEL: am6:
 ; CHECK:		mov.w	r15, &baz+2
 
 %T = type { i16, [2 x i8] }
@@ -62,6 +62,6 @@ define void @am7(i16 %n, i8 %a) nounwind {
 	store i8 %a, i8* %2
 	ret void
 }
-; CHECK: am7:
+; CHECK-LABEL: am7:
 ; CHECK:		mov.b	r14, duh+2(r15)
 
diff --git a/test/CodeGen/MSP430/Inst16mi.ll b/test/CodeGen/MSP430/Inst16mi.ll
index 33d7aa4..e9ab75c 100644
--- a/test/CodeGen/MSP430/Inst16mi.ll
+++ b/test/CodeGen/MSP430/Inst16mi.ll
@@ -5,14 +5,14 @@ target triple = "msp430-generic-generic"
 @foo = common global i16 0, align 2
 
 define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.w	#2, &foo
 	store i16 2, i16 * @foo
 	ret void
 }
 
 define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w	#2, &foo
 	%1 = load i16* @foo
 	%2 = add i16 %1, 2
@@ -21,7 +21,7 @@ define void @add() nounwind {
 }
 
 define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w	#2, &foo
 	%1 = load i16* @foo
 	%2 = and i16 %1, 2
@@ -30,7 +30,7 @@ define void @and() nounwind {
 }
 
 define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w	#2, &foo
 	%1 = load i16* @foo
 	%2 = or i16 %1, 2
@@ -39,7 +39,7 @@ define void @bis() nounwind {
 }
 
 define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w	#2, &foo
 	%1 = load i16* @foo
 	%2 = xor i16 %1, 2
diff --git a/test/CodeGen/MSP430/Inst16mm.ll b/test/CodeGen/MSP430/Inst16mm.ll
index d4ae811..5c93e37 100644
--- a/test/CodeGen/MSP430/Inst16mm.ll
+++ b/test/CodeGen/MSP430/Inst16mm.ll
@@ -5,7 +5,7 @@ target triple = "msp430-generic-generic"
 @bar = common global i16 0, align 2
 
 define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.w	&bar, &foo
         %1 = load i16* @bar
         store i16 %1, i16* @foo
@@ -13,7 +13,7 @@ define void @mov() nounwind {
 }
 
 define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w	&bar, &foo
 	%1 = load i16* @bar
 	%2 = load i16* @foo
@@ -23,7 +23,7 @@ define void @add() nounwind {
 }
 
 define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w	&bar, &foo
 	%1 = load i16* @bar
 	%2 = load i16* @foo
@@ -33,7 +33,7 @@ define void @and() nounwind {
 }
 
 define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w	&bar, &foo
 	%1 = load i16* @bar
 	%2 = load i16* @foo
@@ -43,7 +43,7 @@ define void @bis() nounwind {
 }
 
 define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w	&bar, &foo
 	%1 = load i16* @bar
 	%2 = load i16* @foo
@@ -63,7 +63,7 @@ entry:
  store i16 0, i16* %retval
  %0 = load i16* %retval                          ; <i16> [#uses=1]
  ret i16 %0
-; CHECK: mov2:
+; CHECK-LABEL: mov2:
 ; CHECK:	mov.w	2(r1), 6(r1)
 ; CHECK:	mov.w	0(r1), 4(r1)
 }
diff --git a/test/CodeGen/MSP430/Inst16mr.ll b/test/CodeGen/MSP430/Inst16mr.ll
index 2613f01..2010048 100644
--- a/test/CodeGen/MSP430/Inst16mr.ll
+++ b/test/CodeGen/MSP430/Inst16mr.ll
@@ -4,14 +4,14 @@ target triple = "msp430-generic-generic"
 @foo = common global i16 0, align 2
 
 define void @mov(i16 %a) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.w	r15, &foo
 	store i16 %a, i16* @foo
 	ret void
 }
 
 define void @add(i16 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w	r15, &foo
 	%1 = load i16* @foo
 	%2 = add i16 %a, %1
@@ -20,7 +20,7 @@ define void @add(i16 %a) nounwind {
 }
 
 define void @and(i16 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w	r15, &foo
 	%1 = load i16* @foo
 	%2 = and i16 %a, %1
@@ -29,7 +29,7 @@ define void @and(i16 %a) nounwind {
 }
 
 define void @bis(i16 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w	r15, &foo
 	%1 = load i16* @foo
 	%2 = or i16 %a, %1
@@ -38,7 +38,7 @@ define void @bis(i16 %a) nounwind {
 }
 
 define void @bic(i16 zeroext %m) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
 ; CHECK: bic.w   r15, &foo
         %1 = xor i16 %m, -1
         %2 = load i16* @foo
@@ -48,7 +48,7 @@ define void @bic(i16 zeroext %m) nounwind {
 }
 
 define void @xor(i16 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w	r15, &foo
 	%1 = load i16* @foo
 	%2 = xor i16 %a, %1
diff --git a/test/CodeGen/MSP430/Inst16ri.ll b/test/CodeGen/MSP430/Inst16ri.ll
index 5115a23..f89f686 100644
--- a/test/CodeGen/MSP430/Inst16ri.ll
+++ b/test/CodeGen/MSP430/Inst16ri.ll
@@ -3,34 +3,34 @@ target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i16 @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.w	#1, r15
 	ret i16 1
 }
 
 define i16 @add(i16 %a, i16 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w	#1, r15
 	%1 = add i16 %a, 1
 	ret i16 %1
 }
 
 define i16 @and(i16 %a, i16 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w	#1, r15
 	%1 = and i16 %a, 1
 	ret i16 %1
 }
 
 define i16 @bis(i16 %a, i16 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w	#1, r15
 	%1 = or i16 %a, 1
 	ret i16 %1
 }
 
 define i16 @xor(i16 %a, i16 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w	#1, r15
 	%1 = xor i16 %a, 1
 	ret i16 %1
diff --git a/test/CodeGen/MSP430/Inst16rm.ll b/test/CodeGen/MSP430/Inst16rm.ll
index 02e89c7..e6c5261 100644
--- a/test/CodeGen/MSP430/Inst16rm.ll
+++ b/test/CodeGen/MSP430/Inst16rm.ll
@@ -4,7 +4,7 @@ target triple = "msp430-generic-generic"
 @foo = common global i16 0, align 2
 
 define i16 @add(i16 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w	&foo, r15
 	%1 = load i16* @foo
 	%2 = add i16 %a, %1
@@ -12,7 +12,7 @@ define i16 @add(i16 %a) nounwind {
 }
 
 define i16 @and(i16 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w	&foo, r15
 	%1 = load i16* @foo
 	%2 = and i16 %a, %1
@@ -20,7 +20,7 @@ define i16 @and(i16 %a) nounwind {
 }
 
 define i16 @bis(i16 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w	&foo, r15
 	%1 = load i16* @foo
 	%2 = or i16 %a, %1
@@ -28,7 +28,7 @@ define i16 @bis(i16 %a) nounwind {
 }
 
 define i16  @bic(i16 %a) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
 ; CHECK: bic.w	&foo, r15
         %1 = load i16* @foo
         %2 = xor i16 %1, -1
@@ -37,7 +37,7 @@ define i16  @bic(i16 %a) nounwind {
 }
 
 define i16 @xor(i16 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w	&foo, r15
 	%1 = load i16* @foo
 	%2 = xor i16 %a, %1
diff --git a/test/CodeGen/MSP430/Inst16rr.ll b/test/CodeGen/MSP430/Inst16rr.ll
index 2f1ba5b..d74bfae 100644
--- a/test/CodeGen/MSP430/Inst16rr.ll
+++ b/test/CodeGen/MSP430/Inst16rr.ll
@@ -3,34 +3,34 @@ target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i16 @mov(i16 %a, i16 %b) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.w	r14, r15
 	ret i16 %b
 }
 
 define i16 @add(i16 %a, i16 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w	r14, r15
 	%1 = add i16 %a, %b
 	ret i16 %1
 }
 
 define i16 @and(i16 %a, i16 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w	r14, r15
 	%1 = and i16 %a, %b
 	ret i16 %1
 }
 
 define i16 @bis(i16 %a, i16 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w	r14, r15
 	%1 = or i16 %a, %b
 	ret i16 %1
 }
 
 define i16 @bic(i16 %a, i16 %b) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
 ; CHECK: bic.w	r14, r15
         %1 = xor i16 %b, -1
         %2 = and i16 %a, %1
@@ -38,7 +38,7 @@ define i16 @bic(i16 %a, i16 %b) nounwind {
 }
 
 define i16 @xor(i16 %a, i16 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w	r14, r15
 	%1 = xor i16 %a, %b
 	ret i16 %1
diff --git a/test/CodeGen/MSP430/Inst8mi.ll b/test/CodeGen/MSP430/Inst8mi.ll
index ef318ce..a2c7b71 100644
--- a/test/CodeGen/MSP430/Inst8mi.ll
+++ b/test/CodeGen/MSP430/Inst8mi.ll
@@ -4,14 +4,14 @@ target triple = "msp430-generic-generic"
 @foo = common global i8 0, align 1
 
 define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.b	#2, &foo
 	store i8 2, i8 * @foo
 	ret void
 }
 
 define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.b	#2, &foo
 	%1 = load i8* @foo
 	%2 = add i8 %1, 2
@@ -20,7 +20,7 @@ define void @add() nounwind {
 }
 
 define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.b	#2, &foo
 	%1 = load i8* @foo
 	%2 = and i8 %1, 2
@@ -29,7 +29,7 @@ define void @and() nounwind {
 }
 
 define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.b	#2, &foo
 	%1 = load i8* @foo
 	%2 = or i8 %1, 2
@@ -38,7 +38,7 @@ define void @bis() nounwind {
 }
 
 define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.b	#2, &foo
 	%1 = load i8* @foo
 	%2 = xor i8 %1, 2
diff --git a/test/CodeGen/MSP430/Inst8mm.ll b/test/CodeGen/MSP430/Inst8mm.ll
index a2987ac..d1ce8bc 100644
--- a/test/CodeGen/MSP430/Inst8mm.ll
+++ b/test/CodeGen/MSP430/Inst8mm.ll
@@ -6,7 +6,7 @@ target triple = "msp430-generic-generic"
 @bar = common global i8 0, align 1
 
 define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.b	&bar, &foo
         %1 = load i8* @bar
         store i8 %1, i8* @foo
@@ -14,7 +14,7 @@ define void @mov() nounwind {
 }
 
 define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.b	&bar, &foo
 	%1 = load i8* @bar
 	%2 = load i8* @foo
@@ -24,7 +24,7 @@ define void @add() nounwind {
 }
 
 define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.b	&bar, &foo
 	%1 = load i8* @bar
 	%2 = load i8* @foo
@@ -34,7 +34,7 @@ define void @and() nounwind {
 }
 
 define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.b	&bar, &foo
 	%1 = load i8* @bar
 	%2 = load i8* @foo
@@ -44,7 +44,7 @@ define void @bis() nounwind {
 }
 
 define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.b	&bar, &foo
 	%1 = load i8* @bar
 	%2 = load i8* @foo
diff --git a/test/CodeGen/MSP430/Inst8mr.ll b/test/CodeGen/MSP430/Inst8mr.ll
index 428d1fa..0b35667 100644
--- a/test/CodeGen/MSP430/Inst8mr.ll
+++ b/test/CodeGen/MSP430/Inst8mr.ll
@@ -4,14 +4,14 @@ target triple = "msp430-generic-generic"
 @foo = common global i8 0, align 1
 
 define void @mov(i8 %a) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.b	r15, &foo
 	store i8 %a, i8* @foo
 	ret void
 }
 
 define void @and(i8 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.b	r15, &foo
 	%1 = load i8* @foo
 	%2 = and i8 %a, %1
@@ -20,7 +20,7 @@ define void @and(i8 %a) nounwind {
 }
 
 define void @add(i8 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.b	r15, &foo
 	%1 = load i8* @foo
 	%2 = add i8 %a, %1
@@ -29,7 +29,7 @@ define void @add(i8 %a) nounwind {
 }
 
 define void @bis(i8 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.b	r15, &foo
 	%1 = load i8* @foo
 	%2 = or i8 %a, %1
@@ -38,7 +38,7 @@ define void @bis(i8 %a) nounwind {
 }
 
 define void @bic(i8 zeroext %m) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
 ; CHECK: bic.b   r15, &foo
         %1 = xor i8 %m, -1
         %2 = load i8* @foo
@@ -48,7 +48,7 @@ define void @bic(i8 zeroext %m) nounwind {
 }
 
 define void @xor(i8 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.b	r15, &foo
 	%1 = load i8* @foo
 	%2 = xor i8 %a, %1
diff --git a/test/CodeGen/MSP430/Inst8ri.ll b/test/CodeGen/MSP430/Inst8ri.ll
index ac3418a..ec0dff9 100644
--- a/test/CodeGen/MSP430/Inst8ri.ll
+++ b/test/CodeGen/MSP430/Inst8ri.ll
@@ -3,34 +3,34 @@ target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i8 @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.b	#1, r15
 	ret i8 1
 }
 
 define i8 @add(i8 %a, i8 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.b	#1, r15
 	%1 = add i8 %a, 1
 	ret i8 %1
 }
 
 define i8 @and(i8 %a, i8 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.b	#1, r15
 	%1 = and i8 %a, 1
 	ret i8 %1
 }
 
 define i8 @bis(i8 %a, i8 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.b	#1, r15
 	%1 = or i8 %a, 1
 	ret i8 %1
 }
 
 define i8 @xor(i8 %a, i8 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.b	#1, r15
 	%1 = xor i8 %a, 1
 	ret i8 %1
diff --git a/test/CodeGen/MSP430/Inst8rm.ll b/test/CodeGen/MSP430/Inst8rm.ll
index c062f04..308163e 100644
--- a/test/CodeGen/MSP430/Inst8rm.ll
+++ b/test/CodeGen/MSP430/Inst8rm.ll
@@ -4,7 +4,7 @@ target triple = "msp430-generic-generic"
 @foo = common global i8 0, align 1
 
 define i8 @add(i8 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.b	&foo, r15
 	%1 = load i8* @foo
 	%2 = add i8 %a, %1
@@ -12,7 +12,7 @@ define i8 @add(i8 %a) nounwind {
 }
 
 define i8 @and(i8 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.b	&foo, r15
 	%1 = load i8* @foo
 	%2 = and i8 %a, %1
@@ -20,7 +20,7 @@ define i8 @and(i8 %a) nounwind {
 }
 
 define i8 @bis(i8 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.b	&foo, r15
 	%1 = load i8* @foo
 	%2 = or i8 %a, %1
@@ -28,7 +28,7 @@ define i8 @bis(i8 %a) nounwind {
 }
 
 define i8  @bic(i8 %a) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
 ; CHECK: bic.b  &foo, r15
         %1 = load i8* @foo
         %2 = xor i8 %1, -1
@@ -37,7 +37,7 @@ define i8  @bic(i8 %a) nounwind {
 }
 
 define i8 @xor(i8 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.b	&foo, r15
 	%1 = load i8* @foo
 	%2 = xor i8 %a, %1
diff --git a/test/CodeGen/MSP430/Inst8rr.ll b/test/CodeGen/MSP430/Inst8rr.ll
index b9c17d9..76e8d19 100644
--- a/test/CodeGen/MSP430/Inst8rr.ll
+++ b/test/CodeGen/MSP430/Inst8rr.ll
@@ -3,34 +3,34 @@ target datalayout = "e-p:16:8:8-i8:8:8-i8:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i8 @mov(i8 %a, i8 %b) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.{{[bw]}} r14, r15
 	ret i8 %b
 }
 
 define i8 @add(i8 %a, i8 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.b
 	%1 = add i8 %a, %b
 	ret i8 %1
 }
 
 define i8 @and(i8 %a, i8 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w	r14, r15
 	%1 = and i8 %a, %b
 	ret i8 %1
 }
 
 define i8 @bis(i8 %a, i8 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w	r14, r15
 	%1 = or i8 %a, %b
 	ret i8 %1
 }
 
 define i8 @bic(i8 %a, i8 %b) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
 ; CHECK: bic.b  r14, r15
         %1 = xor i8 %b, -1
         %2 = and i8 %a, %1
@@ -38,7 +38,7 @@ define i8 @bic(i8 %a, i8 %b) nounwind {
 }
 
 define i8 @xor(i8 %a, i8 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w	r14, r15
 	%1 = xor i8 %a, %b
 	ret i8 %1
diff --git a/test/CodeGen/MSP430/bit.ll b/test/CodeGen/MSP430/bit.ll
index 03d672b..2ffc191 100644
--- a/test/CodeGen/MSP430/bit.ll
+++ b/test/CodeGen/MSP430/bit.ll
@@ -11,7 +11,7 @@ define i8 @bitbrr(i8 %a, i8 %b) nounwind {
 	%t3 = zext i1 %t2 to i8
 	ret i8 %t3
 }
-; CHECK: bitbrr:
+; CHECK-LABEL: bitbrr:
 ; CHECK: bit.b	r14, r15
 
 define i8 @bitbri(i8 %a) nounwind {
@@ -20,7 +20,7 @@ define i8 @bitbri(i8 %a) nounwind {
 	%t3 = zext i1 %t2 to i8
 	ret i8 %t3
 }
-; CHECK: bitbri:
+; CHECK-LABEL: bitbri:
 ; CHECK: bit.b	#15, r15
 
 define i8 @bitbir(i8 %a) nounwind {
@@ -29,7 +29,7 @@ define i8 @bitbir(i8 %a) nounwind {
 	%t3 = zext i1 %t2 to i8
 	ret i8 %t3
 }
-; CHECK: bitbir:
+; CHECK-LABEL: bitbir:
 ; CHECK: bit.b	#15, r15
 
 define i8 @bitbmi() nounwind {
@@ -39,7 +39,7 @@ define i8 @bitbmi() nounwind {
 	%t4 = zext i1 %t3 to i8
 	ret i8 %t4
 }
-; CHECK: bitbmi:
+; CHECK-LABEL: bitbmi:
 ; CHECK: bit.b	#15, &foo8
 
 define i8 @bitbim() nounwind {
@@ -49,7 +49,7 @@ define i8 @bitbim() nounwind {
 	%t4 = zext i1 %t3 to i8
 	ret i8 %t4
 }
-; CHECK: bitbim:
+; CHECK-LABEL: bitbim:
 ; CHECK: bit.b	#15, &foo8
 
 define i8 @bitbrm(i8 %a) nounwind {
@@ -59,7 +59,7 @@ define i8 @bitbrm(i8 %a) nounwind {
 	%t4 = zext i1 %t3 to i8
 	ret i8 %t4
 }
-; CHECK: bitbrm:
+; CHECK-LABEL: bitbrm:
 ; CHECK: bit.b	&foo8, r15
 
 define i8 @bitbmr(i8 %a) nounwind {
@@ -69,7 +69,7 @@ define i8 @bitbmr(i8 %a) nounwind {
 	%t4 = zext i1 %t3 to i8
 	ret i8 %t4
 }
-; CHECK: bitbmr:
+; CHECK-LABEL: bitbmr:
 ; CHECK: bit.b	r15, &foo8
 
 define i8 @bitbmm() nounwind {
@@ -80,7 +80,7 @@ define i8 @bitbmm() nounwind {
 	%t5 = zext i1 %t4 to i8
 	ret i8 %t5
 }
-; CHECK: bitbmm:
+; CHECK-LABEL: bitbmm:
 ; CHECK: bit.b	&bar8, &foo8
 
 @foo16 = external global i16
@@ -92,7 +92,7 @@ define i16 @bitwrr(i16 %a, i16 %b) nounwind {
 	%t3 = zext i1 %t2 to i16
 	ret i16 %t3
 }
-; CHECK: bitwrr:
+; CHECK-LABEL: bitwrr:
 ; CHECK: bit.w	r14, r15
 
 define i16 @bitwri(i16 %a) nounwind {
@@ -101,7 +101,7 @@ define i16 @bitwri(i16 %a) nounwind {
 	%t3 = zext i1 %t2 to i16
 	ret i16 %t3
 }
-; CHECK: bitwri:
+; CHECK-LABEL: bitwri:
 ; CHECK: bit.w	#4080, r15
 
 define i16 @bitwir(i16 %a) nounwind {
@@ -110,7 +110,7 @@ define i16 @bitwir(i16 %a) nounwind {
 	%t3 = zext i1 %t2 to i16
 	ret i16 %t3
 }
-; CHECK: bitwir:
+; CHECK-LABEL: bitwir:
 ; CHECK: bit.w	#4080, r15
 
 define i16 @bitwmi() nounwind {
@@ -120,7 +120,7 @@ define i16 @bitwmi() nounwind {
 	%t4 = zext i1 %t3 to i16
 	ret i16 %t4
 }
-; CHECK: bitwmi:
+; CHECK-LABEL: bitwmi:
 ; CHECK: bit.w	#4080, &foo16
 
 define i16 @bitwim() nounwind {
@@ -130,7 +130,7 @@ define i16 @bitwim() nounwind {
 	%t4 = zext i1 %t3 to i16
 	ret i16 %t4
 }
-; CHECK: bitwim:
+; CHECK-LABEL: bitwim:
 ; CHECK: bit.w	#4080, &foo16
 
 define i16 @bitwrm(i16 %a) nounwind {
@@ -140,7 +140,7 @@ define i16 @bitwrm(i16 %a) nounwind {
 	%t4 = zext i1 %t3 to i16
 	ret i16 %t4
 }
-; CHECK: bitwrm:
+; CHECK-LABEL: bitwrm:
 ; CHECK: bit.w	&foo16, r15
 
 define i16 @bitwmr(i16 %a) nounwind {
@@ -150,7 +150,7 @@ define i16 @bitwmr(i16 %a) nounwind {
 	%t4 = zext i1 %t3 to i16
 	ret i16 %t4
 }
-; CHECK: bitwmr:
+; CHECK-LABEL: bitwmr:
 ; CHECK: bit.w	r15, &foo16
 
 define i16 @bitwmm() nounwind {
@@ -161,6 +161,6 @@ define i16 @bitwmm() nounwind {
 	%t5 = zext i1 %t4 to i16
 	ret i16 %t5
 }
-; CHECK: bitwmm:
+; CHECK-LABEL: bitwmm:
 ; CHECK: bit.w	&bar16, &foo16
 
diff --git a/test/CodeGen/MSP430/byval.ll b/test/CodeGen/MSP430/byval.ll
index 9dda0a0..bd38e95 100644
--- a/test/CodeGen/MSP430/byval.ll
+++ b/test/CodeGen/MSP430/byval.ll
@@ -8,7 +8,7 @@ target triple = "msp430---elf"
 
 define i16 @callee(%struct.Foo* byval %f) nounwind {
 entry:
-; CHECK: callee:
+; CHECK-LABEL: callee:
 ; CHECK: mov.w 2(r1), r15
   %0 = getelementptr inbounds %struct.Foo* %f, i32 0, i32 0
   %1 = load i16* %0, align 2
@@ -17,7 +17,7 @@ entry:
 
 define void @caller() nounwind {
 entry:
-; CHECK: caller:
+; CHECK-LABEL: caller:
 ; CHECK: mov.w &foo+4, 4(r1)
 ; CHECK-NEXT: mov.w &foo+2, 2(r1)
 ; CHECK-NEXT: mov.w &foo, 0(r1)
diff --git a/test/CodeGen/MSP430/fp.ll b/test/CodeGen/MSP430/fp.ll
index c3273ef..0180905 100644
--- a/test/CodeGen/MSP430/fp.ll
+++ b/test/CodeGen/MSP430/fp.ll
@@ -5,7 +5,7 @@ target triple = "msp430---elf"
 
 define void @fp() nounwind {
 entry:
-; CHECK: fp:
+; CHECK-LABEL: fp:
 ; CHECK: push.w r4
 ; CHECK: mov.w r1, r4
 ; CHECK: sub.w #2, r1
diff --git a/test/CodeGen/MSP430/postinc.ll b/test/CodeGen/MSP430/postinc.ll
index 8f01b83..8d55fd3 100644
--- a/test/CodeGen/MSP430/postinc.ll
+++ b/test/CodeGen/MSP430/postinc.ll
@@ -11,7 +11,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
   %add = add i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
@@ -33,7 +33,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
-; CHECK: sub:
+; CHECK-LABEL: sub:
 ; CHECK: sub.w @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
   %add = sub i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
@@ -55,7 +55,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
-; CHECK: or:
+; CHECK-LABEL: or:
 ; CHECK: bis.w @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
   %add = or i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
@@ -77,7 +77,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
   %add = xor i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
@@ -99,7 +99,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
   %add = and i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
diff --git a/test/CodeGen/MSP430/setcc.ll b/test/CodeGen/MSP430/setcc.ll
index 05f9acd..d5a8057 100644
--- a/test/CodeGen/MSP430/setcc.ll
+++ b/test/CodeGen/MSP430/setcc.ll
@@ -8,7 +8,7 @@ define i16 @sccweqand(i16 %a, i16 %b) nounwind {
 	%t3 = zext i1 %t2 to i16
 	ret i16 %t3
 }
-; CHECK: sccweqand:
+; CHECK-LABEL: sccweqand:
 ; CHECK:	bit.w	r14, r15
 ; CHECK:	mov.w	r2, r15
 ; CHECK:	rra.w   r15
@@ -20,7 +20,7 @@ define i16 @sccwneand(i16 %a, i16 %b) nounwind {
 	%t3 = zext i1 %t2 to i16
 	ret i16 %t3
 }
-; CHECK: sccwneand:
+; CHECK-LABEL: sccwneand:
 ; CHECK: 	bit.w	r14, r15
 ; CHECK:	mov.w	r2, r15
 ; CHECK:	and.w	#1, r15
@@ -30,7 +30,7 @@ define i16 @sccwne(i16 %a, i16 %b) nounwind {
 	%t2 = zext i1 %t1 to i16
 	ret i16 %t2
 }
-; CHECK:sccwne:
+; CHECK-LABEL:sccwne:
 ; CHECK:	cmp.w	r14, r15
 ; CHECK:	mov.w	r2, r12
 ; CHECK:	rra.w	r12
@@ -42,7 +42,7 @@ define i16 @sccweq(i16 %a, i16 %b) nounwind {
 	%t2 = zext i1 %t1 to i16
 	ret i16 %t2
 }
-; CHECK:sccweq:
+; CHECK-LABEL:sccweq:
 ; CHECK:	cmp.w	r14, r15
 ; CHECK:	mov.w	r2, r15
 ; CHECK:	rra.w	r15
@@ -53,7 +53,7 @@ define i16 @sccwugt(i16 %a, i16 %b) nounwind {
 	%t2 = zext i1 %t1 to i16
 	ret i16 %t2
 }
-; CHECK:sccwugt:
+; CHECK-LABEL:sccwugt:
 ; CHECK:	cmp.w	r15, r14
 ; CHECK:	mov.w	#1, r15
 ; CHECK:	bic.w	r2, r15
@@ -63,7 +63,7 @@ define i16 @sccwuge(i16 %a, i16 %b) nounwind {
 	%t2 = zext i1 %t1 to i16
 	ret i16 %t2
 }
-; CHECK:sccwuge:
+; CHECK-LABEL:sccwuge:
 ; CHECK:	cmp.w	r14, r15
 ; CHECK:	mov.w	r2, r15
 ; CHECK:	and.w	#1, r15
@@ -73,7 +73,7 @@ define i16 @sccwult(i16 %a, i16 %b) nounwind {
 	%t2 = zext i1 %t1 to i16
 	ret i16 %t2
 }
-; CHECK:sccwult:
+; CHECK-LABEL:sccwult:
 ; CHECK:	cmp.w	r14, r15
 ; CHECK:	mov.w	#1, r15
 ; CHECK:	bic.w	r2, r15
@@ -83,7 +83,7 @@ define i16 @sccwule(i16 %a, i16 %b) nounwind {
 	%t2 = zext i1 %t1 to i16
 	ret i16 %t2
 }
-; CHECK:sccwule:
+; CHECK-LABEL:sccwule:
 ; CHECK:	cmp.w	r15, r14
 ; CHECK:	mov.w	r2, r15
 ; CHECK:	and.w	#1, r15
diff --git a/test/CodeGen/MSP430/shifts.ll b/test/CodeGen/MSP430/shifts.ll
index b5b3054..22ae59e 100644
--- a/test/CodeGen/MSP430/shifts.ll
+++ b/test/CodeGen/MSP430/shifts.ll
@@ -4,7 +4,7 @@ target triple = "msp430-elf"
 
 define zeroext i8 @lshr8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
 entry:
-; CHECK: lshr8:
+; CHECK-LABEL: lshr8:
 ; CHECK: rrc.b
   %shr = lshr i8 %a, %cnt
   ret i8 %shr
@@ -12,7 +12,7 @@ entry:
 
 define signext i8 @ashr8(i8 signext %a, i8 zeroext %cnt) nounwind readnone {
 entry:
-; CHECK: ashr8:
+; CHECK-LABEL: ashr8:
 ; CHECK: rra.b
   %shr = ashr i8 %a, %cnt
   ret i8 %shr
@@ -28,7 +28,7 @@ entry:
 
 define zeroext i16 @lshr16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
 entry:
-; CHECK: lshr16:
+; CHECK-LABEL: lshr16:
 ; CHECK: rrc.w
   %shr = lshr i16 %a, %cnt
   ret i16 %shr
@@ -36,7 +36,7 @@ entry:
 
 define signext i16 @ashr16(i16 signext %a, i16 zeroext %cnt) nounwind readnone {
 entry:
-; CHECK: ashr16:
+; CHECK-LABEL: ashr16:
 ; CHECK: rra.w
   %shr = ashr i16 %a, %cnt
   ret i16 %shr
@@ -44,7 +44,7 @@ entry:
 
 define zeroext i16 @shl16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
 entry:
-; CHECK: shl16:
+; CHECK-LABEL: shl16:
 ; CHECK: rla.w
   %shl = shl i16 %a, %cnt
   ret i16 %shl
diff --git a/test/CodeGen/MSP430/vararg.ll b/test/CodeGen/MSP430/vararg.ll
index 603d3ec..9e511fc 100644
--- a/test/CodeGen/MSP430/vararg.ll
+++ b/test/CodeGen/MSP430/vararg.ll
@@ -9,7 +9,7 @@ declare void @llvm.va_copy(i8*, i8*) nounwind
 
 define void @va_start(i16 %a, ...) nounwind {
 entry:
-; CHECK: va_start:
+; CHECK-LABEL: va_start:
 ; CHECK: sub.w #2, r1
   %vl = alloca i8*, align 2
   %vl1 = bitcast i8** %vl to i8*
@@ -23,7 +23,7 @@ entry:
 
 define i16 @va_arg(i8* %vl) nounwind {
 entry:
-; CHECK: va_arg:
+; CHECK-LABEL: va_arg:
   %vl.addr = alloca i8*, align 2
 ; CHECK: mov.w r15, 0(r1)
   store i8* %vl, i8** %vl.addr, align 2
@@ -37,7 +37,7 @@ entry:
 
 define void @va_copy(i8* %vl) nounwind {
 entry:
-; CHECK: va_copy:
+; CHECK-LABEL: va_copy:
   %vl.addr = alloca i8*, align 2
   %vl2 = alloca i8*, align 2
 ; CHECK: mov.w r15, 2(r1)
diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll
index 6bc9ce2..54268cd 100644
--- a/test/CodeGen/Mips/atomic.ll
+++ b/test/CodeGen/Mips/atomic.ll
@@ -8,7 +8,7 @@ entry:
   %0 = atomicrmw add i32* @x, i32 %incr monotonic
   ret i32 %0
 
-; CHECK-EL:   AtomicLoadAdd32:
+; CHECK-EL-LABEL:   AtomicLoadAdd32:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EL:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EL:   ll      $[[R1:[0-9]+]], 0($[[R0]])
@@ -16,7 +16,7 @@ entry:
 ; CHECK-EL:   sc      $[[R2]], 0($[[R0]])
 ; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
 
-; CHECK-EB:   AtomicLoadAdd32:
+; CHECK-EB-LABEL:   AtomicLoadAdd32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EB:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EB:   ll      $[[R1:[0-9]+]], 0($[[R0]])
@@ -30,7 +30,7 @@ entry:
   %0 = atomicrmw nand i32* @x, i32 %incr monotonic
   ret i32 %0
 
-; CHECK-EL:   AtomicLoadNand32:
+; CHECK-EL-LABEL:   AtomicLoadNand32:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EL:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EL:   ll      $[[R1:[0-9]+]], 0($[[R0]])
@@ -39,7 +39,7 @@ entry:
 ; CHECK-EL:   sc      $[[R2]], 0($[[R0]])
 ; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
 
-; CHECK-EB:   AtomicLoadNand32:
+; CHECK-EB-LABEL:   AtomicLoadNand32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EB:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EB:   ll      $[[R1:[0-9]+]], 0($[[R0]])
@@ -57,14 +57,14 @@ entry:
   %0 = atomicrmw xchg i32* @x, i32 %tmp monotonic
   ret i32 %0
 
-; CHECK-EL:   AtomicSwap32:
+; CHECK-EL-LABEL:   AtomicSwap32:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EL:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EL:   ll      ${{[0-9]+}}, 0($[[R0]])
 ; CHECK-EL:   sc      $[[R2:[0-9]+]], 0($[[R0]])
 ; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
 
-; CHECK-EB:   AtomicSwap32:
+; CHECK-EB-LABEL:   AtomicSwap32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EB:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EB:   ll      ${{[0-9]+}}, 0($[[R0]])
@@ -80,7 +80,7 @@ entry:
   %0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic
   ret i32 %0
 
-; CHECK-EL:   AtomicCmpSwap32:
+; CHECK-EL-LABEL:   AtomicCmpSwap32:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EL:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EL:   ll      $2, 0($[[R0]])
@@ -89,7 +89,7 @@ entry:
 ; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
 ; CHECK-EL:   $[[BB1]]:
 
-; CHECK-EB:   AtomicCmpSwap32:
+; CHECK-EB-LABEL:   AtomicCmpSwap32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EB:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EB:   ll      $2, 0($[[R0]])
@@ -108,7 +108,7 @@ entry:
   %0 = atomicrmw add i8* @y, i8 %incr monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicLoadAdd8:
+; CHECK-EL-LABEL:   AtomicLoadAdd8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -133,7 +133,7 @@ entry:
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicLoadAdd8:
+; CHECK-EB-LABEL:   AtomicLoadAdd8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -165,7 +165,7 @@ entry:
   %0 = atomicrmw sub i8* @y, i8 %incr monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicLoadSub8:
+; CHECK-EL-LABEL:   AtomicLoadSub8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -190,7 +190,7 @@ entry:
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicLoadSub8:
+; CHECK-EB-LABEL:   AtomicLoadSub8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -222,7 +222,7 @@ entry:
   %0 = atomicrmw nand i8* @y, i8 %incr monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicLoadNand8:
+; CHECK-EL-LABEL:   AtomicLoadNand8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -248,7 +248,7 @@ entry:
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicLoadNand8:
+; CHECK-EB-LABEL:   AtomicLoadNand8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -281,7 +281,7 @@ entry:
   %0 = atomicrmw xchg i8* @y, i8 %newval monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicSwap8:
+; CHECK-EL-LABEL:   AtomicSwap8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -305,7 +305,7 @@ entry:
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicSwap8:
+; CHECK-EB-LABEL:   AtomicSwap8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -336,7 +336,7 @@ entry:
   %0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicCmpSwap8:
+; CHECK-EL-LABEL:   AtomicCmpSwap8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -365,7 +365,7 @@ entry:
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicCmpSwap8:
+; CHECK-EB-LABEL:   AtomicCmpSwap8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -403,14 +403,14 @@ entry:
   %0 = atomicrmw add i32* @countsint, i32 %v seq_cst
   ret i32 %0 
 
-; CHECK-EL:   CheckSync:
+; CHECK-EL-LABEL:   CheckSync:
 ; CHECK-EL:   sync 0
 ; CHECK-EL:   ll
 ; CHECK-EL:   sc
 ; CHECK-EL:   beq
 ; CHECK-EL:   sync 0
 
-; CHECK-EB:   CheckSync:
+; CHECK-EB-LABEL:   CheckSync:
 ; CHECK-EB:   sync 0
 ; CHECK-EB:   ll
 ; CHECK-EB:   sc
diff --git a/test/CodeGen/Mips/atomicops.ll b/test/CodeGen/Mips/atomicops.ll
index b9c3804..0f0f01a 100644
--- a/test/CodeGen/Mips/atomicops.ll
+++ b/test/CodeGen/Mips/atomicops.ll
@@ -7,7 +7,7 @@ entry:
   %0 = atomicrmw add i32* %mem, i32 %val seq_cst
   %add = add nsw i32 %0, %c
   ret i32 %add
-; 16: foo:
+; 16-LABEL: foo:
 ; 16:	lw	${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
 ; 16: 	lw	${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
 }
@@ -26,7 +26,7 @@ entry:
   %4 = atomicrmw xchg i32* %x, i32 1 seq_cst
   %5 = load volatile i32* %x, align 4
   %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %4, i32 %5) nounwind
-; 16: main:
+; 16-LABEL: main:
 ; 16:	lw	${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
 ; 16: 	lw	${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
 ; 16:	lw	${{[0-9]+}}, %call16(__sync_val_compare_and_swap_4)(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/biggot.ll b/test/CodeGen/Mips/biggot.ll
index c4ad851..da287ee 100644
--- a/test/CodeGen/Mips/biggot.ll
+++ b/test/CodeGen/Mips/biggot.ll
@@ -31,12 +31,12 @@ declare void @foo0(i32)
 
 define void @foo2(i32* nocapture %d, i32* nocapture %s, i32 %n) nounwind {
 entry:
-; O32: foo2:
+; O32-LABEL: foo2:
 ; O32: lui $[[R2:[0-9]+]], %call_hi(memcpy)
 ; O32: addu  $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
 ; O32: lw  ${{[0-9]+}}, %call_lo(memcpy)($[[R3]])
 
-; N64: foo2:
+; N64-LABEL: foo2:
 ; N64: lui $[[R2:[0-9]+]], %call_hi(memcpy)
 ; N64: daddu  $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
 ; N64: ld  ${{[0-9]+}}, %call_lo(memcpy)($[[R3]])
diff --git a/test/CodeGen/Mips/brdelayslot.ll b/test/CodeGen/Mips/brdelayslot.ll
index d076f74..82e4730 100644
--- a/test/CodeGen/Mips/brdelayslot.ll
+++ b/test/CodeGen/Mips/brdelayslot.ll
@@ -31,7 +31,7 @@ declare void @foo2(i32)
 ;
 define void @foo3(i32 %a) nounwind {
 entry:
-; Default:     foo3:
+; Default-LABEL:     foo3:
 ; Default:     jalr
 ; Default:     cvt.d.w
 
@@ -49,7 +49,7 @@ declare void @foo4(double)
 ; Check that branch delay slot can be filled with an instruction with operand
 ; $1.
 ;
-; Default:     foo5:
+; Default-LABEL:     foo5:
 ; Default-NOT: nop
 
 define void @foo5(i32 %a) nounwind {
@@ -76,7 +76,7 @@ if.end:
 
 ; Check that delay slot filler can place mov.s or mov.d in delay slot.
 ;
-; Default:     foo6:
+; Default-LABEL:     foo6:
 ; Default-NOT: nop
 ; Default:     .end foo6
 
@@ -90,7 +90,7 @@ declare void @foo7(double, float)
 
 ; Check that a store can move past other memory instructions.
 ;
-; STATICO1:      foo8:
+; STATICO1-LABEL:      foo8:
 ; STATICO1:      jalr ${{[0-9]+}}
 ; STATICO1-NEXT: sw ${{[0-9]+}}, %lo(g1)
 
@@ -109,7 +109,7 @@ entry:
 ; Test searchForward. Check that the second jal's slot is filled with another
 ; instruction in the same block.
 ;
-; FORWARD:     foo10:
+; FORWARD-LABEL:     foo10:
 ; FORWARD:     jal foo11
 ; FORWARD:     jal foo11
 ; FORWARD-NOT: nop
@@ -130,7 +130,7 @@ declare void @foo11()
 ; Check that delay slots of branches in both the entry block and loop body are
 ; filled.
 ;
-; SUCCBB:      succbbs_loop1:
+; SUCCBB-LABEL:      succbbs_loop1:
 ; SUCCBB:      blez $5, $BB
 ; SUCCBB-NEXT: addiu
 ; SUCCBB:      bne ${{[0-9]+}}, $zero, $BB
@@ -158,7 +158,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 ; Check that the first branch has its slot filled.
 ;
-; SUCCBB:      succbbs_br1:
+; SUCCBB-LABEL:      succbbs_br1:
 ; SUCCBB:      beq ${{[0-9]+}}, $zero, $BB
 ; SUCCBB-NEXT: lw $25, %call16(foo100)
 
diff --git a/test/CodeGen/Mips/bswap.ll b/test/CodeGen/Mips/bswap.ll
index a8fc2cd..0da2d2b 100644
--- a/test/CodeGen/Mips/bswap.ll
+++ b/test/CodeGen/Mips/bswap.ll
@@ -3,7 +3,7 @@
 
 define i32 @bswap32(i32 %x) nounwind readnone {
 entry:
-; MIPS32: bswap32:
+; MIPS32-LABEL: bswap32:
 ; MIPS32: wsbh $[[R0:[0-9]+]]
 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
   %or.3 = call i32 @llvm.bswap.i32(i32 %x)
@@ -12,7 +12,7 @@ entry:
 
 define i64 @bswap64(i64 %x) nounwind readnone {
 entry:
-; MIPS64: bswap64:
+; MIPS64-LABEL: bswap64:
 ; MIPS64: dsbh $[[R0:[0-9]+]]
 ; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
   %or.7 = call i64 @llvm.bswap.i64(i64 %x)
diff --git a/test/CodeGen/Mips/check-noat.ll b/test/CodeGen/Mips/check-noat.ll
index bfeff67..cfcd367 100644
--- a/test/CodeGen/Mips/check-noat.ll
+++ b/test/CodeGen/Mips/check-noat.ll
@@ -2,7 +2,7 @@
 
 define void @f() nounwind readnone {
 entry:
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: .set  noat
 ; CHECK: .set  at
 
diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll
index a969297..c24c5ac 100644
--- a/test/CodeGen/Mips/cmov.ll
+++ b/test/CodeGen/Mips/cmov.ll
@@ -22,11 +22,11 @@ entry:
 @c = global i32 1, align 4
 @d = global i32 0, align 4
 
-; O32: cmov2:
+; O32-LABEL: cmov2:
 ; O32: addiu $[[R1:[0-9]+]], ${{[a-z0-9]+}}, %got(d)
 ; O32: addiu $[[R0:[0-9]+]], ${{[a-z0-9]+}}, %got(c)
 ; O32: movn  $[[R1]], $[[R0]], ${{[0-9]+}}
-; N64: cmov2:
+; N64-LABEL: cmov2:
 ; N64: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
 ; N64: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)
 ; N64: movn  $[[R1]], $[[R0]], ${{[0-9]+}}
@@ -39,7 +39,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: cmov3:
+; O32-LABEL: cmov3:
 ; O32: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 define i32 @cmov3(i32 %a, i32 %b, i32 %c) nounwind readnone {
@@ -49,7 +49,7 @@ entry:
   ret i32 %cond
 }
 
-; N64: cmov4:
+; N64-LABEL: cmov4:
 ; N64: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 define i64 @cmov4(i32 %a, i64 %b, i64 %c) nounwind readnone {
@@ -67,7 +67,7 @@ entry:
 ;  (movz t, (setlt a, N + 1), f)
 ; if N + 1 fits in 16-bit.
 
-; O32: slti0:
+; O32-LABEL: slti0:
 ; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -78,7 +78,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: slti1:
+; O32-LABEL: slti1:
 ; O32: slt ${{[0-9]+}}
 
 define i32 @slti1(i32 %a) {
@@ -88,7 +88,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: slti2:
+; O32-LABEL: slti2:
 ; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -99,7 +99,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: slti3:
+; O32-LABEL: slti3:
 ; O32: slt ${{[0-9]+}}
 
 define i32 @slti3(i32 %a) {
@@ -111,7 +111,7 @@ entry:
 
 ; 64-bit patterns.
 
-; N64: slti64_0:
+; N64-LABEL: slti64_0:
 ; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -122,7 +122,7 @@ entry:
   ret i64 %conv
 }
 
-; N64: slti64_1:
+; N64-LABEL: slti64_1:
 ; N64: slt ${{[0-9]+}}
 
 define i64 @slti64_1(i64 %a) {
@@ -132,7 +132,7 @@ entry:
   ret i64 %conv
 }
 
-; N64: slti64_2:
+; N64-LABEL: slti64_2:
 ; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -143,7 +143,7 @@ entry:
   ret i64 %conv
 }
 
-; N64: slti64_3:
+; N64-LABEL: slti64_3:
 ; N64: slt ${{[0-9]+}}
 
 define i64 @slti64_3(i64 %a) {
@@ -155,7 +155,7 @@ entry:
 
 ; sltiu instructions.
 
-; O32: sltiu0:
+; O32-LABEL: sltiu0:
 ; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -166,7 +166,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: sltiu1:
+; O32-LABEL: sltiu1:
 ; O32: sltu ${{[0-9]+}}
 
 define i32 @sltiu1(i32 %a) {
@@ -176,7 +176,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: sltiu2:
+; O32-LABEL: sltiu2:
 ; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -187,7 +187,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: sltiu3:
+; O32-LABEL: sltiu3:
 ; O32: sltu ${{[0-9]+}}
 
 define i32 @sltiu3(i32 %a) {
diff --git a/test/CodeGen/Mips/const-mult.ll b/test/CodeGen/Mips/const-mult.ll
index 2918464..8c0cbe3 100644
--- a/test/CodeGen/Mips/const-mult.ll
+++ b/test/CodeGen/Mips/const-mult.ll
@@ -2,7 +2,7 @@
 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK
 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK64
 
-; CHECK: mul5_32:
+; CHECK-LABEL: mul5_32:
 ; CHECK: sll $[[R0:[0-9]+]], $4, 2
 ; CHECK: addu ${{[0-9]+}}, $[[R0]], $4
 
@@ -12,7 +12,7 @@ entry:
   ret i32 %mul
 }
 
-; CHECK:     mul27_32:
+; CHECK-LABEL:     mul27_32:
 ; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
 ; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
 ; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 5
@@ -24,7 +24,7 @@ entry:
   ret i32 %mul
 }
 
-; CHECK:     muln2147483643_32:
+; CHECK-LABEL:     muln2147483643_32:
 ; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
 ; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
 ; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 31
@@ -36,7 +36,7 @@ entry:
   ret i32 %mul
 }
 
-; CHECK64:     muln9223372036854775805_64:
+; CHECK64-LABEL:     muln9223372036854775805_64:
 ; CHECK64-DAG: dsll $[[R0:[0-9]+]], $4, 1
 ; CHECK64-DAG: daddu $[[R1:[0-9]+]], $[[R0]], $4
 ; CHECK64-DAG: dsll $[[R2:[0-9]+]], $4, 63
diff --git a/test/CodeGen/Mips/divrem.ll b/test/CodeGen/Mips/divrem.ll
index 47cebbe..a983c46 100644
--- a/test/CodeGen/Mips/divrem.ll
+++ b/test/CodeGen/Mips/divrem.ll
@@ -2,12 +2,12 @@
 ; RUN: llc -march=mips -mno-check-zero-division < %s |\
 ; RUN: FileCheck %s -check-prefix=NOCHECK
 
-; TRAP: sdiv1:
+; TRAP-LABEL: sdiv1:
 ; TRAP: div $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; TRAP: teq $[[R0]], $zero, 7
 ; TRAP: mflo
 
-; NOCHECK: sdiv1:
+; NOCHECK-LABEL: sdiv1:
 ; NOCHECK-NOT: teq
 ; NOCHECK: .end sdiv1
 
@@ -17,7 +17,7 @@ entry:
   ret i32 %div
 }
 
-; TRAP: srem1:
+; TRAP-LABEL: srem1:
 ; TRAP: div $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; TRAP: teq $[[R0]], $zero, 7
 ; TRAP: mfhi
@@ -28,7 +28,7 @@ entry:
   ret i32 %rem
 }
 
-; TRAP: udiv1:
+; TRAP-LABEL: udiv1:
 ; TRAP: divu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; TRAP: teq $[[R0]], $zero, 7
 ; TRAP: mflo
@@ -39,7 +39,7 @@ entry:
   ret i32 %div
 }
 
-; TRAP: urem1:
+; TRAP-LABEL: urem1:
 ; TRAP: divu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; TRAP: teq $[[R0]], $zero, 7
 ; TRAP: mfhi
diff --git a/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll b/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
index 9f2f066..a5fe34c 100644
--- a/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
+++ b/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s
 
-; CHECK: select_v2q15_eq_:
+; CHECK-LABEL: select_v2q15_eq_:
 ; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.ph ${{[0-9]+}}, $6, $7
 
@@ -17,7 +17,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_lt_:
+; CHECK-LABEL: select_v2q15_lt_:
 ; CHECK: cmp.lt.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, $6, $7
 
@@ -34,7 +34,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_le_:
+; CHECK-LABEL: select_v2q15_le_:
 ; CHECK: cmp.le.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, $6, $7
 
@@ -51,7 +51,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_ne_:
+; CHECK-LABEL: select_v2q15_ne_:
 ; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.ph ${{[0-9]+}}, $7, $6
 
@@ -68,7 +68,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_gt_:
+; CHECK-LABEL: select_v2q15_gt_:
 ; CHECK: cmp.le.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, $7, $6
 
@@ -85,7 +85,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_ge_:
+; CHECK-LABEL: select_v2q15_ge_:
 ; CHECK: cmp.lt.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, $7, $6
 
@@ -102,7 +102,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_eq_:
+; CHECK-LABEL: select_v4ui8_eq_:
 ; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.qb ${{[0-9]+}}, $6, $7
 
@@ -119,7 +119,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_lt_:
+; CHECK-LABEL: select_v4ui8_lt_:
 ; CHECK: cmpu.lt.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, $6, $7
 
@@ -136,7 +136,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_le_:
+; CHECK-LABEL: select_v4ui8_le_:
 ; CHECK: cmpu.le.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, $6, $7
 
@@ -153,7 +153,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_ne_:
+; CHECK-LABEL: select_v4ui8_ne_:
 ; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.qb ${{[0-9]+}}, $7, $6
 
@@ -170,7 +170,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_gt_:
+; CHECK-LABEL: select_v4ui8_gt_:
 ; CHECK: cmpu.le.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, $7, $6
 
@@ -187,7 +187,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_ge_:
+; CHECK-LABEL: select_v4ui8_ge_:
 ; CHECK: cmpu.lt.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, $7, $6
 
@@ -204,7 +204,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2ui16_lt_:
+; CHECK-LABEL: select_v2ui16_lt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -221,7 +221,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2ui16_le_:
+; CHECK-LABEL: select_v2ui16_le_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -238,7 +238,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2ui16_gt_:
+; CHECK-LABEL: select_v2ui16_gt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -255,7 +255,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2ui16_ge_:
+; CHECK-LABEL: select_v2ui16_ge_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -272,7 +272,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4i8_lt_:
+; CHECK-LABEL: select_v4i8_lt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -289,7 +289,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4i8_le_:
+; CHECK-LABEL: select_v4i8_le_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -306,7 +306,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4i8_gt_:
+; CHECK-LABEL: select_v4i8_gt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -323,7 +323,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4i8_ge_:
+; CHECK-LABEL: select_v4i8_ge_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -340,7 +340,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_eq_:
+; CHECK-LABEL: compare_v2q15_eq_:
 ; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -355,7 +355,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_lt_:
+; CHECK-LABEL: compare_v2q15_lt_:
 ; CHECK: cmp.lt.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -370,7 +370,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_le_:
+; CHECK-LABEL: compare_v2q15_le_:
 ; CHECK: cmp.le.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -385,7 +385,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_ne_:
+; CHECK-LABEL: compare_v2q15_ne_:
 ; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -400,7 +400,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_gt_:
+; CHECK-LABEL: compare_v2q15_gt_:
 ; CHECK: cmp.le.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -415,7 +415,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_ge_:
+; CHECK-LABEL: compare_v2q15_ge_:
 ; CHECK: cmp.lt.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -430,7 +430,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_eq_:
+; CHECK-LABEL: compare_v4ui8_eq_:
 ; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -445,7 +445,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_lt_:
+; CHECK-LABEL: compare_v4ui8_lt_:
 ; CHECK: cmpu.lt.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -460,7 +460,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_le_:
+; CHECK-LABEL: compare_v4ui8_le_:
 ; CHECK: cmpu.le.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -475,7 +475,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_ne_:
+; CHECK-LABEL: compare_v4ui8_ne_:
 ; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -490,7 +490,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_gt_:
+; CHECK-LABEL: compare_v4ui8_gt_:
 ; CHECK: cmpu.le.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -505,7 +505,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_ge_:
+; CHECK-LABEL: compare_v4ui8_ge_:
 ; CHECK: cmpu.lt.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -520,7 +520,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2ui16_lt_:
+; CHECK-LABEL: compare_v2ui16_lt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -535,7 +535,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2ui16_le_:
+; CHECK-LABEL: compare_v2ui16_le_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -550,7 +550,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2ui16_gt_:
+; CHECK-LABEL: compare_v2ui16_gt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -565,7 +565,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2ui16_ge_:
+; CHECK-LABEL: compare_v2ui16_ge_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -580,7 +580,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4i8_lt_:
+; CHECK-LABEL: compare_v4i8_lt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -595,7 +595,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4i8_le_:
+; CHECK-LABEL: compare_v4i8_le_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -610,7 +610,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4i8_gt_:
+; CHECK-LABEL: compare_v4i8_gt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -625,7 +625,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4i8_ge_:
+; CHECK-LABEL: compare_v4i8_ge_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
diff --git a/test/CodeGen/Mips/dsp-patterns.ll b/test/CodeGen/Mips/dsp-patterns.ll
index ae0167b..f5bb3ab 100644
--- a/test/CodeGen/Mips/dsp-patterns.ll
+++ b/test/CodeGen/Mips/dsp-patterns.ll
@@ -128,7 +128,7 @@ entry:
   ret i64 %add
 }
 
-; R1: shift1_v2i16_shl_:
+; R1-LABEL: shift1_v2i16_shl_:
 ; R1: shll.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
 
 define { i32 } @shift1_v2i16_shl_(i32 %a0.coerce) {
@@ -140,7 +140,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v2i16_sra_:
+; R1-LABEL: shift1_v2i16_sra_:
 ; R1: shra.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
 
 define { i32 } @shift1_v2i16_sra_(i32 %a0.coerce) {
@@ -152,9 +152,9 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v2ui16_srl_:
+; R1-LABEL: shift1_v2ui16_srl_:
 ; R1-NOT: shrl.ph
-; R2: shift1_v2ui16_srl_:
+; R2-LABEL: shift1_v2ui16_srl_:
 ; R2: shrl.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
 
 define { i32 } @shift1_v2ui16_srl_(i32 %a0.coerce) {
@@ -166,7 +166,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v4i8_shl_:
+; R1-LABEL: shift1_v4i8_shl_:
 ; R1: shll.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
 
 define { i32 } @shift1_v4i8_shl_(i32 %a0.coerce) {
@@ -178,9 +178,9 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v4i8_sra_:
+; R1-LABEL: shift1_v4i8_sra_:
 ; R1-NOT: shra.qb
-; R2: shift1_v4i8_sra_:
+; R2-LABEL: shift1_v4i8_sra_:
 ; R2: shra.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
 
 define { i32 } @shift1_v4i8_sra_(i32 %a0.coerce) {
@@ -192,7 +192,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v4ui8_srl_:
+; R1-LABEL: shift1_v4ui8_srl_:
 ; R1: shrl.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
 
 define { i32 } @shift1_v4ui8_srl_(i32 %a0.coerce) {
diff --git a/test/CodeGen/Mips/ex2.ll b/test/CodeGen/Mips/ex2.ll
index 74bdb6c..9f074d1 100644
--- a/test/CodeGen/Mips/ex2.ll
+++ b/test/CodeGen/Mips/ex2.ll
@@ -4,7 +4,7 @@
 @_ZTIPKc = external constant i8*
 
 define i32 @main() {
-; 16: main:
+; 16-LABEL: main:
 ; 16: 	.cfi_startproc
 ; 16: 	save	$ra, $s0, $s1, 32
 ; 16:   .cfi_def_cfa_offset 32
diff --git a/test/CodeGen/Mips/inlineasm-operand-code.ll b/test/CodeGen/Mips/inlineasm-operand-code.ll
index 0197899..7bb4adc 100644
--- a/test/CodeGen/Mips/inlineasm-operand-code.ll
+++ b/test/CodeGen/Mips/inlineasm-operand-code.ll
@@ -10,7 +10,7 @@
 ; X with -3
 define i32 @constraint_X() nounwind {
 entry:
-;CHECK_LITTLE_32:   constraint_X:
+;CHECK_LITTLE_32-LABEL:   constraint_X:
 ;CHECK_LITTLE_32: #APP
 ;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd
 ;CHECK_LITTLE_32: #NO_APP
@@ -21,7 +21,7 @@ entry:
 ; x with -3
 define i32 @constraint_x() nounwind {
 entry:
-;CHECK_LITTLE_32:   constraint_x:
+;CHECK_LITTLE_32-LABEL:   constraint_x:
 ;CHECK_LITTLE_32: #APP
 ;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},0xfffd
 ;CHECK_LITTLE_32: #NO_APP
@@ -32,7 +32,7 @@ entry:
 ; d with -3
 define i32 @constraint_d() nounwind {
 entry:
-;CHECK_LITTLE_32:   constraint_d:
+;CHECK_LITTLE_32-LABEL:   constraint_d:
 ;CHECK_LITTLE_32:   #APP
 ;CHECK_LITTLE_32:   addi ${{[0-9]+}},${{[0-9]+}},-3
 ;CHECK_LITTLE_32:   #NO_APP
@@ -43,7 +43,7 @@ entry:
 ; m with -3
 define i32 @constraint_m() nounwind {
 entry:
-;CHECK_LITTLE_32:   constraint_m:
+;CHECK_LITTLE_32-LABEL:   constraint_m:
 ;CHECK_LITTLE_32:   #APP
 ;CHECK_LITTLE_32:   addi ${{[0-9]+}},${{[0-9]+}},-4
 ;CHECK_LITTLE_32:   #NO_APP
@@ -54,7 +54,7 @@ entry:
 ; z with -3
 define i32 @constraint_z() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_z:
+;CHECK_LITTLE_32-LABEL: constraint_z:
 ;CHECK_LITTLE_32:    #APP
 ;CHECK_LITTLE_32:    addi ${{[0-9]+}},${{[0-9]+}},-3
 ;CHECK_LITTLE_32:    #NO_APP
@@ -71,7 +71,7 @@ entry:
 ; a long long in 32 bit mode (use to assert)
 define i32 @constraint_longlong() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_longlong:
+;CHECK_LITTLE_32-LABEL: constraint_longlong:
 ;CHECK_LITTLE_32:    #APP
 ;CHECK_LITTLE_32:    addi ${{[0-9]+}},${{[0-9]+}},3
 ;CHECK_LITTLE_32:    #NO_APP
@@ -82,7 +82,7 @@ entry:
 ; D, in little endian the source reg will be 4 bytes into the long long
 define i32 @constraint_D() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_D:
+;CHECK_LITTLE_32-LABEL: constraint_D:
 ;CHECK_LITTLE_32:    lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_LITTLE_32:    lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_LITTLE_32:    lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -91,7 +91,7 @@ entry:
 ;CHECK_LITTLE_32:    #NO_APP
 
 ; D, in big endian the source reg will also be 4 bytes into the long long
-;CHECK_BIG_32:    constraint_D:
+;CHECK_BIG_32-LABEL:    constraint_D:
 ;CHECK_BIG_32:       lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_BIG_32:       lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_BIG_32:       lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -107,7 +107,7 @@ entry:
 ; L, in little endian the source reg will be 0 bytes into the long long
 define i32 @constraint_L() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_L:
+;CHECK_LITTLE_32-LABEL: constraint_L:
 ;CHECK_LITTLE_32:    lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_LITTLE_32:    lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_LITTLE_32:    lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -115,7 +115,7 @@ entry:
 ;CHECK_LITTLE_32:    or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
 ;CHECK_LITTLE_32:    #NO_APP
 ; L, in big endian the source reg will be 4 bytes into the long long
-;CHECK_BIG_32: constraint_L:
+;CHECK_BIG_32-LABEL: constraint_L:
 ;CHECK_BIG_32:       lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_BIG_32:       lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_BIG_32:       lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -131,7 +131,7 @@ entry:
 ; M, in little endian the source reg will be 4 bytes into the long long
 define i32 @constraint_M() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_M:
+;CHECK_LITTLE_32-LABEL: constraint_M:
 ;CHECK_LITTLE_32:    lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_LITTLE_32:    lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_LITTLE_32:    lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -139,7 +139,7 @@ entry:
 ;CHECK_LITTLE_32:    or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
 ;CHECK_LITTLE_32:    #NO_APP
 ; M, in big endian the source reg will be 0 bytes into the long long
-;CHECK_BIG_32:    constraint_M:
+;CHECK_BIG_32-LABEL:    constraint_M:
 ;CHECK_BIG_32:       lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_BIG_32:       lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_BIG_32:       lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/largefr1.ll b/test/CodeGen/Mips/largefr1.ll
index 0fe89f7..6c417d8 100644
--- a/test/CodeGen/Mips/largefr1.ll
+++ b/test/CodeGen/Mips/largefr1.ll
@@ -22,7 +22,7 @@ entry:
 
 define i32 @main() nounwind {
 entry:
-; 1: main: 
+; 1-LABEL: main:
 ; 1: 1: 	.word	-797992
 ; 1:            li ${{[0-9]+}}, 12
 ; 1:            sll ${{[0-9]+}}, ${{[0-9]+}}, 16
diff --git a/test/CodeGen/Mips/mips16fpe.ll b/test/CodeGen/Mips/mips16fpe.ll
index 4335436..10c5163 100644
--- a/test/CodeGen/Mips/mips16fpe.ll
+++ b/test/CodeGen/Mips/mips16fpe.ll
@@ -41,7 +41,7 @@
 
 define void @test_addsf3() nounwind {
 entry:
-;16hf: test_addsf3:
+;16hf-LABEL: test_addsf3:
   %0 = load float* @x, align 4
   %1 = load float* @y, align 4
   %add = fadd float %0, %1
@@ -52,7 +52,7 @@ entry:
 
 define void @test_adddf3() nounwind {
 entry:
-;16hf: test_adddf3:
+;16hf-LABEL: test_adddf3:
   %0 = load double* @xd, align 8
   %1 = load double* @yd, align 8
   %add = fadd double %0, %1
@@ -63,7 +63,7 @@ entry:
 
 define void @test_subsf3() nounwind {
 entry:
-;16hf: test_subsf3:
+;16hf-LABEL: test_subsf3:
   %0 = load float* @x, align 4
   %1 = load float* @y, align 4
   %sub = fsub float %0, %1
@@ -74,7 +74,7 @@ entry:
 
 define void @test_subdf3() nounwind {
 entry:
-;16hf: test_subdf3:
+;16hf-LABEL: test_subdf3:
   %0 = load double* @xd, align 8
   %1 = load double* @yd, align 8
   %sub = fsub double %0, %1
@@ -85,7 +85,7 @@ entry:
 
 define void @test_mulsf3() nounwind {
 entry:
-;16hf: test_mulsf3:
+;16hf-LABEL: test_mulsf3:
   %0 = load float* @x, align 4
   %1 = load float* @y, align 4
   %mul = fmul float %0, %1
@@ -96,7 +96,7 @@ entry:
 
 define void @test_muldf3() nounwind {
 entry:
-;16hf: test_muldf3:
+;16hf-LABEL: test_muldf3:
   %0 = load double* @xd, align 8
   %1 = load double* @yd, align 8
   %mul = fmul double %0, %1
@@ -107,7 +107,7 @@ entry:
 
 define void @test_divsf3() nounwind {
 entry:
-;16hf: test_divsf3:
+;16hf-LABEL: test_divsf3:
   %0 = load float* @y, align 4
   %1 = load float* @x, align 4
   %div = fdiv float %0, %1
@@ -118,7 +118,7 @@ entry:
 
 define void @test_divdf3() nounwind {
 entry:
-;16hf: test_divdf3:
+;16hf-LABEL: test_divdf3:
   %0 = load double* @yd, align 8
   %mul = fmul double %0, 2.000000e+00
   %1 = load double* @xd, align 8
@@ -130,7 +130,7 @@ entry:
 
 define void @test_extendsfdf2() nounwind {
 entry:
-;16hf: test_extendsfdf2:
+;16hf-LABEL: test_extendsfdf2:
   %0 = load float* @x, align 4
   %conv = fpext float %0 to double
   store double %conv, double* @extendsfdf2_result, align 8
@@ -140,7 +140,7 @@ entry:
 
 define void @test_truncdfsf2() nounwind {
 entry:
-;16hf: test_truncdfsf2:
+;16hf-LABEL: test_truncdfsf2:
   %0 = load double* @xd2, align 8
   %conv = fptrunc double %0 to float
   store float %conv, float* @truncdfsf2_result, align 4
@@ -150,7 +150,7 @@ entry:
 
 define void @test_fix_truncsfsi() nounwind {
 entry:
-;16hf: test_fix_truncsfsi:
+;16hf-LABEL: test_fix_truncsfsi:
   %0 = load float* @x, align 4
   %conv = fptosi float %0 to i32
   store i32 %conv, i32* @fix_truncsfsi_result, align 4
@@ -160,7 +160,7 @@ entry:
 
 define void @test_fix_truncdfsi() nounwind {
 entry:
-;16hf: test_fix_truncdfsi:
+;16hf-LABEL: test_fix_truncdfsi:
   %0 = load double* @xd, align 8
   %conv = fptosi double %0 to i32
   store i32 %conv, i32* @fix_truncdfsi_result, align 4
@@ -170,7 +170,7 @@ entry:
 
 define void @test_floatsisf() nounwind {
 entry:
-;16hf: test_floatsisf:
+;16hf-LABEL: test_floatsisf:
   %0 = load i32* @si, align 4
   %conv = sitofp i32 %0 to float
   store float %conv, float* @floatsisf_result, align 4
@@ -180,7 +180,7 @@ entry:
 
 define void @test_floatsidf() nounwind {
 entry:
-;16hf: test_floatsidf:
+;16hf-LABEL: test_floatsidf:
   %0 = load i32* @si, align 4
   %conv = sitofp i32 %0 to double
   store double %conv, double* @floatsidf_result, align 8
@@ -190,7 +190,7 @@ entry:
 
 define void @test_floatunsisf() nounwind {
 entry:
-;16hf: test_floatunsisf:
+;16hf-LABEL: test_floatunsisf:
   %0 = load i32* @ui, align 4
   %conv = uitofp i32 %0 to float
   store float %conv, float* @floatunsisf_result, align 4
@@ -200,7 +200,7 @@ entry:
 
 define void @test_floatunsidf() nounwind {
 entry:
-;16hf: test_floatunsidf:
+;16hf-LABEL: test_floatunsidf:
   %0 = load i32* @ui, align 4
   %conv = uitofp i32 %0 to double
   store double %conv, double* @floatunsidf_result, align 8
@@ -210,7 +210,7 @@ entry:
 
 define void @test_eqsf2() nounwind {
 entry:
-;16hf: test_eqsf2:
+;16hf-LABEL: test_eqsf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %cmp = fcmp oeq float %0, %1
@@ -222,7 +222,7 @@ entry:
 
 define void @test_eqdf2() nounwind {
 entry:
-;16hf: test_eqdf2:
+;16hf-LABEL: test_eqdf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %cmp = fcmp oeq double %0, %1
@@ -234,7 +234,7 @@ entry:
 
 define void @test_nesf2() nounwind {
 entry:
-;16hf: test_nesf2:
+;16hf-LABEL: test_nesf2:
   %0 = load float* @x, align 4
   %1 = load float* @y, align 4
   %cmp = fcmp une float %0, %1
@@ -246,7 +246,7 @@ entry:
 
 define void @test_nedf2() nounwind {
 entry:
-;16hf: test_nedf2:
+;16hf-LABEL: test_nedf2:
   %0 = load double* @xd, align 8
   %1 = load double* @yd, align 8
   %cmp = fcmp une double %0, %1
@@ -258,7 +258,7 @@ entry:
 
 define void @test_gesf2() nounwind {
 entry:
-;16hf: test_gesf2:
+;16hf-LABEL: test_gesf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %cmp = fcmp oge float %0, %1
@@ -273,7 +273,7 @@ entry:
 
 define void @test_gedf2() nounwind {
 entry:
-;16hf: test_gedf2:
+;16hf-LABEL: test_gedf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %cmp = fcmp oge double %0, %1
@@ -288,7 +288,7 @@ entry:
 
 define void @test_ltsf2() nounwind {
 entry:
-;16hf: test_ltsf2:
+;16hf-LABEL: test_ltsf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %lnot = fcmp uge float %0, %1
@@ -304,7 +304,7 @@ entry:
 
 define void @test_ltdf2() nounwind {
 entry:
-;16hf: test_ltdf2:
+;16hf-LABEL: test_ltdf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %lnot = fcmp uge double %0, %1
@@ -320,7 +320,7 @@ entry:
 
 define void @test_lesf2() nounwind {
 entry:
-;16hf: test_lesf2:
+;16hf-LABEL: test_lesf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %cmp = fcmp ole float %0, %1
@@ -335,7 +335,7 @@ entry:
 
 define void @test_ledf2() nounwind {
 entry:
-;16hf: test_ledf2:
+;16hf-LABEL: test_ledf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %cmp = fcmp ole double %0, %1
@@ -350,7 +350,7 @@ entry:
 
 define void @test_gtsf2() nounwind {
 entry:
-;16hf: test_gtsf2:
+;16hf-LABEL: test_gtsf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %lnot = fcmp ule float %0, %1
@@ -365,7 +365,7 @@ entry:
 
 define void @test_gtdf2() nounwind {
 entry:
-;16hf: test_gtdf2:
+;16hf-LABEL: test_gtdf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %lnot = fcmp ule double %0, %1
diff --git a/test/CodeGen/Mips/mips64-f128.ll b/test/CodeGen/Mips/mips64-f128.ll
index ab0a3d6..dc8bbfd 100644
--- a/test/CodeGen/Mips/mips64-f128.ll
+++ b/test/CodeGen/Mips/mips64-f128.ll
@@ -7,7 +7,7 @@
 @gf1 = external global float
 @gd1 = external global double
 
-; CHECK: addLD:
+; CHECK-LABEL: addLD:
 ; CHECK: ld $25, %call16(__addtf3)
 
 define fp128 @addLD() {
@@ -18,7 +18,7 @@ entry:
   ret fp128 %add
 }
 
-; CHECK: subLD:
+; CHECK-LABEL: subLD:
 ; CHECK: ld $25, %call16(__subtf3)
 
 define fp128 @subLD() {
@@ -29,7 +29,7 @@ entry:
   ret fp128 %sub
 }
 
-; CHECK: mulLD:
+; CHECK-LABEL: mulLD:
 ; CHECK: ld $25, %call16(__multf3)
 
 define fp128 @mulLD() {
@@ -40,7 +40,7 @@ entry:
   ret fp128 %mul
 }
 
-; CHECK: divLD:
+; CHECK-LABEL: divLD:
 ; CHECK: ld $25, %call16(__divtf3)
 
 define fp128 @divLD() {
@@ -51,7 +51,7 @@ entry:
   ret fp128 %div
 }
 
-; CHECK: conv_LD_char:
+; CHECK-LABEL: conv_LD_char:
 ; CHECK: ld $25, %call16(__floatsitf)
 
 define fp128 @conv_LD_char(i8 signext %a) {
@@ -60,7 +60,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_short:
+; CHECK-LABEL: conv_LD_short:
 ; CHECK: ld $25, %call16(__floatsitf)
 
 define fp128 @conv_LD_short(i16 signext %a) {
@@ -69,7 +69,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_int:
+; CHECK-LABEL: conv_LD_int:
 ; CHECK: ld $25, %call16(__floatsitf)
 
 define fp128 @conv_LD_int(i32 %a) {
@@ -78,7 +78,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_LL:
+; CHECK-LABEL: conv_LD_LL:
 ; CHECK: ld $25, %call16(__floatditf)
 
 define fp128 @conv_LD_LL(i64 %a) {
@@ -87,7 +87,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_UChar:
+; CHECK-LABEL: conv_LD_UChar:
 ; CHECK: ld $25, %call16(__floatunsitf)
 
 define fp128 @conv_LD_UChar(i8 zeroext %a) {
@@ -96,7 +96,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_UShort:
+; CHECK-LABEL: conv_LD_UShort:
 ; CHECK: ld $25, %call16(__floatunsitf)
 
 define fp128 @conv_LD_UShort(i16 zeroext %a) {
@@ -105,7 +105,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_UInt:
+; CHECK-LABEL: conv_LD_UInt:
 ; CHECK: ld $25, %call16(__floatunsitf)
 
 define fp128 @conv_LD_UInt(i32 %a) {
@@ -114,7 +114,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_ULL:
+; CHECK-LABEL: conv_LD_ULL:
 ; CHECK: ld $25, %call16(__floatunditf)
 
 define fp128 @conv_LD_ULL(i64 %a) {
@@ -123,7 +123,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_char_LD:
+; CHECK-LABEL: conv_char_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define signext i8 @conv_char_LD(fp128 %a) {
@@ -132,7 +132,7 @@ entry:
   ret i8 %conv
 }
 
-; CHECK: conv_short_LD:
+; CHECK-LABEL: conv_short_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define signext i16 @conv_short_LD(fp128 %a) {
@@ -141,7 +141,7 @@ entry:
   ret i16 %conv
 }
 
-; CHECK: conv_int_LD:
+; CHECK-LABEL: conv_int_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define i32 @conv_int_LD(fp128 %a) {
@@ -150,7 +150,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: conv_LL_LD:
+; CHECK-LABEL: conv_LL_LD:
 ; CHECK: ld $25, %call16(__fixtfdi)
 
 define i64 @conv_LL_LD(fp128 %a) {
@@ -159,7 +159,7 @@ entry:
   ret i64 %conv
 }
 
-; CHECK: conv_UChar_LD:
+; CHECK-LABEL: conv_UChar_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define zeroext i8 @conv_UChar_LD(fp128 %a) {
@@ -168,7 +168,7 @@ entry:
   ret i8 %conv
 }
 
-; CHECK: conv_UShort_LD:
+; CHECK-LABEL: conv_UShort_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define zeroext i16 @conv_UShort_LD(fp128 %a) {
@@ -177,7 +177,7 @@ entry:
   ret i16 %conv
 }
 
-; CHECK: conv_UInt_LD:
+; CHECK-LABEL: conv_UInt_LD:
 ; CHECK: ld $25, %call16(__fixunstfsi)
 
 define i32 @conv_UInt_LD(fp128 %a) {
@@ -186,7 +186,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: conv_ULL_LD:
+; CHECK-LABEL: conv_ULL_LD:
 ; CHECK: ld $25, %call16(__fixunstfdi)
 
 define i64 @conv_ULL_LD(fp128 %a) {
@@ -195,7 +195,7 @@ entry:
   ret i64 %conv
 }
 
-; CHECK: conv_LD_float:
+; CHECK-LABEL: conv_LD_float:
 ; CHECK: ld $25, %call16(__extendsftf2)
 
 define fp128 @conv_LD_float(float %a) {
@@ -204,7 +204,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_double:
+; CHECK-LABEL: conv_LD_double:
 ; CHECK: ld $25, %call16(__extenddftf2)
 
 define fp128 @conv_LD_double(double %a) {
@@ -213,7 +213,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_float_LD:
+; CHECK-LABEL: conv_float_LD:
 ; CHECK: ld $25, %call16(__trunctfsf2)
 
 define float @conv_float_LD(fp128 %a) {
@@ -222,7 +222,7 @@ entry:
   ret float %conv
 }
 
-; CHECK: conv_double_LD:
+; CHECK-LABEL: conv_double_LD:
 ; CHECK: ld $25, %call16(__trunctfdf2)
 
 define double @conv_double_LD(fp128 %a) {
@@ -231,7 +231,7 @@ entry:
   ret double %conv
 }
 
-; CHECK:             libcall1_fabsl:
+; CHECK-LABEL:             libcall1_fabsl:
 ; CHECK-DAG: ld      $[[R0:[0-9]+]], 8($[[R4:[0-9]+]])
 ; CHECK-DAG: daddiu  $[[R1:[0-9]+]], $zero, 1
 ; CHECK-DAG: dsll    $[[R2:[0-9]+]], $[[R1]], 63
@@ -248,7 +248,7 @@ entry:
 
 declare fp128 @fabsl(fp128) #1
 
-; CHECK: libcall1_ceill:
+; CHECK-LABEL: libcall1_ceill:
 ; CHECK: ld $25, %call16(ceill)
 
 define fp128 @libcall1_ceill() {
@@ -260,7 +260,7 @@ entry:
 
 declare fp128 @ceill(fp128) #1
 
-; CHECK: libcall1_sinl:
+; CHECK-LABEL: libcall1_sinl:
 ; CHECK: ld $25, %call16(sinl)
 
 define fp128 @libcall1_sinl() {
@@ -272,7 +272,7 @@ entry:
 
 declare fp128 @sinl(fp128) #2
 
-; CHECK: libcall1_cosl:
+; CHECK-LABEL: libcall1_cosl:
 ; CHECK: ld $25, %call16(cosl)
 
 define fp128 @libcall1_cosl() {
@@ -284,7 +284,7 @@ entry:
 
 declare fp128 @cosl(fp128) #2
 
-; CHECK: libcall1_expl:
+; CHECK-LABEL: libcall1_expl:
 ; CHECK: ld $25, %call16(expl)
 
 define fp128 @libcall1_expl() {
@@ -296,7 +296,7 @@ entry:
 
 declare fp128 @expl(fp128) #2
 
-; CHECK: libcall1_exp2l:
+; CHECK-LABEL: libcall1_exp2l:
 ; CHECK: ld $25, %call16(exp2l)
 
 define fp128 @libcall1_exp2l() {
@@ -308,7 +308,7 @@ entry:
 
 declare fp128 @exp2l(fp128) #2
 
-; CHECK: libcall1_logl:
+; CHECK-LABEL: libcall1_logl:
 ; CHECK: ld $25, %call16(logl)
 
 define fp128 @libcall1_logl() {
@@ -320,7 +320,7 @@ entry:
 
 declare fp128 @logl(fp128) #2
 
-; CHECK: libcall1_log2l:
+; CHECK-LABEL: libcall1_log2l:
 ; CHECK: ld $25, %call16(log2l)
 
 define fp128 @libcall1_log2l() {
@@ -332,7 +332,7 @@ entry:
 
 declare fp128 @log2l(fp128) #2
 
-; CHECK: libcall1_log10l:
+; CHECK-LABEL: libcall1_log10l:
 ; CHECK: ld $25, %call16(log10l)
 
 define fp128 @libcall1_log10l() {
@@ -344,7 +344,7 @@ entry:
 
 declare fp128 @log10l(fp128) #2
 
-; CHECK: libcall1_nearbyintl:
+; CHECK-LABEL: libcall1_nearbyintl:
 ; CHECK: ld $25, %call16(nearbyintl)
 
 define fp128 @libcall1_nearbyintl() {
@@ -356,7 +356,7 @@ entry:
 
 declare fp128 @nearbyintl(fp128) #1
 
-; CHECK: libcall1_floorl:
+; CHECK-LABEL: libcall1_floorl:
 ; CHECK: ld $25, %call16(floorl)
 
 define fp128 @libcall1_floorl() {
@@ -368,7 +368,7 @@ entry:
 
 declare fp128 @floorl(fp128) #1
 
-; CHECK: libcall1_sqrtl:
+; CHECK-LABEL: libcall1_sqrtl:
 ; CHECK: ld $25, %call16(sqrtl)
 
 define fp128 @libcall1_sqrtl() {
@@ -380,7 +380,7 @@ entry:
 
 declare fp128 @sqrtl(fp128) #2
 
-; CHECK: libcall1_rintl:
+; CHECK-LABEL: libcall1_rintl:
 ; CHECK: ld $25, %call16(rintl)
 
 define fp128 @libcall1_rintl() {
@@ -392,7 +392,7 @@ entry:
 
 declare fp128 @rintl(fp128) #1
 
-; CHECK: libcall_powil:
+; CHECK-LABEL: libcall_powil:
 ; CHECK: ld $25, %call16(__powitf2)
 
 define fp128 @libcall_powil(fp128 %a, i32 %b) {
@@ -403,7 +403,7 @@ entry:
 
 declare fp128 @llvm.powi.f128(fp128, i32) #3
 
-; CHECK:     libcall2_copysignl:
+; CHECK-LABEL:     libcall2_copysignl:
 ; CHECK-DAG: daddiu $[[R2:[0-9]+]], $zero, 1
 ; CHECK-DAG: dsll   $[[R3:[0-9]+]], $[[R2]], 63
 ; CHECK-DAG: ld     $[[R0:[0-9]+]], %got_disp(gld1)
@@ -426,7 +426,7 @@ entry:
 
 declare fp128 @copysignl(fp128, fp128) #1
 
-; CHECK: libcall2_powl:
+; CHECK-LABEL: libcall2_powl:
 ; CHECK: ld $25, %call16(powl)
 
 define fp128 @libcall2_powl() {
@@ -439,7 +439,7 @@ entry:
 
 declare fp128 @powl(fp128, fp128) #2
 
-; CHECK: libcall2_fmodl:
+; CHECK-LABEL: libcall2_fmodl:
 ; CHECK: ld $25, %call16(fmodl)
 
 define fp128 @libcall2_fmodl() {
@@ -452,7 +452,7 @@ entry:
 
 declare fp128 @fmodl(fp128, fp128) #2
 
-; CHECK: libcall3_fmal:
+; CHECK-LABEL: libcall3_fmal:
 ; CHECK: ld $25, %call16(fmal)
 
 define fp128 @libcall3_fmal() {
@@ -466,7 +466,7 @@ entry:
 
 declare fp128 @llvm.fma.f128(fp128, fp128, fp128) #4
 
-; CHECK: cmp_lt:
+; CHECK-LABEL: cmp_lt:
 ; CHECK: ld $25, %call16(__lttf2)
 
 define i32 @cmp_lt(fp128 %a, fp128 %b) {
@@ -476,7 +476,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_le:
+; CHECK-LABEL: cmp_le:
 ; CHECK: ld $25, %call16(__letf2)
 
 define i32 @cmp_le(fp128 %a, fp128 %b) {
@@ -486,7 +486,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_gt:
+; CHECK-LABEL: cmp_gt:
 ; CHECK: ld $25, %call16(__gttf2)
 
 define i32 @cmp_gt(fp128 %a, fp128 %b) {
@@ -496,7 +496,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_ge:
+; CHECK-LABEL: cmp_ge:
 ; CHECK: ld $25, %call16(__getf2)
 
 define i32 @cmp_ge(fp128 %a, fp128 %b) {
@@ -506,7 +506,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_eq:
+; CHECK-LABEL: cmp_eq:
 ; CHECK: ld $25, %call16(__eqtf2)
 
 define i32 @cmp_eq(fp128 %a, fp128 %b) {
@@ -516,7 +516,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_ne:
+; CHECK-LABEL: cmp_ne:
 ; CHECK: ld $25, %call16(__netf2)
 
 define i32 @cmp_ne(fp128 %a, fp128 %b) {
@@ -526,7 +526,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: load_LD_LD:
+; CHECK-LABEL: load_LD_LD:
 ; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1)
 ; CHECK: ld $2, 0($[[R0]])
 ; CHECK: ld $4, 8($[[R0]])
@@ -537,7 +537,7 @@ entry:
   ret fp128 %0
 }
 
-; CHECK: load_LD_float:
+; CHECK-LABEL: load_LD_float:
 ; CHECK: ld   $[[R0:[0-9]+]], %got_disp(gf1)
 ; CHECK: lw   $4, 0($[[R0]])
 ; CHECK: ld   $25, %call16(__extendsftf2)
@@ -550,7 +550,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: load_LD_double:
+; CHECK-LABEL: load_LD_double:
 ; CHECK: ld   $[[R0:[0-9]+]], %got_disp(gd1)
 ; CHECK: ld   $4, 0($[[R0]])
 ; CHECK: ld   $25, %call16(__extenddftf2)
@@ -563,7 +563,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: store_LD_LD:
+; CHECK-LABEL: store_LD_LD:
 ; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1)
 ; CHECK: ld $[[R1:[0-9]+]], 0($[[R0]])
 ; CHECK: ld $[[R2:[0-9]+]], 8($[[R0]])
@@ -578,7 +578,7 @@ entry:
   ret void
 }
 
-; CHECK: store_LD_float:
+; CHECK-LABEL: store_LD_float:
 ; CHECK: ld   $[[R0:[0-9]+]], %got_disp(gld1)
 ; CHECK: ld   $4, 0($[[R0]])
 ; CHECK: ld   $5, 8($[[R0]])
@@ -595,7 +595,7 @@ entry:
   ret void
 }
 
-; CHECK: store_LD_double:
+; CHECK-LABEL: store_LD_double:
 ; CHECK: ld   $[[R0:[0-9]+]], %got_disp(gld1)
 ; CHECK: ld   $4, 0($[[R0]])
 ; CHECK: ld   $5, 8($[[R0]])
@@ -612,7 +612,7 @@ entry:
   ret void
 }
 
-; CHECK: select_LD:
+; CHECK-LABEL: select_LD:
 ; CHECK: movn $8, $6, $4
 ; CHECK: movn $9, $7, $4
 ; CHECK: move $2, $8
@@ -625,7 +625,7 @@ entry:
   ret fp128 %cond
 }
 
-; CHECK: selectCC_LD:
+; CHECK-LABEL: selectCC_LD:
 ; CHECK: move $[[R0:[0-9]+]], $11
 ; CHECK: move $[[R1:[0-9]+]], $10
 ; CHECK: move $[[R2:[0-9]+]], $9
diff --git a/test/CodeGen/Mips/mips64-libcall.ll b/test/CodeGen/Mips/mips64-libcall.ll
index d54598b..290baaf 100644
--- a/test/CodeGen/Mips/mips64-libcall.ll
+++ b/test/CodeGen/Mips/mips64-libcall.ll
@@ -5,7 +5,7 @@
 
 ; Check that %add is not passed in an integer register.
 ;
-; HARD: callfloor:
+; HARD-LABEL: callfloor:
 ; HARD-NOT: dmfc1 $4
 
 define double @callfloor(double %d) nounwind readnone {
@@ -19,7 +19,7 @@ declare double @floor(double) nounwind readnone
 
 ; Check call16.
 ;
-; SOFT: f64add:
+; SOFT-LABEL: f64add:
 ; SOFT: ld $25, %call16(__adddf3)
 
 define double @f64add(double %a, double %b) {
diff --git a/test/CodeGen/Mips/mips64instrs.ll b/test/CodeGen/Mips/mips64instrs.ll
index 2e3df3a..7b06c2d 100644
--- a/test/CodeGen/Mips/mips64instrs.ll
+++ b/test/CodeGen/Mips/mips64instrs.ll
@@ -86,7 +86,7 @@ entry:
 
 define i64 @f14(i64 %a, i64 %b) nounwind readnone {
 entry:
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; CHECK: teq $[[R0]], $zero, 7
 ; CHECK: mflo
@@ -96,7 +96,7 @@ entry:
 
 define i64 @f15(i64 %a, i64 %b) nounwind readnone {
 entry:
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; CHECK: teq $[[R0]], $zero, 7
 ; CHECK: mflo
@@ -106,7 +106,7 @@ entry:
 
 define i64 @f16(i64 %a, i64 %b) nounwind readnone {
 entry:
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; CHECK: teq $[[R0]], $zero, 7
 ; CHECK: mfhi
@@ -116,7 +116,7 @@ entry:
 
 define i64 @f17(i64 %a, i64 %b) nounwind readnone {
 entry:
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; CHECK: teq $[[R0]], $zero, 7
 ; CHECK: mfhi
diff --git a/test/CodeGen/Mips/misha.ll b/test/CodeGen/Mips/misha.ll
index 80637ed..65d3b7b 100644
--- a/test/CodeGen/Mips/misha.ll
+++ b/test/CodeGen/Mips/misha.ll
@@ -25,10 +25,10 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %inc = add nsw i32 %i.010, 1
   %cmp = icmp eq i32 %inc, %conv
   br i1 %cmp, label %for.end, label %for.body
-; 16: sumc:
+; 16-LABEL: sumc:
 ; 16: 	lbu	${{[0-9]+}}, 0(${{[0-9]+}})
 ; 16: 	lbu	${{[0-9]+}}, 0(${{[0-9]+}})
-; 16: sum:
+; 16-LABEL: sum:
 ; 16: 	lhu	${{[0-9]+}}, 0(${{[0-9]+}})
 ; 16: 	lhu	${{[0-9]+}}, 0(${{[0-9]+}})
 
diff --git a/test/CodeGen/Mips/mno-ldc1-sdc1.ll b/test/CodeGen/Mips/mno-ldc1-sdc1.ll
index eae9a22..be9d0b6 100644
--- a/test/CodeGen/Mips/mno-ldc1-sdc1.ll
+++ b/test/CodeGen/Mips/mno-ldc1-sdc1.ll
@@ -8,16 +8,16 @@
 
 @g0 = common global double 0.000000e+00, align 8
 
-; LE-PIC: test_ldc1:
+; LE-PIC-LABEL: test_ldc1:
 ; LE-PIC: lwc1 $f0, 0(${{[0-9]+}})
 ; LE-PIC: lwc1 $f1, 4(${{[0-9]+}})
-; LE-STATIC: test_ldc1:
+; LE-STATIC-LABEL: test_ldc1:
 ; LE-STATIC: lwc1 $f0, %lo(g0)(${{[0-9]+}})
 ; LE-STATIC: lwc1 $f1, %lo(g0+4)(${{[0-9]+}})
-; BE-PIC: test_ldc1:
+; BE-PIC-LABEL: test_ldc1:
 ; BE-PIC: lwc1 $f1, 0(${{[0-9]+}})
 ; BE-PIC: lwc1 $f0, 4(${{[0-9]+}})
-; CHECK-LDC1-SDC1: test_ldc1:
+; CHECK-LDC1-SDC1-LABEL: test_ldc1:
 ; CHECK-LDC1-SDC1: ldc1 $f{{[0-9]+}}
 
 define double @test_ldc1() {
@@ -26,16 +26,16 @@ entry:
   ret double %0
 }
 
-; LE-PIC: test_sdc1:
+; LE-PIC-LABEL: test_sdc1:
 ; LE-PIC: swc1 $f12, 0(${{[0-9]+}})
 ; LE-PIC: swc1 $f13, 4(${{[0-9]+}})
-; LE-STATIC: test_sdc1:
+; LE-STATIC-LABEL: test_sdc1:
 ; LE-STATIC: swc1 $f12, %lo(g0)(${{[0-9]+}})
 ; LE-STATIC: swc1 $f13, %lo(g0+4)(${{[0-9]+}})
-; BE-PIC: test_sdc1:
+; BE-PIC-LABEL: test_sdc1:
 ; BE-PIC: swc1 $f13, 0(${{[0-9]+}})
 ; BE-PIC: swc1 $f12, 4(${{[0-9]+}})
-; CHECK-LDC1-SDC1: test_sdc1:
+; CHECK-LDC1-SDC1-LABEL: test_sdc1:
 ; CHECK-LDC1-SDC1: sdc1 $f{{[0-9]+}}
 
 define void @test_sdc1(double %a) {
diff --git a/test/CodeGen/Mips/o32_cc_vararg.ll b/test/CodeGen/Mips/o32_cc_vararg.ll
index 35332b6..10972e8 100644
--- a/test/CodeGen/Mips/o32_cc_vararg.ll
+++ b/test/CodeGen/Mips/o32_cc_vararg.ll
@@ -27,7 +27,7 @@ entry:
   %tmp = load i32* %b, align 4
   ret i32 %tmp
 
-; CHECK: va1:
+; CHECK-LABEL: va1:
 ; CHECK: addiu   $sp, $sp, -16
 ; CHECK: sw      $7, 28($sp)
 ; CHECK: sw      $6, 24($sp)
@@ -53,7 +53,7 @@ entry:
   %tmp = load double* %b, align 8
   ret double %tmp
 
-; CHECK: va2:
+; CHECK-LABEL: va2:
 ; CHECK: addiu   $sp, $sp, -16
 ; CHECK: sw      $7, 28($sp)
 ; CHECK: sw      $6, 24($sp)
@@ -81,7 +81,7 @@ entry:
   %tmp = load i32* %b, align 4
   ret i32 %tmp
 
-; CHECK: va3:
+; CHECK-LABEL: va3:
 ; CHECK: addiu   $sp, $sp, -16
 ; CHECK: sw      $7, 28($sp)
 ; CHECK: sw      $6, 24($sp)
@@ -104,7 +104,7 @@ entry:
   %tmp = load double* %b, align 8
   ret double %tmp
 
-; CHECK: va4:
+; CHECK-LABEL: va4:
 ; CHECK: addiu   $sp, $sp, -24
 ; CHECK: sw      $7, 36($sp)
 ; CHECK: sw      $6, 32($sp)
@@ -132,7 +132,7 @@ entry:
   %tmp = load i32* %d, align 4
   ret i32 %tmp
 
-; CHECK: va5:
+; CHECK-LABEL: va5:
 ; CHECK: addiu   $sp, $sp, -24
 ; CHECK: sw      $7, 36($sp)
 ; CHECK: lw      $2, 36($sp)
@@ -158,7 +158,7 @@ entry:
   %tmp = load double* %d, align 8
   ret double %tmp
 
-; CHECK: va6:
+; CHECK-LABEL: va6:
 ; CHECK: addiu   $sp, $sp, -24
 ; CHECK: sw      $7, 36($sp)
 ; CHECK: addiu   $[[R0:[0-9]+]], $sp, 36
@@ -186,7 +186,7 @@ entry:
   %tmp = load i32* %c, align 4
   ret i32 %tmp
 
-; CHECK: va7:
+; CHECK-LABEL: va7:
 ; CHECK: addiu   $sp, $sp, -24
 ; CHECK: lw      $2, 40($sp)
 }
@@ -209,7 +209,7 @@ entry:
   %tmp = load double* %c, align 8
   ret double %tmp
 
-; CHECK: va8:
+; CHECK-LABEL: va8:
 ; CHECK: addiu   $sp, $sp, -32
 ; CHECK: addiu   ${{[0-9]+}}, $sp, 48
 ; CHECK: ldc1    $f0, 48($sp)
@@ -235,7 +235,7 @@ entry:
   %tmp = load i32* %d, align 4
   ret i32 %tmp
 
-; CHECK: va9:
+; CHECK-LABEL: va9:
 ; CHECK: addiu   $sp, $sp, -32
 ; CHECK: lw      $2, 52($sp)
 }
@@ -260,7 +260,7 @@ entry:
   %tmp = load double* %d, align 8
   ret double %tmp
 
-; CHECK: va10:
+; CHECK-LABEL: va10:
 ; CHECK: addiu   $sp, $sp, -32
 ; CHECK: addiu   $[[R0:[0-9]+]], $sp, 52
 ; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
diff --git a/test/CodeGen/Mips/private.ll b/test/CodeGen/Mips/private.ll
index d1a67fd..058db0b 100644
--- a/test/CodeGen/Mips/private.ll
+++ b/test/CodeGen/Mips/private.ll
@@ -3,14 +3,14 @@
 ; RUN: llc -march=mips < %s | FileCheck %s
 
 define private void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
   ret void
 }
 
 @baz = private global i32 4
 
 define i32 @bar() {
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: call16($foo)
 ; CHECK: lw $[[R0:[0-9]+]], %got($baz)($
 ; CHECK: lw ${{[0-9]+}}, %lo($baz)($[[R0]])
diff --git a/test/CodeGen/Mips/return-vector.ll b/test/CodeGen/Mips/return-vector.ll
index 6bb9523..0e0d515 100644
--- a/test/CodeGen/Mips/return-vector.ll
+++ b/test/CodeGen/Mips/return-vector.ll
@@ -30,7 +30,7 @@ entry:
   %add7 = add i32 %add5, %add6
   ret i32 %add7
 
-; CHECK:        call_i8:
+; CHECK-LABEL:        call_i8:
 ; CHECK:        call16(i8)
 ; CHECK:        addiu   $4, $sp, 32
 ; CHECK:        lw      $[[R0:[a-z0-9]+]], 60($sp)
@@ -56,7 +56,7 @@ entry:
   %add3 = fadd float %add1, %add2
   ret float %add3
 
-; CHECK:        call_f4:
+; CHECK-LABEL:        call_f4:
 ; CHECK:        call16(f4)
 ; CHECK:        addiu   $4, $sp, 16
 ; CHECK:        lwc1    $[[R0:[a-z0-9]+]], 28($sp)
@@ -78,7 +78,7 @@ entry:
   %add3 = fadd double %add1, %add2
   ret double %add3
 
-; CHECK:        call_d4:
+; CHECK-LABEL:        call_d4:
 ; CHECK:        call16(d4)
 ; CHECK:        addiu   $4, $sp, 32
 ; CHECK:        ldc1    $[[R0:[a-z0-9]+]], 56($sp)
@@ -109,7 +109,7 @@ entry:
   %add3 = add i32 %add1, %add2
   ret i32 %add3
 
-; CHECK:        call_i4:
+; CHECK-LABEL:        call_i4:
 ; CHECK:        call16(i4)
 ; CHECK-NOT:    lw
 ; CHECK:        addu    $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
@@ -126,7 +126,7 @@ entry:
   %add1 = fadd float %v0, %v1
   ret float %add1
 
-; CHECK:        call_f2:
+; CHECK-LABEL:        call_f2:
 ; CHECK:        call16(f2)
 ; CHECK-NOT:    lwc1
 ; CHECK:        add.s    $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
@@ -141,7 +141,7 @@ entry:
   %add1 = fadd double %v0, %v1
   ret double %add1
 
-; CHECK:        call_d2:
+; CHECK-LABEL:        call_d2:
 ; CHECK:        call16(d2)
 ; CHECK-NOT:    ldc1
 ; CHECK:        add.d    $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
@@ -158,7 +158,7 @@ define <8 x i32> @return_i8() {
 entry:
   ret <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
 
-; CHECK:        return_i8:
+; CHECK-LABEL:        return_i8:
 ; CHECK:        sw      $[[R0:[a-z0-9]+]], 28($4)
 ; CHECK:        sw      $[[R1:[a-z0-9]+]], 24($4)
 ; CHECK:        sw      $[[R2:[a-z0-9]+]], 20($4)
@@ -178,7 +178,7 @@ entry:
   %vecins4 = insertelement <4 x float> %vecins3, float %d, i32 3
   ret <4 x float> %vecins4
 
-; CHECK:        return_f4:
+; CHECK-LABEL:        return_f4:
 ; CHECK-DAG:    lwc1    $[[R0:[a-z0-9]+]], 16($sp)
 ; CHECK-DAG:    swc1    $[[R0]], 12($4)
 ; CHECK-DAG:    sw      $7, 8($4)
@@ -195,7 +195,7 @@ entry:
   %vecins4 = insertelement <4 x double> %vecins3, double %d, i32 3
   ret <4 x double> %vecins4
 
-; CHECK:            return_d4:
+; CHECK-LABEL:            return_d4:
 ; CHECK-DAG:        sdc1    $[[R0:[a-z0-9]+]], 24($4)
 ; CHECK-DAG:        sdc1    $[[R1:[a-z0-9]+]], 16($4)
 ; CHECK-DAG:        sdc1    $[[R2:[a-z0-9]+]], 8($4)
@@ -212,7 +212,7 @@ define <4 x i32> @return_i4() {
 entry:
   ret <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 
-; CHECK:        return_i4:
+; CHECK-LABEL:        return_i4:
 ; CHECK:        addiu   $2, $zero, 0
 ; CHECK:        addiu   $3, $zero, 1
 ; CHECK:        addiu   $4, $zero, 2
@@ -226,7 +226,7 @@ entry:
   %vecins2 = insertelement <2 x float> %vecins1, float %b, i32 1
   ret <2 x float> %vecins2
 
-; CHECK:        return_f2:
+; CHECK-LABEL:        return_f2:
 ; CHECK:        mov.s   $f0, $f12
 ; CHECK:        mov.s   $f2, $f14
 }
@@ -238,7 +238,7 @@ entry:
   %vecins2 = insertelement <2 x double> %vecins1, double %b, i32 1
   ret <2 x double> %vecins2
 
-; CHECK:        return_d2:
+; CHECK-LABEL:        return_d2:
 ; CHECK:        mov.d   $f0, $f12
 ; CHECK:        mov.d   $f2, $f14
 }
diff --git a/test/CodeGen/Mips/setcc-se.ll b/test/CodeGen/Mips/setcc-se.ll
index 284cd35..50ee860 100644
--- a/test/CodeGen/Mips/setcc-se.ll
+++ b/test/CodeGen/Mips/setcc-se.ll
@@ -2,7 +2,7 @@
 
 @g1 = external global i32
 
-; CHECK: seteq0:
+; CHECK-LABEL: seteq0:
 ; CHECK: sltiu ${{[0-9]+}}, $4, 1
 
 define i32 @seteq0(i32 %a) {
@@ -12,7 +12,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: setne0:
+; CHECK-LABEL: setne0:
 ; CHECK: sltu ${{[0-9]+}}, $zero, $4
 
 define i32 @setne0(i32 %a) {
@@ -22,7 +22,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: slti_beq0:
+; CHECK-LABEL: slti_beq0:
 ; CHECK: slti $[[R0:[0-9]+]], $4, -32768
 ; CHECK: beq $[[R0]], $zero
 
@@ -39,7 +39,7 @@ if.end:
   ret void
 }
 
-; CHECK: slti_beq1:
+; CHECK-LABEL: slti_beq1:
 ; CHECK: slt ${{[0-9]+}}
 
 define void @slti_beq1(i32 %a) {
@@ -55,7 +55,7 @@ if.end:
   ret void
 }
 
-; CHECK: slti_beq2:
+; CHECK-LABEL: slti_beq2:
 ; CHECK: slti $[[R0:[0-9]+]], $4, 32767
 ; CHECK: beq $[[R0]], $zero
 
@@ -72,7 +72,7 @@ if.end:
   ret void
 }
 
-; CHECK: slti_beq3:
+; CHECK-LABEL: slti_beq3:
 ; CHECK: slt ${{[0-9]+}}
 
 define void @slti_beq3(i32 %a) {
@@ -88,7 +88,7 @@ if.end:
   ret void
 }
 
-; CHECK: sltiu_beq0:
+; CHECK-LABEL: sltiu_beq0:
 ; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
 ; CHECK: beq $[[R0]], $zero
 
@@ -105,7 +105,7 @@ if.end:
   ret void
 }
 
-; CHECK: sltiu_beq1:
+; CHECK-LABEL: sltiu_beq1:
 ; CHECK: sltu ${{[0-9]+}}
 
 define void @sltiu_beq1(i32 %a) {
@@ -121,7 +121,7 @@ if.end:
   ret void
 }
 
-; CHECK: sltiu_beq2:
+; CHECK-LABEL: sltiu_beq2:
 ; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
 ; CHECK: beq $[[R0]], $zero
 
@@ -138,7 +138,7 @@ if.end:
   ret void
 }
 
-; CHECK: sltiu_beq3:
+; CHECK-LABEL: sltiu_beq3:
 ; CHECK: sltu ${{[0-9]+}}
 
 define void @sltiu_beq3(i32 %a) {
diff --git a/test/CodeGen/Mips/sint-fp-store_pattern.ll b/test/CodeGen/Mips/sint-fp-store_pattern.ll
index 23a8aea..c44ea08 100644
--- a/test/CodeGen/Mips/sint-fp-store_pattern.ll
+++ b/test/CodeGen/Mips/sint-fp-store_pattern.ll
@@ -4,7 +4,7 @@
 @gint_ = external global i32
 @gLL_ = external global i64
 
-; 32: store_int_float_:
+; 32-LABEL: store_int_float_:
 ; 32: trunc.w.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 32: swc1 $f[[R0]],
 
@@ -15,10 +15,10 @@ entry:
   ret void
 }
 
-; 32: store_int_double_:
+; 32-LABEL: store_int_double_:
 ; 32: trunc.w.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 32: swc1 $f[[R0]],
-; 64: store_int_double_:
+; 64-LABEL: store_int_double_:
 ; 64: trunc.w.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 64: swc1 $f[[R0]],
 
@@ -29,7 +29,7 @@ entry:
   ret void
 }
 
-; 64: store_LL_float_:
+; 64-LABEL: store_LL_float_:
 ; 64: trunc.l.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 64: sdc1 $f[[R0]],
 
@@ -40,7 +40,7 @@ entry:
   ret void
 }
 
-; 64: store_LL_double_:
+; 64-LABEL: store_LL_double_:
 ; 64: trunc.l.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 64: sdc1 $f[[R0]],
 
diff --git a/test/CodeGen/Mips/stackcoloring.ll b/test/CodeGen/Mips/stackcoloring.ll
index 76cc086..4987dad 100644
--- a/test/CodeGen/Mips/stackcoloring.ll
+++ b/test/CodeGen/Mips/stackcoloring.ll
@@ -2,7 +2,7 @@
 
 @g1 = external global i32*
 
-; CHECK: foo1:
+; CHECK-LABEL: foo1:
 ; CHECK: lw ${{[0-9]+}}, %got(g1)
 ; CHECK: # %for.body
 ; CHECK: # %for.end
diff --git a/test/CodeGen/Mips/stchar.ll b/test/CodeGen/Mips/stchar.ll
index c00c9fd..12eae34 100644
--- a/test/CodeGen/Mips/stchar.ll
+++ b/test/CodeGen/Mips/stchar.ll
@@ -50,8 +50,8 @@ entry:
   %conv1.i = sext i8 %3 to i32
   %call.i = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i32 %conv.i, i32 %conv1.i) nounwind
   ret void
-; 16_b: test:
-; 16_h: test:
+; 16_b-LABEL: test:
+; 16_h-LABEL: test:
 ; 16_b:	sb	${{[0-9]+}}, [[offset1:[0-9]+]](${{[0-9]+}})
 ; 16_b: lb      ${{[0-9]+}}, [[offset1]](${{[0-9]+}})
 ; 16_h:	sh	${{[0-9]+}}, [[offset2:[0-9]+]](${{[0-9]+}})
diff --git a/test/CodeGen/Mips/tls-models.ll b/test/CodeGen/Mips/tls-models.ll
index 8f5789e..1a958dc 100644
--- a/test/CodeGen/Mips/tls-models.ll
+++ b/test/CodeGen/Mips/tls-models.ll
@@ -20,9 +20,9 @@ entry:
   ret i32* @external_gd
 
   ; Non-PIC code can use initial-exec, PIC code has to use general dynamic.
-  ; CHECK-NONPIC:   f1:
+  ; CHECK-NONPIC-LABEL:   f1:
   ; CHECK-NONPIC:   %gottprel
-  ; CHECK-PIC:      f1:
+  ; CHECK-PIC-LABEL:      f1:
   ; CHECK-PIC:      %tlsgd
 }
 
@@ -31,9 +31,9 @@ entry:
   ret i32* @internal_gd
 
   ; Non-PIC code can use local exec, PIC code can use local dynamic.
-  ; CHECK-NONPIC:   f2:
+  ; CHECK-NONPIC-LABEL:   f2:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f2:
+  ; CHECK-PIC-LABEL:      f2:
   ; CHECK-PIC:      %tlsldm
 }
 
@@ -45,9 +45,9 @@ entry:
   ret i32* @external_ld
 
   ; Non-PIC code can use initial exec, PIC should use local dynamic.
-  ; CHECK-NONPIC:   f3:
+  ; CHECK-NONPIC-LABEL:   f3:
   ; CHECK-NONPIC:   %gottprel
-  ; CHECK-PIC:      f3:
+  ; CHECK-PIC-LABEL:      f3:
   ; CHECK-PIC:      %tlsldm
 }
 
@@ -56,9 +56,9 @@ entry:
   ret i32* @internal_ld
 
   ; Non-PIC code can use local exec, PIC code can use local dynamic.
-  ; CHECK-NONPIC:   f4:
+  ; CHECK-NONPIC-LABEL:   f4:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f4:
+  ; CHECK-PIC-LABEL:      f4:
   ; CHECK-PIC:      %tlsldm
 }
 
@@ -70,9 +70,9 @@ entry:
   ret i32* @external_ie
 
   ; Non-PIC and PIC code will use initial exec as specified.
-  ; CHECK-NONPIC:   f5:
+  ; CHECK-NONPIC-LABEL:   f5:
   ; CHECK-NONPIC:   %gottprel
-  ; CHECK-PIC:      f5:
+  ; CHECK-PIC-LABEL:      f5:
   ; CHECK-PIC:      %gottprel
 }
 
@@ -81,9 +81,9 @@ entry:
   ret i32* @internal_ie
 
   ; Non-PIC code can use local exec, PIC code use initial exec as specified.
-  ; CHECK-NONPIC:   f6:
+  ; CHECK-NONPIC-LABEL:   f6:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f6:
+  ; CHECK-PIC-LABEL:      f6:
   ; CHECK-PIC:      %gottprel
 }
 
@@ -95,9 +95,9 @@ entry:
   ret i32* @external_le
 
   ; Non-PIC and PIC code will use local exec as specified.
-  ; CHECK-NONPIC:   f7:
+  ; CHECK-NONPIC-LABEL:   f7:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f7:
+  ; CHECK-PIC-LABEL:      f7:
   ; CHECK-PIC:      %tprel_hi
 }
 
@@ -106,8 +106,8 @@ entry:
   ret i32* @internal_le
 
   ; Non-PIC and PIC code will use local exec as specified.
-  ; CHECK-NONPIC:   f8:
+  ; CHECK-NONPIC-LABEL:   f8:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f8:
+  ; CHECK-PIC-LABEL:      f8:
   ; CHECK-PIC:      %tprel_hi
 }
diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll
index d83edfd..23a8f93 100644
--- a/test/CodeGen/Mips/tls.ll
+++ b/test/CodeGen/Mips/tls.ll
@@ -13,14 +13,14 @@ entry:
   %tmp = load i32* @t1, align 4
   ret i32 %tmp
 
-; PIC:       f1:
+; PIC-LABEL:       f1:
 ; PIC-DAG:   addu    $[[R0:[a-z0-9]+]], $2, $25
 ; PIC-DAG:   lw      $25, %call16(__tls_get_addr)($[[R0]])
 ; PIC-DAG:   addiu   $4, $[[R0]], %tlsgd(t1)
 ; PIC-DAG:   jalr    $25
 ; PIC-DAG:   lw      $2, 0($2)
 
-; STATIC:   f1:
+; STATIC-LABEL:   f1:
 ; STATIC:   lui     $[[R0:[0-9]+]], %tprel_hi(t1)
 ; STATIC:   addiu   $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
 ; STATIC:   rdhwr   $3, $29
@@ -36,19 +36,19 @@ entry:
   %tmp = load i32* @t2, align 4
   ret i32 %tmp
 
-; PIC:       f2:
+; PIC-LABEL:       f2:
 ; PIC-DAG:   addu    $[[R0:[a-z0-9]+]], $2, $25
 ; PIC-DAG:   lw      $25, %call16(__tls_get_addr)($[[R0]])
 ; PIC-DAG:   addiu   $4, $[[R0]], %tlsgd(t2)
 ; PIC-DAG:   jalr    $25
 ; PIC-DAG:   lw      $2, 0($2)
 
-; STATICGP: f2:
+; STATICGP-LABEL: f2:
 ; STATICGP: lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
 ; STATICGP: addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
 ; STATICGP: lw      ${{[0-9]+}}, %gottprel(t2)($[[GP]])
 
-; STATIC:   f2:
+; STATIC-LABEL:   f2:
 ; STATIC:   lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
 ; STATIC:   addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
 ; STATIC:   rdhwr   $3, $29
@@ -61,7 +61,7 @@ entry:
 
 define i32 @f3() nounwind {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 
 ; PIC:   addiu   $4, ${{[a-z0-9]+}}, %tlsldm(f3.i)
 ; PIC:   jalr    $25
diff --git a/test/CodeGen/Mips/tnaked.ll b/test/CodeGen/Mips/tnaked.ll
index f5bdd91..edf1ecf 100644
--- a/test/CodeGen/Mips/tnaked.ll
+++ b/test/CodeGen/Mips/tnaked.ll
@@ -7,7 +7,7 @@ entry:
 }
 
 ; CHECK: 	.ent	tnaked
-; CHECK:          tnaked: 
+; CHECK-LABEL:          tnaked:
 ; CHECK-NOT:	.frame	{{.*}}
 ; CHECK-NOT:     .mask 	{{.*}}
 ; CHECK-NOT:	.fmask	{{.*}}
@@ -19,7 +19,7 @@ entry:
 }
 
 ; CHECK: 	.ent	tnonaked
-; CHECK:         tnonaked: 
+; CHECK-LABEL:         tnonaked:
 ; CHECK:	.frame	$fp,8,$ra
 ; CHECK:        .mask 	0x40000000,-4
 ; CHECK:	.fmask	0x00000000,0
diff --git a/test/CodeGen/PowerPC/2009-09-18-carrybit.ll b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
index 6c23a61..8d5ea8a 100644
--- a/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
+++ b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
@@ -5,7 +5,7 @@ target triple = "powerpc-apple-darwin9.6"
 
 define i64 @foo(i64 %r.0.ph, i64 %q.0.ph, i32 %sr1.1.ph) nounwind {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: subfc
 ; CHECK: subfe
 ; CHECK: subfc
diff --git a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
index d1a3c9f..a25ce07 100644
--- a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
+++ b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
@@ -6,7 +6,7 @@ target triple = "powerpc-apple-darwin9.8"
 define i32 @main() nounwind {
 entry:
 ; Make sure we're generating references using the red zone
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK: stw r2, -12(r1)
   %retval = alloca i32
   %0 = alloca i32
diff --git a/test/CodeGen/PowerPC/addc.ll b/test/CodeGen/PowerPC/addc.ll
index 8c928ce..500d126 100644
--- a/test/CodeGen/PowerPC/addc.ll
+++ b/test/CodeGen/PowerPC/addc.ll
@@ -5,7 +5,7 @@ define i64 @add_ll(i64 %a, i64 %b) nounwind {
 entry:
         %tmp.2 = add i64 %b, %a         ; <i64> [#uses=1]
         ret i64 %tmp.2
-; CHECK: add_ll:
+; CHECK-LABEL: add_ll:
 ; CHECK: addc r4, r6, r4
 ; CHECK: adde r3, r5, r3
 ; CHECK: blr
@@ -15,7 +15,7 @@ define i64 @add_l_5(i64 %a) nounwind {
 entry:
         %tmp.1 = add i64 %a, 5          ; <i64> [#uses=1]
         ret i64 %tmp.1
-; CHECK: add_l_5:
+; CHECK-LABEL: add_l_5:
 ; CHECK: addic r4, r4, 5
 ; CHECK: addze r3, r3
 ; CHECK: blr
@@ -25,7 +25,7 @@ define i64 @add_l_m5(i64 %a) nounwind {
 entry:
         %tmp.1 = add i64 %a, -5         ; <i64> [#uses=1]
         ret i64 %tmp.1
-; CHECK: add_l_m5:
+; CHECK-LABEL: add_l_m5:
 ; CHECK: addic r4, r4, -5
 ; CHECK: addme r3, r3
 ; CHECK: blr
diff --git a/test/CodeGen/PowerPC/anon_aggr.ll b/test/CodeGen/PowerPC/anon_aggr.ll
index cf39168..1525e05 100644
--- a/test/CodeGen/PowerPC/anon_aggr.ll
+++ b/test/CodeGen/PowerPC/anon_aggr.ll
@@ -20,7 +20,7 @@ unequal:
   ret i8* %ptr
 }
 
-; CHECK: func1:
+; CHECK-LABEL: func1:
 ; CHECK: cmpld {{[0-9]+}}, 4, 5
 ; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]]
 ; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
@@ -61,7 +61,7 @@ unequal:
   ret i8* %array2_ptr
 }
 
-; CHECK: func2:
+; CHECK-LABEL: func2:
 ; CHECK: addi [[REG1:[0-9]+]], 1, 64
 ; CHECK: ld [[REG2:[0-9]+]], 8([[REG1]])
 ; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]]
@@ -107,7 +107,7 @@ unequal:
   ret i8* %array2_ptr
 }
 
-; CHECK: func3:
+; CHECK-LABEL: func3:
 ; CHECK: addi [[REG1:[0-9]+]], 1, 64
 ; CHECK: addi [[REG2:[0-9]+]], 1, 48
 ; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]])
@@ -156,7 +156,7 @@ unequal:
   ret i8* %array2_ptr
 }
 
-; CHECK: func4:
+; CHECK-LABEL: func4:
 ; CHECK: addi [[REG1:[0-9]+]], 1, 128
 ; CHECK: ld [[REG2:[0-9]+]], 120(1)
 ; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]])
diff --git a/test/CodeGen/PowerPC/atomic-1.ll b/test/CodeGen/PowerPC/atomic-1.ll
index 838db20..1737916 100644
--- a/test/CodeGen/PowerPC/atomic-1.ll
+++ b/test/CodeGen/PowerPC/atomic-1.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 |  FileCheck %s
 
 define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind {
-; CHECK: exchange_and_add:
+; CHECK-LABEL: exchange_and_add:
 ; CHECK: lwarx {{r[0-9]+}}, 0, {{r[0-9]+}}
   %tmp = atomicrmw add i32* %mem, i32 %val monotonic
 ; CHECK: stwcx. {{r[0-9]+}}, 0, {{r[0-9]+}}
@@ -9,7 +9,7 @@ define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind {
 }
 
 define i32 @exchange_and_cmp(i32* %mem) nounwind {
-; CHECK: exchange_and_cmp:
+; CHECK-LABEL: exchange_and_cmp:
 ; CHECK: lwarx
   %tmp = cmpxchg i32* %mem, i32 0, i32 1 monotonic
 ; CHECK: stwcx.
@@ -18,7 +18,7 @@ define i32 @exchange_and_cmp(i32* %mem) nounwind {
 }
 
 define i32 @exchange(i32* %mem, i32 %val) nounwind {
-; CHECK: exchange:
+; CHECK-LABEL: exchange:
 ; CHECK: lwarx
   %tmp = atomicrmw xchg i32* %mem, i32 1 monotonic
 ; CHECK: stwcx.
diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll
index 40b4a2e..e56a779 100644
--- a/test/CodeGen/PowerPC/atomic-2.ll
+++ b/test/CodeGen/PowerPC/atomic-2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=ppc64 | FileCheck %s
 
 define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
-; CHECK: exchange_and_add:
+; CHECK-LABEL: exchange_and_add:
 ; CHECK: ldarx
   %tmp = atomicrmw add i64* %mem, i64 %val monotonic
 ; CHECK: stdcx.
@@ -9,7 +9,7 @@ define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
 }
 
 define i64 @exchange_and_cmp(i64* %mem) nounwind {
-; CHECK: exchange_and_cmp:
+; CHECK-LABEL: exchange_and_cmp:
 ; CHECK: ldarx
   %tmp = cmpxchg i64* %mem, i64 0, i64 1 monotonic
 ; CHECK: stdcx.
@@ -18,7 +18,7 @@ define i64 @exchange_and_cmp(i64* %mem) nounwind {
 }
 
 define i64 @exchange(i64* %mem, i64 %val) nounwind {
-; CHECK: exchange:
+; CHECK-LABEL: exchange:
 ; CHECK: ldarx
   %tmp = atomicrmw xchg i64* %mem, i64 1 monotonic
 ; CHECK: stdcx.
diff --git a/test/CodeGen/PowerPC/complex-return.ll b/test/CodeGen/PowerPC/complex-return.ll
index f12152f..3eb30e9 100644
--- a/test/CodeGen/PowerPC/complex-return.ll
+++ b/test/CodeGen/PowerPC/complex-return.ll
@@ -23,7 +23,7 @@ entry:
   ret { ppc_fp128, ppc_fp128 } %0
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: lfd 3
 ; CHECK: lfd 4
 ; CHECK: lfd 2
@@ -49,7 +49,7 @@ entry:
   ret { float, float } %0
 }
 
-; CHECK: oof:
+; CHECK-LABEL: oof:
 ; CHECK: lfs 2
 ; CHECK: lfs 1
 
diff --git a/test/CodeGen/PowerPC/dbg.ll b/test/CodeGen/PowerPC/dbg.ll
index 21e3661..840ce98 100644
--- a/test/CodeGen/PowerPC/dbg.ll
+++ b/test/CodeGen/PowerPC/dbg.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -break-anti-dependencies=all -march=ppc64 -mcpu=g5 | FileCheck %s
-; CHECK: main:
+; CHECK-LABEL: main:
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
diff --git a/test/CodeGen/PowerPC/emptystruct.ll b/test/CodeGen/PowerPC/emptystruct.ll
index c6dae82..47cfadd 100644
--- a/test/CodeGen/PowerPC/emptystruct.ll
+++ b/test/CodeGen/PowerPC/emptystruct.ll
@@ -25,7 +25,7 @@ entry:
   ret void
 }
 
-; CHECK: callee:
+; CHECK-LABEL: callee:
 ; CHECK: std 4,
 ; CHECK-NOT: std 5,
 ; CHECK-NOT: std 6,
@@ -42,7 +42,7 @@ entry:
   ret void
 }
 
-; CHECK: caller:
+; CHECK-LABEL: caller:
 ; CHECK: addi 4,
 ; CHECK-NOT: std 5,
 ; CHECK-NOT: std 6,
diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll
index 4b6f88b..fd06fd9 100644
--- a/test/CodeGen/PowerPC/indirectbr.ll
+++ b/test/CodeGen/PowerPC/indirectbr.ll
@@ -6,9 +6,9 @@
 @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
 
 define internal i32 @foo(i32 %i) nounwind {
-; PIC: foo:
-; STATIC: foo:
-; PPC64: foo:
+; PIC-LABEL: foo:
+; STATIC-LABEL: foo:
+; PPC64-LABEL: foo:
 entry:
   %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2]
   %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1]
diff --git a/test/CodeGen/PowerPC/ppc64-toc.ll b/test/CodeGen/PowerPC/ppc64-toc.ll
index 7f30ef8..f349919 100644
--- a/test/CodeGen/PowerPC/ppc64-toc.ll
+++ b/test/CodeGen/PowerPC/ppc64-toc.ll
@@ -8,7 +8,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define i64 @access_int64(i64 %a) nounwind readonly {
 entry:
-; CHECK: access_int64:
+; CHECK-LABEL: access_int64:
 ; CHECK-NEXT: .align  3
 ; CHECK-NEXT: .quad   .L.access_int64
 ; CHECK-NEXT: .quad   .TOC.@tocbase
@@ -23,7 +23,7 @@ entry:
 
 define i64 @internal_static_var(i64 %a) nounwind {
 entry:
-; CHECK: internal_static_var:
+; CHECK-LABEL: internal_static_var:
 ; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
   %0 = load i64* @internal_static_var.x, align 8
   %cmp = icmp eq i64 %0, %a
@@ -33,7 +33,7 @@ entry:
 
 define i32 @access_double(double %a) nounwind readnone {
 entry:
-; CHECK: access_double:
+; CHECK-LABEL: access_double:
 ; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
   %cmp = fcmp oeq double %a, 2.000000e+00
   %conv = zext i1 %cmp to i32 
@@ -43,7 +43,7 @@ entry:
 
 define i32 @access_double_array(double %a, i32 %i) nounwind readonly {
 entry:
-; CHECK: access_double_array:
+; CHECK-LABEL: access_double_array:
   %idxprom = sext i32 %i to i64
   %arrayidx = getelementptr inbounds [32 x double]* @double_array, i64 0, i64 %idxprom
   %0 = load double* %arrayidx, align 8
diff --git a/test/CodeGen/PowerPC/pr13891.ll b/test/CodeGen/PowerPC/pr13891.ll
index 3ae7385..4be65dd 100644
--- a/test/CodeGen/PowerPC/pr13891.ll
+++ b/test/CodeGen/PowerPC/pr13891.ll
@@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 %struct.foo = type { i8, i8 }
 
 define void @_Z5check3foos(%struct.foo* nocapture byval %f, i16 signext %i) noinline {
-; CHECK: _Z5check3foos:
+; CHECK-LABEL: _Z5check3foos:
 ; CHECK: sth 3, {{[0-9]+}}(1)
 ; CHECK: lha {{[0-9]+}}, {{[0-9]+}}(1)
 entry:
diff --git a/test/CodeGen/PowerPC/rounding-ops.ll b/test/CodeGen/PowerPC/rounding-ops.ll
index fa57ee2..2c02900 100644
--- a/test/CodeGen/PowerPC/rounding-ops.ll
+++ b/test/CodeGen/PowerPC/rounding-ops.ll
@@ -10,7 +10,7 @@ define float @test1(float %x) nounwind  {
 ; CHECK-LABEL: test1:
 ; CHECK: frim 1, 1
 
-; CHECK-FM: test1:
+; CHECK-FM-LABEL: test1:
 ; CHECK-FM: frim 1, 1
 }
 
@@ -23,7 +23,7 @@ define double @test2(double %x) nounwind  {
 ; CHECK-LABEL: test2:
 ; CHECK: frim 1, 1
 
-; CHECK-FM: test2:
+; CHECK-FM-LABEL: test2:
 ; CHECK-FM: frim 1, 1
 }
 
@@ -36,7 +36,7 @@ define float @test3(float %x) nounwind  {
 ; CHECK-LABEL: test3:
 ; CHECK-NOT: frin
 
-; CHECK-FM: test3:
+; CHECK-FM-LABEL: test3:
 ; CHECK-FM: frin 1, 1
 }
 
@@ -49,7 +49,7 @@ define double @test4(double %x) nounwind  {
 ; CHECK-LABEL: test4:
 ; CHECK-NOT: frin
 
-; CHECK-FM: test4:
+; CHECK-FM-LABEL: test4:
 ; CHECK-FM: frin 1, 1
 }
 
@@ -62,7 +62,7 @@ define float @test5(float %x) nounwind  {
 ; CHECK-LABEL: test5:
 ; CHECK: frip 1, 1
 
-; CHECK-FM: test5:
+; CHECK-FM-LABEL: test5:
 ; CHECK-FM: frip 1, 1
 }
 
@@ -75,7 +75,7 @@ define double @test6(double %x) nounwind  {
 ; CHECK-LABEL: test6:
 ; CHECK: frip 1, 1
 
-; CHECK-FM: test6:
+; CHECK-FM-LABEL: test6:
 ; CHECK-FM: frip 1, 1
 }
 
@@ -88,7 +88,7 @@ define float @test9(float %x) nounwind  {
 ; CHECK-LABEL: test9:
 ; CHECK: friz 1, 1
 
-; CHECK-FM: test9:
+; CHECK-FM-LABEL: test9:
 ; CHECK-FM: friz 1, 1
 }
 
@@ -101,7 +101,7 @@ define double @test10(double %x) nounwind  {
 ; CHECK-LABEL: test10:
 ; CHECK: friz 1, 1
 
-; CHECK-FM: test10:
+; CHECK-FM-LABEL: test10:
 ; CHECK-FM: friz 1, 1
 }
 
@@ -115,7 +115,7 @@ define void @test11(float %x, float* %y) nounwind  {
 ; CHECK-LABEL: test11:
 ; CHECK-NOT: frin
 
-; CHECK-FM: test11:
+; CHECK-FM-LABEL: test11:
 ; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]]
 ; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]]
 ; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2
@@ -134,7 +134,7 @@ define void @test12(double %x, double* %y) nounwind  {
 ; CHECK-LABEL: test12:
 ; CHECK-NOT: frin
 
-; CHECK-FM: test12:
+; CHECK-FM-LABEL: test12:
 ; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]]
 ; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]]
 ; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2
diff --git a/test/CodeGen/PowerPC/svr4-redzone.ll b/test/CodeGen/PowerPC/svr4-redzone.ll
index 91ff579..7c51b67 100644
--- a/test/CodeGen/PowerPC/svr4-redzone.ll
+++ b/test/CodeGen/PowerPC/svr4-redzone.ll
@@ -7,11 +7,11 @@ entry:
 	%0 = add i32 1, 2
 	ret void
 }
-; PPC32: regalloc:
+; PPC32-LABEL: regalloc:
 ; PPC32-NOT: stwu 1, -{{[0-9]+}}(1)
 ; PPC32: blr
 
-; PPC64: regalloc:
+; PPC64-LABEL: regalloc:
 ; PPC64-NOT: stdu 1, -{{[0-9]+}}(1)
 ; PPC64: blr
 
@@ -20,10 +20,10 @@ entry:
 	%0 = alloca i8, i32 4
 	ret void
 }
-; PPC32: smallstack:
+; PPC32-LABEL: smallstack:
 ; PPC32: stwu 1, -16(1)
 
-; PPC64: smallstack:
+; PPC64-LABEL: smallstack:
 ; PPC64-NOT: stdu 1, -{{[0-9]+}}(1)
 ; PPC64: blr
 
@@ -32,8 +32,8 @@ entry:
 	%0 = alloca i8, i32 230
 	ret void
 }
-; PPC32: bigstack:
+; PPC32-LABEL: bigstack:
 ; PPC32: stwu 1, -240(1)
 
-; PPC64: bigstack:
+; PPC64-LABEL: bigstack:
 ; PPC64: stdu 1, -352(1)
diff --git a/test/CodeGen/PowerPC/tls-2.ll b/test/CodeGen/PowerPC/tls-2.ll
index 20d8fe4..c2faf90 100644
--- a/test/CodeGen/PowerPC/tls-2.ll
+++ b/test/CodeGen/PowerPC/tls-2.ll
@@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-freebsd10.0"
 
 @a = thread_local global i32 0, align 4
 
-;CHECK:          localexec:
+;CHECK-LABEL:          localexec:
 define i32 @localexec() nounwind {
 entry:
 ;CHECK:          addis [[REG1:[0-9]+]], 13, a@tprel@ha
diff --git a/test/CodeGen/PowerPC/tls.ll b/test/CodeGen/PowerPC/tls.ll
index 2daa60a..4e0a822 100644
--- a/test/CodeGen/PowerPC/tls.ll
+++ b/test/CodeGen/PowerPC/tls.ll
@@ -5,8 +5,8 @@ target triple = "powerpc64-unknown-freebsd10.0"
 
 @a = thread_local global i32 0, align 4
 
-;OPT0:          localexec:
-;OPT1:          localexec:
+;OPT0-LABEL:          localexec:
+;OPT1-LABEL:          localexec:
 define i32 @localexec() nounwind {
 entry:
 ;OPT0:          addis [[REG1:[0-9]+]], 13, a@tprel@ha
diff --git a/test/CodeGen/PowerPC/vec_cmp.ll b/test/CodeGen/PowerPC/vec_cmp.ll
index eb41667..83e0e02 100644
--- a/test/CodeGen/PowerPC/vec_cmp.ll
+++ b/test/CodeGen/PowerPC/vec_cmp.ll
@@ -14,7 +14,7 @@ define <2 x i8> @v2si8_cmp(<2 x i8> %x, <2 x i8> %y) nounwind readnone {
   %sext = sext <2 x i1> %cmp to <2 x i8>
   ret <2 x i8> %sext
 }
-; CHECK: v2si8_cmp:
+; CHECK-LABEL: v2si8_cmp:
 ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -23,7 +23,7 @@ define <4 x i8> @v4si8_cmp(<4 x i8> %x, <4 x i8> %y) nounwind readnone {
   %sext = sext <4 x i1> %cmp to <4 x i8>
   ret <4 x i8> %sext
 }
-; CHECK: v4si8_cmp:
+; CHECK-LABEL: v4si8_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -32,7 +32,7 @@ define <8 x i8> @v8si8_cmp(<8 x i8> %x, <8 x i8> %y) nounwind readnone {
   %sext = sext <8 x i1> %cmp to <8 x i8>
   ret <8 x i8> %sext
 }
-; CHECK: v8si8_cmp:
+; CHECK-LABEL: v8si8_cmp:
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -43,7 +43,7 @@ define <16 x i8> @v16si8_cmp_eq(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16si8_cmp_eq:
+; CHECK-LABEL: v16si8_cmp_eq:
 ; CHECK: vcmpequb 2, 2, 3
 
 define <16 x i8> @v16si8_cmp_ne(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -52,7 +52,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:     v16si8_cmp_ne:
+; CHECK-LABEL:     v16si8_cmp_ne:
 ; CHECK:     vcmpequb [[RET:[0-9]+]], 2, 3
 ; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
 
@@ -62,7 +62,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:      v16si8_cmp_le:
+; CHECK-LABEL:      v16si8_cmp_le:
 ; CHECK:      vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsb [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -73,7 +73,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:      v16ui8_cmp_le:
+; CHECK-LABEL:      v16ui8_cmp_le:
 ; CHECK:      vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtub [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -84,7 +84,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16si8_cmp_lt:
+; CHECK-LABEL: v16si8_cmp_lt:
 ; CHECK: vcmpgtsb 2, 3, 2
 
 define <16 x i8> @v16ui8_cmp_lt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -93,7 +93,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16ui8_cmp_lt:
+; CHECK-LABEL: v16ui8_cmp_lt:
 ; CHECK: vcmpgtub 2, 3, 2
 
 define <16 x i8> @v16si8_cmp_gt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -102,7 +102,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16si8_cmp_gt:
+; CHECK-LABEL: v16si8_cmp_gt:
 ; CHECK: vcmpgtsb 2, 2, 3
 
 define <16 x i8> @v16ui8_cmp_gt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -111,7 +111,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16ui8_cmp_gt:
+; CHECK-LABEL: v16ui8_cmp_gt:
 ; CHECK: vcmpgtub 2, 2, 3
 
 define <16 x i8> @v16si8_cmp_ge(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -120,7 +120,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:      v16si8_cmp_ge:
+; CHECK-LABEL:      v16si8_cmp_ge:
 ; CHECK:      vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsb [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -131,7 +131,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:      v16ui8_cmp_ge:
+; CHECK-LABEL:      v16ui8_cmp_ge:
 ; CHECK:      vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtub [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -142,7 +142,7 @@ define <32 x i8> @v32si8_cmp(<32 x i8> %x, <32 x i8> %y) nounwind readnone {
   %sext = sext <32 x i1> %cmp to <32 x i8>
   ret <32 x i8> %sext
 }
-; CHECK: v32si8_cmp:
+; CHECK-LABEL: v32si8_cmp:
 ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
@@ -152,7 +152,7 @@ define <2 x i16> @v2si16_cmp(<2 x i16> %x, <2 x i16> %y) nounwind readnone {
   %sext = sext <2 x i1> %cmp to <2 x i16>
   ret <2 x i16> %sext
 }
-; CHECK: v2si16_cmp:
+; CHECK-LABEL: v2si16_cmp:
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -161,7 +161,7 @@ define <4 x i16> @v4si16_cmp(<4 x i16> %x, <4 x i16> %y) nounwind readnone {
   %sext = sext <4 x i1> %cmp to <4 x i16>
   ret <4 x i16> %sext
 }
-; CHECK: v4si16_cmp:
+; CHECK-LABEL: v4si16_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -173,7 +173,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8si16_cmp_eq:
+; CHECK-LABEL: v8si16_cmp_eq:
 ; CHECK: vcmpequh 2, 2, 3
 
 define <8 x i16> @v8si16_cmp_ne(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -182,7 +182,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8si16_cmp_ne:
+; CHECK-LABEL:      v8si16_cmp_ne:
 ; CHECK:      vcmpequh [[RET:[0-9]+]], 2, 3
 ; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
 
@@ -192,7 +192,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8si16_cmp_le:
+; CHECK-LABEL:      v8si16_cmp_le:
 ; CHECK:      vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsh [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -203,7 +203,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8ui16_cmp_le:
+; CHECK-LABEL:      v8ui16_cmp_le:
 ; CHECK:      vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtuh [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -214,7 +214,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8si16_cmp_lt:
+; CHECK-LABEL: v8si16_cmp_lt:
 ; CHECK: vcmpgtsh 2, 3, 2
 
 define <8 x i16> @v8ui16_cmp_lt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -223,7 +223,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8ui16_cmp_lt:
+; CHECK-LABEL: v8ui16_cmp_lt:
 ; CHECK: vcmpgtuh 2, 3, 2
 
 define <8 x i16> @v8si16_cmp_gt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -232,7 +232,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8si16_cmp_gt:
+; CHECK-LABEL: v8si16_cmp_gt:
 ; CHECK: vcmpgtsh 2, 2, 3
 
 define <8 x i16> @v8ui16_cmp_gt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -241,7 +241,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8ui16_cmp_gt:
+; CHECK-LABEL: v8ui16_cmp_gt:
 ; CHECK: vcmpgtuh 2, 2, 3
 
 define <8 x i16> @v8si16_cmp_ge(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -250,7 +250,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8si16_cmp_ge:
+; CHECK-LABEL:      v8si16_cmp_ge:
 ; CHECK:      vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsh [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -261,7 +261,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8ui16_cmp_ge:
+; CHECK-LABEL:      v8ui16_cmp_ge:
 ; CHECK:      vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtuh [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -272,7 +272,7 @@ define <16 x i16> @v16si16_cmp(<16 x i16> %x, <16 x i16> %y) nounwind readnone {
   %sext = sext <16 x i1> %cmp to <16 x i16>
   ret <16 x i16> %sext
 }
-; CHECK: v16si16_cmp:
+; CHECK-LABEL: v16si16_cmp:
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
@@ -282,7 +282,7 @@ define <32 x i16> @v32si16_cmp(<32 x i16> %x, <32 x i16> %y) nounwind readnone {
   %sext = sext <32 x i1> %cmp to <32 x i16>
   ret <32 x i16> %sext
 }
-; CHECK: v32si16_cmp:
+; CHECK-LABEL: v32si16_cmp:
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -294,7 +294,7 @@ define <2 x i32> @v2si32_cmp(<2 x i32> %x, <2 x i32> %y) nounwind readnone {
   %sext = sext <2 x i1> %cmp to <2 x i32>
   ret <2 x i32> %sext
 }
-; CHECK: v2si32_cmp:
+; CHECK-LABEL: v2si32_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -306,7 +306,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4si32_cmp_eq:
+; CHECK-LABEL: v4si32_cmp_eq:
 ; CHECK: vcmpequw 2, 2, 3
 
 define <4 x i32> @v4si32_cmp_ne(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -315,7 +315,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4si32_cmp_ne:
+; CHECK-LABEL:      v4si32_cmp_ne:
 ; CHECK:      vcmpequw [[RCMP:[0-9]+]], 2, 3
 ; CHECK-NEXT: vnor     2, [[RCMP]], [[RCMP]]
 
@@ -325,7 +325,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4si32_cmp_le:
+; CHECK-LABEL:      v4si32_cmp_le:
 ; CHECK:      vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsw [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -336,7 +336,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4ui32_cmp_le:
+; CHECK-LABEL:      v4ui32_cmp_le:
 ; CHECK:      vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtuw [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -347,7 +347,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4si32_cmp_lt:
+; CHECK-LABEL: v4si32_cmp_lt:
 ; CHECK: vcmpgtsw 2, 3, 2
 
 define <4 x i32> @v4ui32_cmp_lt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -356,7 +356,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4ui32_cmp_lt:
+; CHECK-LABEL: v4ui32_cmp_lt:
 ; CHECK: vcmpgtuw 2, 3, 2
 
 define <4 x i32> @v4si32_cmp_gt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -365,7 +365,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4si32_cmp_gt:
+; CHECK-LABEL: v4si32_cmp_gt:
 ; CHECK: vcmpgtsw 2, 2, 3
 
 define <4 x i32> @v4ui32_cmp_gt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -374,7 +374,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4ui32_cmp_gt:
+; CHECK-LABEL: v4ui32_cmp_gt:
 ; CHECK: vcmpgtuw 2, 2, 3
 
 define <4 x i32> @v4si32_cmp_ge(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -383,7 +383,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4si32_cmp_ge:
+; CHECK-LABEL:      v4si32_cmp_ge:
 ; CHECK:      vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsw [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -394,7 +394,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4ui32_cmp_ge:
+; CHECK-LABEL:      v4ui32_cmp_ge:
 ; CHECK:      vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtuw [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -405,7 +405,7 @@ define <8 x i32> @v8si32_cmp(<8 x i32> %x, <8 x i32> %y) nounwind readnone {
   %sext = sext <8 x i1> %cmp to <8 x i32>
   ret <8 x i32> %sext
 }
-; CHECK: v8si32_cmp:
+; CHECK-LABEL: v8si32_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
@@ -415,7 +415,7 @@ define <16 x i32> @v16si32_cmp(<16 x i32> %x, <16 x i32> %y) nounwind readnone {
   %sext = sext <16 x i1> %cmp to <16 x i32>
   ret <16 x i32> %sext
 }
-; CHECK: v16si32_cmp:
+; CHECK-LABEL: v16si32_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -427,7 +427,7 @@ define <32 x i32> @v32si32_cmp(<32 x i32> %x, <32 x i32> %y) nounwind readnone {
   %sext = sext <32 x i1> %cmp to <32 x i32>
   ret <32 x i32> %sext
 }
-; CHECK: v32si32_cmp:
+; CHECK-LABEL: v32si32_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -445,7 +445,7 @@ entry:
   %0 = bitcast <2 x i32> %sext to <2 x float>
   ret <2 x float> %0
 }
-; CHECK: v2f32_cmp:
+; CHECK-LABEL: v2f32_cmp:
 ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -458,7 +458,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK: v4f32_cmp_eq:
+; CHECK-LABEL: v4f32_cmp_eq:
 ; CHECK: vcmpeqfp 2, 2, 3
 
 define <4 x float> @v4f32_cmp_ne(<4 x float> %x, <4 x float> %y) nounwind readnone {
@@ -468,7 +468,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK:      v4f32_cmp_ne:
+; CHECK-LABEL:      v4f32_cmp_ne:
 ; CHECK:      vcmpeqfp [[RET:[0-9]+]], 2, 3
 ; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
 
@@ -479,7 +479,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK:      v4f32_cmp_le:
+; CHECK-LABEL:      v4f32_cmp_le:
 ; CHECK:      vcmpeqfp [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtfp [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -491,7 +491,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK: v4f32_cmp_lt:
+; CHECK-LABEL: v4f32_cmp_lt:
 ; CHECK: vcmpgtfp 2, 3, 2
 
 define <4 x float> @v4f32_cmp_ge(<4 x float> %x, <4 x float> %y) nounwind readnone {
@@ -501,7 +501,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK: v4f32_cmp_ge:
+; CHECK-LABEL: v4f32_cmp_ge:
 ; CHECK: vcmpgefp 2, 2, 3
 
 define <4 x float> @v4f32_cmp_gt(<4 x float> %x, <4 x float> %y) nounwind readnone {
@@ -511,7 +511,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK: v4f32_cmp_gt:
+; CHECK-LABEL: v4f32_cmp_gt:
 ; CHECK: vcmpgtfp 2, 2, 3
 
 
@@ -522,6 +522,6 @@ entry:
   %0 = bitcast <8 x i32> %sext to <8 x float>
   ret <8 x float> %0
 }
-; CHECK: v8f32_cmp:
+; CHECK-LABEL: v8f32_cmp:
 ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
diff --git a/test/CodeGen/PowerPC/vec_conv.ll b/test/CodeGen/PowerPC/vec_conv.ll
index a475e94..a39ae91 100644
--- a/test/CodeGen/PowerPC/vec_conv.ll
+++ b/test/CodeGen/PowerPC/vec_conv.ll
@@ -17,7 +17,7 @@ entry:
   store <4 x i32> %1, <4 x i32>* %y, align 16
   ret void
 }
-;CHECK: v4f32_to_v4i32:
+;CHECK-LABEL: v4f32_to_v4i32:
 ;CHECK: vctsxs {{[0-9]+}}, {{[0-9]+}}, 0
 
 
@@ -29,7 +29,7 @@ entry:
   store <4 x i32> %1, <4 x i32>* %y, align 16
   ret void
 }
-;CHECK: v4f32_to_v4u32:
+;CHECK-LABEL: v4f32_to_v4u32:
 ;CHECK: vctuxs {{[0-9]+}}, {{[0-9]+}}, 0
 
 
@@ -41,7 +41,7 @@ entry:
   store <4 x float> %1, <4 x float>* %y, align 16
   ret void
 }
-;CHECK: v4i32_to_v4f32:
+;CHECK-LABEL: v4i32_to_v4f32:
 ;CHECK: vcfsx {{[0-9]+}}, {{[0-9]+}}, 0
 
 
@@ -53,5 +53,5 @@ entry:
   store <4 x float> %1, <4 x float>* %y, align 16
   ret void
 }
-;CHECK: v4u32_to_v4f32:
+;CHECK-LABEL: v4u32_to_v4f32:
 ;CHECK: vcfux {{[0-9]+}}, {{[0-9]+}}, 0
diff --git a/test/CodeGen/PowerPC/vec_extload.ll b/test/CodeGen/PowerPC/vec_extload.ll
index 998645d..6373a26 100644
--- a/test/CodeGen/PowerPC/vec_extload.ll
+++ b/test/CodeGen/PowerPC/vec_extload.ll
@@ -14,7 +14,7 @@ define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) {
   %c = sext <16 x i4> %b to <16 x i8>
   ret <16 x i8> %c
 }
-; CHECK: v16si8_sext_in_reg:
+; CHECK-LABEL: v16si8_sext_in_reg:
 ; CHECK: vslb
 ; CHECK: vsrab
 ; CHECK: blr 
@@ -26,7 +26,7 @@ define <16 x i8> @v16si8_zext_in_reg(<16 x i8> %a) {
   %c = zext <16 x i4> %b to <16 x i8>
   ret <16 x i8> %c
 }
-; CHECK:      v16si8_zext_in_reg:
+; CHECK-LABEL:      v16si8_zext_in_reg:
 ; CHECK:      vspltisb [[VMASK:[0-9]+]], 15
 ; CHECK-NEXT: vand 2, 2, [[VMASK]]
 
@@ -36,7 +36,7 @@ define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) {
   %c = sext <8 x i8> %b to <8 x i16>
   ret <8 x i16> %c
 }
-; CHECK: v8si16_sext_in_reg:
+; CHECK-LABEL: v8si16_sext_in_reg:
 ; CHECK: vslh
 ; CHECK: vsrah
 ; CHECK: blr 
@@ -48,7 +48,7 @@ define <8 x i16> @v8si16_zext_in_reg(<8 x i16> %a) {
   %c = zext <8 x i8> %b to <8 x i16>
   ret <8 x i16> %c
 }
-; CHECK:      v8si16_zext_in_reg:
+; CHECK-LABEL:      v8si16_zext_in_reg:
 ; CHECK:      ld [[RMASKTOC:[0-9]+]], .LC{{[0-9]+}}@toc(2)
 ; CHECK-NEXT: lvx [[VMASK:[0-9]+]], {{[0-9]+}}, [[RMASKTOC]]
 ; CHECK-NEXT: vand 2, 2, [[VMASK]]
@@ -60,7 +60,7 @@ define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) {
   %c = sext <4 x i16> %b to <4 x i32>
   ret <4 x i32> %c
 }
-; CHECK: v4si32_sext_in_reg:
+; CHECK-LABEL: v4si32_sext_in_reg:
 ; CHECK: vslw
 ; CHECK: vsraw
 ; CHECK: blr 
@@ -71,7 +71,7 @@ define <4 x i32> @v4si32_zext_in_reg(<4 x i32> %a) {
   %c = zext <4 x i16> %b to <4 x i32>
   ret <4 x i32> %c
 }
-; CHECK:      v4si32_zext_in_reg:
+; CHECK-LABEL:      v4si32_zext_in_reg:
 ; CHECK:      vspltisw [[VMASK:[0-9]+]], -16
 ; CHECK-NEXT: vsrw [[VMASK]], [[VMASK]], [[VMASK]]
 ; CHECK-NEXT: vand 2, 2, [[VMASK]]
diff --git a/test/CodeGen/PowerPC/vec_rounding.ll b/test/CodeGen/PowerPC/vec_rounding.ll
index 7c55638..ace187b 100644
--- a/test/CodeGen/PowerPC/vec_rounding.ll
+++ b/test/CodeGen/PowerPC/vec_rounding.ll
@@ -12,7 +12,7 @@ define <2 x double> @floor_v2f64(<2 x double> %p)
   %t = call <2 x double> @llvm.floor.v2f64(<2 x double> %p)
   ret <2 x double> %t
 }
-; CHECK: floor_v2f64:
+; CHECK-LABEL: floor_v2f64:
 ; CHECK: frim
 ; CHECK: frim
 
@@ -22,7 +22,7 @@ define <4 x double> @floor_v4f64(<4 x double> %p)
   %t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p)
   ret <4 x double> %t
 }
-; CHECK: floor_v4f64:
+; CHECK-LABEL: floor_v4f64:
 ; CHECK: frim
 ; CHECK: frim
 ; CHECK: frim
@@ -34,7 +34,7 @@ define <2 x double> @ceil_v2f64(<2 x double> %p)
   %t = call <2 x double> @llvm.ceil.v2f64(<2 x double> %p)
   ret <2 x double> %t
 }
-; CHECK: ceil_v2f64:
+; CHECK-LABEL: ceil_v2f64:
 ; CHECK: frip
 ; CHECK: frip
 
@@ -44,7 +44,7 @@ define <4 x double> @ceil_v4f64(<4 x double> %p)
   %t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
   ret <4 x double> %t
 }
-; CHECK: ceil_v4f64:
+; CHECK-LABEL: ceil_v4f64:
 ; CHECK: frip
 ; CHECK: frip
 ; CHECK: frip
@@ -56,7 +56,7 @@ define <2 x double> @trunc_v2f64(<2 x double> %p)
   %t = call <2 x double> @llvm.trunc.v2f64(<2 x double> %p)
   ret <2 x double> %t
 }
-; CHECK: trunc_v2f64:
+; CHECK-LABEL: trunc_v2f64:
 ; CHECK: friz
 ; CHECK: friz
 
@@ -66,7 +66,7 @@ define <4 x double> @trunc_v4f64(<4 x double> %p)
   %t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
   ret <4 x double> %t
 }
-; CHECK: trunc_v4f64:
+; CHECK-LABEL: trunc_v4f64:
 ; CHECK: friz
 ; CHECK: friz
 ; CHECK: friz
@@ -78,7 +78,7 @@ define <2 x double> @nearbyint_v2f64(<2 x double> %p)
   %t = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p)
   ret <2 x double> %t
 }
-; CHECK: nearbyint_v2f64:
+; CHECK-LABEL: nearbyint_v2f64:
 ; CHECK: bl nearbyint
 ; CHECK: bl nearbyint
 
@@ -88,7 +88,7 @@ define <4 x double> @nearbyint_v4f64(<4 x double> %p)
   %t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
   ret <4 x double> %t
 }
-; CHECK: nearbyint_v4f64:
+; CHECK-LABEL: nearbyint_v4f64:
 ; CHECK: bl nearbyint
 ; CHECK: bl nearbyint
 ; CHECK: bl nearbyint
@@ -101,7 +101,7 @@ define <4 x float> @floor_v4f32(<4 x float> %p)
   %t = call <4 x float> @llvm.floor.v4f32(<4 x float> %p)
   ret <4 x float> %t
 }
-; CHECK: floor_v4f32:
+; CHECK-LABEL: floor_v4f32:
 ; CHECK: vrfim
 
 declare <8 x float> @llvm.floor.v8f32(<8 x float> %p)
@@ -110,7 +110,7 @@ define <8 x float> @floor_v8f32(<8 x float> %p)
   %t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p)
   ret <8 x float> %t
 }
-; CHECK: floor_v8f32:
+; CHECK-LABEL: floor_v8f32:
 ; CHECK: vrfim
 ; CHECK: vrfim
 
@@ -120,7 +120,7 @@ define <4 x float> @ceil_v4f32(<4 x float> %p)
   %t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %p)
   ret <4 x float> %t
 }
-; CHECK: ceil_v4f32:
+; CHECK-LABEL: ceil_v4f32:
 ; CHECK: vrfip
 
 declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
@@ -129,7 +129,7 @@ define <8 x float> @ceil_v8f32(<8 x float> %p)
   %t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
   ret <8 x float> %t
 }
-; CHECK: ceil_v8f32:
+; CHECK-LABEL: ceil_v8f32:
 ; CHECK: vrfip
 ; CHECK: vrfip
 
@@ -139,7 +139,7 @@ define <4 x float> @trunc_v4f32(<4 x float> %p)
   %t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %p)
   ret <4 x float> %t
 }
-; CHECK: trunc_v4f32:
+; CHECK-LABEL: trunc_v4f32:
 ; CHECK: vrfiz
 
 declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
@@ -148,7 +148,7 @@ define <8 x float> @trunc_v8f32(<8 x float> %p)
   %t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
   ret <8 x float> %t
 }
-; CHECK: trunc_v8f32:
+; CHECK-LABEL: trunc_v8f32:
 ; CHECK: vrfiz
 ; CHECK: vrfiz
 
@@ -158,7 +158,7 @@ define <4 x float> @nearbyint_v4f32(<4 x float> %p)
   %t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p)
   ret <4 x float> %t
 }
-; CHECK: nearbyint_v4f32:
+; CHECK-LABEL: nearbyint_v4f32:
 ; CHECK: vrfin
 
 declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
@@ -167,6 +167,6 @@ define <8 x float> @nearbyint_v8f32(<8 x float> %p)
   %t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
   ret <8 x float> %t
 }
-; CHECK: nearbyint_v8f32:
+; CHECK-LABEL: nearbyint_v8f32:
 ; CHECK: vrfin
 ; CHECK: vrfin
diff --git a/test/CodeGen/PowerPC/vec_sqrt.ll b/test/CodeGen/PowerPC/vec_sqrt.ll
index 055da1a..a85c3ff 100644
--- a/test/CodeGen/PowerPC/vec_sqrt.ll
+++ b/test/CodeGen/PowerPC/vec_sqrt.ll
@@ -18,7 +18,7 @@ entry:
   ret <2 x float> %sqrt
 }
 ; sqrt (<2 x float>) is promoted to sqrt (<4 x float>)
-; CHECK: v2f32_sqrt:
+; CHECK-LABEL: v2f32_sqrt:
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
@@ -29,7 +29,7 @@ entry:
   %sqrt = call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %x)
   ret <4 x float> %sqrt
 }
-; CHECK: v4f32_sqrt:
+; CHECK-LABEL: v4f32_sqrt:
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
@@ -40,7 +40,7 @@ entry:
   %sqrt = call <8 x float> @llvm.sqrt.v8f32 (<8 x float> %x)
   ret <8 x float> %sqrt
 }
-; CHECK: v8f32_sqrt:
+; CHECK-LABEL: v8f32_sqrt:
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
@@ -55,7 +55,7 @@ entry:
   %sqrt = call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %x)
   ret <2 x double> %sqrt
 }
-; CHECK: v2f64_sqrt:
+; CHECK-LABEL: v2f64_sqrt:
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
 
@@ -64,7 +64,7 @@ entry:
   %sqrt = call <4 x double> @llvm.sqrt.v4f64 (<4 x double> %x)
   ret <4 x double> %sqrt
 }
-; CHECK: v4f64_sqrt:
+; CHECK-LABEL: v4f64_sqrt:
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
diff --git a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
index 4a59527..dc12b97 100644
--- a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
+++ b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
@@ -109,7 +109,7 @@ declare i32 @func(i32*)
 
 define i32 @restore_add(i32 %a, i32 %b) {
 entry:
-;CHECK:  restore_add:
+;CHECK-LABEL:  restore_add:
 ;CHECK:  jmp %i7+8
 ;CHECK:  restore %o0, %i1, %o0
   %0 = tail call i32 @bar(i32 %a) nounwind
@@ -119,7 +119,7 @@ entry:
 
 define i32 @restore_add_imm(i32 %a) {
 entry:
-;CHECK:  restore_add_imm:
+;CHECK-LABEL:  restore_add_imm:
 ;CHECK:  jmp %i7+8
 ;CHECK:  restore %o0, 20, %o0
   %0 = tail call i32 @bar(i32 %a) nounwind
@@ -129,7 +129,7 @@ entry:
 
 define i32 @restore_or(i32 %a) {
 entry:
-;CHECK:  restore_or:
+;CHECK-LABEL:  restore_or:
 ;CHECK:  jmp %i7+8
 ;CHECK:  restore %g0, %o0, %o0
   %0 = tail call i32 @bar(i32 %a) nounwind
@@ -138,7 +138,7 @@ entry:
 
 define i32 @restore_or_imm(i32 %a) {
 entry:
-;CHECK:  restore_or_imm:
+;CHECK-LABEL:  restore_or_imm:
 ;CHECK:  or %o0, 20, %i0
 ;CHECK:  jmp %i7+8
 ;CHECK:  restore %g0, %g0, %g0
diff --git a/test/CodeGen/SPARC/64bit.ll b/test/CodeGen/SPARC/64bit.ll
index a5ea4d9..f778f9d 100644
--- a/test/CodeGen/SPARC/64bit.ll
+++ b/test/CodeGen/SPARC/64bit.ll
@@ -1,10 +1,10 @@
 ; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s
 ; RUN: llc < %s -march=sparcv9  | FileCheck %s -check-prefix=OPT
 
-; CHECK: ret2:
+; CHECK-LABEL: ret2:
 ; CHECK: or %g0, %i1, %i0
 
-; OPT: ret2:
+; OPT-LABEL: ret2:
 ; OPT: jmp %o7+8
 ; OPT: or %g0, %o1, %o0
 define i64 @ret2(i64 %a, i64 %b) {
@@ -14,7 +14,7 @@ define i64 @ret2(i64 %a, i64 %b) {
 ; CHECK: shl_imm
 ; CHECK: sllx %i0, 7, %i0
 
-; OPT: shl_imm:
+; OPT-LABEL: shl_imm:
 ; OPT: jmp %o7+8
 ; OPT: sllx %o0, 7, %o0
 define i64 @shl_imm(i64 %a) {
@@ -25,7 +25,7 @@ define i64 @shl_imm(i64 %a) {
 ; CHECK: sra_reg
 ; CHECK: srax %i0, %i1, %i0
 
-; OPT: sra_reg:
+; OPT-LABEL: sra_reg:
 ; OPT: jmp %o7+8
 ; OPT: srax %o0, %o1, %o0
 define i64 @sra_reg(i64 %a, i64 %b) {
@@ -271,11 +271,11 @@ define double @bitcast_f64_i64(i64 %x) {
   ret double %y
 }
 
-; CHECK: store_zero:
+; CHECK-LABEL: store_zero:
 ; CHECK: stx %g0, [%i0]
 ; CHECK: stx %g0, [%i1+8]
 
-; OPT:  store_zero:
+; OPT-LABEL:  store_zero:
 ; OPT:  stx %g0, [%o0]
 ; OPT:  stx %g0, [%o1+8]
 define i64 @store_zero(i64* nocapture %a, i64* nocapture %b) {
diff --git a/test/CodeGen/SPARC/basictest.ll b/test/CodeGen/SPARC/basictest.ll
index 7004af9..ba85825 100644
--- a/test/CodeGen/SPARC/basictest.ll
+++ b/test/CodeGen/SPARC/basictest.ll
@@ -25,7 +25,7 @@ define i32 @test2(i32 %X, i32 %Y) {
 ; CHECK: xnor %o0, %o1, %o0
 }
 
-; CHECK: store_zero:
+; CHECK-LABEL: store_zero:
 ; CHECK: st   %g0, [%o0]
 ; CHECK: st   %g0, [%o1+4]
 define i32 @store_zero(i32* %a, i32* %b) {
diff --git a/test/CodeGen/SPARC/blockaddr.ll b/test/CodeGen/SPARC/blockaddr.ll
index a7e85fe..c3d5270 100644
--- a/test/CodeGen/SPARC/blockaddr.ll
+++ b/test/CodeGen/SPARC/blockaddr.ll
@@ -15,13 +15,13 @@ entry:
   ret i8* %x
 }
 
-; abs32: func_block_addr:
+; abs32-LABEL: func_block_addr:
 ; abs32: sethi %hi([[BLK:.+]]), [[R:%[gilo][0-7]]]
 ; abs32: call dummy
 ; abs32: add  [[R]], %lo([[BLK]]), %o0
 ; abs32: jmp %o0
 
-; abs44: func_block_addr:
+; abs44-LABEL: func_block_addr:
 ; abs44: sethi %h44([[BLK:.+]]), [[R:%[gilo][0-7]]]
 ; abs44: add [[R]], %m44([[BLK]]), [[R1:%[gilo][0-7]]]
 ; abs44: sllx [[R1]], 12, [[R2:%[gilo][0-7]]]
@@ -29,7 +29,7 @@ entry:
 ; abs44: add [[R2]], %l44([[BLK]]), %o0
 ; abs44: jmp %o0
 
-; abs64: func_block_addr:
+; abs64-LABEL: func_block_addr:
 ; abs64: sethi %hi([[BLK:.+]]), [[R:%[gilo][0-7]]]
 ; abs64: add [[R]], %lo([[BLK]]), [[R1:%[gilo][0-7]]]
 ; abs64: sethi %hh([[BLK]]), [[R2:%[gilo][0-7]]]
diff --git a/test/CodeGen/SPARC/float.ll b/test/CodeGen/SPARC/float.ll
index b35eb6c..8dfd371 100644
--- a/test/CodeGen/SPARC/float.ll
+++ b/test/CodeGen/SPARC/float.ll
@@ -7,7 +7,7 @@
 ; V8:     call get_double
 ; V8:     fnegs %f0, %f0
 
-; V8-UNOPT:     test_neg:
+; V8-UNOPT-LABEL:     test_neg:
 ; V8-UNOPT:     fnegs
 ; V8-UNOPT:     ! implicit-def
 ; V8-UNOPT:     fmovs {{.+}}, %f0
@@ -26,7 +26,7 @@ entry:
 ; V8-LABEL:     test_abs:
 ; V8:     fabss %f0, %f0
 
-; V8-UNOPT:     test_abs:
+; V8-UNOPT-LABEL:     test_abs:
 ; V8-UNOPT:     fabss
 ; V8-UNOPT:     ! implicit-def
 ; V8-UNOPT:     fmovs {{.+}}, %f0
diff --git a/test/CodeGen/SPARC/leafproc.ll b/test/CodeGen/SPARC/leafproc.ll
index a162df1..0a7ae08 100644
--- a/test/CodeGen/SPARC/leafproc.ll
+++ b/test/CodeGen/SPARC/leafproc.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=sparc -disable-sparc-leaf-proc=0 < %s | FileCheck %s
 
-; CHECK:      func_nobody:
+; CHECK-LABEL:      func_nobody:
 ; CHECK:      jmp %o7+8
 ; CHECK-NEXT: nop
 define void @func_nobody() {
@@ -9,7 +9,7 @@ entry:
 }
 
 
-; CHECK:      return_int_const:
+; CHECK-LABEL:      return_int_const:
 ; CHECK:      jmp %o7+8
 ; CHECK-NEXT: or %g0, 1729, %o0
 define i32 @return_int_const() {
@@ -17,7 +17,7 @@ entry:
   ret i32 1729
 }
 
-; CHECK:      return_double_const:
+; CHECK-LABEL:      return_double_const:
 ; CHECK:      sethi
 ; CHECK:      jmp %o7+8
 ; CHECK-NEXT: ldd {{.*}}, %f0
@@ -27,7 +27,7 @@ entry:
   ret double 0.000000e+00
 }
 
-; CHECK:      leaf_proc_with_args:
+; CHECK-LABEL:      leaf_proc_with_args:
 ; CHECK:      add {{%o[0-1]}}, {{%o[0-1]}}, [[R:%[go][0-7]]]
 ; CHECK:      jmp %o7+8
 ; CHECK-NEXT: add [[R]], %o2, %o0
@@ -39,7 +39,7 @@ entry:
   ret i32 %1
 }
 
-; CHECK:     leaf_proc_with_args_in_stack:
+; CHECK-LABEL:     leaf_proc_with_args_in_stack:
 ; CHECK-DAG: ld [%sp+92], {{%[go][0-7]}}
 ; CHECK-DAG: ld [%sp+96], {{%[go][0-7]}}
 ; CHECK:     jmp %o7+8
@@ -56,7 +56,7 @@ entry:
   ret i32 %6
 }
 
-; CHECK:      leaf_proc_with_local_array:
+; CHECK-LABEL:      leaf_proc_with_local_array:
 ; CHECK:      add %sp, -104, %sp
 ; CHECK:      or %g0, 1, [[R1:%[go][0-7]]]
 ; CHECK:      st [[R1]], [%sp+96]
diff --git a/test/CodeGen/SystemZ/addr-01.ll b/test/CodeGen/SystemZ/addr-01.ll
index bf2ad7b..cf4ed89 100644
--- a/test/CodeGen/SystemZ/addr-01.ll
+++ b/test/CodeGen/SystemZ/addr-01.ll
@@ -5,7 +5,7 @@
 
 ; A simple index address.
 define void @f1(i64 %addr, i64 %index) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lb %r0, 0(%r3,%r2)
 ; CHECK: br %r14
   %add = add i64 %addr, %index
@@ -16,7 +16,7 @@ define void @f1(i64 %addr, i64 %index) {
 
 ; An address with an index and a displacement (order 1).
 define void @f2(i64 %addr, i64 %index) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lb %r0, 100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, %index
@@ -28,7 +28,7 @@ define void @f2(i64 %addr, i64 %index) {
 
 ; An address with an index and a displacement (order 2).
 define void @f3(i64 %addr, i64 %index) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lb %r0, 100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, 100
@@ -40,7 +40,7 @@ define void @f3(i64 %addr, i64 %index) {
 
 ; An address with an index and a subtracted displacement (order 1).
 define void @f4(i64 %addr, i64 %index) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lb %r0, -100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, %index
@@ -52,7 +52,7 @@ define void @f4(i64 %addr, i64 %index) {
 
 ; An address with an index and a subtracted displacement (order 2).
 define void @f5(i64 %addr, i64 %index) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lb %r0, -100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = sub i64 %addr, 100
@@ -64,7 +64,7 @@ define void @f5(i64 %addr, i64 %index) {
 
 ; An address with an index and a displacement added using OR.
 define void @f6(i64 %addr, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
 ; CHECK: lb %r0, 6(%r3,[[BASE]])
 ; CHECK: br %r14
@@ -78,7 +78,7 @@ define void @f6(i64 %addr, i64 %index) {
 
 ; Like f6, but without the masking.  This OR doesn't count as a displacement.
 define void @f7(i64 %addr, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oill %r2, 6
 ; CHECK: lb %r0, 0(%r3,%r2)
 ; CHECK: br %r14
@@ -92,7 +92,7 @@ define void @f7(i64 %addr, i64 %index) {
 ; Like f6, but with the OR applied after the index.  We don't know anything
 ; about the alignment of %add here.
 define void @f8(i64 %addr, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
 ; CHECK: agr [[BASE]], %r3
 ; CHECK: oill [[BASE]], 6
diff --git a/test/CodeGen/SystemZ/addr-02.ll b/test/CodeGen/SystemZ/addr-02.ll
index 6e5c92f..66a7986 100644
--- a/test/CodeGen/SystemZ/addr-02.ll
+++ b/test/CodeGen/SystemZ/addr-02.ll
@@ -6,7 +6,7 @@
 
 ; A simple index address.
 define void @f1(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lb %r0, 0(%r3,%r2)
 ; CHECK: br %r14
   %add = add i64 %addr, %index
@@ -18,7 +18,7 @@ define void @f1(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a displacement (order 1).
 define void @f2(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lb %r0, 100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, %index
@@ -31,7 +31,7 @@ define void @f2(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a displacement (order 2).
 define void @f3(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lb %r0, 100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, 100
@@ -44,7 +44,7 @@ define void @f3(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a subtracted displacement (order 1).
 define void @f4(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lb %r0, -100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, %index
@@ -57,7 +57,7 @@ define void @f4(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a subtracted displacement (order 2).
 define void @f5(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lb %r0, -100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = sub i64 %addr, 100
@@ -70,7 +70,7 @@ define void @f5(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a displacement added using OR.
 define void @f6(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
 ; CHECK: lb %r0, 6(%r3,[[BASE]])
 ; CHECK: br %r14
@@ -85,7 +85,7 @@ define void @f6(i64 %addr, i64 %index, i8 **%dst) {
 
 ; Like f6, but without the masking.  This OR doesn't count as a displacement.
 define void @f7(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oill %r2, 6
 ; CHECK: lb %r0, 0(%r3,%r2)
 ; CHECK: br %r14
@@ -100,7 +100,7 @@ define void @f7(i64 %addr, i64 %index, i8 **%dst) {
 ; Like f6, but with the OR applied after the index.  We don't know anything
 ; about the alignment of %add here.
 define void @f8(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
 ; CHECK: agr [[BASE]], %r3
 ; CHECK: oill [[BASE]], 6
diff --git a/test/CodeGen/SystemZ/addr-03.ll b/test/CodeGen/SystemZ/addr-03.ll
index dbdb9f1..1146926 100644
--- a/test/CodeGen/SystemZ/addr-03.ll
+++ b/test/CodeGen/SystemZ/addr-03.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lb %r0, 0
 ; CHECK: br %r14
   %ptr = inttoptr i64 0 to i8 *
@@ -12,7 +12,7 @@ define void @f1() {
 }
 
 define void @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lb %r0, -524288
 ; CHECK: br %r14
   %ptr = inttoptr i64 -524288 to i8 *
@@ -21,7 +21,7 @@ define void @f2() {
 }
 
 define void @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: lb %r0, -524289
 ; CHECK: br %r14
   %ptr = inttoptr i64 -524289 to i8 *
@@ -30,7 +30,7 @@ define void @f3() {
 }
 
 define void @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lb %r0, 524287
 ; CHECK: br %r14
   %ptr = inttoptr i64 524287 to i8 *
@@ -39,7 +39,7 @@ define void @f4() {
 }
 
 define void @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: lb %r0, 524288
 ; CHECK: br %r14
   %ptr = inttoptr i64 524288 to i8 *
diff --git a/test/CodeGen/SystemZ/alloca-01.ll b/test/CodeGen/SystemZ/alloca-01.ll
index df14e27..2cd9a3a 100644
--- a/test/CodeGen/SystemZ/alloca-01.ll
+++ b/test/CodeGen/SystemZ/alloca-01.ll
@@ -21,34 +21,34 @@ define i64 @f1(i64 %length, i64 %index) {
 ;    risbg %r1, %r1, 0, 188, 0
 ;    lgr %r15, %r1
 ;
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: la [[REG1:%r[0-5]]], 7(%r2)
 ; CHECK-DAG: risbg [[REG2:%r[0-5]]], [[REG1]], 0, 188, 0
 ; CHECK-DAG: lgr [[REG3:%r[0-5]]], %r15
 ; CHECK: sgr [[REG3]], [[REG2]]
 ; CHECK: lgr %r15, [[REG3]]
 ;
-; CHECK-A: f1:
+; CHECK-A-LABEL: f1:
 ; CHECK-A: lgr %r15, %r1
 ; CHECK-A: la %r2, 176(%r1)
 ;
-; CHECK-B: f1:
+; CHECK-B-LABEL: f1:
 ; CHECK-B: lgr %r15, %r1
 ; CHECK-B: la %r3, 177(%r1)
 ;
-; CHECK-C: f1:
+; CHECK-C-LABEL: f1:
 ; CHECK-C: lgr %r15, %r1
 ; CHECK-C: la %r4, 4095({{%r3,%r1|%r1,%r3}})
 ;
-; CHECK-D: f1:
+; CHECK-D-LABEL: f1:
 ; CHECK-D: lgr %r15, %r1
 ; CHECK-D: lay %r5, 4096({{%r3,%r1|%r1,%r3}})
 ;
-; CHECK-E: f1:
+; CHECK-E-LABEL: f1:
 ; CHECK-E: lgr %r15, %r1
 ; CHECK-E: lay %r6, 4271({{%r3,%r1|%r1,%r3}})
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: lgr %r11, %r15
 ; CHECK-FP: lmg %r6, %r15, 224(%r11)
   %a = alloca i8, i64 %length
diff --git a/test/CodeGen/SystemZ/alloca-02.ll b/test/CodeGen/SystemZ/alloca-02.ll
index 41c987a..b6ed7f7 100644
--- a/test/CodeGen/SystemZ/alloca-02.ll
+++ b/test/CodeGen/SystemZ/alloca-02.ll
@@ -9,27 +9,27 @@
 declare i64 @bar(i8 *%a)
 
 define i64 @f1(i64 %length, i64 %index) {
-; CHECK-A: f1:
+; CHECK-A-LABEL: f1:
 ; CHECK-A: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-A: la %r2, 160([[ADDR]])
 ; CHECK-A: mvi 0(%r2), 0
 ;
-; CHECK-B: f1:
+; CHECK-B-LABEL: f1:
 ; CHECK-B: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-B: la %r2, 160([[ADDR]])
 ; CHECK-B: mvi 4095(%r2), 1
 ;
-; CHECK-C: f1:
+; CHECK-C-LABEL: f1:
 ; CHECK-C: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-C: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
 ; CHECK-C: mvi 0([[TMP]]), 2
 ;
-; CHECK-D: f1:
+; CHECK-D-LABEL: f1:
 ; CHECK-D: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-D: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
 ; CHECK-D: mvi 4095([[TMP]]), 3
 ;
-; CHECK-E: f1:
+; CHECK-E-LABEL: f1:
 ; CHECK-E: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-E: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
 ; CHECK-E: mviy 4096([[TMP]]), 4
diff --git a/test/CodeGen/SystemZ/and-01.ll b/test/CodeGen/SystemZ/and-01.ll
index 0da13f9..f893148 100644
--- a/test/CodeGen/SystemZ/and-01.ll
+++ b/test/CodeGen/SystemZ/and-01.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Check NR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: nr %r2, %r3
 ; CHECK: br %r14
   %and = and i32 %a, %b
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the N range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: n %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +25,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned N range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: n %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -36,7 +36,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use NY instead of N.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ny %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -47,7 +47,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned NY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ny %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -59,7 +59,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: n %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned NY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ny %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -82,7 +82,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the NY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ny %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -94,7 +94,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: n %r2, 0(%r3)
 ; CHECK: br %r14
@@ -106,7 +106,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that N allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: n %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -119,7 +119,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that NY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: ny %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -132,7 +132,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
 
 ; Check that ANDs of spilled values can use N rather than NR.
 define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: n %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/and-02.ll b/test/CodeGen/SystemZ/and-02.ll
index 152c1b8..0f39e18 100644
--- a/test/CodeGen/SystemZ/and-02.ll
+++ b/test/CodeGen/SystemZ/and-02.ll
@@ -4,7 +4,7 @@
 
 ; ANDs with 1 should use RISBG
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: risbg %r2, %r2, 63, 191, 0
 ; CHECK: br %r14
   %and = and i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; ...same for 2.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: risbg %r2, %r2, 62, 190, 0
 ; CHECK: br %r14
   %and = and i32 %a, 2
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; ...and 3.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: risbg %r2, %r2, 62, 191, 0
 ; CHECK: br %r14
   %and = and i32 %a, 3
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; ...and 4.
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: risbg %r2, %r2, 61, 189, 0
 ; CHECK: br %r14
   %and = and i32 %a, 4
@@ -40,7 +40,7 @@ define i32 @f4(i32 %a) {
 
 ; Check the lowest useful NILF value.
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nilf %r2, 5
 ; CHECK: br %r14
   %and = and i32 %a, 5
@@ -49,7 +49,7 @@ define i32 @f5(i32 %a) {
 
 ; Check the highest 16-bit constant that must be handled by NILF.
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nilf %r2, 65533
 ; CHECK: br %r14
   %and = and i32 %a, 65533
@@ -58,7 +58,7 @@ define i32 @f6(i32 %a) {
 
 ; ANDs of 0xffff are zero extensions from i16.
 define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llhr %r2, %r2
 ; CHECK: br %r14
   %and = and i32 %a, 65535
@@ -67,7 +67,7 @@ define i32 @f7(i32 %a) {
 
 ; Check the next value up, which can use RISBG.
 define i32 @f8(i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: risbg %r2, %r2, 47, 175, 0
 ; CHECK: br %r14
   %and = and i32 %a, 65536
@@ -76,7 +76,7 @@ define i32 @f8(i32 %a) {
 
 ; Check the next value up, which must again use NILF.
 define i32 @f9(i32 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: nilf %r2, 65537
 ; CHECK: br %r14
   %and = and i32 %a, 65537
@@ -85,7 +85,7 @@ define i32 @f9(i32 %a) {
 
 ; This value is in range of NILH, but we use RISBG instead.
 define i32 @f10(i32 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: risbg %r2, %r2, 47, 191, 0
 ; CHECK: br %r14
   %and = and i32 %a, 131071
@@ -94,7 +94,7 @@ define i32 @f10(i32 %a) {
 
 ; Check the lowest useful NILH value.
 define i32 @f11(i32 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: nilh %r2, 2
 ; CHECK: br %r14
   %and = and i32 %a, 196607
@@ -103,7 +103,7 @@ define i32 @f11(i32 %a) {
 
 ; Check the highest useful NILH value.
 define i32 @f12(i32 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: nilh %r2, 65530
 ; CHECK: br %r14
   %and = and i32 %a, -327681
@@ -112,7 +112,7 @@ define i32 @f12(i32 %a) {
 
 ; Check the equivalent of NILH of 65531, which can use RISBG.
 define i32 @f13(i32 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: risbg %r2, %r2, 46, 172, 0
 ; CHECK: br %r14
   %and = and i32 %a, -262145
@@ -121,7 +121,7 @@ define i32 @f13(i32 %a) {
 
 ; ...same for 65532.
 define i32 @f14(i32 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: risbg %r2, %r2, 48, 173, 0
 ; CHECK: br %r14
   %and = and i32 %a, -196609
@@ -130,7 +130,7 @@ define i32 @f14(i32 %a) {
 
 ; ...and 65533.
 define i32 @f15(i32 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: risbg %r2, %r2, 47, 173, 0
 ; CHECK: br %r14
   %and = and i32 %a, -131073
@@ -139,7 +139,7 @@ define i32 @f15(i32 %a) {
 
 ; Check the highest useful NILF value.
 define i32 @f16(i32 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: nilf %r2, 4294901758
 ; CHECK: br %r14
   %and = and i32 %a, -65538
@@ -149,7 +149,7 @@ define i32 @f16(i32 %a) {
 ; Check the next value up, which is the equivalent of an NILH of 65534.
 ; We use RISBG instead.
 define i32 @f17(i32 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: risbg %r2, %r2, 48, 174, 0
 ; CHECK: br %r14
   %and = and i32 %a, -65537
@@ -158,7 +158,7 @@ define i32 @f17(i32 %a) {
 
 ; Check the next value up, which can also use RISBG.
 define i32 @f18(i32 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: risbg %r2, %r2, 32, 175, 0
 ; CHECK: br %r14
   %and = and i32 %a, -65536
@@ -167,7 +167,7 @@ define i32 @f18(i32 %a) {
 
 ; ...and again.
 define i32 @f19(i32 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: risbg %r2, %r2, 63, 175, 0
 ; CHECK: br %r14
   %and = and i32 %a, -65535
@@ -176,7 +176,7 @@ define i32 @f19(i32 %a) {
 
 ; Check the next value up again, which is the lowest useful NILL value.
 define i32 @f20(i32 %a) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK: nill %r2, 2
 ; CHECK: br %r14
   %and = and i32 %a, -65534
@@ -185,7 +185,7 @@ define i32 @f20(i32 %a) {
 
 ; Check the highest useful NILL value.
 define i32 @f21(i32 %a) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK: nill %r2, 65530
 ; CHECK: br %r14
   %and = and i32 %a, -6
@@ -194,7 +194,7 @@ define i32 @f21(i32 %a) {
 
 ; Check the next value up, which can use RISBG.
 define i32 @f22(i32 %a) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK: risbg %r2, %r2, 62, 188, 0
 ; CHECK: br %r14
   %and = and i32 %a, -5
@@ -203,7 +203,7 @@ define i32 @f22(i32 %a) {
 
 ; ...and again.
 define i32 @f23(i32 %a) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
 ; CHECK: risbg %r2, %r2, 32, 189, 0
 ; CHECK: br %r14
   %and = and i32 %a, -4
@@ -212,7 +212,7 @@ define i32 @f23(i32 %a) {
 
 ; ...and again.
 define i32 @f24(i32 %a) {
-; CHECK: f24:
+; CHECK-LABEL: f24:
 ; CHECK: risbg %r2, %r2, 63, 189, 0
 ; CHECK: br %r14
   %and = and i32 %a, -3
@@ -221,7 +221,7 @@ define i32 @f24(i32 %a) {
 
 ; Check the last useful mask.
 define i32 @f25(i32 %a) {
-; CHECK: f25:
+; CHECK-LABEL: f25:
 ; CHECK: risbg %r2, %r2, 32, 190, 0
 ; CHECK: br %r14
   %and = and i32 %a, -2
diff --git a/test/CodeGen/SystemZ/and-03.ll b/test/CodeGen/SystemZ/and-03.ll
index 172098b..ca262cf 100644
--- a/test/CodeGen/SystemZ/and-03.ll
+++ b/test/CodeGen/SystemZ/and-03.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check NGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ngr %r2, %r3
 ; CHECK: br %r14
   %and = and i64 %a, %b
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check NG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ng %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -25,7 +25,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned NG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ng %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ng %r2, 0(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned NG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ng %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -60,7 +60,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the NG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ng %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: ng %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that NG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ng %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that ANDs of spilled values can use NG rather than NGR.
 define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: ng %r2, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/and-04.ll b/test/CodeGen/SystemZ/and-04.ll
index e94def6..9c2f4a6 100644
--- a/test/CodeGen/SystemZ/and-04.ll
+++ b/test/CodeGen/SystemZ/and-04.ll
@@ -4,7 +4,7 @@
 
 ; Use RISBG for a single bit.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: risbg %r2, %r2, 63, 191, 0
 ; CHECK: br %r14
   %and = and i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Likewise 0xfffe.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: risbg %r2, %r2, 48, 190, 0
 ; CHECK: br %r14
   %and = and i64 %a, 65534
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; ...but 0xffff is a 16-bit zero extension.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llghr %r2, %r2
 ; CHECK: br %r14
   %and = and i64 %a, 65535
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check the next value up, which can again use RISBG.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: risbg %r2, %r2, 47, 175, 0
 ; CHECK: br %r14
   %and = and i64 %a, 65536
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a) {
 
 ; Check 0xfffffffe, which can also use RISBG.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: risbg %r2, %r2, 32, 190, 0
 ; CHECK: br %r14
   %and = and i64 %a, 4294967294
@@ -49,7 +49,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the next value up, which is a 32-bit zero extension.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: llgfr %r2, %r2
 ; CHECK: br %r14
   %and = and i64 %a, 4294967295
@@ -58,7 +58,7 @@ define i64 @f6(i64 %a) {
 
 ; Check the lowest useful NIHF value (0x00000002_ffffffff).
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: nihf %r2, 2
 ; CHECK: br %r14
   %and = and i64 %a, 12884901887
@@ -67,7 +67,7 @@ define i64 @f7(i64 %a) {
 
 ; Check the lowest useful NIHH value (0x0002ffff_ffffffff).
 define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: nihh %r2, 2
 ; CHECK: br %r14
   %and = and i64 %a, 844424930131967
@@ -76,7 +76,7 @@ define i64 @f8(i64 %a) {
 
 ; Check the highest useful NIHH value (0xfffaffff_ffffffff).
 define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: nihh %r2, 65530
 ; CHECK: br %r14
   %and = and i64 %a, -1407374883553281
@@ -85,7 +85,7 @@ define i64 @f9(i64 %a) {
 
 ; Check the highest useful NIHF value (0xfffefffe_ffffffff).
 define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: nihf %r2, 4294901758
 ; CHECK: br %r14
   %and = and i64 %a, -281479271677953
@@ -94,7 +94,7 @@ define i64 @f10(i64 %a) {
 
 ; Check the lowest useful NIHL value (0xffff0002_ffffffff).
 define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: nihl %r2, 2
 ; CHECK: br %r14
   %and = and i64 %a, -281462091808769
@@ -103,7 +103,7 @@ define i64 @f11(i64 %a) {
 
 ; Check the highest useful NIHL value (0xfffffffa_ffffffff).
 define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: nihl %r2, 65530
 ; CHECK: br %r14
   %and = and i64 %a, -21474836481
@@ -112,7 +112,7 @@ define i64 @f12(i64 %a) {
 
 ; Check the lowest useful NILF range (0xffffffff_00000002).
 define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: nilf %r2, 2
 ; CHECK: br %r14
   %and = and i64 %a, -4294967294
@@ -121,7 +121,7 @@ define i64 @f13(i64 %a) {
 
 ; Check the low end of the NILH range (0xffffffff_0002ffff).
 define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: nilh %r2, 2
 ; CHECK: br %r14
   %and = and i64 %a, -4294770689
@@ -130,7 +130,7 @@ define i64 @f14(i64 %a) {
 
 ; Check the next value up, which must use NILF.
 define i64 @f15(i64 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: nilf %r2, 196608
 ; CHECK: br %r14
   %and = and i64 %a, -4294770688
@@ -139,7 +139,7 @@ define i64 @f15(i64 %a) {
 
 ; Check the highest useful NILH value (0xffffffff_fffaffff).
 define i64 @f16(i64 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: nilh %r2, 65530
 ; CHECK: br %r14
   %and = and i64 %a, -327681
@@ -148,7 +148,7 @@ define i64 @f16(i64 %a) {
 
 ; Check the maximum useful NILF value (0xffffffff_fffefffe).
 define i64 @f17(i64 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: nilf %r2, 4294901758
 ; CHECK: br %r14
   %and = and i64 %a, -65538
@@ -157,7 +157,7 @@ define i64 @f17(i64 %a) {
 
 ; Check the lowest useful NILL value (0xffffffff_ffff0002).
 define i64 @f18(i64 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: nill %r2, 2
 ; CHECK: br %r14
   %and = and i64 %a, -65534
@@ -166,7 +166,7 @@ define i64 @f18(i64 %a) {
 
 ; Check the highest useful NILL value.
 define i64 @f19(i64 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: nill %r2, 65530
 ; CHECK: br %r14
   %and = and i64 %a, -6
diff --git a/test/CodeGen/SystemZ/and-05.ll b/test/CodeGen/SystemZ/and-05.ll
index 4573911..dafd9d5 100644
--- a/test/CodeGen/SystemZ/and-05.ll
+++ b/test/CodeGen/SystemZ/and-05.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful constant, expressed as a signed integer.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ni 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a signed integer.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -26,7 +26,7 @@ define void @f2(i8 *%ptr) {
 
 ; Check the lowest useful constant, expressed as an unsigned integer.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ni 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -37,7 +37,7 @@ define void @f3(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a unsigned integer.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -48,7 +48,7 @@ define void @f4(i8 *%ptr) {
 
 ; Check the high end of the NI range.
 define void @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ni 4095(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -60,7 +60,7 @@ define void @f5(i8 *%src) {
 
 ; Check the next byte up, which should use NIY instead of NI.
 define void @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: niy 4096(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -72,7 +72,7 @@ define void @f6(i8 *%src) {
 
 ; Check the high end of the NIY range.
 define void @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: niy 524287(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -85,7 +85,7 @@ define void @f7(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, 524288
 ; CHECK: ni 0(%r2), 127
 ; CHECK: br %r14
@@ -98,7 +98,7 @@ define void @f8(i8 *%src) {
 
 ; Check the high end of the negative NIY range.
 define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: niy -1(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -110,7 +110,7 @@ define void @f9(i8 *%src) {
 
 ; Check the low end of the NIY range.
 define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: niy -524288(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -123,7 +123,7 @@ define void @f10(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, -524289
 ; CHECK: ni 0(%r2), 127
 ; CHECK: br %r14
@@ -136,7 +136,7 @@ define void @f11(i8 *%src) {
 
 ; Check that NI does not allow an index
 define void @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agr %r2, %r3
 ; CHECK: ni 4095(%r2), 127
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define void @f12(i64 %src, i64 %index) {
 
 ; Check that NIY does not allow an index
 define void @f13(i64 %src, i64 %index) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agr %r2, %r3
 ; CHECK: niy 4096(%r2), 127
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/and-06.ll b/test/CodeGen/SystemZ/and-06.ll
index bbb5e7b..f796618 100644
--- a/test/CodeGen/SystemZ/and-06.ll
+++ b/test/CodeGen/SystemZ/and-06.ll
@@ -5,7 +5,7 @@
 
 ; Zero extension to 32 bits, negative constant.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -18,7 +18,7 @@ define void @f1(i8 *%ptr) {
 
 ; Zero extension to 64 bits, negative constant.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -31,7 +31,7 @@ define void @f2(i8 *%ptr) {
 
 ; Zero extension to 32 bits, positive constant.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define void @f3(i8 *%ptr) {
 
 ; Zero extension to 64 bits, positive constant.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -57,7 +57,7 @@ define void @f4(i8 *%ptr) {
 
 ; Sign extension to 32 bits, negative constant.
 define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -70,7 +70,7 @@ define void @f5(i8 *%ptr) {
 
 ; Sign extension to 64 bits, negative constant.
 define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -83,7 +83,7 @@ define void @f6(i8 *%ptr) {
 
 ; Sign extension to 32 bits, positive constant.
 define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -96,7 +96,7 @@ define void @f7(i8 *%ptr) {
 
 ; Sign extension to 64 bits, positive constant.
 define void @f8(i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/args-01.ll b/test/CodeGen/SystemZ/args-01.ll
index 50e8003..3105503 100644
--- a/test/CodeGen/SystemZ/args-01.ll
+++ b/test/CodeGen/SystemZ/args-01.ll
@@ -20,7 +20,7 @@ declare void @bar(i8, i16, i32, i64, float, double, fp128, i64,
 ; The order of the CHECK-STACK stores doesn't matter.  It would be OK to reorder
 ; them in response to future code changes.
 define void @foo() {
-; CHECK-INT: foo:
+; CHECK-INT-LABEL: foo:
 ; CHECK-INT-DAG: lhi %r2, 1
 ; CHECK-INT-DAG: lhi %r3, 2
 ; CHECK-INT-DAG: lhi %r4, 3
@@ -28,31 +28,31 @@ define void @foo() {
 ; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
 ; CHECK-INT: brasl %r14, bar@PLT
 ;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
 ; CHECK-FLOAT: lzer %f0
 ; CHECK-FLOAT: lcebr %f4, %f0
 ; CHECK-FLOAT: brasl %r14, bar@PLT
 ;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
 ; CHECK-DOUBLE: lzdr %f2
 ; CHECK-DOUBLE: lcdbr %f6, %f2
 ; CHECK-DOUBLE: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
 ; CHECK-FP128-1: aghi %r15, -256
 ; CHECK-FP128-1: lzxr %f0
 ; CHECK-FP128-1-DAG: std %f0, 224(%r15)
 ; CHECK-FP128-1-DAG: std %f2, 232(%r15)
 ; CHECK-FP128-1: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
 ; CHECK-FP128-2: aghi %r15, -256
 ; CHECK-FP128-2: lzxr %f0
 ; CHECK-FP128-2-DAG: std %f0, 240(%r15)
 ; CHECK-FP128-2-DAG: std %f2, 248(%r15)
 ; CHECK-FP128-2: brasl %r14, bar@PLT
 ;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
 ; CHECK-STACK: aghi %r15, -256
 ; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
 ; CHECK-STACK: stg [[REGISTER]], 216(%r15)
diff --git a/test/CodeGen/SystemZ/args-02.ll b/test/CodeGen/SystemZ/args-02.ll
index b964d51..8686df8 100644
--- a/test/CodeGen/SystemZ/args-02.ll
+++ b/test/CodeGen/SystemZ/args-02.ll
@@ -21,7 +21,7 @@ declare void @bar(i8 signext, i16 signext, i32 signext, i64, float, double,
 ; The order of the CHECK-STACK stores doesn't matter.  It would be OK to reorder
 ; them in response to future code changes.
 define void @foo() {
-; CHECK-INT: foo:
+; CHECK-INT-LABEL: foo:
 ; CHECK-INT-DAG: lghi %r2, -1
 ; CHECK-INT-DAG: lghi %r3, -2
 ; CHECK-INT-DAG: lghi %r4, -3
@@ -29,31 +29,31 @@ define void @foo() {
 ; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
 ; CHECK-INT: brasl %r14, bar@PLT
 ;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
 ; CHECK-FLOAT: lzer %f0
 ; CHECK-FLOAT: lcebr %f4, %f0
 ; CHECK-FLOAT: brasl %r14, bar@PLT
 ;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
 ; CHECK-DOUBLE: lzdr %f2
 ; CHECK-DOUBLE: lcdbr %f6, %f2
 ; CHECK-DOUBLE: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
 ; CHECK-FP128-1: aghi %r15, -256
 ; CHECK-FP128-1: lzxr %f0
 ; CHECK-FP128-1-DAG: std %f0, 224(%r15)
 ; CHECK-FP128-1-DAG: std %f2, 232(%r15)
 ; CHECK-FP128-1: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
 ; CHECK-FP128-2: aghi %r15, -256
 ; CHECK-FP128-2: lzxr %f0
 ; CHECK-FP128-2-DAG: std %f0, 240(%r15)
 ; CHECK-FP128-2-DAG: std %f2, 248(%r15)
 ; CHECK-FP128-2: brasl %r14, bar@PLT
 ;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
 ; CHECK-STACK: aghi %r15, -256
 ; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
 ; CHECK-STACK: stg [[REGISTER]], 216(%r15)
diff --git a/test/CodeGen/SystemZ/args-03.ll b/test/CodeGen/SystemZ/args-03.ll
index 28c3338..d7d3ea1 100644
--- a/test/CodeGen/SystemZ/args-03.ll
+++ b/test/CodeGen/SystemZ/args-03.ll
@@ -21,7 +21,7 @@ declare void @bar(i8 zeroext, i16 zeroext, i32 zeroext, i64, float, double,
 ; The order of the CHECK-STACK stores doesn't matter.  It would be OK to reorder
 ; them in response to future code changes.
 define void @foo() {
-; CHECK-INT: foo:
+; CHECK-INT-LABEL: foo:
 ; CHECK-INT-DAG: lghi %r2, 255
 ; CHECK-INT-DAG: llill %r3, 65534
 ; CHECK-INT-DAG: llilf %r4, 4294967293
@@ -29,31 +29,31 @@ define void @foo() {
 ; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
 ; CHECK-INT: brasl %r14, bar@PLT
 ;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
 ; CHECK-FLOAT: lzer %f0
 ; CHECK-FLOAT: lcebr %f4, %f0
 ; CHECK-FLOAT: brasl %r14, bar@PLT
 ;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
 ; CHECK-DOUBLE: lzdr %f2
 ; CHECK-DOUBLE: lcdbr %f6, %f2
 ; CHECK-DOUBLE: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
 ; CHECK-FP128-1: aghi %r15, -256
 ; CHECK-FP128-1: lzxr %f0
 ; CHECK-FP128-1-DAG: std %f0, 224(%r15)
 ; CHECK-FP128-1-DAG: std %f2, 232(%r15)
 ; CHECK-FP128-1: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
 ; CHECK-FP128-2: aghi %r15, -256
 ; CHECK-FP128-2: lzxr %f0
 ; CHECK-FP128-2-DAG: std %f0, 240(%r15)
 ; CHECK-FP128-2-DAG: std %f2, 248(%r15)
 ; CHECK-FP128-2: brasl %r14, bar@PLT
 ;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
 ; CHECK-STACK: aghi %r15, -256
 ; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
 ; CHECK-STACK: stg [[REGISTER]], 216(%r15)
diff --git a/test/CodeGen/SystemZ/args-04.ll b/test/CodeGen/SystemZ/args-04.ll
index 8340494..1178bb4 100644
--- a/test/CodeGen/SystemZ/args-04.ll
+++ b/test/CodeGen/SystemZ/args-04.ll
@@ -5,7 +5,7 @@
 
 ; Do some arithmetic so that we can see the register being used.
 define i8 @f1(i8 %r2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ahi %r2, 1
 ; CHECK: br %r14
   %y = add i8 %r2, 1
@@ -13,21 +13,21 @@ define i8 @f1(i8 %r2) {
 }
 
 define i16 @f2(i8 %r2, i16 %r3) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: {{lr|lgr}} %r2, %r3
 ; CHECK: br %r14
   ret i16 %r3
 }
 
 define i32 @f3(i8 %r2, i16 %r3, i32 %r4) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: {{lr|lgr}} %r2, %r4
 ; CHECK: br %r14
   ret i32 %r4
 }
 
 define i64 @f4(i8 %r2, i16 %r3, i32 %r4, i64 %r5) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: {{lr|lgr}} %r2, %r5
 ; CHECK: br %r14
   ret i64 %r5
@@ -35,7 +35,7 @@ define i64 @f4(i8 %r2, i16 %r3, i32 %r4, i64 %r5) {
 
 ; Do some arithmetic so that we can see the register being used.
 define float @f5(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aebr %f0, %f0
 ; CHECK: br %r14
   %y = fadd float %f0, %f0
@@ -43,7 +43,7 @@ define float @f5(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0) {
 }
 
 define double @f6(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   ret double %f2
@@ -54,7 +54,7 @@ define double @f6(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2) {
 ; be copied.
 define void @f7(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                 fp128 %r6) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ld %f0, 0(%r6)
 ; CHECK: ld %f2, 8(%r6)
 ; CHECK: axbr %f0, %f0
@@ -68,7 +68,7 @@ define void @f7(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 
 define i64 @f8(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                fp128 %r6, i64 %s1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lg %r2, 160(%r15)
 ; CHECK: br %r14
   ret i64 %s1
@@ -76,7 +76,7 @@ define i64 @f8(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 
 define float @f9(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                  fp128 %r6, i64 %s1, float %f4) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ler %f0, %f4
 ; CHECK: br %r14
   ret float %f4
@@ -84,7 +84,7 @@ define float @f9(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 
 define double @f10(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                    fp128 %r6, i64 %s1, float %f4, double %f6) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ldr %f0, %f6
 ; CHECK: br %r14
   ret double %f6
@@ -92,7 +92,7 @@ define double @f10(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 
 define i64 @f11(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                 fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lg %r2, 168(%r15)
 ; CHECK: br %r14
   ret i64 %s2
@@ -102,7 +102,7 @@ define i64 @f11(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 define float @f12(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                   fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2,
                   float %s3) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: le %f0, 180(%r15)
 ; CHECK: br %r14
   ret float %s3
@@ -112,7 +112,7 @@ define float @f12(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 define void @f13(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                  fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2,
                  float %s3, fp128 %s4) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: lg [[REGISTER:%r[1-5]+]], 184(%r15)
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: ld %f2, 8([[REGISTER]])
diff --git a/test/CodeGen/SystemZ/args-05.ll b/test/CodeGen/SystemZ/args-05.ll
index 9fa193a..8a6ef4c 100644
--- a/test/CodeGen/SystemZ/args-05.ll
+++ b/test/CodeGen/SystemZ/args-05.ll
@@ -4,7 +4,7 @@
 
 ; Zero extension of something that is already zero-extended.
 define void @f1(i32 zeroext %r2, i64 *%r3) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: stg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define void @f1(i32 zeroext %r2, i64 *%r3) {
 
 ; Sign extension of something that is already sign-extended.
 define void @f2(i32 signext %r2, i64 *%r3) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: stg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define void @f2(i32 signext %r2, i64 *%r3) {
 
 ; Sign extension of something that is already zero-extended.
 define void @f3(i32 zeroext %r2, i64 *%r3) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgfr [[REGISTER:%r[0-5]+]], %r2
 ; CHECK: stg [[REGISTER]], 0(%r3)
 ; CHECK: br %r14
@@ -37,7 +37,7 @@ define void @f3(i32 zeroext %r2, i64 *%r3) {
 
 ; Zero extension of something that is already sign-extended.
 define void @f4(i32 signext %r2, i64 *%r3) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgfr [[REGISTER:%r[0-5]+]], %r2
 ; CHECK: stg [[REGISTER]], 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/args-06.ll b/test/CodeGen/SystemZ/args-06.ll
index b2f8bee..a89fe9b 100644
--- a/test/CodeGen/SystemZ/args-06.ll
+++ b/test/CodeGen/SystemZ/args-06.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i8 @f1(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ar %r2, %r3
 ; CHECK: ar %r2, %r4
 ; CHECK: ar %r2, %r5
@@ -22,7 +22,7 @@ define i8 @f1(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g) {
 }
 
 define i16 @f2(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ar %r2, %r3
 ; CHECK: ar %r2, %r4
 ; CHECK: ar %r2, %r5
@@ -40,7 +40,7 @@ define i16 @f2(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g) {
 }
 
 define i32 @f3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ar %r2, %r3
 ; CHECK: ar %r2, %r4
 ; CHECK: ar %r2, %r5
@@ -58,7 +58,7 @@ define i32 @f3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) {
 }
 
 define i64 @f4(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agr %r2, %r3
 ; CHECK: agr %r2, %r4
 ; CHECK: agr %r2, %r5
diff --git a/test/CodeGen/SystemZ/asm-01.ll b/test/CodeGen/SystemZ/asm-01.ll
index 016d04c..801378c 100644
--- a/test/CodeGen/SystemZ/asm-01.ll
+++ b/test/CodeGen/SystemZ/asm-01.ll
@@ -5,7 +5,7 @@
 
 ; Check the lowest range.
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
@@ -15,7 +15,7 @@ define void @f1(i64 %base) {
 
 ; Check the next lowest byte.
 define void @f2(i64 %base) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r2, -1
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ define void @f2(i64 %base) {
 
 ; Check the highest range.
 define void @f3(i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah 4095(%r2)
 ; CHECK: br %r14
   %add = add i64 %base, 4095
@@ -38,7 +38,7 @@ define void @f3(i64 %base) {
 
 ; Check the next highest byte.
 define void @f4(i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define void @f4(i64 %base) {
 
 ; Check that indices aren't allowed
 define void @f5(i64 %base, i64 %index) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agr %r2, %r3
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-02.ll b/test/CodeGen/SystemZ/asm-02.ll
index 12d8bec..ad1e35b 100644
--- a/test/CodeGen/SystemZ/asm-02.ll
+++ b/test/CodeGen/SystemZ/asm-02.ll
@@ -5,7 +5,7 @@
 
 ; Check the lowest range.
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
@@ -15,7 +15,7 @@ define void @f1(i64 %base) {
 
 ; Check the next lowest byte.
 define void @f2(i64 %base) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r2, -1
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ define void @f2(i64 %base) {
 
 ; Check the highest range.
 define void @f3(i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah 4095(%r2)
 ; CHECK: br %r14
   %add = add i64 %base, 4095
@@ -38,7 +38,7 @@ define void @f3(i64 %base) {
 
 ; Check the next highest byte.
 define void @f4(i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-03.ll b/test/CodeGen/SystemZ/asm-03.ll
index a6f3f2a..fa3e1a7 100644
--- a/test/CodeGen/SystemZ/asm-03.ll
+++ b/test/CodeGen/SystemZ/asm-03.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
diff --git a/test/CodeGen/SystemZ/asm-04.ll b/test/CodeGen/SystemZ/asm-04.ll
index 0560949..af7ea9f 100644
--- a/test/CodeGen/SystemZ/asm-04.ll
+++ b/test/CodeGen/SystemZ/asm-04.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
diff --git a/test/CodeGen/SystemZ/asm-05.ll b/test/CodeGen/SystemZ/asm-05.ll
index dae90b0..e18cb75 100644
--- a/test/CodeGen/SystemZ/asm-05.ll
+++ b/test/CodeGen/SystemZ/asm-05.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
diff --git a/test/CodeGen/SystemZ/asm-06.ll b/test/CodeGen/SystemZ/asm-06.ll
index c0e24a3..f9848a2 100644
--- a/test/CodeGen/SystemZ/asm-06.ll
+++ b/test/CodeGen/SystemZ/asm-06.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r1, 1
 ; CHECK: blah %r2 %r1
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define i64 @f1() {
 }
 
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r1, 2
 ; CHECK: blah %r2 %r1
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define i64 @f2() {
 }
 
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lhi %r1, 3
 ; CHECK: blah %r2 %r1
 ; CHECK: br %r14
@@ -30,7 +30,7 @@ define i64 @f3() {
 }
 
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lghi %r1, 4
 ; CHECK: blah %r2 %r1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-07.ll b/test/CodeGen/SystemZ/asm-07.ll
index e07286d..bf63150 100644
--- a/test/CodeGen/SystemZ/asm-07.ll
+++ b/test/CodeGen/SystemZ/asm-07.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r0, 1
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define i64 @f1() {
 }
 
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r0, 2
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define i64 @f2() {
 }
 
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lhi %r0, 3
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -30,7 +30,7 @@ define i64 @f3() {
 }
 
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lghi %r0, 4
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-08.ll b/test/CodeGen/SystemZ/asm-08.ll
index 15abc4d..1662337 100644
--- a/test/CodeGen/SystemZ/asm-08.ll
+++ b/test/CodeGen/SystemZ/asm-08.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r0, 1
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define i64 @f1() {
 }
 
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r0, 2
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define i64 @f2() {
 }
 
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lhi %r0, 3
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -30,7 +30,7 @@ define i64 @f3() {
 }
 
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lghi %r0, 4
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-09.ll b/test/CodeGen/SystemZ/asm-09.ll
index 1541170..5cd7efb 100644
--- a/test/CodeGen/SystemZ/asm-09.ll
+++ b/test/CodeGen/SystemZ/asm-09.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i32 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r0, 100
 ; CHECK: blah %r0
 ; CHECK: st %r0, 0(%r2)
@@ -14,7 +14,7 @@ define void @f1(i32 *%dst) {
 }
 
 define void @f2(i32 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r0, 101
 ; CHECK: blah %r0
 ; CHECK: st %r0, 0(%r2)
@@ -25,7 +25,7 @@ define void @f2(i32 *%dst) {
 }
 
 define void @f3(i32 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lhi %r0, 102
 ; CHECK: blah %r0
 ; CHECK: st %r0, 0(%r2)
@@ -37,7 +37,7 @@ define void @f3(i32 *%dst) {
 
 ; FIXME: this uses "lhi %r0, 103", but should use "lghi %r0, 103".
 define void @f4(i32 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: blah %r0
 ; CHECK: st %r0, 0(%r2)
 ; CHECK: br %r14
@@ -47,7 +47,7 @@ define void @f4(i32 *%dst) {
 }
 
 define i64 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lghi %r2, 104
 ; CHECK: blah %r2
 ; CHECK: br %r14
@@ -56,7 +56,7 @@ define i64 @f5() {
 }
 
 define i64 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lghi %r2, 105
 ; CHECK: blah %r2
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define i64 @f6() {
 }
 
 define i64 @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lghi %r2, 106
 ; CHECK: blah %r2
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define i64 @f7() {
 }
 
 define i64 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lghi %r2, 107
 ; CHECK: blah %r2
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-10.ll b/test/CodeGen/SystemZ/asm-10.ll
index 676c202..0eccc19 100644
--- a/test/CodeGen/SystemZ/asm-10.ll
+++ b/test/CodeGen/SystemZ/asm-10.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lzer %f1
 ; CHECK: blah %f0 %f1
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define float @f1() {
 }
 
 define double @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lzdr %f1
 ; CHECK: blah %f0 %f1
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define double @f2() {
 }
 
 define double @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lzxr %f1
 ; CHECK: blah %f0 %f1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-11.ll b/test/CodeGen/SystemZ/asm-11.ll
index 9bd8d7c..8aeb784 100644
--- a/test/CodeGen/SystemZ/asm-11.ll
+++ b/test/CodeGen/SystemZ/asm-11.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the first valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi [[REG:%r[0-5]]], -1
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 0
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 0)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test the last valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah %r2 255
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 255)
@@ -32,7 +32,7 @@ define i32 @f3() {
 
 ; Test 1 above the last valid value.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lhi [[REG:%r[0-5]]], 256
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-12.ll b/test/CodeGen/SystemZ/asm-12.ll
index dd920f1..feecbac 100644
--- a/test/CodeGen/SystemZ/asm-12.ll
+++ b/test/CodeGen/SystemZ/asm-12.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the first valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi [[REG:%r[0-5]]], -1
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 0
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 0)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test the last valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah %r2 4095
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 4095)
@@ -32,7 +32,7 @@ define i32 @f3() {
 
 ; Test 1 above the last valid value.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lhi [[REG:%r[0-5]]], 4096
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-13.ll b/test/CodeGen/SystemZ/asm-13.ll
index af3fdb3..b881700 100644
--- a/test/CodeGen/SystemZ/asm-13.ll
+++ b/test/CodeGen/SystemZ/asm-13.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the first valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: iilf [[REG:%r[0-5]]], 4294934527
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 -32768
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rK" (i32 -32768)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test the last valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah %r2 32767
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rK" (i32 32767)
@@ -32,7 +32,7 @@ define i32 @f3() {
 
 ; Test 1 above the last valid value.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llill [[REG:%r[0-5]]], 32768
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-14.ll b/test/CodeGen/SystemZ/asm-14.ll
index b6b28d6..bcd8b1e 100644
--- a/test/CodeGen/SystemZ/asm-14.ll
+++ b/test/CodeGen/SystemZ/asm-14.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the first valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: iilf [[REG:%r[0-5]]], 4294443007
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 -524288
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rL" (i32 -524288)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test the last valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah %r2 524287
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rL" (i32 524287)
@@ -32,7 +32,7 @@ define i32 @f3() {
 
 ; Test 1 above the last valid value.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llilh [[REG:%r[0-5]]], 8
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-15.ll b/test/CodeGen/SystemZ/asm-15.ll
index 4d0e2b4..886ee0e 100644
--- a/test/CodeGen/SystemZ/asm-15.ll
+++ b/test/CodeGen/SystemZ/asm-15.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: iilf [[REG:%r[0-5]]], 2147483646
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 2147483647
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483647)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test 1 above the valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llilh [[REG:%r[0-5]]], 32768
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-16.ll b/test/CodeGen/SystemZ/asm-16.ll
index 4d0e2b4..886ee0e 100644
--- a/test/CodeGen/SystemZ/asm-16.ll
+++ b/test/CodeGen/SystemZ/asm-16.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: iilf [[REG:%r[0-5]]], 2147483646
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 2147483647
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483647)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test 1 above the valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llilh [[REG:%r[0-5]]], 32768
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-17.ll b/test/CodeGen/SystemZ/asm-17.ll
index f2fbba6..33234fc 100644
--- a/test/CodeGen/SystemZ/asm-17.ll
+++ b/test/CodeGen/SystemZ/asm-17.ll
@@ -4,7 +4,7 @@
 
 ; Test i32 GPRs.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r4, 1
 ; CHECK: blah %r4
 ; CHECK: lr %r2, %r4
@@ -15,7 +15,7 @@ define i32 @f1() {
 
 ; Test i64 GPRs.
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lghi %r4, 1
 ; CHECK: blah %r4
 ; CHECK: lgr %r2, %r4
@@ -26,7 +26,7 @@ define i64 @f2() {
 
 ; Test i32 FPRs.
 define float @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lzer %f4
 ; CHECK: blah %f4
 ; CHECK: ler %f0, %f4
@@ -37,7 +37,7 @@ define float @f3() {
 
 ; Test i64 FPRs.
 define double @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lzdr %f4
 ; CHECK: blah %f4
 ; CHECK: ldr %f0, %f4
@@ -48,7 +48,7 @@ define double @f4() {
 
 ; Test i128 FPRs.
 define void @f5(fp128 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lzxr %f4
 ; CHECK: blah %f4
 ; CHECK-DAG: std %f4, 0(%r2)
@@ -61,7 +61,7 @@ define void @f5(fp128 *%dest) {
 
 ; Test clobbers of GPRs and CC.
 define i32 @f6(i32 %in) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lr [[REG:%r[01345]]], %r2
 ; CHECK: blah
 ; CHECK: lr %r2, [[REG]]
@@ -72,7 +72,7 @@ define i32 @f6(i32 %in) {
 
 ; Test clobbers of FPRs and CC.
 define float @f7(float %in) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ler [[REG:%f[1-7]]], %f0
 ; CHECK: blah
 ; CHECK: ler %f0, [[REG]]
diff --git a/test/CodeGen/SystemZ/atomic-load-01.ll b/test/CodeGen/SystemZ/atomic-load-01.ll
index 3e86bcf..a5bc883 100644
--- a/test/CodeGen/SystemZ/atomic-load-01.ll
+++ b/test/CodeGen/SystemZ/atomic-load-01.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that loads are handled.
 ; The CS-based sequence is probably far too conservative.
 define i8 @f1(i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs
 ; CHECK: br %r14
   %val = load atomic i8 *%src seq_cst, align 1
diff --git a/test/CodeGen/SystemZ/atomic-load-02.ll b/test/CodeGen/SystemZ/atomic-load-02.ll
index d6168ce..2c9bbdb 100644
--- a/test/CodeGen/SystemZ/atomic-load-02.ll
+++ b/test/CodeGen/SystemZ/atomic-load-02.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that loads are handled.
 ; The CS-based sequence is probably far too conservative.
 define i16 @f1(i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs
 ; CHECK: br %r14
   %val = load atomic i16 *%src seq_cst, align 2
diff --git a/test/CodeGen/SystemZ/atomic-load-03.ll b/test/CodeGen/SystemZ/atomic-load-03.ll
index fcf0cf3..1fb41f5 100644
--- a/test/CodeGen/SystemZ/atomic-load-03.ll
+++ b/test/CodeGen/SystemZ/atomic-load-03.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that loads are handled.
 ; Using CS is probably too conservative.
 define i32 @f1(i32 %dummy, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r2, 0
 ; CHECK: cs %r2, %r2, 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomic-load-04.ll b/test/CodeGen/SystemZ/atomic-load-04.ll
index 9593d35..92cac40 100644
--- a/test/CodeGen/SystemZ/atomic-load-04.ll
+++ b/test/CodeGen/SystemZ/atomic-load-04.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that loads are handled.
 ; Using CSG is probably too conservative.
 define i64 @f1(i64 %dummy, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lghi %r2, 0
 ; CHECK: csg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomic-store-01.ll b/test/CodeGen/SystemZ/atomic-store-01.ll
index b316e5c..53ed24f 100644
--- a/test/CodeGen/SystemZ/atomic-store-01.ll
+++ b/test/CodeGen/SystemZ/atomic-store-01.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that stores are handled.
 ; The CS-based sequence is probably far too conservative.
 define void @f1(i8 %val, i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs
 ; CHECK: br %r14
   store atomic i8 %val, i8 *%src seq_cst, align 1
diff --git a/test/CodeGen/SystemZ/atomic-store-02.ll b/test/CodeGen/SystemZ/atomic-store-02.ll
index c761714..42d6695 100644
--- a/test/CodeGen/SystemZ/atomic-store-02.ll
+++ b/test/CodeGen/SystemZ/atomic-store-02.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that stores are handled.
 ; The CS-based sequence is probably far too conservative.
 define void @f1(i16 %val, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs
 ; CHECK: br %r14
   store atomic i16 %val, i16 *%src seq_cst, align 2
diff --git a/test/CodeGen/SystemZ/atomic-store-03.ll b/test/CodeGen/SystemZ/atomic-store-03.ll
index cbf1e51..0954f6f 100644
--- a/test/CodeGen/SystemZ/atomic-store-03.ll
+++ b/test/CodeGen/SystemZ/atomic-store-03.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that stores are handled.
 ; Using CS is probably too conservative.
 define void @f1(i32 %val, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r0, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: cs %r0, %r2, 0(%r3)
diff --git a/test/CodeGen/SystemZ/atomic-store-04.ll b/test/CodeGen/SystemZ/atomic-store-04.ll
index a2d83c5..d418278 100644
--- a/test/CodeGen/SystemZ/atomic-store-04.ll
+++ b/test/CodeGen/SystemZ/atomic-store-04.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that stores are handled.
 ; Using CS is probably too conservative.
 define void @f1(i64 %val, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r0, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: csg %r0, %r2, 0(%r3)
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-01.ll b/test/CodeGen/SystemZ/atomicrmw-add-01.ll
index 3074c54..2e1947f 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-01.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: ar {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check addition of -1.  We add 0xff000000 to the rotated word.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi [[ROT]], -16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 -1 seq_cst
   ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check addition of 1.  We add 0x01000000 to the rotated word.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi [[ROT]], 16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We add 0x7f000000 to the rotated word.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi [[ROT]], 2130706432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
 ; Check addition of a large unsigned value.  We add 0xfe000000 to the
 ; rotated word, expressed as a negative AFI operand.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi [[ROT]], -33554432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 254 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-02.ll b/test/CodeGen/SystemZ/atomicrmw-add-02.ll
index 24c336b..76f7c2e 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-02.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: ar {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check addition of -1.  We add 0xffff0000 to the rotated word.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi [[ROT]], -65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 -1 seq_cst
   ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check addition of 1.  We add 0x00010000 to the rotated word.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi [[ROT]], 65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We add 0x7fff0000 to the rotated word.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi [[ROT]], 2147418112
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
 ; Check addition of a large unsigned value.  We add 0xfffe0000 to the
 ; rotated word, expressed as a negative AFI operand.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi [[ROT]], -131072
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 65534 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-03.ll b/test/CodeGen/SystemZ/atomicrmw-add-03.ll
index e319057..04813f9 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-03.ll
@@ -4,7 +4,7 @@
 
 ; Check addition of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check addition of 1, which can use AHI.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the AHI range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ahi %r0, 32767
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 32767 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which must use AFI.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi %r0, 32768
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 32768 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the AFI range.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi %r0, 2147483647
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 2147483647 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which gets treated as a negative operand.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi %r0, -2147483648
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 2147483648 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check addition of -1, which can use AHI.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ahi %r0, -1
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 -1 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the AHI range.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ahi %r0, -32768
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 -32768 seq_cst
@@ -86,7 +86,7 @@ define i32 @f8(i32 %dummy, i32 *%src) {
 
 ; Check the next value down, which must use AFI instead.
 define i32 @f9(i32 %dummy, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: afi %r0, -32769
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 -32769 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-04.ll b/test/CodeGen/SystemZ/atomicrmw-add-04.ll
index b2cbaca..f3814f2 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-04.ll
@@ -4,7 +4,7 @@
 
 ; Check addition of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check addition of 1, which can use AGHI.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the AGHI range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r0, 32767
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 32767 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use AGFI.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r0, 32768
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 32768 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the AGFI range.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r0, 2147483647
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 2147483647 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register addition.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agr
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 2147483648 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check addition of -1, which can use AGHI.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: aghi %r0, -1
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -1 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the AGHI range.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r0, -32768
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -32768 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
 
 ; Check the next value down, which must use AGFI instead.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r0, -32769
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -32769 seq_cst
@@ -95,7 +95,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the AGFI range.
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r0, -2147483648
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -2147483648 seq_cst
@@ -104,7 +104,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
 
 ; Check the next value down, which must use a register addition.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agr
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -2147483649 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-01.ll b/test/CodeGen/SystemZ/atomicrmw-and-01.ll
index cd4104d..243cf15 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-01.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: oilf %r3, 16777215
 ; CHECK-SHIFT2: rll
@@ -48,7 +48,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We AND the rotated word with 0x80ffffff.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -61,7 +61,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -69,7 +69,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -77,13 +77,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check ANDs of -2 (-1 isn't useful).  We AND the rotated word with 0xfeffffff.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh [[ROT]], 65279
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 -2 seq_cst
   ret i8 %res
@@ -91,13 +91,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check ANDs of 1.  We AND the rotated word with 0x01ffffff.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilh [[ROT]], 511
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -105,13 +105,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We AND the rotated word with 0x7fffffff.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nilh [[ROT]], 32767
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -120,13 +120,13 @@ define i8 @f5(i8 *%src) {
 ; Check ANDs of a large unsigned value.  We AND the rotated word with
 ; 0xfdffffff.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nilh [[ROT]], 65023
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 253 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-02.ll b/test/CodeGen/SystemZ/atomicrmw-and-02.ll
index a19d187..31247a3 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-02.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: oill %r3, 65535
 ; CHECK-SHIFT2: rll
@@ -48,7 +48,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We AND the rotated word with 0x8000ffff.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -61,7 +61,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -69,7 +69,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -77,13 +77,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check ANDs of -2 (-1 isn't useful).  We AND the rotated word with 0xfffeffff.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh [[ROT]], 65534
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 -2 seq_cst
   ret i16 %res
@@ -91,13 +91,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check ANDs of 1.  We AND the rotated word with 0x0001ffff.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilh [[ROT]], 1
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -105,13 +105,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We AND the rotated word with 0x7fffffff.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nilh [[ROT]], 32767
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -120,13 +120,13 @@ define i16 @f5(i16 *%src) {
 ; Check ANDs of a large unsigned value.  We AND the rotated word with
 ; 0xfffdffff.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nilh [[ROT]], 65533
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 65533 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-03.ll b/test/CodeGen/SystemZ/atomicrmw-and-03.ll
index 8449a7c..dd02828 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-03.ll
@@ -4,7 +4,7 @@
 
 ; Check ANDs of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check ANDs of 1.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check ANDs of the low end of the NILH range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 65535 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which must use NILF.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilf %r0, 65536
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 65536 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful NILL value.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nill %r0, 65534
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 -2 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the NILL range.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nill %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 -65536 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful NILH value, which is one less than the above.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: nilh %r0, 65534
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 -65537 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the highest useful NILF value, which is one less than the above.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: nilf %r0, 4294901758
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 -65538 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-04.ll b/test/CodeGen/SystemZ/atomicrmw-and-04.ll
index ade7617..6a9f81a 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-04.ll
@@ -4,7 +4,7 @@
 
 ; Check ANDs of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check ANDs of 1, which must be done using a register.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ngr
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 1 seq_cst
@@ -27,7 +27,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NIHF range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ngr
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 4294967296 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NIHH range.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nihh %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 281474976710655 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ngr
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 281474976710656 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NILL value.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: nill %r0, 65534
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -2 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NILL range.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: nill %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -65536 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NILH value, which is one less than the above.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: nilh %r0, 65534
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -65537 seq_cst
@@ -95,7 +95,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NILF value, which is one less than the above.
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: nilf %r0, 4294901758
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -65538 seq_cst
@@ -104,7 +104,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NILH range.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: nilh %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -4294901761 seq_cst
@@ -113,7 +113,7 @@ define i64 @f11(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NILF range.
 define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: nilf %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -4294967296 seq_cst
@@ -122,7 +122,7 @@ define i64 @f12(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NIHL value, which is one less than the above.
 define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: nihl %r0, 65534
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -4294967297 seq_cst
@@ -131,7 +131,7 @@ define i64 @f13(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NIHL range.
 define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: nihl %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -281470681743361 seq_cst
@@ -140,7 +140,7 @@ define i64 @f14(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NIHH value, which is 1<<32 less than the above.
 define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: nihh %r0, 65534
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -281474976710657 seq_cst
@@ -149,7 +149,7 @@ define i64 @f15(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NIHF value, which is 1<<32 less than the above.
 define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: nihf %r0, 4294901758
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -281479271677953 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
index 9e1e7ff..1a9db87 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -28,7 +28,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -36,7 +36,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3
@@ -49,7 +49,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check signed maximum.
 define i8 @f2(i8 *%src, i8 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -64,7 +64,7 @@ define i8 @f2(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -72,7 +72,7 @@ define i8 @f2(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3
@@ -85,7 +85,7 @@ define i8 @f2(i8 *%src, i8 %b) {
 
 ; Check unsigned minimum.
 define i8 @f3(i8 *%src, i8 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -101,7 +101,7 @@ define i8 @f3(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -109,7 +109,7 @@ define i8 @f3(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -122,7 +122,7 @@ define i8 @f3(i8 *%src, i8 %b) {
 
 ; Check unsigned maximum.
 define i8 @f4(i8 *%src, i8 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -138,7 +138,7 @@ define i8 @f4(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -146,7 +146,7 @@ define i8 @f4(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -160,15 +160,15 @@ define i8 @f4(i8 *%src, i8 %b) {
 ; Check the lowest useful signed minimum value.  We need to load 0x81000000
 ; into the source register.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 33024
 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw min i8 *%src, i8 -127 seq_cst
   ret i8 %res
@@ -177,15 +177,15 @@ define i8 @f5(i8 *%src) {
 ; Check the highest useful signed maximum value.  We need to load 0x7e000000
 ; into the source register.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32256
 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw max i8 *%src, i8 126 seq_cst
   ret i8 %res
@@ -194,15 +194,15 @@ define i8 @f6(i8 *%src) {
 ; Check the lowest useful unsigned minimum value.  We need to load 0x01000000
 ; into the source register.
 define i8 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 256
 ; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f7:
+; CHECK-SHIFT1-LABEL: f7:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f7:
+; CHECK-SHIFT2-LABEL: f7:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw umin i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -211,15 +211,15 @@ define i8 @f7(i8 *%src) {
 ; Check the highest useful unsigned maximum value.  We need to load 0xfe000000
 ; into the source register.
 define i8 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65024
 ; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f8:
+; CHECK-SHIFT1-LABEL: f8:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f8:
+; CHECK-SHIFT2-LABEL: f8:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw umax i8 *%src, i8 254 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
index 78c95df..2f6d3ed 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -28,7 +28,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -36,7 +36,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3
@@ -49,7 +49,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check signed maximum.
 define i16 @f2(i16 *%src, i16 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -64,7 +64,7 @@ define i16 @f2(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -72,7 +72,7 @@ define i16 @f2(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3
@@ -85,7 +85,7 @@ define i16 @f2(i16 *%src, i16 %b) {
 
 ; Check unsigned minimum.
 define i16 @f3(i16 *%src, i16 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -101,7 +101,7 @@ define i16 @f3(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -109,7 +109,7 @@ define i16 @f3(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -122,7 +122,7 @@ define i16 @f3(i16 *%src, i16 %b) {
 
 ; Check unsigned maximum.
 define i16 @f4(i16 *%src, i16 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -138,7 +138,7 @@ define i16 @f4(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -146,7 +146,7 @@ define i16 @f4(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -160,15 +160,15 @@ define i16 @f4(i16 *%src, i16 %b) {
 ; Check the lowest useful signed minimum value.  We need to load 0x80010000
 ; into the source register.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32769
 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw min i16 *%src, i16 -32767 seq_cst
   ret i16 %res
@@ -177,15 +177,15 @@ define i16 @f5(i16 *%src) {
 ; Check the highest useful signed maximum value.  We need to load 0x7ffe0000
 ; into the source register.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32766
 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw max i16 *%src, i16 32766 seq_cst
   ret i16 %res
@@ -194,15 +194,15 @@ define i16 @f6(i16 *%src) {
 ; Check the lowest useful unsigned maximum value.  We need to load 0x00010000
 ; into the source register.
 define i16 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 1
 ; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f7:
+; CHECK-SHIFT1-LABEL: f7:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f7:
+; CHECK-SHIFT2-LABEL: f7:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw umin i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -211,15 +211,15 @@ define i16 @f7(i16 *%src) {
 ; Check the highest useful unsigned maximum value.  We need to load 0xfffe0000
 ; into the source register.
 define i16 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65534
 ; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f8:
+; CHECK-SHIFT1-LABEL: f8:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f8:
+; CHECK-SHIFT2-LABEL: f8:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw umax i16 *%src, i16 65534 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
index 9dca13d..13742b2 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
@@ -4,7 +4,7 @@
 
 ; Check signed minium.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lr [[NEW:%r[0-9]+]], %r2
@@ -19,7 +19,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check signed maximum.
 define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lr [[NEW:%r[0-9]+]], %r2
@@ -34,7 +34,7 @@ define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check unsigned minimum.
 define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: clr %r2, %r4
@@ -50,7 +50,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check unsigned maximum.
 define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: clr %r2, %r4
@@ -66,7 +66,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the aligned CS range.
 define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: l %r2, 4092(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
 ; CHECK: br %r14
@@ -77,7 +77,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word up, which requires CSY.
 define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ly %r2, 4096(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the aligned CSY range.
 define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ly %r2, 524284(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
 ; CHECK: br %r14
@@ -99,7 +99,7 @@ define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word up, which needs separate address logic.
 define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, 524288
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -111,7 +111,7 @@ define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the negative aligned CSY range.
 define i32 @f9(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ly %r2, -4(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define i32 @f9(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the low end of the CSY range.
 define i32 @f10(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ly %r2, -524288(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
@@ -133,7 +133,7 @@ define i32 @f10(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word down, which needs separate address logic.
 define i32 @f11(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r3, -524292
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -145,7 +145,7 @@ define i32 @f11(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check that indexed addresses are not allowed.
 define i32 @f12(i32 %dummy, i64 %base, i64 %index, i32 %b) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agr %r3, %r4
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -158,7 +158,7 @@ define i32 @f12(i32 %dummy, i64 %base, i64 %index, i32 %b) {
 
 ; Check that constants are handled.
 define i32 @f13(i32 %dummy, i32 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: lhi [[LIMIT:%r[0-9]+]], 42
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
index d6b5dcd..9efa16b 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
@@ -4,7 +4,7 @@
 
 ; Check signed minium.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lgr [[NEW:%r[0-9]+]], %r2
@@ -19,7 +19,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check signed maximum.
 define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lgr [[NEW:%r[0-9]+]], %r2
@@ -34,7 +34,7 @@ define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check unsigned minimum.
 define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: clgr %r2, %r4
@@ -50,7 +50,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check unsigned maximum.
 define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: clgr %r2, %r4
@@ -66,7 +66,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the high end of the aligned CSG range.
 define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lg %r2, 524280(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
 ; CHECK: br %r14
@@ -77,7 +77,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the next doubleword up, which requires separate address logic.
 define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -89,7 +89,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the low end of the CSG range.
 define i64 @f7(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lg %r2, -524288(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
@@ -100,7 +100,7 @@ define i64 @f7(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the next doubleword down, which requires separate address logic.
 define i64 @f8(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524296
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -112,7 +112,7 @@ define i64 @f8(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check that indexed addresses are not allowed.
 define i64 @f9(i64 %dummy, i64 %base, i64 %index, i64 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agr %r3, %r4
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -125,7 +125,7 @@ define i64 @f9(i64 %dummy, i64 %base, i64 %index, i64 %b) {
 
 ; Check that constants are handled.
 define i64 @f10(i64 %dummy, i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lghi [[LIMIT:%r[0-9]+]], 42
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-01.ll b/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
index 260286f..cdeeaba 100644
--- a/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -27,7 +27,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -35,7 +35,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: oilf %r3, 16777215
 ; CHECK-SHIFT2: rll
@@ -49,7 +49,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We AND the rotated word with 0x80ffffff.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -63,7 +63,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -71,7 +71,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -79,14 +79,14 @@ define i8 @f2(i8 *%src) {
 
 ; Check NANDs of -2 (-1 isn't useful).  We AND the rotated word with 0xfeffffff.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh [[ROT]], 65279
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 -2 seq_cst
   ret i8 %res
@@ -94,14 +94,14 @@ define i8 @f3(i8 *%src) {
 
 ; Check NANDs of 1.  We AND the rotated word with 0x01ffffff.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilh [[ROT]], 511
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -109,14 +109,14 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We AND the rotated word with 0x7fffffff.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nilh [[ROT]], 32767
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -125,14 +125,14 @@ define i8 @f5(i8 *%src) {
 ; Check NANDs of a large unsigned value.  We AND the rotated word with
 ; 0xfdffffff.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nilh [[ROT]], 65023
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 253 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-02.ll b/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
index 383c2e5..60fdbc7 100644
--- a/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -27,7 +27,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -35,7 +35,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: oill %r3, 65535
 ; CHECK-SHIFT2: rll
@@ -49,7 +49,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We AND the rotated word with 0x8000ffff.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -63,7 +63,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -71,7 +71,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -79,14 +79,14 @@ define i16 @f2(i16 *%src) {
 
 ; Check NANDs of -2 (-1 isn't useful).  We AND the rotated word with 0xfffeffff.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh [[ROT]], 65534
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 -2 seq_cst
   ret i16 %res
@@ -94,14 +94,14 @@ define i16 @f3(i16 *%src) {
 
 ; Check ANDs of 1.  We AND the rotated word with 0x0001ffff.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilh [[ROT]], 1
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -109,14 +109,14 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We AND the rotated word with 0x7fffffff.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nilh [[ROT]], 32767
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -125,14 +125,14 @@ define i16 @f5(i16 *%src) {
 ; Check NANDs of a large unsigned value.  We AND the rotated word with
 ; 0xfffdffff.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nilh [[ROT]], 65533
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 65533 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-03.ll b/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
index 56c2416..be306a2 100644
--- a/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
@@ -4,7 +4,7 @@
 
 ; Check NANDs of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -19,7 +19,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check NANDs of 1.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -34,7 +34,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check NANDs of the low end of the NILH range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh %r0, 0
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which must use NILF.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilf %r0, 65536
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -54,7 +54,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful NILL value.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nill %r0, 65534
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the NILL range.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nill %r0, 0
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful NILH value, which is one less than the above.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: nilh %r0, 65534
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the highest useful NILF value, which is one less than the above.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: nilf %r0, 4294901758
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-04.ll b/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
index dee661c..2fb919d 100644
--- a/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
@@ -4,7 +4,7 @@
 
 ; Check NANDs of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -20,7 +20,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check NANDs of 1, which must be done using a register.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ngr
 ; CHECK: br %r14
   %res = atomicrmw nand i64 *%src, i64 1 seq_cst
@@ -29,7 +29,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NIHF range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -45,7 +45,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ngr
 ; CHECK: br %r14
   %res = atomicrmw nand i64 *%src, i64 4294967296 seq_cst
@@ -54,7 +54,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NIHH range.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nihh %r0, 0
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -65,7 +65,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ngr
 ; CHECK: br %r14
   %res = atomicrmw nand i64 *%src, i64 281474976710656 seq_cst
@@ -74,7 +74,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NILL value.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: nill %r0, 65534
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -85,7 +85,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NILL range.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: nill %r0, 0
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -96,7 +96,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NILH value, which is one less than the above.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: nilh %r0, 65534
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -107,7 +107,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NILF value, which is one less than the above.
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: nilf %r0, 4294901758
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -118,7 +118,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NILH range.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: nilh %r0, 0
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -129,7 +129,7 @@ define i64 @f11(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NILF range.
 define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: nilf %r0, 0
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -140,7 +140,7 @@ define i64 @f12(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NIHL value, which is one less than the above.
 define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: nihl %r0, 65534
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -151,7 +151,7 @@ define i64 @f13(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NIHL range.
 define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: nihl %r0, 0
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -162,7 +162,7 @@ define i64 @f14(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NIHH value, which is 1<<32 less than the above.
 define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: nihh %r0, 65534
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -173,7 +173,7 @@ define i64 @f15(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NIHF value, which is 1<<32 less than the above.
 define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: nihf %r0, 4294901758
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-01.ll b/test/CodeGen/SystemZ/atomicrmw-or-01.ll
index c63087e..fe1beed 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-01.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: or {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We OR the rotated word with 0x80000000.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check ORs of -2 (-1 isn't useful).  We OR the rotated word with 0xfe000000.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oilh [[ROT]], 65024
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 -2 seq_cst
   ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check ORs of 1.  We OR the rotated word with 0x01000000.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilh [[ROT]], 256
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We OR the rotated word with 0x7f000000.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilh [[ROT]], 32512
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
 ; Check ORs of a large unsigned value.  We OR the rotated word with
 ; 0xfd000000.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilh [[ROT]], 64768
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 253 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-02.ll b/test/CodeGen/SystemZ/atomicrmw-or-02.ll
index 3b8efcb..73bc282 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-02.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: or {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We OR the rotated word with 0x80000000.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check ORs of -2 (-1 isn't useful).  We OR the rotated word with 0xfffe0000.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oilh [[ROT]], 65534
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 -2 seq_cst
   ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check ORs of 1.  We OR the rotated word with 0x00010000.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilh [[ROT]], 1
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We OR the rotated word with 0x7fff0000.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilh [[ROT]], 32767
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
 ; Check ORs of a large unsigned value.  We OR the rotated word with
 ; 0xfffd0000.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilh [[ROT]], 65533
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 65533 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-03.ll b/test/CodeGen/SystemZ/atomicrmw-or-03.ll
index 1def200..6386847 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-03.ll
@@ -4,7 +4,7 @@
 
 ; Check ORs of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the lowest useful OILL value.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the OILL range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oill %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 65535 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the lowest useful OILH value, which is the next value up.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilh %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 65536 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the lowest useful OILF value, which is the next value up.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilf %r0, 65537
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 65537 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the OILH range.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilh %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 -65536 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which must use OILF.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oilf %r0, 4294901761
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 -65535 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful OILF value.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oilf %r0, 4294967294
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 -2 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-04.ll b/test/CodeGen/SystemZ/atomicrmw-or-04.ll
index be0b23c..de798be 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-04.ll
@@ -4,7 +4,7 @@
 
 ; Check ORs of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the lowest useful OILL value.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lgr %r0, %r2
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OILL range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oill %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 65535 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OILH value, which is the next value up.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilh %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 65536 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OILF value, which is the next value up again.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilf %r0, 65537
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 65537 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OILH range.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilh %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294901760 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use OILF.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oilf %r0, 4294901761
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294901761 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OILF range.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oilf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294967295 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OIHL value, which is one greater than above.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: oihl %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294967296 seq_cst
@@ -96,7 +96,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
 ; Check the next value up, which must use a register.  (We could use
 ; combinations of OIH* and OIL* instead, but that isn't implemented.)
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ogr
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294967297 seq_cst
@@ -105,7 +105,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OIHL range.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: oihl %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 281470681743360 seq_cst
@@ -114,7 +114,7 @@ define i64 @f11(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OIHH value, which is 1<<32 greater than above.
 define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: oihh %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 281474976710656 seq_cst
@@ -123,7 +123,7 @@ define i64 @f12(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OIHF value, which is 1<<32 greater again.
 define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: oihf %r0, 65537
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 281479271677952 seq_cst
@@ -132,7 +132,7 @@ define i64 @f13(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OIHH range.
 define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: oihh %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 18446462598732840960 seq_cst
@@ -141,7 +141,7 @@ define i64 @f14(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register.
 define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: ogr
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 18446462598732840961 seq_cst
@@ -150,7 +150,7 @@ define i64 @f15(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OIHF range.
 define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: oihf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 -4294967296 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-01.ll b/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
index b17c36f..e1060e0 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: sr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check subtraction of -1.  We add 0x01000000 to the rotated word.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi [[ROT]], 16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 -1 seq_cst
   ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check subtraction of -1.  We add 0xff000000 to the rotated word.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi [[ROT]], -16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We add 0x81000000 to the rotated word.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi [[ROT]], -2130706432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
 ; Check subtraction of a large unsigned value.  We add 0x02000000 to the
 ; rotated word.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi [[ROT]], 33554432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 254 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-02.ll b/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
index dbacacd..499a606 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: sr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check subtraction of -1.  We add 0x00010000 to the rotated word.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi [[ROT]], 65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 -1 seq_cst
   ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check subtraction of 1.  We add 0xffff0000 to the rotated word.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi [[ROT]], -65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We add 0x80010000 to the rotated word.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi [[ROT]], -2147418112
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
 ; Check subtraction of a large unsigned value.  We add 0x00020000 to the
 ; rotated word.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi [[ROT]], 131072
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 65534 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-03.ll b/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
index c2821ad..b0c1769 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
@@ -4,7 +4,7 @@
 
 ; Check subtraction of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check subtraction of 1, which can use AHI.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the AHI range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ahi %r0, -32768
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 32768 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the next value down, which must use AFI.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi %r0, -32769
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 32769 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the AFI range.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi %r0, -2147483648
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 2147483648 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which gets treated as a positive operand.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi %r0, 2147483647
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 2147483649 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check subtraction of -1, which can use AHI.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ahi %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 -1 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the AHI range.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ahi %r0, 32767
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 -32767 seq_cst
@@ -86,7 +86,7 @@ define i32 @f8(i32 %dummy, i32 *%src) {
 
 ; Check the next value down, which must use AFI instead.
 define i32 @f9(i32 %dummy, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: afi %r0, 32768
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 -32768 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-04.ll b/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
index 6b3e1c9..c0fd9f9 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
@@ -4,7 +4,7 @@
 
 ; Check subtraction of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check subtraction of 1, which can use AGHI.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the AGHI range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r0, -32768
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 32768 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use AGFI.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r0, -32769
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 32769 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the AGFI range.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r0, -2147483648
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 2147483648 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register operation.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sgr
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 2147483649 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check subtraction of -1, which can use AGHI.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: aghi %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -1 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the AGHI range.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r0, 32767
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -32767 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
 
 ; Check the next value down, which must use AGFI instead.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r0, 32768
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -32768 seq_cst
@@ -95,7 +95,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the AGFI range.
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r0, 2147483647
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -2147483647 seq_cst
@@ -104,7 +104,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
 
 ; Check the next value down, which must use a register operation.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sgr
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -2147483648 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
index a44eadf..d83408f 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
@@ -11,7 +11,7 @@
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -24,7 +24,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
 ; CHECK-SHIFT-NOT: %r3
 ; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT-NOT: %r3
@@ -43,12 +43,12 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; Check exchange with a constant.  We should force the constant into
 ; a register and use the sequence above.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi [[VALUE:%r[0-9]+]], 88
 ; CHECK: risbg {{%r[0-9]+}}, [[VALUE]], 32, 39, 24
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
 ; CHECK-SHIFT: br %r14
   %res = atomicrmw xchg i8 *%src, i8 88 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
index 1b6e846..b00b341 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
@@ -11,7 +11,7 @@
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -24,7 +24,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
 ; CHECK-SHIFT-NOT: %r3
 ; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT-NOT: %r3
@@ -43,12 +43,12 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; Check exchange with a constant.  We should force the constant into
 ; a register and use the sequence above.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi [[VALUE:%r[0-9]+]], -25536
 ; CHECK: risbg {{%r[0-9]+}}, [[VALUE]], 32, 47, 16
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
 ; CHECK-SHIFT: br %r14
   %res = atomicrmw xchg i16 *%src, i16 40000 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
index 4a48826..e5ba4d5 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
@@ -4,7 +4,7 @@
 
 ; Check register exchange.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: cs %r2, %r4, 0(%r3)
@@ -16,7 +16,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the aligned CS range.
 define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 4092(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word up, which requires CSY.
 define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ly %r2, 4096(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
 ; CHECK: br %r14
@@ -38,7 +38,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the aligned CSY range.
 define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ly %r2, 524284(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word up, which needs separate address logic.
 define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -61,7 +61,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the negative aligned CSY range.
 define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ly %r2, -4(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
 ; CHECK: br %r14
@@ -72,7 +72,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the low end of the CSY range.
 define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ly %r2, -524288(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word down, which needs separate address logic.
 define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524292
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -95,7 +95,7 @@ define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check that indexed addresses are not allowed.
 define i32 @f9(i32 %dummy, i64 %base, i64 %index, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agr %r3, %r4
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -109,7 +109,7 @@ define i32 @f9(i32 %dummy, i64 %base, i64 %index, i32 %b) {
 ; Check exchange of a constant.  We should force it into a register and
 ; use the sequence above.
 define i32 @f10(i32 %dummy, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llill [[VALUE:%r[0-9+]]], 40000
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
index ac1f6cd..c19b34d 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
@@ -4,7 +4,7 @@
 
 ; Check register exchange.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: csg %r2, %r4, 0(%r3)
@@ -16,7 +16,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the high end of the aligned CSG range.
 define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 524280(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the next doubleword up, which requires separate address logic.
 define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r3, 524288
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -39,7 +39,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the low end of the CSG range.
 define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lg %r2, -524288(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the next doubleword down, which requires separate address logic.
 define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, -524296
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -62,7 +62,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check that indexed addresses are not allowed.
 define i64 @f6(i64 %dummy, i64 %base, i64 %index, i64 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agr %r3, %r4
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -76,7 +76,7 @@ define i64 @f6(i64 %dummy, i64 %base, i64 %index, i64 %b) {
 ; Check exchange of a constant.  We should force it into a register and
 ; use the sequence above.
 define i64 @f7(i64 %dummy, i64 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llilf [[VALUE:%r[0-9+]]], 3000000000
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-01.ll b/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
index 5f0957a..b457a60 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: xr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We XOR the rotated word with 0x80000000.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check XORs of -1.  We XOR the rotated word with 0xff000000.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 -1 seq_cst
   ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check XORs of 1.  We XOR the rotated word with 0x01000000.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xilf [[ROT]], 16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We XOR the rotated word with 0x7f000000.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xilf [[ROT]], 2130706432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
 ; Check XORs of a large unsigned value.  We XOR the rotated word with
 ; 0xfd000000.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xilf [[ROT]], 4244635648
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 253 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-02.ll b/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
index cdad3ef..fa38d70 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: xr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We XOR the rotated word with 0x80000000.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check XORs of -1.  We XOR the rotated word with 0xffff0000.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 -1 seq_cst
   ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check XORs of 1.  We XOR the rotated word with 0x00010000.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xilf [[ROT]], 65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We XOR the rotated word with 0x7fff0000.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xilf [[ROT]], 2147418112
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
 ; Check XORs of a large unsigned value.  We XOR the rotated word with
 ; 0xfffd0000.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xilf [[ROT]], 4294770688
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 65533 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-03.ll b/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
index 0c19515..292de36 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
@@ -4,7 +4,7 @@
 
 ; Check XORs of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the lowest useful constant.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check an arbitrary constant.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf %r0, 3000000000
 ; CHECK: br %r14
   %res = atomicrmw xor i32 *%src, i32 3000000000 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check bitwise negation.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw xor i32 *%src, i32 -1 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-04.ll b/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
index 6487b88..d767b20 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
@@ -4,7 +4,7 @@
 
 ; Check XORs of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the lowest useful XILF value.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lgr %r0, %r2
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the XILF range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 4294967295 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful XIHF value, which is one greater than above.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xihf %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 4294967296 seq_cst
@@ -51,7 +51,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 ; Check the next value up, which must use a register.  (We could use
 ; combinations of XIH* and XIL* instead, but that isn't implemented.)
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xgr
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 4294967297 seq_cst
@@ -60,7 +60,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the XIHF range.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xihf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 -4294967296 seq_cst
@@ -69,7 +69,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xgr
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 -4294967295 seq_cst
diff --git a/test/CodeGen/SystemZ/branch-01.ll b/test/CodeGen/SystemZ/branch-01.ll
index f201ddd..12ed2d3 100644
--- a/test/CodeGen/SystemZ/branch-01.ll
+++ b/test/CodeGen/SystemZ/branch-01.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i8 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: mvi 0(%r2), 1
 ; CHECK: j .L[[LABEL]]
diff --git a/test/CodeGen/SystemZ/branch-02.ll b/test/CodeGen/SystemZ/branch-02.ll
index 9f71c05..38b5d27 100644
--- a/test/CodeGen/SystemZ/branch-02.ll
+++ b/test/CodeGen/SystemZ/branch-02.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i32 *%src, i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -20,7 +20,7 @@ exit:
 }
 
 define void @f2(i32 *%src, i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -35,7 +35,7 @@ exit:
 }
 
 define void @f3(i32 *%src, i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -50,7 +50,7 @@ exit:
 }
 
 define void @f4(i32 *%src, i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -65,7 +65,7 @@ exit:
 }
 
 define void @f5(i32 *%src, i32 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -80,7 +80,7 @@ exit:
 }
 
 define void @f6(i32 *%src, i32 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
diff --git a/test/CodeGen/SystemZ/branch-03.ll b/test/CodeGen/SystemZ/branch-03.ll
index 9d00f6e..ef31a9c 100644
--- a/test/CodeGen/SystemZ/branch-03.ll
+++ b/test/CodeGen/SystemZ/branch-03.ll
@@ -3,7 +3,7 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 define void @f1(i32 *%src, i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cl %r3, 0(%r2)
@@ -18,7 +18,7 @@ exit:
 }
 
 define void @f2(i32 *%src, i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cl %r3, 0(%r2)
@@ -33,7 +33,7 @@ exit:
 }
 
 define void @f3(i32 *%src, i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cl %r3, 0(%r2)
@@ -48,7 +48,7 @@ exit:
 }
 
 define void @f4(i32 *%src, i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cl %r3, 0(%r2)
diff --git a/test/CodeGen/SystemZ/branch-04.ll b/test/CodeGen/SystemZ/branch-04.ll
index d6826fb..fafb234 100644
--- a/test/CodeGen/SystemZ/branch-04.ll
+++ b/test/CodeGen/SystemZ/branch-04.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(float *%src, float %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -19,7 +19,7 @@ exit:
 }
 
 define void @f2(float *%src, float %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -34,7 +34,7 @@ exit:
 }
 
 define void @f3(float *%src, float %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -49,7 +49,7 @@ exit:
 }
 
 define void @f4(float *%src, float %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -64,7 +64,7 @@ exit:
 }
 
 define void @f5(float *%src, float %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -79,7 +79,7 @@ exit:
 }
 
 define void @f6(float *%src, float %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -94,7 +94,7 @@ exit:
 }
 
 define void @f7(float *%src, float %target) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -109,7 +109,7 @@ exit:
 }
 
 define void @f8(float *%src, float %target) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -124,7 +124,7 @@ exit:
 }
 
 define void @f9(float *%src, float %target) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -139,7 +139,7 @@ exit:
 }
 
 define void @f10(float *%src, float %target) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -154,7 +154,7 @@ exit:
 }
 
 define void @f11(float *%src, float %target) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -169,7 +169,7 @@ exit:
 }
 
 define void @f12(float *%src, float %target) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -186,7 +186,7 @@ exit:
 ; "jno" == "jump if no overflow", which corresponds to "jump if ordered"
 ; rather than "jump if not ordered" after a floating-point comparison.
 define void @f13(float *%src, float %target) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -203,7 +203,7 @@ exit:
 ; "jo" == "jump if overflow", which corresponds to "jump if not ordered"
 ; rather than "jump if ordered" after a floating-point comparison.
 define void @f14(float *%src, float %target) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
diff --git a/test/CodeGen/SystemZ/branch-05.ll b/test/CodeGen/SystemZ/branch-05.ll
index 268692a..d657c9b 100644
--- a/test/CodeGen/SystemZ/branch-05.ll
+++ b/test/CodeGen/SystemZ/branch-05.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i32 @f1(i32 %x, i32 %y, i32 %op) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ahi %r4, -1
 ; CHECK: clfi %r4, 5
 ; CHECK-NEXT: jh
diff --git a/test/CodeGen/SystemZ/branch-06.ll b/test/CodeGen/SystemZ/branch-06.ll
index 5d6610a..13e5a84 100644
--- a/test/CodeGen/SystemZ/branch-06.ll
+++ b/test/CodeGen/SystemZ/branch-06.ll
@@ -5,7 +5,7 @@
 declare i32 @foo()
 
 define void @f1(i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crje %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -19,7 +19,7 @@ exit:
 }
 
 define void @f2(i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjlh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -33,7 +33,7 @@ exit:
 }
 
 define void @f3(i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjle %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -47,7 +47,7 @@ exit:
 }
 
 define void @f4(i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjl %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -61,7 +61,7 @@ exit:
 }
 
 define void @f5(i32 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -75,7 +75,7 @@ exit:
 }
 
 define void @f6(i32 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjhe %r2, {{%r[0-9]+}}, .L[[LABEL]]
diff --git a/test/CodeGen/SystemZ/branch-07.ll b/test/CodeGen/SystemZ/branch-07.ll
index d009af2..b715a05 100644
--- a/test/CodeGen/SystemZ/branch-07.ll
+++ b/test/CodeGen/SystemZ/branch-07.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Test EQ.
 define void @f1(i64 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrje %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -21,7 +21,7 @@ exit:
 
 ; Test NE.
 define void @f2(i64 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjlh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -36,7 +36,7 @@ exit:
 
 ; Test SLE.
 define void @f3(i64 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjle %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -51,7 +51,7 @@ exit:
 
 ; Test SLT.
 define void @f4(i64 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjl %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -66,7 +66,7 @@ exit:
 
 ; Test SGT.
 define void @f5(i64 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -81,7 +81,7 @@ exit:
 
 ; Test SGE.
 define void @f6(i64 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjhe %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -96,7 +96,7 @@ exit:
 
 ; Test a vector of 0/-1 results for i32 EQ.
 define i64 @f7(i64 %a, i64 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lhi [[REG:%r[0-5]]], -1
 ; CHECK: crje {{%r[0-5]}}
 ; CHECK: lhi [[REG]], 0
@@ -112,7 +112,7 @@ define i64 @f7(i64 %a, i64 %b) {
 
 ; Test a vector of 0/-1 results for i32 NE.
 define i64 @f8(i64 %a, i64 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lhi [[REG:%r[0-5]]], -1
 ; CHECK: crjlh {{%r[0-5]}}
 ; CHECK: lhi [[REG]], 0
@@ -128,7 +128,7 @@ define i64 @f8(i64 %a, i64 %b) {
 
 ; Test a vector of 0/-1 results for i64 EQ.
 define void @f9(i64 %a, i64 %b, <2 x i64> *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lghi [[REG:%r[0-5]]], -1
 ; CHECK: crje {{%r[0-5]}}
 ; CHECK: lghi [[REG]], 0
@@ -144,7 +144,7 @@ define void @f9(i64 %a, i64 %b, <2 x i64> *%dest) {
 
 ; Test a vector of 0/-1 results for i64 NE.
 define void @f10(i64 %a, i64 %b, <2 x i64> *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lghi [[REG:%r[0-5]]], -1
 ; CHECK: crjlh {{%r[0-5]}}
 ; CHECK: lghi [[REG]], 0
diff --git a/test/CodeGen/SystemZ/bswap-01.ll b/test/CodeGen/SystemZ/bswap-01.ll
index 23bc35c..7e6c83a 100644
--- a/test/CodeGen/SystemZ/bswap-01.ll
+++ b/test/CodeGen/SystemZ/bswap-01.ll
@@ -7,7 +7,7 @@ declare i64 @llvm.bswap.i64(i64 %a)
 
 ; Check 32-bit register-to-register byteswaps.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lrvr [[REGISTER:%r[0-5]]], %r2
 ; CHECK: br %r14
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
@@ -16,7 +16,7 @@ define i32 @f1(i32 %a) {
 
 ; Check 64-bit register-to-register byteswaps.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lrvgr %r2, %r2
 ; CHECK: br %r14
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
diff --git a/test/CodeGen/SystemZ/bswap-02.ll b/test/CodeGen/SystemZ/bswap-02.ll
index e2ae011..db69ea5 100644
--- a/test/CodeGen/SystemZ/bswap-02.ll
+++ b/test/CodeGen/SystemZ/bswap-02.ll
@@ -6,7 +6,7 @@ declare i32 @llvm.bswap.i32(i32 %a)
 
 ; Check LRV with no displacement.
 define i32 @f1(i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lrv %r2, 0(%r2)
 ; CHECK: br %r14
   %a = load i32 *%src
@@ -16,7 +16,7 @@ define i32 @f1(i32 *%src) {
 
 ; Check the high end of the aligned LRV range.
 define i32 @f2(i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lrv %r2, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -28,7 +28,7 @@ define i32 @f2(i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f3(i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lrv %r2, 0(%r2)
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define i32 @f3(i32 *%src) {
 
 ; Check the high end of the negative aligned LRV range.
 define i32 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lrv %r2, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -51,7 +51,7 @@ define i32 @f4(i32 *%src) {
 
 ; Check the low end of the LRV range.
 define i32 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lrv %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -63,7 +63,7 @@ define i32 @f5(i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524292
 ; CHECK: lrv %r2, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define i32 @f6(i32 *%src) {
 
 ; Check that LRV allows an index.
 define i32 @f7(i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lrv %r2, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define i32 @f7(i64 %src, i64 %index) {
 ; Check that volatile accesses do not use LRV, which might access the
 ; storage multple times.
 define i32 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: l [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: lrvr %r2, [[REG]]
 ; CHECK: br %r14
@@ -101,7 +101,7 @@ define i32 @f8(i32 *%src) {
 ; Test a case where we spill the source of at least one LRVR.  We want
 ; to use LRV if possible.
 define void @f9(i32 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lrv {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i32 *%ptr
diff --git a/test/CodeGen/SystemZ/bswap-03.ll b/test/CodeGen/SystemZ/bswap-03.ll
index e3ccc38..d9e5ad1 100644
--- a/test/CodeGen/SystemZ/bswap-03.ll
+++ b/test/CodeGen/SystemZ/bswap-03.ll
@@ -6,7 +6,7 @@ declare i64 @llvm.bswap.i64(i64 %a)
 
 ; Check LRVG with no displacement.
 define i64 @f1(i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lrvg %r2, 0(%r2)
 ; CHECK: br %r14
   %a = load i64 *%src
@@ -16,7 +16,7 @@ define i64 @f1(i64 *%src) {
 
 ; Check the high end of the aligned LRVG range.
 define i64 @f2(i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lrvg %r2, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -28,7 +28,7 @@ define i64 @f2(i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f3(i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lrvg %r2, 0(%r2)
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define i64 @f3(i64 *%src) {
 
 ; Check the high end of the negative aligned LRVG range.
 define i64 @f4(i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lrvg %r2, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -51,7 +51,7 @@ define i64 @f4(i64 *%src) {
 
 ; Check the low end of the LRVG range.
 define i64 @f5(i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lrvg %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -63,7 +63,7 @@ define i64 @f5(i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524296
 ; CHECK: lrvg %r2, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define i64 @f6(i64 *%src) {
 
 ; Check that LRVG allows an index.
 define i64 @f7(i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lrvg %r2, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define i64 @f7(i64 %src, i64 %index) {
 ; Check that volatile accesses do not use LRVG, which might access the
 ; storage multple times.
 define i64 @f8(i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lg [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: lrvgr %r2, [[REG]]
 ; CHECK: br %r14
@@ -101,7 +101,7 @@ define i64 @f8(i64 *%src) {
 ; Test a case where we spill the source of at least one LRVGR.  We want
 ; to use LRVG if possible.
 define void @f9(i64 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lrvg {{%r[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i64 *%ptr
diff --git a/test/CodeGen/SystemZ/bswap-04.ll b/test/CodeGen/SystemZ/bswap-04.ll
index 63b2020..29d5a7b 100644
--- a/test/CodeGen/SystemZ/bswap-04.ll
+++ b/test/CodeGen/SystemZ/bswap-04.ll
@@ -6,7 +6,7 @@ declare i32 @llvm.bswap.i32(i32 %a)
 
 ; Check STRV with no displacement.
 define void @f1(i32 *%dst, i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: strv %r3, 0(%r2)
 ; CHECK: br %r14
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
@@ -16,7 +16,7 @@ define void @f1(i32 *%dst, i32 %a) {
 
 ; Check the high end of the aligned STRV range.
 define void @f2(i32 *%dst, i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: strv %r3, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 131071
@@ -28,7 +28,7 @@ define void @f2(i32 *%dst, i32 %a) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f3(i32 *%dst, i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: strv %r3, 0(%r2)
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define void @f3(i32 *%dst, i32 %a) {
 
 ; Check the high end of the negative aligned STRV range.
 define void @f4(i32 *%dst, i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: strv %r3, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 -1
@@ -51,7 +51,7 @@ define void @f4(i32 *%dst, i32 %a) {
 
 ; Check the low end of the STRV range.
 define void @f5(i32 *%dst, i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: strv %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 -131072
@@ -63,7 +63,7 @@ define void @f5(i32 *%dst, i32 %a) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i32 *%dst, i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524292
 ; CHECK: strv %r3, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f6(i32 *%dst, i32 %a) {
 
 ; Check that STRV allows an index.
 define void @f7(i64 %src, i64 %index, i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: strv %r4, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define void @f7(i64 %src, i64 %index, i32 %a) {
 ; Check that volatile stores do not use STRV, which might access the
 ; storage multple times.
 define void @f8(i32 *%dst, i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lrvr [[REG:%r[0-5]]], %r3
 ; CHECK: st [[REG]], 0(%r2)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/bswap-05.ll b/test/CodeGen/SystemZ/bswap-05.ll
index 6f25d3c..5c8361e 100644
--- a/test/CodeGen/SystemZ/bswap-05.ll
+++ b/test/CodeGen/SystemZ/bswap-05.ll
@@ -6,7 +6,7 @@ declare i64 @llvm.bswap.i64(i64 %a)
 
 ; Check STRVG with no displacement.
 define void @f1(i64 *%dst, i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: strvg %r3, 0(%r2)
 ; CHECK: br %r14
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
@@ -16,7 +16,7 @@ define void @f1(i64 *%dst, i64 %a) {
 
 ; Check the high end of the aligned STRVG range.
 define void @f2(i64 *%dst, i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: strvg %r3, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 65535
@@ -28,7 +28,7 @@ define void @f2(i64 *%dst, i64 %a) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f3(i64 *%dst, i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: strvg %r3, 0(%r2)
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define void @f3(i64 *%dst, i64 %a) {
 
 ; Check the high end of the negative aligned STRVG range.
 define void @f4(i64 *%dst, i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: strvg %r3, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 -1
@@ -51,7 +51,7 @@ define void @f4(i64 *%dst, i64 %a) {
 
 ; Check the low end of the STRVG range.
 define void @f5(i64 *%dst, i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: strvg %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 -65536
@@ -63,7 +63,7 @@ define void @f5(i64 *%dst, i64 %a) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 *%dst, i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524296
 ; CHECK: strvg %r3, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f6(i64 *%dst, i64 %a) {
 
 ; Check that STRVG allows an index.
 define void @f7(i64 %src, i64 %index, i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: strvg %r4, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define void @f7(i64 %src, i64 %index, i64 %a) {
 ; Check that volatile stores do not use STRVG, which might access the
 ; storage multple times.
 define void @f8(i64 *%dst, i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lrvgr [[REG:%r[0-5]]], %r3
 ; CHECK: stg [[REG]], 0(%r2)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/call-01.ll b/test/CodeGen/SystemZ/call-01.ll
index 1b9172b..42b6afd 100644
--- a/test/CodeGen/SystemZ/call-01.ll
+++ b/test/CodeGen/SystemZ/call-01.ll
@@ -6,7 +6,7 @@ declare i64 @bar()
 
 ; We must allocate 160 bytes for the callee and save and restore %r14.
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: aghi %r15, -160
 ; CHECK: brasl %r14, bar@PLT
diff --git a/test/CodeGen/SystemZ/call-02.ll b/test/CodeGen/SystemZ/call-02.ll
index 07dd67b..5f14d12 100644
--- a/test/CodeGen/SystemZ/call-02.ll
+++ b/test/CodeGen/SystemZ/call-02.ll
@@ -4,7 +4,7 @@
 
 ; We must allocate 160 bytes for the callee and save and restore %r14.
 define i64 @f1(i64() *%bar) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: aghi %r15, -160
 ; CHECK: basr %r14, %r2
diff --git a/test/CodeGen/SystemZ/cmpxchg-01.ll b/test/CodeGen/SystemZ/cmpxchg-01.ll
index bbb0aab..c6f1038 100644
--- a/test/CodeGen/SystemZ/cmpxchg-01.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-01.ll
@@ -11,7 +11,7 @@
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
-; CHECK-MAIN: f1:
+; CHECK-MAIN-LABEL: f1:
 ; CHECK-MAIN-DAG: sllg [[SHIFT:%r[1-9]+]], %r3, 3
 ; CHECK-MAIN-DAG: risbg [[BASE:%r[1-9]+]], %r3, 0, 189, 0
 ; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -27,7 +27,7 @@ define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
 ; CHECK-MAIN-NOT: %r2
 ; CHECK-MAIN: br %r14
 ;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
 ; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r3, 3
 ; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT: rll
@@ -39,13 +39,13 @@ define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
 ; Check compare and swap with constants.  We should force the constants into
 ; registers and use the sequence above.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi [[CMP:%r[0-9]+]], 42
 ; CHECK: risbg [[CMP]], {{%r[0-9]+}}, 32, 55, 0
 ; CHECK: risbg
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
 ; CHECK-SHIFT: lhi [[SWAP:%r[0-9]+]], 88
 ; CHECK-SHIFT: risbg
 ; CHECK-SHIFT: risbg [[SWAP]], {{%r[0-9]+}}, 32, 55, 0
diff --git a/test/CodeGen/SystemZ/cmpxchg-02.ll b/test/CodeGen/SystemZ/cmpxchg-02.ll
index 5f2dd3a..fa2d088 100644
--- a/test/CodeGen/SystemZ/cmpxchg-02.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-02.ll
@@ -11,7 +11,7 @@
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
-; CHECK-MAIN: f1:
+; CHECK-MAIN-LABEL: f1:
 ; CHECK-MAIN-DAG: sllg [[SHIFT:%r[1-9]+]], %r3, 3
 ; CHECK-MAIN-DAG: risbg [[BASE:%r[1-9]+]], %r3, 0, 189, 0
 ; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -27,7 +27,7 @@ define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
 ; CHECK-MAIN-NOT: %r2
 ; CHECK-MAIN: br %r14
 ;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
 ; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r3, 3
 ; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT: rll
@@ -39,13 +39,13 @@ define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
 ; Check compare and swap with constants.  We should force the constants into
 ; registers and use the sequence above.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi [[CMP:%r[0-9]+]], 42
 ; CHECK: risbg [[CMP]], {{%r[0-9]+}}, 32, 47, 0
 ; CHECK: risbg
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
 ; CHECK-SHIFT: lhi [[SWAP:%r[0-9]+]], 88
 ; CHECK-SHIFT: risbg
 ; CHECK-SHIFT: risbg [[SWAP]], {{%r[0-9]+}}, 32, 47, 0
diff --git a/test/CodeGen/SystemZ/cmpxchg-03.ll b/test/CodeGen/SystemZ/cmpxchg-03.ll
index 45e224e..3917979 100644
--- a/test/CodeGen/SystemZ/cmpxchg-03.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-03.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the CS range.
 define i32 @f1(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
   %val = cmpxchg i32 *%src, i32 %cmp, i32 %swap seq_cst
@@ -13,7 +13,7 @@ define i32 @f1(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the high end of the aligned CS range.
 define i32 @f2(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cs %r2, %r3, 4092(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -23,7 +23,7 @@ define i32 @f2(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the next word up, which should use CSY instead of CS.
 define i32 @f3(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: csy %r2, %r3, 4096(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -33,7 +33,7 @@ define i32 @f3(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the high end of the aligned CSY range.
 define i32 @f4(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: csy %r2, %r3, 524284(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -44,7 +44,7 @@ define i32 @f4(i32 %cmp, i32 %swap, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r4, 524288
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define i32 @f5(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the high end of the negative aligned CSY range.
 define i32 @f6(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: csy %r2, %r3, -4(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i32 @f6(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the low end of the CSY range.
 define i32 @f7(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: csy %r2, %r3, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -76,7 +76,7 @@ define i32 @f7(i32 %cmp, i32 %swap, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, -524292
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define i32 @f8(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check that CS does not allow an index.
 define i32 @f9(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agr %r4, %r5
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -99,7 +99,7 @@ define i32 @f9(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
 
 ; Check that CSY does not allow an index.
 define i32 @f10(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r4, %r5
 ; CHECK: csy %r2, %r3, 4096(%r4)
 ; CHECK: br %r14
@@ -112,7 +112,7 @@ define i32 @f10(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
 
 ; Check that a constant %cmp value is loaded into a register first.
 define i32 @f11(i32 %dummy, i32 %swap, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lhi %r2, 1001
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define i32 @f11(i32 %dummy, i32 %swap, i32 *%ptr) {
 
 ; Check that a constant %swap value is loaded into a register first.
 define i32 @f12(i32 %cmp, i32 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: lhi [[SWAP:%r[0-9]+]], 1002
 ; CHECK: cs %r2, [[SWAP]], 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/cmpxchg-04.ll b/test/CodeGen/SystemZ/cmpxchg-04.ll
index f8969ee..f58868f 100644
--- a/test/CodeGen/SystemZ/cmpxchg-04.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-04.ll
@@ -4,7 +4,7 @@
 
 ; Check CSG without a displacement.
 define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
   %val = cmpxchg i64 *%src, i64 %cmp, i64 %swap seq_cst
@@ -13,7 +13,7 @@ define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) {
 
 ; Check the high end of the aligned CSG range.
 define i64 @f2(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: csg %r2, %r3, 524280(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -24,7 +24,7 @@ define i64 @f2(i64 %cmp, i64 %swap, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f3(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r4, 524288
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define i64 @f3(i64 %cmp, i64 %swap, i64 *%src) {
 
 ; Check the high end of the negative aligned CSG range.
 define i64 @f4(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: csg %r2, %r3, -8(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -45,7 +45,7 @@ define i64 @f4(i64 %cmp, i64 %swap, i64 *%src) {
 
 ; Check the low end of the CSG range.
 define i64 @f5(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: csg %r2, %r3, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -56,7 +56,7 @@ define i64 @f5(i64 %cmp, i64 %swap, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r4, -524296
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i64 @f6(i64 %cmp, i64 %swap, i64 *%src) {
 
 ; Check that CSG does not allow an index.
 define i64 @f7(i64 %cmp, i64 %swap, i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agr %r4, %r5
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -79,7 +79,7 @@ define i64 @f7(i64 %cmp, i64 %swap, i64 %src, i64 %index) {
 
 ; Check that a constant %cmp value is loaded into a register first.
 define i64 @f8(i64 %dummy, i64 %swap, i64 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lghi %r2, 1001
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -89,7 +89,7 @@ define i64 @f8(i64 %dummy, i64 %swap, i64 *%ptr) {
 
 ; Check that a constant %swap value is loaded into a register first.
 define i64 @f9(i64 %cmp, i64 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lghi [[SWAP:%r[0-9]+]], 1002
 ; CHECK: csg %r2, [[SWAP]], 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/cond-store-01.ll b/test/CodeGen/SystemZ/cond-store-01.ll
index fadcae5..a734eee 100644
--- a/test/CodeGen/SystemZ/cond-store-01.ll
+++ b/test/CodeGen/SystemZ/cond-store-01.ll
@@ -6,7 +6,7 @@ declare void @foo(i8 *)
 
 ; Test the simple case, with the loaded value first.
 define void @f1(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -22,7 +22,7 @@ define void @f1(i8 *%ptr, i8 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f2(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -39,7 +39,7 @@ define void @f2(i8 *%ptr, i8 %alt, i32 %limit) {
 ; Test cases where the value is explicitly sign-extended to 32 bits, with the
 ; loaded value first.
 define void @f3(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -57,7 +57,7 @@ define void @f3(i8 *%ptr, i32 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f4(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -76,7 +76,7 @@ define void @f4(i8 *%ptr, i32 %alt, i32 %limit) {
 ; Test cases where the value is explicitly zero-extended to 32 bits, with the
 ; loaded value first.
 define void @f5(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -94,7 +94,7 @@ define void @f5(i8 *%ptr, i32 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f6(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -113,7 +113,7 @@ define void @f6(i8 *%ptr, i32 %alt, i32 %limit) {
 ; Test cases where the value is explicitly sign-extended to 64 bits, with the
 ; loaded value first.
 define void @f7(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -131,7 +131,7 @@ define void @f7(i8 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f8(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -150,7 +150,7 @@ define void @f8(i8 *%ptr, i64 %alt, i32 %limit) {
 ; Test cases where the value is explicitly zero-extended to 64 bits, with the
 ; loaded value first.
 define void @f9(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -168,7 +168,7 @@ define void @f9(i8 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f10(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -186,7 +186,7 @@ define void @f10(i8 *%ptr, i64 %alt, i32 %limit) {
 
 ; Check the high end of the STC range.
 define void @f11(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -203,7 +203,7 @@ define void @f11(i8 *%base, i8 %alt, i32 %limit) {
 
 ; Check the next byte up, which should use STCY instead of STC.
 define void @f12(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -220,7 +220,7 @@ define void @f12(i8 *%base, i8 %alt, i32 %limit) {
 
 ; Check the high end of the STCY range.
 define void @f13(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -238,7 +238,7 @@ define void @f13(i8 *%base, i8 %alt, i32 %limit) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f14(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -256,7 +256,7 @@ define void @f14(i8 *%base, i8 %alt, i32 %limit) {
 
 ; Check the low end of the STCY range.
 define void @f15(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -274,7 +274,7 @@ define void @f15(i8 *%base, i8 %alt, i32 %limit) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f16(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -292,7 +292,7 @@ define void @f16(i8 *%base, i8 %alt, i32 %limit) {
 
 ; Check that STCY allows an index.
 define void @f17(i64 %base, i64 %index, i8 %alt, i32 %limit) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -311,7 +311,7 @@ define void @f17(i64 %base, i64 %index, i8 %alt, i32 %limit) {
 
 ; Check that volatile loads are not matched.
 define void @f18(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: lb {{%r[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -326,7 +326,7 @@ define void @f18(i8 *%ptr, i8 %alt, i32 %limit) {
 
 ; ...likewise stores.  In this case we should have a conditional load into %r3.
 define void @f19(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: lb %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -345,7 +345,7 @@ define void @f19(i8 *%ptr, i8 %alt, i32 %limit) {
 ; to restrict the test to a stronger ordering.
 define void @f20(i8 *%ptr, i8 %alt, i32 %limit) {
 ; FIXME: should use a normal load instead of CS.
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK: cs {{%r[0-9]+}},
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -361,7 +361,7 @@ define void @f20(i8 *%ptr, i8 %alt, i32 %limit) {
 ; ...likewise stores.
 define void @f21(i8 *%ptr, i8 %alt, i32 %limit) {
 ; FIXME: should use a normal store instead of CS.
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: lb %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -376,7 +376,7 @@ define void @f21(i8 *%ptr, i8 %alt, i32 %limit) {
 
 ; Try a frame index base.
 define void @f22(i8 %alt, i32 %limit) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK-NOT: %r15
 ; CHECK: jl [[LABEL:[^ ]*]]
diff --git a/test/CodeGen/SystemZ/cond-store-02.ll b/test/CodeGen/SystemZ/cond-store-02.ll
index 51f3ffc..58550bf 100644
--- a/test/CodeGen/SystemZ/cond-store-02.ll
+++ b/test/CodeGen/SystemZ/cond-store-02.ll
@@ -6,7 +6,7 @@ declare void @foo(i16 *)
 
 ; Test the simple case, with the loaded value first.
 define void @f1(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -22,7 +22,7 @@ define void @f1(i16 *%ptr, i16 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f2(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -39,7 +39,7 @@ define void @f2(i16 *%ptr, i16 %alt, i32 %limit) {
 ; Test cases where the value is explicitly sign-extended to 32 bits, with the
 ; loaded value first.
 define void @f3(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -57,7 +57,7 @@ define void @f3(i16 *%ptr, i32 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f4(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -76,7 +76,7 @@ define void @f4(i16 *%ptr, i32 %alt, i32 %limit) {
 ; Test cases where the value is explicitly zero-extended to 32 bits, with the
 ; loaded value first.
 define void @f5(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -94,7 +94,7 @@ define void @f5(i16 *%ptr, i32 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f6(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -113,7 +113,7 @@ define void @f6(i16 *%ptr, i32 %alt, i32 %limit) {
 ; Test cases where the value is explicitly sign-extended to 64 bits, with the
 ; loaded value first.
 define void @f7(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -131,7 +131,7 @@ define void @f7(i16 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f8(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -150,7 +150,7 @@ define void @f8(i16 *%ptr, i64 %alt, i32 %limit) {
 ; Test cases where the value is explicitly zero-extended to 64 bits, with the
 ; loaded value first.
 define void @f9(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -168,7 +168,7 @@ define void @f9(i16 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f10(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -186,7 +186,7 @@ define void @f10(i16 *%ptr, i64 %alt, i32 %limit) {
 
 ; Check the high end of the aligned STH range.
 define void @f11(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -203,7 +203,7 @@ define void @f11(i16 *%base, i16 %alt, i32 %limit) {
 
 ; Check the next halfword up, which should use STHY instead of STH.
 define void @f12(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -220,7 +220,7 @@ define void @f12(i16 *%base, i16 %alt, i32 %limit) {
 
 ; Check the high end of the aligned STHY range.
 define void @f13(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -238,7 +238,7 @@ define void @f13(i16 *%base, i16 %alt, i32 %limit) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f14(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -256,7 +256,7 @@ define void @f14(i16 *%base, i16 %alt, i32 %limit) {
 
 ; Check the low end of the STHY range.
 define void @f15(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -274,7 +274,7 @@ define void @f15(i16 *%base, i16 %alt, i32 %limit) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f16(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -292,7 +292,7 @@ define void @f16(i16 *%base, i16 %alt, i32 %limit) {
 
 ; Check that STHY allows an index.
 define void @f17(i64 %base, i64 %index, i16 %alt, i32 %limit) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -311,7 +311,7 @@ define void @f17(i64 %base, i64 %index, i16 %alt, i32 %limit) {
 
 ; Check that volatile loads are not matched.
 define void @f18(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: lh {{%r[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -326,7 +326,7 @@ define void @f18(i16 *%ptr, i16 %alt, i32 %limit) {
 
 ; ...likewise stores.  In this case we should have a conditional load into %r3.
 define void @f19(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: lh %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -345,7 +345,7 @@ define void @f19(i16 *%ptr, i16 %alt, i32 %limit) {
 ; to restrict the test to a stronger ordering.
 define void @f20(i16 *%ptr, i16 %alt, i32 %limit) {
 ; FIXME: should use a normal load instead of CS.
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK: cs {{%r[0-9]+}},
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -361,7 +361,7 @@ define void @f20(i16 *%ptr, i16 %alt, i32 %limit) {
 ; ...likewise stores.
 define void @f21(i16 *%ptr, i16 %alt, i32 %limit) {
 ; FIXME: should use a normal store instead of CS.
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: lh %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -376,7 +376,7 @@ define void @f21(i16 *%ptr, i16 %alt, i32 %limit) {
 
 ; Try a frame index base.
 define void @f22(i16 %alt, i32 %limit) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK-NOT: %r15
 ; CHECK: jl [[LABEL:[^ ]*]]
diff --git a/test/CodeGen/SystemZ/cond-store-03.ll b/test/CodeGen/SystemZ/cond-store-03.ll
index 6f19fbc..ba076b0 100644
--- a/test/CodeGen/SystemZ/cond-store-03.ll
+++ b/test/CodeGen/SystemZ/cond-store-03.ll
@@ -6,7 +6,7 @@ declare void @foo(i32 *)
 
 ; Test the simple case, with the loaded value first.
 define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -22,7 +22,7 @@ define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -39,7 +39,7 @@ define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
 ; Test cases where the value is explicitly sign-extended to 64 bits, with the
 ; loaded value first.
 define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -57,7 +57,7 @@ define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -76,7 +76,7 @@ define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
 ; Test cases where the value is explicitly zero-extended to 32 bits, with the
 ; loaded value first.
 define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -94,7 +94,7 @@ define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -112,7 +112,7 @@ define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
 
 ; Check the high end of the aligned ST range.
 define void @f7(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -129,7 +129,7 @@ define void @f7(i32 *%base, i32 %alt, i32 %limit) {
 
 ; Check the next word up, which should use STY instead of ST.
 define void @f8(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -146,7 +146,7 @@ define void @f8(i32 *%base, i32 %alt, i32 %limit) {
 
 ; Check the high end of the aligned STY range.
 define void @f9(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -164,7 +164,7 @@ define void @f9(i32 *%base, i32 %alt, i32 %limit) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f10(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -182,7 +182,7 @@ define void @f10(i32 *%base, i32 %alt, i32 %limit) {
 
 ; Check the low end of the STY range.
 define void @f11(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -200,7 +200,7 @@ define void @f11(i32 *%base, i32 %alt, i32 %limit) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f12(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -218,7 +218,7 @@ define void @f12(i32 *%base, i32 %alt, i32 %limit) {
 
 ; Check that STY allows an index.
 define void @f13(i64 %base, i64 %index, i32 %alt, i32 %limit) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -237,7 +237,7 @@ define void @f13(i64 %base, i64 %index, i32 %alt, i32 %limit) {
 
 ; Check that volatile loads are not matched.
 define void @f14(i32 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l {{%r[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -252,7 +252,7 @@ define void @f14(i32 *%ptr, i32 %alt, i32 %limit) {
 
 ; ...likewise stores.  In this case we should have a conditional load into %r3.
 define void @f15(i32 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: l %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -271,7 +271,7 @@ define void @f15(i32 *%ptr, i32 %alt, i32 %limit) {
 ; to restrict the test to a stronger ordering.
 define void @f16(i32 *%ptr, i32 %alt, i32 %limit) {
 ; FIXME: should use a normal load instead of CS.
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cs {{%r[0-5]}}, {{%r[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -287,7 +287,7 @@ define void @f16(i32 *%ptr, i32 %alt, i32 %limit) {
 ; ...likewise stores.
 define void @f17(i32 *%ptr, i32 %alt, i32 %limit) {
 ; FIXME: should use a normal store instead of CS.
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: l %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -302,7 +302,7 @@ define void @f17(i32 *%ptr, i32 %alt, i32 %limit) {
 
 ; Try a frame index base.
 define void @f18(i32 %alt, i32 %limit) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK-NOT: %r15
 ; CHECK: jl [[LABEL:[^ ]*]]
diff --git a/test/CodeGen/SystemZ/cond-store-04.ll b/test/CodeGen/SystemZ/cond-store-04.ll
index 22f5fd4..f00c94c 100644
--- a/test/CodeGen/SystemZ/cond-store-04.ll
+++ b/test/CodeGen/SystemZ/cond-store-04.ll
@@ -6,7 +6,7 @@ declare void @foo(i64 *)
 
 ; Test with the loaded value first.
 define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -22,7 +22,7 @@ define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -38,7 +38,7 @@ define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
 
 ; Check the high end of the aligned STG range.
 define void @f3(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -56,7 +56,7 @@ define void @f3(i64 *%base, i64 %alt, i32 %limit) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f4(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -74,7 +74,7 @@ define void @f4(i64 *%base, i64 %alt, i32 %limit) {
 
 ; Check the low end of the STG range.
 define void @f5(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -92,7 +92,7 @@ define void @f5(i64 *%base, i64 %alt, i32 %limit) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -110,7 +110,7 @@ define void @f6(i64 *%base, i64 %alt, i32 %limit) {
 
 ; Check that STG allows an index.
 define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -129,7 +129,7 @@ define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) {
 
 ; Check that volatile loads are not matched.
 define void @f8(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lg {{%r[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -144,7 +144,7 @@ define void @f8(i64 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...likewise stores.  In this case we should have a conditional load into %r3.
 define void @f9(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: lg %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -163,7 +163,7 @@ define void @f9(i64 *%ptr, i64 %alt, i32 %limit) {
 ; to restrict the test to a stronger ordering.
 define void @f10(i64 *%ptr, i64 %alt, i32 %limit) {
 ; FIXME: should use a normal load instead of CSG.
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: csg {{%r[0-5]}}, {{%r[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -179,7 +179,7 @@ define void @f10(i64 *%ptr, i64 %alt, i32 %limit) {
 ; ...likewise stores.
 define void @f11(i64 *%ptr, i64 %alt, i32 %limit) {
 ; FIXME: should use a normal store instead of CSG.
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: lg %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -194,7 +194,7 @@ define void @f11(i64 *%ptr, i64 %alt, i32 %limit) {
 
 ; Try a frame index base.
 define void @f12(i64 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK-NOT: %r15
 ; CHECK: jl [[LABEL:[^ ]*]]
diff --git a/test/CodeGen/SystemZ/cond-store-05.ll b/test/CodeGen/SystemZ/cond-store-05.ll
index 5bcfed0..131d102 100644
--- a/test/CodeGen/SystemZ/cond-store-05.ll
+++ b/test/CodeGen/SystemZ/cond-store-05.ll
@@ -6,7 +6,7 @@ declare void @foo(float *)
 
 ; Test with the loaded value first.
 define void @f1(float *%ptr, float %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -22,7 +22,7 @@ define void @f1(float *%ptr, float %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f2(float *%ptr, float %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -38,7 +38,7 @@ define void @f2(float *%ptr, float %alt, i32 %limit) {
 
 ; Check the high end of the aligned STE range.
 define void @f3(float *%base, float %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -55,7 +55,7 @@ define void @f3(float *%base, float %alt, i32 %limit) {
 
 ; Check the next word up, which should use STEY instead of STE.
 define void @f4(float *%base, float %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -72,7 +72,7 @@ define void @f4(float *%base, float %alt, i32 %limit) {
 
 ; Check the high end of the aligned STEY range.
 define void @f5(float *%base, float %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -90,7 +90,7 @@ define void @f5(float *%base, float %alt, i32 %limit) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(float *%base, float %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -108,7 +108,7 @@ define void @f6(float *%base, float %alt, i32 %limit) {
 
 ; Check the low end of the STEY range.
 define void @f7(float *%base, float %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -126,7 +126,7 @@ define void @f7(float *%base, float %alt, i32 %limit) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(float *%base, float %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -144,7 +144,7 @@ define void @f8(float *%base, float %alt, i32 %limit) {
 
 ; Check that STEY allows an index.
 define void @f9(i64 %base, i64 %index, float %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -163,7 +163,7 @@ define void @f9(i64 %base, i64 %index, float %alt, i32 %limit) {
 
 ; Check that volatile loads are not matched.
 define void @f10(float *%ptr, float %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: le {{%f[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -178,7 +178,7 @@ define void @f10(float *%ptr, float %alt, i32 %limit) {
 
 ; ...likewise stores.  In this case we should have a conditional load into %f0.
 define void @f11(float *%ptr, float %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -193,7 +193,7 @@ define void @f11(float *%ptr, float %alt, i32 %limit) {
 
 ; Try a frame index base.
 define void @f12(float %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK-NOT: %r15
 ; CHECK: jl [[LABEL:[^ ]*]]
diff --git a/test/CodeGen/SystemZ/cond-store-06.ll b/test/CodeGen/SystemZ/cond-store-06.ll
index 203a0b0..1c2d716 100644
--- a/test/CodeGen/SystemZ/cond-store-06.ll
+++ b/test/CodeGen/SystemZ/cond-store-06.ll
@@ -6,7 +6,7 @@ declare void @foo(double *)
 
 ; Test with the loaded value first.
 define void @f1(double *%ptr, double %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -22,7 +22,7 @@ define void @f1(double *%ptr, double %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f2(double *%ptr, double %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -38,7 +38,7 @@ define void @f2(double *%ptr, double %alt, i32 %limit) {
 
 ; Check the high end of the aligned STD range.
 define void @f3(double *%base, double %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -55,7 +55,7 @@ define void @f3(double *%base, double %alt, i32 %limit) {
 
 ; Check the next doubleword up, which should use STDY instead of STD.
 define void @f4(double *%base, double %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -72,7 +72,7 @@ define void @f4(double *%base, double %alt, i32 %limit) {
 
 ; Check the high end of the aligned STDY range.
 define void @f5(double *%base, double %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -90,7 +90,7 @@ define void @f5(double *%base, double %alt, i32 %limit) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(double *%base, double %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -108,7 +108,7 @@ define void @f6(double *%base, double %alt, i32 %limit) {
 
 ; Check the low end of the STDY range.
 define void @f7(double *%base, double %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -126,7 +126,7 @@ define void @f7(double *%base, double %alt, i32 %limit) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(double *%base, double %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -144,7 +144,7 @@ define void @f8(double *%base, double %alt, i32 %limit) {
 
 ; Check that STDY allows an index.
 define void @f9(i64 %base, i64 %index, double %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -163,7 +163,7 @@ define void @f9(i64 %base, i64 %index, double %alt, i32 %limit) {
 
 ; Check that volatile loads are not matched.
 define void @f10(double *%ptr, double %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ld {{%f[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -178,7 +178,7 @@ define void @f10(double *%ptr, double %alt, i32 %limit) {
 
 ; ...likewise stores.  In this case we should have a conditional load into %f0.
 define void @f11(double *%ptr, double %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -193,7 +193,7 @@ define void @f11(double *%ptr, double %alt, i32 %limit) {
 
 ; Try a frame index base.
 define void @f12(double %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK-NOT: %r15
 ; CHECK: jl [[LABEL:[^ ]*]]
diff --git a/test/CodeGen/SystemZ/fp-abs-01.ll b/test/CodeGen/SystemZ/fp-abs-01.ll
index 81b3fb2..0b4067d 100644
--- a/test/CodeGen/SystemZ/fp-abs-01.ll
+++ b/test/CodeGen/SystemZ/fp-abs-01.ll
@@ -5,7 +5,7 @@
 ; Test f32.
 declare float @llvm.fabs.f32(float %f)
 define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lpebr %f0, %f0
 ; CHECK: br %r14
   %res = call float @llvm.fabs.f32(float %f)
@@ -15,7 +15,7 @@ define float @f1(float %f) {
 ; Test f64.
 declare double @llvm.fabs.f64(double %f)
 define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lpdbr %f0, %f0
 ; CHECK: br %r14
   %res = call double @llvm.fabs.f64(double %f)
@@ -27,7 +27,7 @@ define double @f2(double %f) {
 ; processing so that using FPRs is unequivocally better.
 declare fp128 @llvm.fabs.f128(fp128 %f)
 define void @f3(fp128 *%ptr, fp128 *%ptr2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lpxbr
 ; CHECK: dxbr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-abs-02.ll b/test/CodeGen/SystemZ/fp-abs-02.ll
index 513d49c..909c48a 100644
--- a/test/CodeGen/SystemZ/fp-abs-02.ll
+++ b/test/CodeGen/SystemZ/fp-abs-02.ll
@@ -5,7 +5,7 @@
 ; Test f32.
 declare float @llvm.fabs.f32(float %f)
 define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lnebr %f0, %f0
 ; CHECK: br %r14
   %abs = call float @llvm.fabs.f32(float %f)
@@ -16,7 +16,7 @@ define float @f1(float %f) {
 ; Test f64.
 declare double @llvm.fabs.f64(double %f)
 define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lndbr %f0, %f0
 ; CHECK: br %r14
   %abs = call double @llvm.fabs.f64(double %f)
@@ -29,7 +29,7 @@ define double @f2(double %f) {
 ; extra processing so that using FPRs is unequivocally better.
 declare fp128 @llvm.fabs.f128(fp128 %f)
 define void @f3(fp128 *%ptr, fp128 *%ptr2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lnxbr
 ; CHECK: dxbr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-add-01.ll b/test/CodeGen/SystemZ/fp-add-01.ll
index c25820a..28a2128 100644
--- a/test/CodeGen/SystemZ/fp-add-01.ll
+++ b/test/CodeGen/SystemZ/fp-add-01.ll
@@ -6,7 +6,7 @@ declare float @foo()
 
 ; Check register addition.
 define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aebr %f0, %f2
 ; CHECK: br %r14
   %res = fadd float %f1, %f2
@@ -15,7 +15,7 @@ define float @f1(float %f1, float %f2) {
 
 ; Check the low end of the AEB range.
 define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aeb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -25,7 +25,7 @@ define float @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned AEB range.
 define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -37,7 +37,7 @@ define float @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: aeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define float @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: aeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define float @f5(float %f1, float *%base) {
 
 ; Check that AEB allows indices.
 define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: aeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define float @f6(float %f1, float *%base, i64 %index) {
 
 ; Check that additions of spilled values can use AEB rather than AEBR.
 define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: aeb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-add-02.ll b/test/CodeGen/SystemZ/fp-add-02.ll
index 58afc13..067c747 100644
--- a/test/CodeGen/SystemZ/fp-add-02.ll
+++ b/test/CodeGen/SystemZ/fp-add-02.ll
@@ -6,7 +6,7 @@ declare double @foo()
 
 ; Check register addition.
 define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: adbr %f0, %f2
 ; CHECK: br %r14
   %res = fadd double %f1, %f2
@@ -15,7 +15,7 @@ define double @f1(double %f1, double %f2) {
 
 ; Check the low end of the ADB range.
 define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: adb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load double *%ptr
@@ -25,7 +25,7 @@ define double @f2(double %f1, double *%ptr) {
 
 ; Check the high end of the aligned ADB range.
 define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: adb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -37,7 +37,7 @@ define double @f3(double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: adb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define double @f4(double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: adb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define double @f5(double %f1, double *%base) {
 
 ; Check that ADB allows indices.
 define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: adb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define double @f6(double %f1, double *%base, i64 %index) {
 
 ; Check that additions of spilled values can use ADB rather than ADBR.
 define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: adb %f0, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-add-03.ll b/test/CodeGen/SystemZ/fp-add-03.ll
index 13ffb02..cb4042e 100644
--- a/test/CodeGen/SystemZ/fp-add-03.ll
+++ b/test/CodeGen/SystemZ/fp-add-03.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit addition.
 define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r2)
 ; CHECK: ld %f3, 8(%r2)
diff --git a/test/CodeGen/SystemZ/fp-cmp-01.ll b/test/CodeGen/SystemZ/fp-cmp-01.ll
index 5aef57f..d59640e 100644
--- a/test/CodeGen/SystemZ/fp-cmp-01.ll
+++ b/test/CodeGen/SystemZ/fp-cmp-01.ll
@@ -6,7 +6,7 @@ declare float @foo()
 
 ; Check comparison with registers.
 define i64 @f1(i64 %a, i64 %b, float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cebr %f0, %f2
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -18,7 +18,7 @@ define i64 @f1(i64 %a, i64 %b, float %f1, float %f2) {
 
 ; Check the low end of the CEB range.
 define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ceb %f0, 0(%r4)
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -31,7 +31,7 @@ define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) {
 
 ; Check the high end of the aligned CEB range.
 define i64 @f3(i64 %a, i64 %b, float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ceb %f0, 4092(%r4)
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -46,7 +46,7 @@ define i64 @f3(i64 %a, i64 %b, float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 %b, float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r4, 4096
 ; CHECK: ceb %f0, 0(%r4)
 ; CHECK-NEXT: je
@@ -61,7 +61,7 @@ define i64 @f4(i64 %a, i64 %b, float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define i64 @f5(i64 %a, i64 %b, float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r4, -4
 ; CHECK: ceb %f0, 0(%r4)
 ; CHECK-NEXT: je
@@ -76,7 +76,7 @@ define i64 @f5(i64 %a, i64 %b, float %f1, float *%base) {
 
 ; Check that CEB allows indices.
 define i64 @f6(i64 %a, i64 %b, float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r5, 2
 ; CHECK: ceb %f0, 400(%r1,%r4)
 ; CHECK-NEXT: je
@@ -92,7 +92,7 @@ define i64 @f6(i64 %a, i64 %b, float %f1, float *%base, i64 %index) {
 
 ; Check that comparisons of spilled values can use CEB rather than CEBR.
 define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: ceb {{%f[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-cmp-02.ll b/test/CodeGen/SystemZ/fp-cmp-02.ll
index c5bdd56..48374a7 100644
--- a/test/CodeGen/SystemZ/fp-cmp-02.ll
+++ b/test/CodeGen/SystemZ/fp-cmp-02.ll
@@ -6,7 +6,7 @@ declare double @foo()
 
 ; Check comparison with registers.
 define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cdbr %f0, %f2
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -18,7 +18,7 @@ define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) {
 
 ; Check the low end of the CDB range.
 define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdb %f0, 0(%r4)
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -31,7 +31,7 @@ define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) {
 
 ; Check the high end of the aligned CDB range.
 define i64 @f3(i64 %a, i64 %b, double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cdb %f0, 4088(%r4)
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -46,7 +46,7 @@ define i64 @f3(i64 %a, i64 %b, double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 %b, double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r4, 4096
 ; CHECK: cdb %f0, 0(%r4)
 ; CHECK-NEXT: je
@@ -61,7 +61,7 @@ define i64 @f4(i64 %a, i64 %b, double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define i64 @f5(i64 %a, i64 %b, double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r4, -8
 ; CHECK: cdb %f0, 0(%r4)
 ; CHECK-NEXT: je
@@ -76,7 +76,7 @@ define i64 @f5(i64 %a, i64 %b, double %f1, double *%base) {
 
 ; Check that CDB allows indices.
 define i64 @f6(i64 %a, i64 %b, double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r5, 3
 ; CHECK: cdb %f0, 800(%r1,%r4)
 ; CHECK-NEXT: je
@@ -92,7 +92,7 @@ define i64 @f6(i64 %a, i64 %b, double %f1, double *%base, i64 %index) {
 
 ; Check that comparisons of spilled values can use CDB rather than CDBR.
 define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: cdb {{%f[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-cmp-03.ll b/test/CodeGen/SystemZ/fp-cmp-03.ll
index 1a5009e..3badc46 100644
--- a/test/CodeGen/SystemZ/fp-cmp-03.ll
+++ b/test/CodeGen/SystemZ/fp-cmp-03.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit comparison.
 define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r4)
 ; CHECK: ld %f3, 8(%r4)
diff --git a/test/CodeGen/SystemZ/fp-const-01.ll b/test/CodeGen/SystemZ/fp-const-01.ll
index 65209d6..3a4ddf0 100644
--- a/test/CodeGen/SystemZ/fp-const-01.ll
+++ b/test/CodeGen/SystemZ/fp-const-01.ll
@@ -4,7 +4,7 @@
 
 ; Test f32.
 define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lzer %f0
 ; CHECK: br %r14
   ret float 0.0
@@ -12,7 +12,7 @@ define float @f1() {
 
 ; Test f64.
 define double @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lzdr %f0
 ; CHECK: br %r14
   ret double 0.0
@@ -20,7 +20,7 @@ define double @f2() {
 
 ; Test f128.
 define void @f3(fp128 *%x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lzxr %f0
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
diff --git a/test/CodeGen/SystemZ/fp-const-02.ll b/test/CodeGen/SystemZ/fp-const-02.ll
index 2dedf54..96f8578 100644
--- a/test/CodeGen/SystemZ/fp-const-02.ll
+++ b/test/CodeGen/SystemZ/fp-const-02.ll
@@ -4,7 +4,7 @@
 
 ; Test f32.
 define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lzer [[REGISTER:%f[0-5]+]]
 ; CHECK: lcebr %f0, [[REGISTER]]
 ; CHECK: br %r14
@@ -13,7 +13,7 @@ define float @f1() {
 
 ; Test f64.
 define double @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lzdr [[REGISTER:%f[0-5]+]]
 ; CHECK: lcdbr %f0, [[REGISTER]]
 ; CHECK: br %r14
@@ -22,7 +22,7 @@ define double @f2() {
 
 ; Test f128.
 define void @f3(fp128 *%x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lzxr [[REGISTER:%f[0-5]+]]
 ; CHECK: lcxbr %f0, [[REGISTER]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-const-03.ll b/test/CodeGen/SystemZ/fp-const-03.ll
index 4c287e4..b2ae94d 100644
--- a/test/CodeGen/SystemZ/fp-const-03.ll
+++ b/test/CodeGen/SystemZ/fp-const-03.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]]], {{.*}}
 ; CHECK: le %f0, 0([[REGISTER]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-const-04.ll b/test/CodeGen/SystemZ/fp-const-04.ll
index 847c380..d552688 100644
--- a/test/CodeGen/SystemZ/fp-const-04.ll
+++ b/test/CodeGen/SystemZ/fp-const-04.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define double @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]]], {{.*}}
 ; CHECK: ldeb %f0, 0([[REGISTER]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-const-05.ll b/test/CodeGen/SystemZ/fp-const-05.ll
index 48f84ce..d81e3db 100644
--- a/test/CodeGen/SystemZ/fp-const-05.ll
+++ b/test/CodeGen/SystemZ/fp-const-05.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: lxeb %f0, 0([[REGISTER]])
 ; CHECK: std %f0, 0(%r2)
diff --git a/test/CodeGen/SystemZ/fp-const-06.ll b/test/CodeGen/SystemZ/fp-const-06.ll
index 1da3d5e..088810b 100644
--- a/test/CodeGen/SystemZ/fp-const-06.ll
+++ b/test/CodeGen/SystemZ/fp-const-06.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define double @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-const-07.ll b/test/CodeGen/SystemZ/fp-const-07.ll
index 5a10845..87e8f68 100644
--- a/test/CodeGen/SystemZ/fp-const-07.ll
+++ b/test/CodeGen/SystemZ/fp-const-07.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: lxdb %f0, 0([[REGISTER]])
 ; CHECK: std %f0, 0(%r2)
diff --git a/test/CodeGen/SystemZ/fp-const-08.ll b/test/CodeGen/SystemZ/fp-const-08.ll
index 6a8a1ab..8845adb 100644
--- a/test/CodeGen/SystemZ/fp-const-08.ll
+++ b/test/CodeGen/SystemZ/fp-const-08.ll
@@ -6,7 +6,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: ld %f2, 8([[REGISTER]])
diff --git a/test/CodeGen/SystemZ/fp-const-09.ll b/test/CodeGen/SystemZ/fp-const-09.ll
index 435dcba..0c7d726 100644
--- a/test/CodeGen/SystemZ/fp-const-09.ll
+++ b/test/CodeGen/SystemZ/fp-const-09.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: ld %f2, 8([[REGISTER]])
diff --git a/test/CodeGen/SystemZ/fp-conv-01.ll b/test/CodeGen/SystemZ/fp-conv-01.ll
index 6c8ef48..49ed43b 100644
--- a/test/CodeGen/SystemZ/fp-conv-01.ll
+++ b/test/CodeGen/SystemZ/fp-conv-01.ll
@@ -4,7 +4,7 @@
 
 ; Test f64->f32.
 define float @f1(double %d1, double %d2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ledbr %f0, %f2
 ; CHECK: br %r14
   %res = fptrunc double %d2 to float
@@ -13,7 +13,7 @@ define float @f1(double %d1, double %d2) {
 
 ; Test f128->f32.
 define float @f2(fp128 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lexbr %f0, %f0
 ; CHECK: br %r14
   %val = load fp128 *%ptr
@@ -24,7 +24,7 @@ define float @f2(fp128 *%ptr) {
 ; Make sure that we don't use %f0 as the destination of LEXBR when %f2
 ; is still live.
 define void @f3(float *%dst, fp128 *%ptr, float %d1, float %d2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lexbr %f1, %f1
 ; CHECK: aebr %f1, %f2
 ; CHECK: ste %f1, 0(%r2)
@@ -38,7 +38,7 @@ define void @f3(float *%dst, fp128 *%ptr, float %d1, float %d2) {
 
 ; Test f128->f64.
 define double @f4(fp128 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldxbr %f0, %f0
 ; CHECK: br %r14
   %val = load fp128 *%ptr
@@ -48,7 +48,7 @@ define double @f4(fp128 *%ptr) {
 
 ; Like f3, but for f128->f64.
 define void @f5(double *%dst, fp128 *%ptr, double %d1, double %d2) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldxbr %f1, %f1
 ; CHECK: adbr %f1, %f2
 ; CHECK: std %f1, 0(%r2)
diff --git a/test/CodeGen/SystemZ/fp-conv-02.ll b/test/CodeGen/SystemZ/fp-conv-02.ll
index eb405da..93fb7c8 100644
--- a/test/CodeGen/SystemZ/fp-conv-02.ll
+++ b/test/CodeGen/SystemZ/fp-conv-02.ll
@@ -4,7 +4,7 @@
 
 ; Check register extension.
 define double @f1(float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldebr %f0, %f0
 ; CHECK: br %r14
   %res = fpext float %val to double
@@ -13,7 +13,7 @@ define double @f1(float %val) {
 
 ; Check the low end of the LDEB range.
 define double @f2(float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldeb %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load float *%ptr
@@ -23,7 +23,7 @@ define double @f2(float *%ptr) {
 
 ; Check the high end of the aligned LDEB range.
 define double @f3(float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ldeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -35,7 +35,7 @@ define double @f3(float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: ldeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -47,7 +47,7 @@ define double @f4(float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: ldeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -59,7 +59,7 @@ define double @f5(float *%base) {
 
 ; Check that LDEB allows indices.
 define double @f6(float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: ldeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -73,7 +73,7 @@ define double @f6(float *%base, i64 %index) {
 ; Test a case where we spill the source of at least one LDEBR.  We want
 ; to use LDEB if possible.
 define void @f7(double *%ptr1, float *%ptr2) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ldeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile float *%ptr2
diff --git a/test/CodeGen/SystemZ/fp-conv-03.ll b/test/CodeGen/SystemZ/fp-conv-03.ll
index 963653c..d42ce66 100644
--- a/test/CodeGen/SystemZ/fp-conv-03.ll
+++ b/test/CodeGen/SystemZ/fp-conv-03.ll
@@ -4,7 +4,7 @@
 
 ; Check register extension.
 define void @f1(fp128 *%dst, float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -16,7 +16,7 @@ define void @f1(fp128 *%dst, float %val) {
 
 ; Check the low end of the LXEB range.
 define void @f2(fp128 *%dst, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lxeb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -29,7 +29,7 @@ define void @f2(fp128 *%dst, float *%ptr) {
 
 ; Check the high end of the aligned LXEB range.
 define void @f3(fp128 *%dst, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lxeb %f0, 4092(%r3)
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -44,7 +44,7 @@ define void @f3(fp128 *%dst, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f4(fp128 *%dst, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r3, 4096
 ; CHECK: lxeb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -59,7 +59,7 @@ define void @f4(fp128 *%dst, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f5(fp128 *%dst, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r3, -4
 ; CHECK: lxeb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -74,7 +74,7 @@ define void @f5(fp128 *%dst, float *%base) {
 
 ; Check that LXEB allows indices.
 define void @f6(fp128 *%dst, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r4, 2
 ; CHECK: lxeb %f0, 400(%r1,%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -91,7 +91,7 @@ define void @f6(fp128 *%dst, float *%base, i64 %index) {
 ; Test a case where we spill the source of at least one LXEBR.  We want
 ; to use LXEB if possible.
 define void @f7(fp128 *%ptr1, float *%ptr2) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lxeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile float *%ptr2
diff --git a/test/CodeGen/SystemZ/fp-conv-04.ll b/test/CodeGen/SystemZ/fp-conv-04.ll
index f8a66f8..518d6c2 100644
--- a/test/CodeGen/SystemZ/fp-conv-04.ll
+++ b/test/CodeGen/SystemZ/fp-conv-04.ll
@@ -4,7 +4,7 @@
 
 ; Check register extension.
 define void @f1(fp128 *%dst, double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxdbr %f0, %f0
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -16,7 +16,7 @@ define void @f1(fp128 *%dst, double %val) {
 
 ; Check the low end of the LXDB range.
 define void @f2(fp128 *%dst, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lxdb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -29,7 +29,7 @@ define void @f2(fp128 *%dst, double *%ptr) {
 
 ; Check the high end of the aligned LXDB range.
 define void @f3(fp128 *%dst, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lxdb %f0, 4088(%r3)
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -44,7 +44,7 @@ define void @f3(fp128 *%dst, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f4(fp128 *%dst, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r3, 4096
 ; CHECK: lxdb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -59,7 +59,7 @@ define void @f4(fp128 *%dst, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f5(fp128 *%dst, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r3, -8
 ; CHECK: lxdb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -74,7 +74,7 @@ define void @f5(fp128 *%dst, double *%base) {
 
 ; Check that LXDB allows indices.
 define void @f6(fp128 *%dst, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r4, 3
 ; CHECK: lxdb %f0, 800(%r1,%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -91,7 +91,7 @@ define void @f6(fp128 *%dst, double *%base, i64 %index) {
 ; Test a case where we spill the source of at least one LXDBR.  We want
 ; to use LXDB if possible.
 define void @f7(fp128 *%ptr1, double *%ptr2) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lxdb {{%f[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
   %val0 = load volatile double *%ptr2
diff --git a/test/CodeGen/SystemZ/fp-conv-05.ll b/test/CodeGen/SystemZ/fp-conv-05.ll
index 2d88732..deeffbf 100644
--- a/test/CodeGen/SystemZ/fp-conv-05.ll
+++ b/test/CodeGen/SystemZ/fp-conv-05.ll
@@ -4,7 +4,7 @@
 
 ; Check i32->f32.
 define float @f1(i32 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cefbr %f0, %r2
 ; CHECK: br %r14
   %conv = sitofp i32 %i to float
@@ -13,7 +13,7 @@ define float @f1(i32 %i) {
 
 ; Check i32->f64.
 define double @f2(i32 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdfbr %f0, %r2
 ; CHECK: br %r14
   %conv = sitofp i32 %i to double
@@ -22,7 +22,7 @@ define double @f2(i32 %i) {
 
 ; Check i32->f128.
 define void @f3(i32 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxfbr %f0, %r2
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
diff --git a/test/CodeGen/SystemZ/fp-conv-06.ll b/test/CodeGen/SystemZ/fp-conv-06.ll
index 1b39b67..466c145 100644
--- a/test/CodeGen/SystemZ/fp-conv-06.ll
+++ b/test/CodeGen/SystemZ/fp-conv-06.ll
@@ -5,7 +5,7 @@
 ; Check i32->f32.  There is no native instruction, so we must promote
 ; to i64 first.
 define float @f1(i32 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
 ; CHECK: cegbr %f0, [[REGISTER]]
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define float @f1(i32 %i) {
 
 ; Check i32->f64.
 define double @f2(i32 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
 ; CHECK: cdgbr %f0, [[REGISTER]]
 ; CHECK: br %r14
@@ -25,7 +25,7 @@ define double @f2(i32 %i) {
 
 ; Check i32->f128.
 define void @f3(i32 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
 ; CHECK: cxgbr %f0, [[REGISTER]]
 ; CHECK: std %f0, 0(%r3)
diff --git a/test/CodeGen/SystemZ/fp-conv-07.ll b/test/CodeGen/SystemZ/fp-conv-07.ll
index 0ebbd37..aba5c4c 100644
--- a/test/CodeGen/SystemZ/fp-conv-07.ll
+++ b/test/CodeGen/SystemZ/fp-conv-07.ll
@@ -4,7 +4,7 @@
 
 ; Test i64->f32.
 define float @f1(i64 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cegbr %f0, %r2
 ; CHECK: br %r14
   %conv = sitofp i64 %i to float
@@ -13,7 +13,7 @@ define float @f1(i64 %i) {
 
 ; Test i64->f64.
 define double @f2(i64 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdgbr %f0, %r2
 ; CHECK: br %r14
   %conv = sitofp i64 %i to double
@@ -22,7 +22,7 @@ define double @f2(i64 %i) {
 
 ; Test i64->f128.
 define void @f3(i64 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxgbr %f0, %r2
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
diff --git a/test/CodeGen/SystemZ/fp-conv-08.ll b/test/CodeGen/SystemZ/fp-conv-08.ll
index 2cb9746..69b2d13 100644
--- a/test/CodeGen/SystemZ/fp-conv-08.ll
+++ b/test/CodeGen/SystemZ/fp-conv-08.ll
@@ -5,7 +5,7 @@
 ; Test i64->f32.  There's no native support for unsigned i64-to-fp conversions,
 ; but we should be able to implement them using signed i64-to-fp conversions.
 define float @f1(i64 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cegbr
 ; CHECK: aebr
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define float @f1(i64 %i) {
 
 ; Test i64->f64.
 define double @f2(i64 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldgr
 ; CHECK: adbr
 ; CHECK: br %r14
@@ -25,7 +25,7 @@ define double @f2(i64 %i) {
 
 ; Test i64->f128.
 define void @f3(i64 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxgbr
 ; CHECK: axbr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-conv-09.ll b/test/CodeGen/SystemZ/fp-conv-09.ll
index e3c0352..6aee736 100644
--- a/test/CodeGen/SystemZ/fp-conv-09.ll
+++ b/test/CodeGen/SystemZ/fp-conv-09.ll
@@ -4,7 +4,7 @@
 
 ; Test f32->i32.
 define i32 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cfebr %r2, 5, %f0
 ; CHECK: br %r14
   %conv = fptosi float %f to i32
@@ -13,7 +13,7 @@ define i32 @f1(float %f) {
 
 ; Test f64->i32.
 define i32 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cfdbr %r2, 5, %f0
 ; CHECK: br %r14
   %conv = fptosi double %f to i32
@@ -22,7 +22,7 @@ define i32 @f2(double %f) {
 
 ; Test f128->i32.
 define i32 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: cfxbr %r2, 5, %f0
diff --git a/test/CodeGen/SystemZ/fp-conv-10.ll b/test/CodeGen/SystemZ/fp-conv-10.ll
index bb8878b..723d19d 100644
--- a/test/CodeGen/SystemZ/fp-conv-10.ll
+++ b/test/CodeGen/SystemZ/fp-conv-10.ll
@@ -9,7 +9,7 @@
 
 ; Test f32->i32.
 define i32 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cebr
 ; CHECK: sebr
 ; CHECK: cfebr
@@ -21,7 +21,7 @@ define i32 @f1(float %f) {
 
 ; Test f64->i32.
 define i32 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdbr
 ; CHECK: sdbr
 ; CHECK: cfdbr
@@ -33,7 +33,7 @@ define i32 @f2(double %f) {
 
 ; Test f128->i32.
 define i32 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxbr
 ; CHECK: sxbr
 ; CHECK: cfxbr
diff --git a/test/CodeGen/SystemZ/fp-conv-11.ll b/test/CodeGen/SystemZ/fp-conv-11.ll
index 2a36cb9..46f4cb3 100644
--- a/test/CodeGen/SystemZ/fp-conv-11.ll
+++ b/test/CodeGen/SystemZ/fp-conv-11.ll
@@ -4,7 +4,7 @@
 
 ; Test f32->i64.
 define i64 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgebr %r2, 5, %f0
 ; CHECK: br %r14
   %conv = fptosi float %f to i64
@@ -13,7 +13,7 @@ define i64 @f1(float %f) {
 
 ; Test f64->i64.
 define i64 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgdbr %r2, 5, %f0
 ; CHECK: br %r14
   %conv = fptosi double %f to i64
@@ -22,7 +22,7 @@ define i64 @f2(double %f) {
 
 ; Test f128->i64.
 define i64 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: cgxbr %r2, 5, %f0
diff --git a/test/CodeGen/SystemZ/fp-conv-12.ll b/test/CodeGen/SystemZ/fp-conv-12.ll
index 4445b14..6cc343a 100644
--- a/test/CodeGen/SystemZ/fp-conv-12.ll
+++ b/test/CodeGen/SystemZ/fp-conv-12.ll
@@ -8,7 +8,7 @@
 
 ; Test f32->i64.
 define i64 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cebr
 ; CHECK: sebr
 ; CHECK: cgebr
@@ -20,7 +20,7 @@ define i64 @f1(float %f) {
 
 ; Test f64->i64.
 define i64 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdbr
 ; CHECK: sdbr
 ; CHECK: cgdbr
@@ -32,7 +32,7 @@ define i64 @f2(double %f) {
 
 ; Test f128->i64.
 define i64 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxbr
 ; CHECK: sxbr
 ; CHECK: cgxbr
diff --git a/test/CodeGen/SystemZ/fp-copysign-01.ll b/test/CodeGen/SystemZ/fp-copysign-01.ll
index 458d475..50177e5 100644
--- a/test/CodeGen/SystemZ/fp-copysign-01.ll
+++ b/test/CodeGen/SystemZ/fp-copysign-01.ll
@@ -9,7 +9,7 @@ declare fp128 @copysignl(fp128, fp128) readnone
 
 ; Test f32 copies in which the sign comes from an f32.
 define float @f1(float %a, float %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %f2
 ; CHECK: cpsdr %f0, %f0, %f2
 ; CHECK: br %r14
@@ -19,7 +19,7 @@ define float @f1(float %a, float %b) {
 
 ; Test f32 copies in which the sign comes from an f64.
 define float @f2(float %a, double %bd) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %f2
 ; CHECK: cpsdr %f0, %f0, %f2
 ; CHECK: br %r14
@@ -30,7 +30,7 @@ define float @f2(float %a, double %bd) {
 
 ; Test f32 copies in which the sign comes from an f128.
 define float @f3(float %a, fp128 *%bptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r2)
 ; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2)
 ; CHECK: cpsdr %f0, %f0, [[BHIGH]]
@@ -43,7 +43,7 @@ define float @f3(float %a, fp128 *%bptr) {
 
 ; Test f64 copies in which the sign comes from an f32.
 define double @f4(double %a, float %bf) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %f2
 ; CHECK: cpsdr %f0, %f0, %f2
 ; CHECK: br %r14
@@ -54,7 +54,7 @@ define double @f4(double %a, float %bf) {
 
 ; Test f64 copies in which the sign comes from an f64.
 define double @f5(double %a, double %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %f2
 ; CHECK: cpsdr %f0, %f0, %f2
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ define double @f5(double %a, double %b) {
 
 ; Test f64 copies in which the sign comes from an f128.
 define double @f6(double %a, fp128 *%bptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r2)
 ; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2)
 ; CHECK: cpsdr %f0, %f0, [[BHIGH]]
@@ -79,7 +79,7 @@ define double @f6(double %a, fp128 *%bptr) {
 ; need any register shuffling here; %a should be tied to %c, with CPSDR
 ; just changing the high register.
 define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3)
 ; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3)
 ; CHECK: cpsdr [[AHIGH]], [[AHIGH]], %f0
@@ -95,7 +95,7 @@ define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) {
 
 ; As above, but the sign comes from an f64.
 define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3)
 ; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3)
 ; CHECK: cpsdr [[AHIGH]], [[AHIGH]], %f0
@@ -112,7 +112,7 @@ define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) {
 ; As above, but the sign comes from an f128.  Don't require the low part
 ; of %b to be loaded, since it isn't used.
 define void @f9(fp128 *%cptr, fp128 *%aptr, fp128 *%bptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3)
 ; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3)
 ; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r4)
diff --git a/test/CodeGen/SystemZ/fp-div-01.ll b/test/CodeGen/SystemZ/fp-div-01.ll
index 3e58123..1b99463 100644
--- a/test/CodeGen/SystemZ/fp-div-01.ll
+++ b/test/CodeGen/SystemZ/fp-div-01.ll
@@ -6,7 +6,7 @@ declare float @foo()
 
 ; Check register division.
 define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: debr %f0, %f2
 ; CHECK: br %r14
   %res = fdiv float %f1, %f2
@@ -15,7 +15,7 @@ define float @f1(float %f1, float %f2) {
 
 ; Check the low end of the DEB range.
 define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: deb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -25,7 +25,7 @@ define float @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned DEB range.
 define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: deb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -37,7 +37,7 @@ define float @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: deb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define float @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: deb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define float @f5(float %f1, float *%base) {
 
 ; Check that DEB allows indices.
 define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: deb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define float @f6(float %f1, float *%base, i64 %index) {
 
 ; Check that divisions of spilled values can use DEB rather than DEBR.
 define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: deb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-div-02.ll b/test/CodeGen/SystemZ/fp-div-02.ll
index 31b1988..513664b 100644
--- a/test/CodeGen/SystemZ/fp-div-02.ll
+++ b/test/CodeGen/SystemZ/fp-div-02.ll
@@ -6,7 +6,7 @@ declare double @foo()
 
 ; Check register division.
 define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ddbr %f0, %f2
 ; CHECK: br %r14
   %res = fdiv double %f1, %f2
@@ -15,7 +15,7 @@ define double @f1(double %f1, double %f2) {
 
 ; Check the low end of the DDB range.
 define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ddb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load double *%ptr
@@ -25,7 +25,7 @@ define double @f2(double %f1, double *%ptr) {
 
 ; Check the high end of the aligned DDB range.
 define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ddb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -37,7 +37,7 @@ define double @f3(double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: ddb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define double @f4(double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: ddb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define double @f5(double %f1, double *%base) {
 
 ; Check that DDB allows indices.
 define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: ddb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define double @f6(double %f1, double *%base, i64 %index) {
 
 ; Check that divisions of spilled values can use DDB rather than DDBR.
 define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: ddb %f0, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-div-03.ll b/test/CodeGen/SystemZ/fp-div-03.ll
index 18f2d74..079b349 100644
--- a/test/CodeGen/SystemZ/fp-div-03.ll
+++ b/test/CodeGen/SystemZ/fp-div-03.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit division.
 define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r2)
 ; CHECK: ld %f3, 8(%r2)
diff --git a/test/CodeGen/SystemZ/fp-move-01.ll b/test/CodeGen/SystemZ/fp-move-01.ll
index 73cd978..d16502f 100644
--- a/test/CodeGen/SystemZ/fp-move-01.ll
+++ b/test/CodeGen/SystemZ/fp-move-01.ll
@@ -4,14 +4,14 @@
 
 ; Test f32 moves.
 define float @f1(float %a, float %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ler %f0, %f2
   ret float %b
 }
 
 ; Test f64 moves.
 define double @f2(double %a, double %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldr %f0, %f2
   ret double %b
 }
@@ -19,7 +19,7 @@ define double @f2(double %a, double %b) {
 ; Test f128 moves.  Since f128s are passed by reference, we need to force
 ; a copy by other means.
 define void @f3(fp128 *%x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lxr
 ; CHECK: axbr
   %val = load volatile fp128 *%x
diff --git a/test/CodeGen/SystemZ/fp-move-02.ll b/test/CodeGen/SystemZ/fp-move-02.ll
index 165d025..b6fc0d5 100644
--- a/test/CodeGen/SystemZ/fp-move-02.ll
+++ b/test/CodeGen/SystemZ/fp-move-02.ll
@@ -10,7 +10,7 @@ declare double @bar()
 ; Test 32-bit moves from GPRs to FPRs.  The GPR must be moved into the high
 ; 32 bits of the FPR.
 define float @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 32
 ; CHECK: ldgr %f0, [[REGISTER]]
   %res = bitcast i32 %a to float
@@ -20,7 +20,7 @@ define float @f1(i32 %a) {
 ; Like f1, but create a situation where the shift can be folded with
 ; surrounding code.
 define float @f2(i64 %big) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: risbg [[REGISTER:%r[0-5]]], %r2, 0, 159, 31
 ; CHECK: ldgr %f0, [[REGISTER]]
   %shift = lshr i64 %big, 1
@@ -31,7 +31,7 @@ define float @f2(i64 %big) {
 
 ; Another example of the same thing.
 define float @f3(i64 %big) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: risbg [[REGISTER:%r[0-5]]], %r2, 0, 159, 2
 ; CHECK: ldgr %f0, [[REGISTER]]
   %shift = ashr i64 %big, 30
@@ -42,7 +42,7 @@ define float @f3(i64 %big) {
 
 ; Like f1, but the value to transfer is already in the high 32 bits.
 define float @f4(i64 %big) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: risbg [[REG:%r[0-5]]], %r2, 0, 159, 0
 ; CHECK-NOT: [[REG]]
@@ -55,7 +55,7 @@ define float @f4(i64 %big) {
 
 ; Test 64-bit moves from GPRs to FPRs.
 define double @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldgr %f0, %r2
   %res = bitcast i64 %a to double
   ret double %res
@@ -65,7 +65,7 @@ define double @f5(i64 %a) {
 ; so this goes through memory.
 ; FIXME: it would be better to use one MVC here.
 define void @f6(fp128 *%a, i128 *%b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lg
 ; CHECK: mvc
 ; CHECK: stg
@@ -79,7 +79,7 @@ define void @f6(fp128 *%a, i128 *%b) {
 ; Test 32-bit moves from FPRs to GPRs.  The high 32 bits of the FPR should
 ; be moved into the low 32 bits of the GPR.
 define i32 @f7(float %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgdr [[REGISTER:%r[0-5]]], %f0
 ; CHECK: srlg %r2, [[REGISTER]], 32
   %res = bitcast float %a to i32
@@ -88,7 +88,7 @@ define i32 @f7(float %a) {
 
 ; Test 64-bit moves from FPRs to GPRs.
 define i64 @f8(double %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lgdr %r2, %f0
   %res = bitcast double %a to i64
   ret i64 %res
@@ -96,7 +96,7 @@ define i64 @f8(double %a) {
 
 ; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
 define void @f9(fp128 *%a, i128 *%b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ld
 ; CHECK: ld
 ; CHECK: std
@@ -110,7 +110,7 @@ define void @f9(fp128 *%a, i128 *%b) {
 ; Test cases where the destination of an LGDR needs to be spilled.
 ; We shouldn't have any integer stack stores or floating-point loads.
 define void @f10(double %extra) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: dptr
 ; CHECK-NOT: stg {{.*}}(%r15)
 ; CHECK: %loop
@@ -172,7 +172,7 @@ exit:
 
 ; ...likewise LDGR, with the requirements the other way around.
 define void @f11(i64 %mask) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: iptr
 ; CHECK-NOT: std {{.*}}(%r15)
 ; CHECK: %loop
@@ -235,7 +235,7 @@ exit:
 ; Test cases where the source of an LDGR needs to be spilled.
 ; We shouldn't have any integer stack stores or floating-point loads.
 define void @f12() {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: %loop
 ; CHECK-NOT: std {{.*}}(%r15)
 ; CHECK: %exit
@@ -314,7 +314,7 @@ exit:
 
 ; ...likewise LGDR, with the requirements the other way around.
 define void @f13() {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: %loop
 ; CHECK-NOT: stg {{.*}}(%r15)
 ; CHECK: %exit
diff --git a/test/CodeGen/SystemZ/fp-move-03.ll b/test/CodeGen/SystemZ/fp-move-03.ll
index 37dbdfa..1273358 100644
--- a/test/CodeGen/SystemZ/fp-move-03.ll
+++ b/test/CodeGen/SystemZ/fp-move-03.ll
@@ -4,7 +4,7 @@
 
 ; Test the low end of the LE range.
 define float @f1(float *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load float *%src
@@ -13,7 +13,7 @@ define float @f1(float *%src) {
 
 ; Test the high end of the LE range.
 define float @f2(float *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: le %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 1023
@@ -23,7 +23,7 @@ define float @f2(float *%src) {
 
 ; Check the next word up, which should use LEY instead of LE.
 define float @f3(float *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ley %f0, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 1024
@@ -33,7 +33,7 @@ define float @f3(float *%src) {
 
 ; Check the high end of the aligned LEY range.
 define float @f4(float *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ley %f0, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 131071
@@ -44,7 +44,7 @@ define float @f4(float *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f5(float *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define float @f5(float *%src) {
 
 ; Check the high end of the negative aligned LEY range.
 define float @f6(float *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ley %f0, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 -1
@@ -65,7 +65,7 @@ define float @f6(float *%src) {
 
 ; Check the low end of the LEY range.
 define float @f7(float *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ley %f0, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 -131072
@@ -76,7 +76,7 @@ define float @f7(float *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f8(float *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524292
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define float @f8(float *%src) {
 
 ; Check that LE allows an index.
 define float @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: le %f0, 4092({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define float @f9(i64 %src, i64 %index) {
 
 ; Check that LEY allows an index.
 define float @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ley %f0, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/fp-move-04.ll b/test/CodeGen/SystemZ/fp-move-04.ll
index 72e90d1..1b0278f 100644
--- a/test/CodeGen/SystemZ/fp-move-04.ll
+++ b/test/CodeGen/SystemZ/fp-move-04.ll
@@ -4,7 +4,7 @@
 
 ; Test the low end of the LD range.
 define double @f1(double *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load double *%src
@@ -13,7 +13,7 @@ define double @f1(double *%src) {
 
 ; Test the high end of the LD range.
 define double @f2(double *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ld %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 511
@@ -23,7 +23,7 @@ define double @f2(double *%src) {
 
 ; Check the next doubleword up, which should use LDY instead of LD.
 define double @f3(double *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ldy %f0, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 512
@@ -33,7 +33,7 @@ define double @f3(double *%src) {
 
 ; Check the high end of the aligned LDY range.
 define double @f4(double *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldy %f0, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 65535
@@ -44,7 +44,7 @@ define double @f4(double *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f5(double *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define double @f5(double *%src) {
 
 ; Check the high end of the negative aligned LDY range.
 define double @f6(double *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ldy %f0, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 -1
@@ -65,7 +65,7 @@ define double @f6(double *%src) {
 
 ; Check the low end of the LDY range.
 define double @f7(double *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ldy %f0, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 -65536
@@ -76,7 +76,7 @@ define double @f7(double *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f8(double *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524296
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define double @f8(double *%src) {
 
 ; Check that LD allows an index.
 define double @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ld %f0, 4095({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define double @f9(i64 %src, i64 %index) {
 
 ; Check that LDY allows an index.
 define double @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ldy %f0, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/fp-move-05.ll b/test/CodeGen/SystemZ/fp-move-05.ll
index 66ad048..d302a0f 100644
--- a/test/CodeGen/SystemZ/fp-move-05.ll
+++ b/test/CodeGen/SystemZ/fp-move-05.ll
@@ -4,7 +4,7 @@
 
 ; Check loads with no offset.
 define double @f1(i64 %src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define double @f1(i64 %src) {
 
 ; Check the highest aligned offset that allows LD for both halves.
 define double @f2(i64 %src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ld %f0, 4080(%r2)
 ; CHECK: ld %f2, 4088(%r2)
 ; CHECK: br %r14
@@ -29,7 +29,7 @@ define double @f2(i64 %src) {
 
 ; Check the next doubleword up, which requires a mixture of LD and LDY.
 define double @f3(i64 %src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ld %f0, 4088(%r2)
 ; CHECK: ldy %f2, 4096(%r2)
 ; CHECK: br %r14
@@ -42,7 +42,7 @@ define double @f3(i64 %src) {
 
 ; Check the next doubleword after that, which requires LDY for both halves.
 define double @f4(i64 %src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldy %f0, 4096(%r2)
 ; CHECK: ldy %f2, 4104(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define double @f4(i64 %src) {
 
 ; Check the highest aligned offset that allows LDY for both halves.
 define double @f5(i64 %src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldy %f0, 524272(%r2)
 ; CHECK: ldy %f2, 524280(%r2)
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(i64 %src) {
 ; Check the next doubleword up, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f6(i64 %src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lay %r1, 524280(%r2)
 ; CHECK: ld %f0, 0(%r1)
 ; CHECK: ld %f2, 8(%r1)
@@ -84,7 +84,7 @@ define double @f6(i64 %src) {
 ; Check the highest aligned negative offset, which needs a combination of
 ; LDY and LD.
 define double @f7(i64 %src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ldy %f0, -8(%r2)
 ; CHECK: ld %f2, 0(%r2)
 ; CHECK: br %r14
@@ -97,7 +97,7 @@ define double @f7(i64 %src) {
 
 ; Check the next doubleword down, which requires LDY for both halves.
 define double @f8(i64 %src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ldy %f0, -16(%r2)
 ; CHECK: ldy %f2, -8(%r2)
 ; CHECK: br %r14
@@ -110,7 +110,7 @@ define double @f8(i64 %src) {
 
 ; Check the lowest offset that allows LDY for both halves.
 define double @f9(i64 %src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ldy %f0, -524288(%r2)
 ; CHECK: ldy %f2, -524280(%r2)
 ; CHECK: br %r14
@@ -124,7 +124,7 @@ define double @f9(i64 %src) {
 ; Check the next doubleword down, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f10(i64 %src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524296
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
@@ -138,7 +138,7 @@ define double @f10(i64 %src) {
 
 ; Check that indices are allowed.
 define double @f11(i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: ld %f0, 4088({{%r2,%r3|%r3,%r2}})
 ; CHECK: ldy %f2, 4096({{%r2,%r3|%r3,%r2}})
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-move-06.ll b/test/CodeGen/SystemZ/fp-move-06.ll
index b660c2a..da67691 100644
--- a/test/CodeGen/SystemZ/fp-move-06.ll
+++ b/test/CodeGen/SystemZ/fp-move-06.ll
@@ -4,7 +4,7 @@
 
 ; Test the low end of the STE range.
 define void @f1(float *%ptr, float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: br %r14
   store float %val, float *%ptr
@@ -13,7 +13,7 @@ define void @f1(float *%ptr, float %val) {
 
 ; Test the high end of the STE range.
 define void @f2(float *%src, float %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ste %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 1023
@@ -23,7 +23,7 @@ define void @f2(float *%src, float %val) {
 
 ; Check the next word up, which should use STEY instead of STE.
 define void @f3(float *%src, float %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stey %f0, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 1024
@@ -33,7 +33,7 @@ define void @f3(float *%src, float %val) {
 
 ; Check the high end of the aligned STEY range.
 define void @f4(float *%src, float %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stey %f0, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 131071
@@ -44,7 +44,7 @@ define void @f4(float *%src, float %val) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f5(float *%src, float %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define void @f5(float *%src, float %val) {
 
 ; Check the high end of the negative aligned STEY range.
 define void @f6(float *%src, float %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: stey %f0, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 -1
@@ -65,7 +65,7 @@ define void @f6(float *%src, float %val) {
 
 ; Check the low end of the STEY range.
 define void @f7(float *%src, float %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: stey %f0, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 -131072
@@ -76,7 +76,7 @@ define void @f7(float *%src, float %val) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(float *%src, float %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524292
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define void @f8(float *%src, float %val) {
 
 ; Check that STE allows an index.
 define void @f9(i64 %src, i64 %index, float %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ste %f0, 4092({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define void @f9(i64 %src, i64 %index, float %val) {
 
 ; Check that STEY allows an index.
 define void @f10(i64 %src, i64 %index, float %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: stey %f0, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/fp-move-07.ll b/test/CodeGen/SystemZ/fp-move-07.ll
index 0cb0474..a4f1820 100644
--- a/test/CodeGen/SystemZ/fp-move-07.ll
+++ b/test/CodeGen/SystemZ/fp-move-07.ll
@@ -4,7 +4,7 @@
 
 ; Test the low end of the STD range.
 define void @f1(double *%src, double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: br %r14
   store double %val, double *%src
@@ -13,7 +13,7 @@ define void @f1(double *%src, double %val) {
 
 ; Test the high end of the STD range.
 define void @f2(double *%src, double %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: std %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 511
@@ -23,7 +23,7 @@ define void @f2(double *%src, double %val) {
 
 ; Check the next doubleword up, which should use STDY instead of STD.
 define void @f3(double *%src, double %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stdy %f0, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 512
@@ -33,7 +33,7 @@ define void @f3(double *%src, double %val) {
 
 ; Check the high end of the aligned STDY range.
 define void @f4(double *%src, double %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stdy %f0, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 65535
@@ -44,7 +44,7 @@ define void @f4(double *%src, double %val) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f5(double *%src, double %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define void @f5(double *%src, double %val) {
 
 ; Check the high end of the negative aligned STDY range.
 define void @f6(double *%src, double %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: stdy %f0, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 -1
@@ -65,7 +65,7 @@ define void @f6(double *%src, double %val) {
 
 ; Check the low end of the STDY range.
 define void @f7(double *%src, double %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: stdy %f0, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 -65536
@@ -76,7 +76,7 @@ define void @f7(double *%src, double %val) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(double *%src, double %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524296
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define void @f8(double *%src, double %val) {
 
 ; Check that STD allows an index.
 define void @f9(i64 %src, i64 %index, double %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: std %f0, 4095({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define void @f9(i64 %src, i64 %index, double %val) {
 
 ; Check that STDY allows an index.
 define void @f10(i64 %src, i64 %index, double %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: stdy %f0, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/fp-move-08.ll b/test/CodeGen/SystemZ/fp-move-08.ll
index 448d2ac..88038ab 100644
--- a/test/CodeGen/SystemZ/fp-move-08.ll
+++ b/test/CodeGen/SystemZ/fp-move-08.ll
@@ -4,7 +4,7 @@
 
 ; Check stores with no offset.
 define void @f1(i64 %src, double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define void @f1(i64 %src, double %val) {
 
 ; Check the highest aligned offset that allows STD for both halves.
 define void @f2(i64 %src, double %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: std %f0, 4080(%r2)
 ; CHECK: std %f2, 4088(%r2)
 ; CHECK: br %r14
@@ -29,7 +29,7 @@ define void @f2(i64 %src, double %val) {
 
 ; Check the next doubleword up, which requires a mixture of STD and STDY.
 define void @f3(i64 %src, double %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: std %f0, 4088(%r2)
 ; CHECK: stdy %f2, 4096(%r2)
 ; CHECK: br %r14
@@ -42,7 +42,7 @@ define void @f3(i64 %src, double %val) {
 
 ; Check the next doubleword after that, which requires STDY for both halves.
 define void @f4(i64 %src, double %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stdy %f0, 4096(%r2)
 ; CHECK: stdy %f2, 4104(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define void @f4(i64 %src, double %val) {
 
 ; Check the highest aligned offset that allows STDY for both halves.
 define void @f5(i64 %src, double %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stdy %f0, 524272(%r2)
 ; CHECK: stdy %f2, 524280(%r2)
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define void @f5(i64 %src, double %val) {
 ; Check the next doubleword up, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 %src, double %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lay %r1, 524280(%r2)
 ; CHECK: std %f0, 0(%r1)
 ; CHECK: std %f2, 8(%r1)
@@ -84,7 +84,7 @@ define void @f6(i64 %src, double %val) {
 ; Check the highest aligned negative offset, which needs a combination of
 ; STDY and STD.
 define void @f7(i64 %src, double %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: stdy %f0, -8(%r2)
 ; CHECK: std %f2, 0(%r2)
 ; CHECK: br %r14
@@ -97,7 +97,7 @@ define void @f7(i64 %src, double %val) {
 
 ; Check the next doubleword down, which requires STDY for both halves.
 define void @f8(i64 %src, double %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: stdy %f0, -16(%r2)
 ; CHECK: stdy %f2, -8(%r2)
 ; CHECK: br %r14
@@ -110,7 +110,7 @@ define void @f8(i64 %src, double %val) {
 
 ; Check the lowest offset that allows STDY for both halves.
 define void @f9(i64 %src, double %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: stdy %f0, -524288(%r2)
 ; CHECK: stdy %f2, -524280(%r2)
 ; CHECK: br %r14
@@ -124,7 +124,7 @@ define void @f9(i64 %src, double %val) {
 ; Check the next doubleword down, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f10(i64 %src, double %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524296
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -138,7 +138,7 @@ define void @f10(i64 %src, double %val) {
 
 ; Check that indices are allowed.
 define void @f11(i64 %src, i64 %index, double %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: std %f0, 4088({{%r2,%r3|%r3,%r2}})
 ; CHECK: stdy %f2, 4096({{%r2,%r3|%r3,%r2}})
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-mul-01.ll b/test/CodeGen/SystemZ/fp-mul-01.ll
index 3e6428a..7562d6b 100644
--- a/test/CodeGen/SystemZ/fp-mul-01.ll
+++ b/test/CodeGen/SystemZ/fp-mul-01.ll
@@ -6,7 +6,7 @@ declare float @foo()
 
 ; Check register multiplication.
 define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: meebr %f0, %f2
 ; CHECK: br %r14
   %res = fmul float %f1, %f2
@@ -15,7 +15,7 @@ define float @f1(float %f1, float %f2) {
 
 ; Check the low end of the MEEB range.
 define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: meeb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -25,7 +25,7 @@ define float @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned MEEB range.
 define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: meeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -37,7 +37,7 @@ define float @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: meeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define float @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: meeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define float @f5(float %f1, float *%base) {
 
 ; Check that MEEB allows indices.
 define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: meeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define float @f6(float %f1, float *%base, i64 %index) {
 
 ; Check that multiplications of spilled values can use MEEB rather than MEEBR.
 define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: meeb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-mul-02.ll b/test/CodeGen/SystemZ/fp-mul-02.ll
index 6326389..cf4448f 100644
--- a/test/CodeGen/SystemZ/fp-mul-02.ll
+++ b/test/CodeGen/SystemZ/fp-mul-02.ll
@@ -6,7 +6,7 @@ declare float @foo()
 
 ; Check register multiplication.
 define double @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mdebr %f0, %f2
 ; CHECK: br %r14
   %f1x = fpext float %f1 to double
@@ -17,7 +17,7 @@ define double @f1(float %f1, float %f2) {
 
 ; Check the low end of the MDEB range.
 define double @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mdeb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -29,7 +29,7 @@ define double @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned MDEB range.
 define double @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mdeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -43,7 +43,7 @@ define double @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mdeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -57,7 +57,7 @@ define double @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: mdeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define double @f5(float %f1, float *%base) {
 
 ; Check that MDEB allows indices.
 define double @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: mdeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -86,7 +86,7 @@ define double @f6(float %f1, float *%base, i64 %index) {
 
 ; Check that multiplications of spilled values can use MDEB rather than MDEBR.
 define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mdeb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-mul-03.ll b/test/CodeGen/SystemZ/fp-mul-03.ll
index 5c5d230..6d296f0 100644
--- a/test/CodeGen/SystemZ/fp-mul-03.ll
+++ b/test/CodeGen/SystemZ/fp-mul-03.ll
@@ -6,7 +6,7 @@ declare double @foo()
 
 ; Check register multiplication.
 define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mdbr %f0, %f2
 ; CHECK: br %r14
   %res = fmul double %f1, %f2
@@ -15,7 +15,7 @@ define double @f1(double %f1, double %f2) {
 
 ; Check the low end of the MDB range.
 define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mdb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load double *%ptr
@@ -25,7 +25,7 @@ define double @f2(double %f1, double *%ptr) {
 
 ; Check the high end of the aligned MDB range.
 define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mdb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -37,7 +37,7 @@ define double @f3(double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define double @f4(double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: mdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define double @f5(double %f1, double *%base) {
 
 ; Check that MDB allows indices.
 define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: mdb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define double @f6(double %f1, double *%base, i64 %index) {
 
 ; Check that multiplications of spilled values can use MDB rather than MDBR.
 define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mdb %f0, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-mul-04.ll b/test/CodeGen/SystemZ/fp-mul-04.ll
index c7f734f..3c4325e 100644
--- a/test/CodeGen/SystemZ/fp-mul-04.ll
+++ b/test/CodeGen/SystemZ/fp-mul-04.ll
@@ -8,7 +8,7 @@ declare double @foo()
 ; point of view, because %f2 is the low register of the FP128 %f0.  Pass the
 ; multiplier in %f4 instead.
 define void @f1(double %f1, double %dummy, double %f2, fp128 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mxdbr %f0, %f4
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -22,7 +22,7 @@ define void @f1(double %f1, double %dummy, double %f2, fp128 *%dst) {
 
 ; Check the low end of the MXDB range.
 define void @f2(double %f1, double *%ptr, fp128 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mxdb %f0, 0(%r2)
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
@@ -37,7 +37,7 @@ define void @f2(double %f1, double *%ptr, fp128 *%dst) {
 
 ; Check the high end of the aligned MXDB range.
 define void @f3(double %f1, double *%base, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mxdb %f0, 4088(%r2)
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
@@ -54,7 +54,7 @@ define void @f3(double %f1, double *%base, fp128 *%dst) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f4(double %f1, double *%base, fp128 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mxdb %f0, 0(%r2)
 ; CHECK: std %f0, 0(%r3)
@@ -71,7 +71,7 @@ define void @f4(double %f1, double *%base, fp128 *%dst) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f5(double %f1, double *%base, fp128 *%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: mxdb %f0, 0(%r2)
 ; CHECK: std %f0, 0(%r3)
@@ -88,7 +88,7 @@ define void @f5(double %f1, double *%base, fp128 *%dst) {
 
 ; Check that MXDB allows indices.
 define void @f6(double %f1, double *%base, i64 %index, fp128 *%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: mxdb %f0, 800(%r1,%r2)
 ; CHECK: std %f0, 0(%r4)
@@ -106,7 +106,7 @@ define void @f6(double %f1, double *%base, i64 %index, fp128 *%dst) {
 
 ; Check that multiplications of spilled values can use MXDB rather than MXDBR.
 define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mxdb %f0, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-mul-05.ll b/test/CodeGen/SystemZ/fp-mul-05.ll
index df5bc4e..0be1fe8 100644
--- a/test/CodeGen/SystemZ/fp-mul-05.ll
+++ b/test/CodeGen/SystemZ/fp-mul-05.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit multiplication.
 define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r2)
 ; CHECK: ld %f3, 8(%r2)
diff --git a/test/CodeGen/SystemZ/fp-mul-06.ll b/test/CodeGen/SystemZ/fp-mul-06.ll
index 8124c68..3f631a6 100644
--- a/test/CodeGen/SystemZ/fp-mul-06.ll
+++ b/test/CodeGen/SystemZ/fp-mul-06.ll
@@ -3,7 +3,7 @@
 declare float @llvm.fma.f32(float %f1, float %f2, float %f3)
 
 define float @f1(float %f1, float %f2, float %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: maebr %f4, %f0, %f2
 ; CHECK: ler %f0, %f4
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define float @f1(float %f1, float %f2, float %acc) {
 }
 
 define float @f2(float %f1, float *%ptr, float %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: maeb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
@@ -22,7 +22,7 @@ define float @f2(float %f1, float *%ptr, float %acc) {
 }
 
 define float @f3(float %f1, float *%base, float %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: maeb %f2, %f0, 4092(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
@@ -36,7 +36,7 @@ define float @f4(float %f1, float *%base, float %acc) {
 ; The important thing here is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: maeb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
@@ -51,7 +51,7 @@ define float @f5(float %f1, float *%base, float %acc) {
 ; Here too the important thing is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: maeb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
@@ -63,7 +63,7 @@ define float @f5(float %f1, float *%base, float %acc) {
 }
 
 define float @f6(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: maeb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ler %f0, %f2
@@ -75,7 +75,7 @@ define float @f6(float %f1, float *%base, i64 %index, float %acc) {
 }
 
 define float @f7(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: maeb %f2, %f0, 4092({{%r1,%r2|%r2,%r1}})
 ; CHECK: ler %f0, %f2
@@ -88,7 +88,7 @@ define float @f7(float %f1, float *%base, i64 %index, float %acc) {
 }
 
 define float @f8(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
 ; CHECK: maeb %f2, %f0, 0(%r1)
diff --git a/test/CodeGen/SystemZ/fp-mul-07.ll b/test/CodeGen/SystemZ/fp-mul-07.ll
index b8e4483..e4f5904 100644
--- a/test/CodeGen/SystemZ/fp-mul-07.ll
+++ b/test/CodeGen/SystemZ/fp-mul-07.ll
@@ -3,7 +3,7 @@
 declare double @llvm.fma.f64(double %f1, double %f2, double %f3)
 
 define double @f1(double %f1, double %f2, double %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: madbr %f4, %f0, %f2
 ; CHECK: ldr %f0, %f4
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define double @f1(double %f1, double %f2, double %acc) {
 }
 
 define double @f2(double %f1, double *%ptr, double %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: madb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -22,7 +22,7 @@ define double @f2(double %f1, double *%ptr, double %acc) {
 }
 
 define double @f3(double %f1, double *%base, double %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: madb %f2, %f0, 4088(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -36,7 +36,7 @@ define double @f4(double %f1, double *%base, double %acc) {
 ; The important thing here is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: madb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
@@ -51,7 +51,7 @@ define double @f5(double %f1, double *%base, double %acc) {
 ; Here too the important thing is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: madb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
@@ -63,7 +63,7 @@ define double @f5(double %f1, double *%base, double %acc) {
 }
 
 define double @f6(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: madb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ldr %f0, %f2
@@ -75,7 +75,7 @@ define double @f6(double %f1, double *%base, i64 %index, double %acc) {
 }
 
 define double @f7(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: madb %f2, %f0, 4088({{%r1,%r2|%r2,%r1}})
 ; CHECK: ldr %f0, %f2
@@ -88,7 +88,7 @@ define double @f7(double %f1, double *%base, i64 %index, double %acc) {
 }
 
 define double @f8(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
 ; CHECK: madb %f2, %f0, 0(%r1)
diff --git a/test/CodeGen/SystemZ/fp-mul-08.ll b/test/CodeGen/SystemZ/fp-mul-08.ll
index 5c14740..ab5fcb2 100644
--- a/test/CodeGen/SystemZ/fp-mul-08.ll
+++ b/test/CodeGen/SystemZ/fp-mul-08.ll
@@ -3,7 +3,7 @@
 declare float @llvm.fma.f32(float %f1, float %f2, float %f3)
 
 define float @f1(float %f1, float %f2, float %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msebr %f4, %f0, %f2
 ; CHECK: ler %f0, %f4
 ; CHECK: br %r14
@@ -13,7 +13,7 @@ define float @f1(float %f1, float %f2, float %acc) {
 }
 
 define float @f2(float %f1, float *%ptr, float %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mseb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
@@ -24,7 +24,7 @@ define float @f2(float %f1, float *%ptr, float %acc) {
 }
 
 define float @f3(float %f1, float *%base, float %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mseb %f2, %f0, 4092(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define float @f4(float %f1, float *%base, float %acc) {
 ; The important thing here is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mseb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
@@ -55,7 +55,7 @@ define float @f5(float %f1, float *%base, float %acc) {
 ; Here too the important thing is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: mseb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
@@ -68,7 +68,7 @@ define float @f5(float %f1, float *%base, float %acc) {
 }
 
 define float @f6(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: mseb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ler %f0, %f2
@@ -81,7 +81,7 @@ define float @f6(float %f1, float *%base, i64 %index, float %acc) {
 }
 
 define float @f7(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: mseb %f2, %f0, 4092({{%r1,%r2|%r2,%r1}})
 ; CHECK: ler %f0, %f2
@@ -95,7 +95,7 @@ define float @f7(float %f1, float *%base, i64 %index, float %acc) {
 }
 
 define float @f8(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
 ; CHECK: mseb %f2, %f0, 0(%r1)
diff --git a/test/CodeGen/SystemZ/fp-mul-09.ll b/test/CodeGen/SystemZ/fp-mul-09.ll
index bcae1e3..7e74096 100644
--- a/test/CodeGen/SystemZ/fp-mul-09.ll
+++ b/test/CodeGen/SystemZ/fp-mul-09.ll
@@ -3,7 +3,7 @@
 declare double @llvm.fma.f64(double %f1, double %f2, double %f3)
 
 define double @f1(double %f1, double %f2, double %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msdbr %f4, %f0, %f2
 ; CHECK: ldr %f0, %f4
 ; CHECK: br %r14
@@ -13,7 +13,7 @@ define double @f1(double %f1, double %f2, double %acc) {
 }
 
 define double @f2(double %f1, double *%ptr, double %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: msdb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -24,7 +24,7 @@ define double @f2(double %f1, double *%ptr, double %acc) {
 }
 
 define double @f3(double %f1, double *%base, double %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: msdb %f2, %f0, 4088(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define double @f4(double %f1, double *%base, double %acc) {
 ; The important thing here is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: msdb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
@@ -55,7 +55,7 @@ define double @f5(double %f1, double *%base, double %acc) {
 ; Here too the important thing is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: msdb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
@@ -68,7 +68,7 @@ define double @f5(double %f1, double *%base, double %acc) {
 }
 
 define double @f6(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: msdb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ldr %f0, %f2
@@ -81,7 +81,7 @@ define double @f6(double %f1, double *%base, i64 %index, double %acc) {
 }
 
 define double @f7(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: msdb %f2, %f0, 4088({{%r1,%r2|%r2,%r1}})
 ; CHECK: ldr %f0, %f2
@@ -95,7 +95,7 @@ define double @f7(double %f1, double *%base, i64 %index, double %acc) {
 }
 
 define double @f8(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
 ; CHECK: msdb %f2, %f0, 0(%r1)
diff --git a/test/CodeGen/SystemZ/fp-neg-01.ll b/test/CodeGen/SystemZ/fp-neg-01.ll
index 09a4a53..1cc6d81 100644
--- a/test/CodeGen/SystemZ/fp-neg-01.ll
+++ b/test/CodeGen/SystemZ/fp-neg-01.ll
@@ -4,7 +4,7 @@
 
 ; Test f32.
 define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lcebr %f0, %f0
 ; CHECK: br %r14
   %res = fsub float -0.0, %f
@@ -13,7 +13,7 @@ define float @f1(float %f) {
 
 ; Test f64.
 define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lcdbr %f0, %f0
 ; CHECK: br %r14
   %res = fsub double -0.0, %f
@@ -24,7 +24,7 @@ define double @f2(double %f) {
 ; be better implemented using an XI on the upper byte.  Do some extra
 ; processing so that using FPRs is unequivocally better.
 define void @f3(fp128 *%ptr, fp128 *%ptr2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lcxbr
 ; CHECK: dxbr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-round-01.ll b/test/CodeGen/SystemZ/fp-round-01.ll
index 20325c3..f2530dc 100644
--- a/test/CodeGen/SystemZ/fp-round-01.ll
+++ b/test/CodeGen/SystemZ/fp-round-01.ll
@@ -6,7 +6,7 @@
 ; Test f32.
 declare float @llvm.rint.f32(float %f)
 define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: fiebr %f0, 0, %f0
 ; CHECK: br %r14
   %res = call float @llvm.rint.f32(float %f)
@@ -16,7 +16,7 @@ define float @f1(float %f) {
 ; Test f64.
 declare double @llvm.rint.f64(double %f)
 define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: fidbr %f0, 0, %f0
 ; CHECK: br %r14
   %res = call double @llvm.rint.f64(double %f)
@@ -26,7 +26,7 @@ define double @f2(double %f) {
 ; Test f128.
 declare fp128 @llvm.rint.f128(fp128 %f)
 define void @f3(fp128 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: fixbr %f0, 0, %f0
 ; CHECK: br %r14
   %src = load fp128 *%ptr
diff --git a/test/CodeGen/SystemZ/fp-sqrt-01.ll b/test/CodeGen/SystemZ/fp-sqrt-01.ll
index faba390..b6568d6 100644
--- a/test/CodeGen/SystemZ/fp-sqrt-01.ll
+++ b/test/CodeGen/SystemZ/fp-sqrt-01.ll
@@ -6,7 +6,7 @@ declare float @llvm.sqrt.f32(float %f)
 
 ; Check register square root.
 define float @f1(float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sqebr %f0, %f0
 ; CHECK: br %r14
   %res = call float @llvm.sqrt.f32(float %val)
@@ -15,7 +15,7 @@ define float @f1(float %val) {
 
 ; Check the low end of the SQEB range.
 define float @f2(float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sqeb %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load float *%ptr
@@ -25,7 +25,7 @@ define float @f2(float *%ptr) {
 
 ; Check the high end of the aligned SQEB range.
 define float @f3(float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sqeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -37,7 +37,7 @@ define float @f3(float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: sqeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define float @f4(float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: sqeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define float @f5(float *%base) {
 
 ; Check that SQEB allows indices.
 define float @f6(float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: sqeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define float @f6(float *%base, i64 %index) {
 ; Test a case where we spill the source of at least one SQEBR.  We want
 ; to use SQEB if possible.
 define void @f7(float *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sqeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile float *%ptr
diff --git a/test/CodeGen/SystemZ/fp-sqrt-02.ll b/test/CodeGen/SystemZ/fp-sqrt-02.ll
index e90f7a3..b07a2c6 100644
--- a/test/CodeGen/SystemZ/fp-sqrt-02.ll
+++ b/test/CodeGen/SystemZ/fp-sqrt-02.ll
@@ -6,7 +6,7 @@ declare double @llvm.sqrt.f64(double %f)
 
 ; Check register square root.
 define double @f1(double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sqdbr %f0, %f0
 ; CHECK: br %r14
   %res = call double @llvm.sqrt.f64(double %val)
@@ -15,7 +15,7 @@ define double @f1(double %val) {
 
 ; Check the low end of the SQDB range.
 define double @f2(double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sqdb %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load double *%ptr
@@ -25,7 +25,7 @@ define double @f2(double *%ptr) {
 
 ; Check the high end of the aligned SQDB range.
 define double @f3(double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sqdb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -37,7 +37,7 @@ define double @f3(double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: sqdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define double @f4(double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: sqdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define double @f5(double *%base) {
 
 ; Check that SQDB allows indices.
 define double @f6(double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: sqdb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define double @f6(double *%base, i64 %index) {
 ; Test a case where we spill the source of at least one SQDBR.  We want
 ; to use SQDB if possible.
 define void @f7(double *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sqdb {{%f[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
   %val0 = load volatile double *%ptr
diff --git a/test/CodeGen/SystemZ/fp-sqrt-03.ll b/test/CodeGen/SystemZ/fp-sqrt-03.ll
index 1b49af4..7142644 100644
--- a/test/CodeGen/SystemZ/fp-sqrt-03.ll
+++ b/test/CodeGen/SystemZ/fp-sqrt-03.ll
@@ -6,7 +6,7 @@ declare fp128 @llvm.sqrt.f128(fp128 %f)
 
 ; There's no memory form of SQXBR.
 define void @f1(fp128 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: sqxbr %f0, %f0
diff --git a/test/CodeGen/SystemZ/fp-sub-01.ll b/test/CodeGen/SystemZ/fp-sub-01.ll
index 88ce7fb..76f46f6 100644
--- a/test/CodeGen/SystemZ/fp-sub-01.ll
+++ b/test/CodeGen/SystemZ/fp-sub-01.ll
@@ -6,7 +6,7 @@ declare float @foo()
 
 ; Check register subtraction.
 define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sebr %f0, %f2
 ; CHECK: br %r14
   %res = fsub float %f1, %f2
@@ -15,7 +15,7 @@ define float @f1(float %f1, float %f2) {
 
 ; Check the low end of the SEB range.
 define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: seb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -25,7 +25,7 @@ define float @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned SEB range.
 define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: seb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -37,7 +37,7 @@ define float @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: seb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define float @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: seb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define float @f5(float %f1, float *%base) {
 
 ; Check that SEB allows indices.
 define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: seb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define float @f6(float %f1, float *%base, i64 %index) {
 
 ; Check that subtractions of spilled values can use SEB rather than SEBR.
 define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: seb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-sub-02.ll b/test/CodeGen/SystemZ/fp-sub-02.ll
index b6409fc..99cafed 100644
--- a/test/CodeGen/SystemZ/fp-sub-02.ll
+++ b/test/CodeGen/SystemZ/fp-sub-02.ll
@@ -6,7 +6,7 @@ declare double @foo()
 
 ; Check register subtraction.
 define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sdbr %f0, %f2
 ; CHECK: br %r14
   %res = fsub double %f1, %f2
@@ -15,7 +15,7 @@ define double @f1(double %f1, double %f2) {
 
 ; Check the low end of the SDB range.
 define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sdb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load double *%ptr
@@ -25,7 +25,7 @@ define double @f2(double %f1, double *%ptr) {
 
 ; Check the high end of the aligned SDB range.
 define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sdb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -37,7 +37,7 @@ define double @f3(double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: sdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define double @f4(double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: sdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define double @f5(double %f1, double *%base) {
 
 ; Check that SDB allows indices.
 define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: sdb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define double @f6(double %f1, double *%base, i64 %index) {
 
 ; Check that subtractions of spilled values can use SDB rather than SDBR.
 define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: sdb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-sub-03.ll b/test/CodeGen/SystemZ/fp-sub-03.ll
index 82bb94d..a1404c4 100644
--- a/test/CodeGen/SystemZ/fp-sub-03.ll
+++ b/test/CodeGen/SystemZ/fp-sub-03.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit subtraction.
 define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r2)
 ; CHECK: ld %f3, 8(%r2)
diff --git a/test/CodeGen/SystemZ/frame-01.ll b/test/CodeGen/SystemZ/frame-01.ll
index ad1ee53..f61836c 100644
--- a/test/CodeGen/SystemZ/frame-01.ll
+++ b/test/CodeGen/SystemZ/frame-01.ll
@@ -7,7 +7,7 @@ declare void @foo(i32 *)
 
 ; The CFA offset is 160 (the caller-allocated part of the frame) + 168.
 define void @f1(i64 %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -168
 ; CHECK: .cfi_def_cfa_offset 328
 ; CHECK: stg %r2, 160(%r15)
@@ -24,7 +24,7 @@ define void @f1(i64 %x) {
 ; 12-bit offsets that end up being out of range.  Fill the remaining
 ; 32760 - 176 bytes by allocating (32760 - 176) / 8 = 4073 doublewords.
 define void @f2(i64 %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -32760
 ; CHECK: .cfi_def_cfa_offset 32920
 ; CHECK: stg %r2, 176(%r15)
@@ -39,7 +39,7 @@ define void @f2(i64 %x) {
 ; Allocate one more doubleword.  This is the one frame size that we can
 ; allocate using AGHI but must free using AGFI.
 define void @f3(i64 %x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -32768
 ; CHECK: .cfi_def_cfa_offset 32928
 ; CHECK: stg %r2, 176(%r15)
@@ -54,7 +54,7 @@ define void @f3(i64 %x) {
 ; Allocate another doubleword on top of that.  The allocation and free
 ; must both use AGFI.
 define void @f4(i64 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r15, -32776
 ; CHECK: .cfi_def_cfa_offset 32936
 ; CHECK: stg %r2, 176(%r15)
@@ -69,7 +69,7 @@ define void @f4(i64 %x) {
 ; The largest size that can be both allocated and freed using AGFI.
 ; At this point the frame is too big to represent properly in the CFI.
 define void @f5(i64 %x) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r15, -2147483640
 ; CHECK: stg %r2, 176(%r15)
 ; CHECK: agfi %r15, 2147483640
@@ -83,7 +83,7 @@ define void @f5(i64 %x) {
 ; The only frame size that can be allocated using a single AGFI but which
 ; must be freed using two instructions.
 define void @f6(i64 %x) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r15, -2147483648
 ; CHECK: stg %r2, 176(%r15)
 ; CHECK: agfi %r15, 2147483640
@@ -98,7 +98,7 @@ define void @f6(i64 %x) {
 ; The smallest frame size that needs two instructions to both allocate
 ; and free the frame.
 define void @f7(i64 %x) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r15, -2147483648
 ; CHECK: aghi %r15, -8
 ; CHECK: stg %r2, 176(%r15)
@@ -113,7 +113,7 @@ define void @f7(i64 %x) {
 
 ; Make sure that LA can be rematerialized.
 define void @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: la %r2, 164(%r15)
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: la %r2, 164(%r15)
diff --git a/test/CodeGen/SystemZ/frame-02.ll b/test/CodeGen/SystemZ/frame-02.ll
index 589703e..9a7f8ea 100644
--- a/test/CodeGen/SystemZ/frame-02.ll
+++ b/test/CodeGen/SystemZ/frame-02.ll
@@ -7,7 +7,7 @@
 ; should be exactly 160 + 8 * 8 = 224.  The CFA offset is 160
 ; (the caller-allocated part of the frame) + 224.
 define void @f1(float *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -224
 ; CHECK: .cfi_def_cfa_offset 384
 ; CHECK: std %f8, 216(%r15)
@@ -91,7 +91,7 @@ define void @f1(float *%ptr) {
 ; Like f1, but requires one fewer FPR.  We allocate in numerical order,
 ; so %f15 is the one that gets dropped.
 define void @f2(float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -216
 ; CHECK: .cfi_def_cfa_offset 376
 ; CHECK: std %f8, 208(%r15)
@@ -169,7 +169,7 @@ define void @f2(float *%ptr) {
 
 ; Like f1, but should require only one call-saved FPR.
 define void @f3(float *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -168
 ; CHECK: .cfi_def_cfa_offset 328
 ; CHECK: std %f8, 160(%r15)
@@ -218,7 +218,7 @@ define void @f3(float *%ptr) {
 ; This function should use all call-clobbered FPRs but no call-saved ones.
 ; It shouldn't need to create a frame.
 define void @f4(float *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %f8
 ; CHECK-NOT: %f9
diff --git a/test/CodeGen/SystemZ/frame-03.ll b/test/CodeGen/SystemZ/frame-03.ll
index 3c4a499..db146c7 100644
--- a/test/CodeGen/SystemZ/frame-03.ll
+++ b/test/CodeGen/SystemZ/frame-03.ll
@@ -9,7 +9,7 @@
 ; should be exactly 160 + 8 * 8 = 224.  The CFA offset is 160
 ; (the caller-allocated part of the frame) + 224.
 define void @f1(double *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -224
 ; CHECK: .cfi_def_cfa_offset 384
 ; CHECK: std %f8, 216(%r15)
@@ -93,7 +93,7 @@ define void @f1(double *%ptr) {
 ; Like f1, but requires one fewer FPR.  We allocate in numerical order,
 ; so %f15 is the one that gets dropped.
 define void @f2(double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -216
 ; CHECK: .cfi_def_cfa_offset 376
 ; CHECK: std %f8, 208(%r15)
@@ -171,7 +171,7 @@ define void @f2(double *%ptr) {
 
 ; Like f1, but should require only one call-saved FPR.
 define void @f3(double *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -168
 ; CHECK: .cfi_def_cfa_offset 328
 ; CHECK: std %f8, 160(%r15)
@@ -220,7 +220,7 @@ define void @f3(double *%ptr) {
 ; This function should use all call-clobbered FPRs but no call-saved ones.
 ; It shouldn't need to create a frame.
 define void @f4(double *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %f8
 ; CHECK-NOT: %f9
diff --git a/test/CodeGen/SystemZ/frame-04.ll b/test/CodeGen/SystemZ/frame-04.ll
index 360f85c..93c59a3 100644
--- a/test/CodeGen/SystemZ/frame-04.ll
+++ b/test/CodeGen/SystemZ/frame-04.ll
@@ -8,7 +8,7 @@
 ; should be exactly 160 + 8 * 8 = 224.  The CFA offset is 160
 ; (the caller-allocated part of the frame) + 224.
 define void @f1(fp128 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -224
 ; CHECK: .cfi_def_cfa_offset 384
 ; CHECK: std %f8, 216(%r15)
@@ -68,7 +68,7 @@ define void @f1(fp128 *%ptr) {
 ; Like f1, but requires one fewer FPR pair.  We allocate in numerical order,
 ; so %f13+%f15 is the pair that gets dropped.
 define void @f2(fp128 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -208
 ; CHECK: .cfi_def_cfa_offset 368
 ; CHECK: std %f8, 200(%r15)
@@ -121,7 +121,7 @@ define void @f2(fp128 *%ptr) {
 ; Like f1, but requires only one call-saved FPR pair.  We allocate in
 ; numerical order so the pair should be %f8+%f10.
 define void @f3(fp128 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -176
 ; CHECK: .cfi_def_cfa_offset 336
 ; CHECK: std %f8, 168(%r15)
@@ -160,7 +160,7 @@ define void @f3(fp128 *%ptr) {
 ; This function should use all call-clobbered FPRs but no call-saved ones.
 ; It shouldn't need to create a frame.
 define void @f4(fp128 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %f8
 ; CHECK-NOT: %f9
diff --git a/test/CodeGen/SystemZ/frame-05.ll b/test/CodeGen/SystemZ/frame-05.ll
index 3a159fc..f95284d 100644
--- a/test/CodeGen/SystemZ/frame-05.ll
+++ b/test/CodeGen/SystemZ/frame-05.ll
@@ -14,7 +14,7 @@
 ; Use a different address for the final store, so that we can check that
 ; %r15 isn't referenced again until after that.
 define void @f1(i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r6, -112
@@ -82,7 +82,7 @@ define void @f1(i32 *%ptr) {
 ; from %r14 down, so that the STMG/LMG sequences aren't any longer than
 ; they need to be.
 define void @f2(i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r7, %r15, 56(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r7, -104
@@ -145,7 +145,7 @@ define void @f2(i32 *%ptr) {
 
 ; Like f1, but only needs one call-saved GPR, which ought to be %r14.
 define void @f3(i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r14, -48
@@ -188,7 +188,7 @@ define void @f3(i32 *%ptr) {
 ; This function should use all call-clobbered GPRs but no call-saved ones.
 ; It shouldn't need to touch the stack at all.
 define void @f4(i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %r6
 ; CHECK-NOT: %r7
diff --git a/test/CodeGen/SystemZ/frame-06.ll b/test/CodeGen/SystemZ/frame-06.ll
index 4c361f1..ad22f10 100644
--- a/test/CodeGen/SystemZ/frame-06.ll
+++ b/test/CodeGen/SystemZ/frame-06.ll
@@ -11,7 +11,7 @@
 ; Use a different address for the final store, so that we can check that
 ; %r15 isn't referenced again until after that.
 define void @f1(i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r6, -112
@@ -79,7 +79,7 @@ define void @f1(i64 *%ptr) {
 ; from %r14 down, so that the STMG/LMG sequences aren't any longer than
 ; they need to be.
 define void @f2(i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r7, %r15, 56(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r7, -104
@@ -142,7 +142,7 @@ define void @f2(i64 *%ptr) {
 
 ; Like f1, but only needs one call-saved GPR, which ought to be %r14.
 define void @f3(i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r14, -48
@@ -185,7 +185,7 @@ define void @f3(i64 *%ptr) {
 ; This function should use all call-clobbered GPRs but no call-saved ones.
 ; It shouldn't need to touch the stack at all.
 define void @f4(i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %r6
 ; CHECK-NOT: %r7
diff --git a/test/CodeGen/SystemZ/frame-07.ll b/test/CodeGen/SystemZ/frame-07.ll
index b5999ae..eab3137 100644
--- a/test/CodeGen/SystemZ/frame-07.ll
+++ b/test/CodeGen/SystemZ/frame-07.ll
@@ -9,7 +9,7 @@
 ; as well as the 8 FPR save slots.  Get a frame of size 4128 by allocating
 ; (4128 - 176 - 8 * 8) / 8 = 486 extra doublewords.
 define void @f1(double *%ptr, i64 %x) {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: aghi %r15, -4128
 ; CHECK-NOFP: .cfi_def_cfa_offset 4288
 ; CHECK-NOFP: stdy %f8, 4120(%r15)
@@ -40,7 +40,7 @@ define void @f1(double *%ptr, i64 %x) {
 ; CHECK-NOFP: aghi %r15, 4128
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: stmg %r11, %r15, 88(%r15)
 ; CHECK-FP: aghi %r15, -4128
 ; CHECK-FP: .cfi_def_cfa_offset 4288
@@ -129,7 +129,7 @@ define void @f1(double *%ptr, i64 %x) {
 ; As above, get a frame of size 524320 by allocating
 ; (524320 - 176 - 8 * 8) / 8 = 65510 extra doublewords.
 define void @f2(double *%ptr, i64 %x) {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: agfi %r15, -524320
 ; CHECK-NOFP: .cfi_def_cfa_offset 524480
 ; CHECK-NOFP: llilh [[INDEX:%r[1-5]]], 8
@@ -161,7 +161,7 @@ define void @f2(double *%ptr, i64 %x) {
 ; CHECK-NOFP: agfi %r15, 524320
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: stmg %r11, %r15, 88(%r15)
 ; CHECK-FP: agfi %r15, -524320
 ; CHECK-FP: .cfi_def_cfa_offset 524480
diff --git a/test/CodeGen/SystemZ/frame-08.ll b/test/CodeGen/SystemZ/frame-08.ll
index 8db4dd3..da2a614 100644
--- a/test/CodeGen/SystemZ/frame-08.ll
+++ b/test/CodeGen/SystemZ/frame-08.ll
@@ -7,7 +7,7 @@
 ; so get a frame of size 524232 by allocating (524232 - 176) / 8 = 65507
 ; extra doublewords.
 define void @f1(i32 *%ptr, i64 %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK: .cfi_offset %r6, -112
 ; CHECK: .cfi_offset %r7, -104
@@ -75,7 +75,7 @@ define void @f1(i32 *%ptr, i64 %x) {
 ; so get a frame of size 524168 by allocating (524168 - 176) / 8 = 65499
 ; extra doublewords.
 define void @f2(i32 *%ptr, i64 %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: .cfi_offset %r14, -48
 ; CHECK: .cfi_offset %r15, -40
@@ -110,7 +110,7 @@ define void @f2(i32 *%ptr, i64 %x) {
 ; frame size that needs two instructions to perform the final LMG for
 ; %r6 and above.
 define void @f3(i32 *%ptr, i64 %x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK: .cfi_offset %r6, -112
 ; CHECK: .cfi_offset %r7, -104
@@ -177,7 +177,7 @@ define void @f3(i32 *%ptr, i64 %x) {
 ; frame size that needs two instructions to perform the final LMG for
 ; %r14 and %r15.
 define void @f4(i32 *%ptr, i64 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: .cfi_offset %r14, -48
 ; CHECK: .cfi_offset %r15, -40
@@ -211,7 +211,7 @@ define void @f4(i32 *%ptr, i64 %x) {
 ; This is the largest frame size for which the prepatory increment for
 ; "lmg %r14, %r15, ..." can be done using AGHI.
 define void @f5(i32 *%ptr, i64 %x) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: .cfi_offset %r14, -48
 ; CHECK: .cfi_offset %r15, -40
@@ -245,7 +245,7 @@ define void @f5(i32 *%ptr, i64 %x) {
 ; This is the smallest frame size for which the prepatory increment for
 ; "lmg %r14, %r15, ..." needs to be done using AGFI.
 define void @f6(i32 *%ptr, i64 %x) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: .cfi_offset %r14, -48
 ; CHECK: .cfi_offset %r15, -40
diff --git a/test/CodeGen/SystemZ/frame-09.ll b/test/CodeGen/SystemZ/frame-09.ll
index 6b6341a..8a4f99c 100644
--- a/test/CodeGen/SystemZ/frame-09.ll
+++ b/test/CodeGen/SystemZ/frame-09.ll
@@ -6,7 +6,7 @@
 ; We don't need to allocate any more than the caller-provided 160-byte
 ; area though.
 define i32 @f1(i32 %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: .cfi_offset %r11, -72
 ; CHECK: .cfi_offset %r15, -40
@@ -22,7 +22,7 @@ define i32 @f1(i32 %x) {
 ; Make sure that frame accesses after the initial allocation are relative
 ; to %r11 rather than %r15.
 define void @f2(i64 %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: .cfi_offset %r11, -72
 ; CHECK: .cfi_offset %r15, -40
@@ -41,7 +41,7 @@ define void @f2(i64 %x) {
 ; This function should require all GPRs but no other spill slots.
 ; It shouldn't need to allocate its own frame.
 define void @f3(i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %r11
@@ -111,7 +111,7 @@ define void @f3(i32 *%ptr) {
 ; emergency spill slots at 160(%r11), so create a frame of size 524192
 ; by allocating (524192 - 176) / 8 = 65502 doublewords.
 define void @f4(i64 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: .cfi_offset %r11, -72
 ; CHECK: .cfi_offset %r15, -40
@@ -131,7 +131,7 @@ define void @f4(i64 %x) {
 
 ; The next frame size larger than f4.
 define void @f5(i64 %x) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: .cfi_offset %r11, -72
 ; CHECK: .cfi_offset %r15, -40
diff --git a/test/CodeGen/SystemZ/frame-10.ll b/test/CodeGen/SystemZ/frame-10.ll
index 399a412..b96973a 100644
--- a/test/CodeGen/SystemZ/frame-10.ll
+++ b/test/CodeGen/SystemZ/frame-10.ll
@@ -5,7 +5,7 @@
 declare i8 *@llvm.stacksave()
 
 define void @f1(i8 **%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stg %r15, 0(%r2)
 ; CHECK: br %r14
   %addr = call i8 *@llvm.stacksave()
diff --git a/test/CodeGen/SystemZ/frame-11.ll b/test/CodeGen/SystemZ/frame-11.ll
index 8422205..5145b4d 100644
--- a/test/CodeGen/SystemZ/frame-11.ll
+++ b/test/CodeGen/SystemZ/frame-11.ll
@@ -7,7 +7,7 @@ declare void @llvm.stackrestore(i8 *)
 ; we should use a frame pointer and tear down the frame based on %r11
 ; rather than %r15.
 define void @f1(i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: lgr %r11, %r15
 ; CHECK: lgr %r15, %r2
diff --git a/test/CodeGen/SystemZ/frame-13.ll b/test/CodeGen/SystemZ/frame-13.ll
index 75793a0..1d38354 100644
--- a/test/CodeGen/SystemZ/frame-13.ll
+++ b/test/CodeGen/SystemZ/frame-13.ll
@@ -22,11 +22,11 @@
 ; in order to put another object at offset 4088 is (4088 - 176) / 4 = 978
 ; words.
 define void @f1() {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: mvhi 4092(%r15), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: mvhi 4092(%r11), 42
 ; CHECK-FP: br %r14
   %region1 = alloca [978 x i32], align 8
@@ -40,12 +40,12 @@ define void @f1() {
 
 ; Test the first out-of-range offset.  We cannot use an index register here.
 define void @f2() {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: lay %r1, 4096(%r15)
 ; CHECK-NOFP: mvhi 0(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: lay %r1, 4096(%r11)
 ; CHECK-FP: mvhi 0(%r1), 42
 ; CHECK-FP: br %r14
@@ -60,12 +60,12 @@ define void @f2() {
 
 ; Test the next offset after that.
 define void @f3() {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
 ; CHECK-NOFP: lay %r1, 4096(%r15)
 ; CHECK-NOFP: mvhi 4(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
 ; CHECK-FP: lay %r1, 4096(%r11)
 ; CHECK-FP: mvhi 4(%r1), 42
 ; CHECK-FP: br %r14
@@ -80,12 +80,12 @@ define void @f3() {
 
 ; Add 4096 bytes (1024 words) to the size of each object and repeat.
 define void @f4() {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
 ; CHECK-NOFP: lay %r1, 4096(%r15)
 ; CHECK-NOFP: mvhi 4092(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
 ; CHECK-FP: lay %r1, 4096(%r11)
 ; CHECK-FP: mvhi 4092(%r1), 42
 ; CHECK-FP: br %r14
@@ -100,12 +100,12 @@ define void @f4() {
 
 ; ...as above.
 define void @f5() {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
 ; CHECK-NOFP: lay %r1, 8192(%r15)
 ; CHECK-NOFP: mvhi 0(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
 ; CHECK-FP: lay %r1, 8192(%r11)
 ; CHECK-FP: mvhi 0(%r1), 42
 ; CHECK-FP: br %r14
@@ -120,12 +120,12 @@ define void @f5() {
 
 ; ...as above.
 define void @f6() {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
 ; CHECK-NOFP: lay %r1, 8192(%r15)
 ; CHECK-NOFP: mvhi 4(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
 ; CHECK-FP: lay %r1, 8192(%r11)
 ; CHECK-FP: mvhi 4(%r1), 42
 ; CHECK-FP: br %r14
@@ -142,12 +142,12 @@ define void @f6() {
 ; being at offset 8192.  This time we need objects of (8192 - 176) / 4 = 2004
 ; words.
 define void @f7() {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
 ; CHECK-NOFP: lay %r1, 8192(%r15)
 ; CHECK-NOFP: mvhi 4092(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
 ; CHECK-FP: lay %r1, 8192(%r11)
 ; CHECK-FP: mvhi 4092(%r1), 42
 ; CHECK-FP: br %r14
@@ -163,12 +163,12 @@ define void @f7() {
 ; Keep the object-relative offset the same but bump the size of the
 ; objects by one doubleword.
 define void @f8() {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
 ; CHECK-NOFP: lay %r1, 12288(%r15)
 ; CHECK-NOFP: mvhi 4(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
 ; CHECK-FP: lay %r1, 12288(%r11)
 ; CHECK-FP: mvhi 4(%r1), 42
 ; CHECK-FP: br %r14
@@ -185,12 +185,12 @@ define void @f8() {
 ; should force an LAY from the outset.  We don't yet do any kind of anchor
 ; optimization, so there should be no offset on the MVHI itself.
 define void @f9() {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
 ; CHECK-NOFP: lay %r1, 12296(%r15)
 ; CHECK-NOFP: mvhi 0(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
 ; CHECK-FP: lay %r1, 12296(%r11)
 ; CHECK-FP: mvhi 0(%r1), 42
 ; CHECK-FP: br %r14
@@ -207,14 +207,14 @@ define void @f9() {
 ; call-clobbered registers are live and no call-saved ones have been
 ; allocated).
 define void @f10(i32 *%vptr) {
-; CHECK-NOFP: f10:
+; CHECK-NOFP-LABEL: f10:
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: lay [[REGISTER]], 4096(%r15)
 ; CHECK-NOFP: mvhi 0([[REGISTER]]), 42
 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f10:
+; CHECK-FP-LABEL: f10:
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: lay [[REGISTER]], 4096(%r11)
 ; CHECK-FP: mvhi 0([[REGISTER]]), 42
@@ -244,7 +244,7 @@ define void @f10(i32 *%vptr) {
 ; However, the FP case uses %r11 as the frame pointer and must therefore
 ; spill a second register.  This leads to an extra displacement of 8.
 define void @f11(i32 *%vptr) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
 ; CHECK-NOFP: stmg %r6, %r15,
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: lay [[REGISTER]], 4096(%r15)
@@ -253,7 +253,7 @@ define void @f11(i32 *%vptr) {
 ; CHECK-NOFP: lmg %r6, %r15,
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
 ; CHECK-FP: stmg %r6, %r15,
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: lay [[REGISTER]], 4096(%r11)
diff --git a/test/CodeGen/SystemZ/frame-14.ll b/test/CodeGen/SystemZ/frame-14.ll
index 29fab98..22a45ee 100644
--- a/test/CodeGen/SystemZ/frame-14.ll
+++ b/test/CodeGen/SystemZ/frame-14.ll
@@ -20,11 +20,11 @@
 ; emergency spill slots at 160(%r15), the amount that we need to allocate
 ; in order to put another object at offset 4088 is 4088 - 176 = 3912 bytes.
 define void @f1() {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: mvi 4095(%r15), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: mvi 4095(%r11), 42
 ; CHECK-FP: br %r14
   %region1 = alloca [3912 x i8], align 8
@@ -38,11 +38,11 @@ define void @f1() {
 
 ; Test the first offset that is out-of-range of the 12-bit form.
 define void @f2() {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: mviy 4096(%r15), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: mviy 4096(%r11), 42
 ; CHECK-FP: br %r14
   %region1 = alloca [3912 x i8], align 8
@@ -59,11 +59,11 @@ define void @f2() {
 ; The last in-range doubleword offset is 524280, so by the same reasoning
 ; as above, we need to allocate objects of 524280 - 176 = 524104 bytes.
 define void @f3() {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
 ; CHECK-NOFP: mviy 524287(%r15), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
 ; CHECK-FP: mviy 524287(%r11), 42
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
@@ -79,13 +79,13 @@ define void @f3() {
 ; and the offset is also out of LAY's range, so expect a constant load
 ; followed by an addition.
 define void @f4() {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mvi 0(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mvi 0(%r1), 42
@@ -102,13 +102,13 @@ define void @f4() {
 ; Add 4095 to the previous offset, to test the other end of the MVI range.
 ; The instruction will actually be STCY before frame lowering.
 define void @f5() {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mvi 4095(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mvi 4095(%r1), 42
@@ -124,13 +124,13 @@ define void @f5() {
 
 ; Test the next offset after that, which uses MVIY instead of MVI.
 define void @f6() {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mviy 4096(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mviy 4096(%r1), 42
@@ -149,13 +149,13 @@ define void @f6() {
 ; anchors 0x10000 bytes apart, so that the high part can be loaded using
 ; LLILH while still using MVI in more cases than 0x40000 anchors would.
 define void @f7() {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
 ; CHECK-NOFP: llilh %r1, 23
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mviy 65535(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
 ; CHECK-FP: llilh %r1, 23
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mviy 65535(%r1), 42
@@ -172,13 +172,13 @@ define void @f7() {
 ; Keep the object-relative offset the same but bump the size of the
 ; objects by one doubleword.
 define void @f8() {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
 ; CHECK-NOFP: llilh %r1, 24
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mvi 7(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
 ; CHECK-FP: llilh %r1, 24
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mvi 7(%r1), 42
@@ -200,14 +200,14 @@ define void @f8() {
 ; The LA then gets lowered into the LLILH/LA form.  The exact sequence
 ; isn't that important though.
 define void @f9() {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
 ; CHECK-NOFP: llilh [[R1:%r[1-5]]], 16
 ; CHECK-NOFP: la [[R2:%r[1-5]]], 8([[R1]],%r15)
 ; CHECK-NOFP: agfi [[R2]], 524288
 ; CHECK-NOFP: mvi 0([[R2]]), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
 ; CHECK-FP: llilh [[R1:%r[1-5]]], 16
 ; CHECK-FP: la [[R2:%r[1-5]]], 8([[R1]],%r11)
 ; CHECK-FP: agfi [[R2]], 524288
@@ -226,7 +226,7 @@ define void @f9() {
 ; call-clobbered registers are live and no call-saved ones have been
 ; allocated).
 define void @f10(i32 *%vptr) {
-; CHECK-NOFP: f10:
+; CHECK-NOFP-LABEL: f10:
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: llilh [[REGISTER]], 8
 ; CHECK-NOFP: agr [[REGISTER]], %r15
@@ -234,7 +234,7 @@ define void @f10(i32 *%vptr) {
 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f10:
+; CHECK-FP-LABEL: f10:
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: llilh [[REGISTER]], 8
 ; CHECK-FP: agr [[REGISTER]], %r11
@@ -265,7 +265,7 @@ define void @f10(i32 *%vptr) {
 ; However, the FP case uses %r11 as the frame pointer and must therefore
 ; spill a second register.  This leads to an extra displacement of 8.
 define void @f11(i32 *%vptr) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
 ; CHECK-NOFP: stmg %r6, %r15,
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: llilh [[REGISTER]], 8
@@ -275,7 +275,7 @@ define void @f11(i32 *%vptr) {
 ; CHECK-NOFP: lmg %r6, %r15,
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
 ; CHECK-FP: stmg %r6, %r15,
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: llilh [[REGISTER]], 8
diff --git a/test/CodeGen/SystemZ/frame-15.ll b/test/CodeGen/SystemZ/frame-15.ll
index af804da..d8b291d 100644
--- a/test/CodeGen/SystemZ/frame-15.ll
+++ b/test/CodeGen/SystemZ/frame-15.ll
@@ -24,11 +24,11 @@ declare void @foo(float *%ptr1, float *%ptr2)
 ; in order to put another object at offset 4088 is (4088 - 176) / 4 = 978
 ; words.
 define void @f1(double *%dst) {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r11)
 ; CHECK-FP: br %r14
   %region1 = alloca [978 x float], align 8
@@ -49,12 +49,12 @@ define void @f1(double *%dst) {
 
 ; Test the first out-of-range offset.
 define void @f2(double *%dst) {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: lghi %r1, 4096
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: lghi %r1, 4096
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -76,12 +76,12 @@ define void @f2(double *%dst) {
 
 ; Test the next offset after that.
 define void @f3(double *%dst) {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
 ; CHECK-NOFP: lghi %r1, 4096
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
 ; CHECK-FP: lghi %r1, 4096
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -103,12 +103,12 @@ define void @f3(double *%dst) {
 
 ; Add 4096 bytes (1024 words) to the size of each object and repeat.
 define void @f4(double *%dst) {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
 ; CHECK-NOFP: lghi %r1, 4096
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
 ; CHECK-FP: lghi %r1, 4096
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -130,12 +130,12 @@ define void @f4(double *%dst) {
 
 ; ...as above.
 define void @f5(double *%dst) {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
 ; CHECK-NOFP: lghi %r1, 8192
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
 ; CHECK-FP: lghi %r1, 8192
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -157,12 +157,12 @@ define void @f5(double *%dst) {
 
 ; ...as above.
 define void @f6(double *%dst) {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
 ; CHECK-NOFP: lghi %r1, 8192
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
 ; CHECK-FP: lghi %r1, 8192
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -186,12 +186,12 @@ define void @f6(double *%dst) {
 ; being at offset 8192.  This time we need objects of (8192 - 168) / 4 = 2004
 ; words.
 define void @f7(double *%dst) {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
 ; CHECK-NOFP: lghi %r1, 8192
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
 ; CHECK-FP: lghi %r1, 8192
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -214,12 +214,12 @@ define void @f7(double *%dst) {
 ; Keep the object-relative offset the same but bump the size of the
 ; objects by one doubleword.
 define void @f8(double *%dst) {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
 ; CHECK-NOFP: lghi %r1, 12288
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
 ; CHECK-FP: lghi %r1, 12288
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -243,12 +243,12 @@ define void @f8(double *%dst) {
 ; should force an LAY from the outset.  We don't yet do any kind of anchor
 ; optimization, so there should be no offset on the LDEB itself.
 define void @f9(double *%dst) {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
 ; CHECK-NOFP: lay %r1, 12296(%r15)
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
 ; CHECK-FP: lay %r1, 12296(%r11)
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1)
 ; CHECK-FP: br %r14
@@ -273,14 +273,14 @@ define void @f9(double *%dst) {
 ; %vptr and %dst are copied to call-saved registers, freeing up %r2 and
 ; %r3 during the main test.
 define void @f10(i32 *%vptr, double *%dst) {
-; CHECK-NOFP: f10:
+; CHECK-NOFP-LABEL: f10:
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: lghi [[REGISTER]], 4096
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r15)
 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f10:
+; CHECK-FP-LABEL: f10:
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: lghi [[REGISTER]], 4096
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r11)
@@ -318,13 +318,13 @@ define void @f10(i32 *%vptr, double *%dst) {
 
 ; Repeat f2 in a case where the index register is already occupied.
 define void @f11(double *%dst, i64 %index) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
 ; CHECK-NOFP: lgr [[REGISTER:%r[1-9][0-5]?]], %r3
 ; CHECK-NOFP: lay %r1, 4096(%r15)
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r1)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
 ; CHECK-FP: lgr [[REGISTER:%r[1-9][0-5]?]], %r3
 ; CHECK-FP: lay %r1, 4096(%r11)
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r1)
diff --git a/test/CodeGen/SystemZ/frame-16.ll b/test/CodeGen/SystemZ/frame-16.ll
index dc67da9..9f43b49 100644
--- a/test/CodeGen/SystemZ/frame-16.ll
+++ b/test/CodeGen/SystemZ/frame-16.ll
@@ -20,11 +20,11 @@
 ; emergency spill slots at 160(%r15), the amount that we need to allocate
 ; in order to put another object at offset 4088 is 4088 - 176 = 3912 bytes.
 define void @f1(i8 %byte) {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: stc %r2, 4095(%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: stc %r2, 4095(%r11)
 ; CHECK-FP: br %r14
   %region1 = alloca [3912 x i8], align 8
@@ -38,11 +38,11 @@ define void @f1(i8 %byte) {
 
 ; Test the first offset that is out-of-range of the 12-bit form.
 define void @f2(i8 %byte) {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: stcy %r2, 4096(%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: stcy %r2, 4096(%r11)
 ; CHECK-FP: br %r14
   %region1 = alloca [3912 x i8], align 8
@@ -59,11 +59,11 @@ define void @f2(i8 %byte) {
 ; The last in-range doubleword offset is 524280, so by the same reasoning
 ; as above, we need to allocate objects of 524280 - 176 = 524104 bytes.
 define void @f3(i8 %byte) {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
 ; CHECK-NOFP: stcy %r2, 524287(%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
 ; CHECK-FP: stcy %r2, 524287(%r11)
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
@@ -79,12 +79,12 @@ define void @f3(i8 %byte) {
 ; and the offset is also out of LAY's range, so expect a constant load
 ; followed by an addition.
 define void @f4(i8 %byte) {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: stc %r2, 0(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: stc %r2, 0(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -100,12 +100,12 @@ define void @f4(i8 %byte) {
 ; Add 4095 to the previous offset, to test the other end of the STC range.
 ; The instruction will actually be STCY before frame lowering.
 define void @f5(i8 %byte) {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: stc %r2, 4095(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: stc %r2, 4095(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -120,12 +120,12 @@ define void @f5(i8 %byte) {
 
 ; Test the next offset after that, which uses STCY instead of STC.
 define void @f6(i8 %byte) {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: stcy %r2, 4096(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: stcy %r2, 4096(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -143,12 +143,12 @@ define void @f6(i8 %byte) {
 ; anchors 0x10000 bytes apart, so that the high part can be loaded using
 ; LLILH while still using STC in more cases than 0x40000 anchors would.
 define void @f7(i8 %byte) {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
 ; CHECK-NOFP: llilh %r1, 23
 ; CHECK-NOFP: stcy %r2, 65535(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
 ; CHECK-FP: llilh %r1, 23
 ; CHECK-FP: stcy %r2, 65535(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -164,12 +164,12 @@ define void @f7(i8 %byte) {
 ; Keep the object-relative offset the same but bump the size of the
 ; objects by one doubleword.
 define void @f8(i8 %byte) {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
 ; CHECK-NOFP: llilh %r1, 24
 ; CHECK-NOFP: stc %r2, 7(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
 ; CHECK-FP: llilh %r1, 24
 ; CHECK-FP: stc %r2, 7(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -190,14 +190,14 @@ define void @f8(i8 %byte) {
 ; The LA then gets lowered into the LLILH/LA form.  The exact sequence
 ; isn't that important though.
 define void @f9(i8 %byte) {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
 ; CHECK-NOFP: llilh [[R1:%r[1-5]]], 16
 ; CHECK-NOFP: la [[R2:%r[1-5]]], 8([[R1]],%r15)
 ; CHECK-NOFP: agfi [[R2]], 524288
 ; CHECK-NOFP: stc %r2, 0([[R2]])
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
 ; CHECK-FP: llilh [[R1:%r[1-5]]], 16
 ; CHECK-FP: la [[R2:%r[1-5]]], 8([[R1]],%r11)
 ; CHECK-FP: agfi [[R2]], 524288
@@ -216,14 +216,14 @@ define void @f9(i8 %byte) {
 ; call-clobbered registers are live and no call-saved ones have been
 ; allocated).
 define void @f10(i32 *%vptr, i8 %byte) {
-; CHECK-NOFP: f10:
+; CHECK-NOFP-LABEL: f10:
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: llilh [[REGISTER]], 8
 ; CHECK-NOFP: stc %r3, 0([[REGISTER]],%r15)
 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f10:
+; CHECK-FP-LABEL: f10:
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: llilh [[REGISTER]], 8
 ; CHECK-FP: stc %r3, 0([[REGISTER]],%r11)
@@ -251,7 +251,7 @@ define void @f10(i32 *%vptr, i8 %byte) {
 ; However, the FP case uses %r11 as the frame pointer and must therefore
 ; spill a second register.  This leads to an extra displacement of 8.
 define void @f11(i32 *%vptr, i8 %byte) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
 ; CHECK-NOFP: stmg %r6, %r15,
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: llilh [[REGISTER]], 8
@@ -260,7 +260,7 @@ define void @f11(i32 *%vptr, i8 %byte) {
 ; CHECK-NOFP: lmg %r6, %r15,
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
 ; CHECK-FP: stmg %r6, %r15,
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: llilh [[REGISTER]], 8
@@ -305,13 +305,13 @@ define void @f11(i32 *%vptr, i8 %byte) {
 
 ; Repeat f4 in a case where the index register is already occupied.
 define void @f12(i8 %byte, i64 %index) {
-; CHECK-NOFP: f12:
+; CHECK-NOFP-LABEL: f12:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: stc %r2, 0(%r3,%r1)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f12:
+; CHECK-FP-LABEL: f12:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: stc %r2, 0(%r3,%r1)
diff --git a/test/CodeGen/SystemZ/frame-17.ll b/test/CodeGen/SystemZ/frame-17.ll
index 613d9f8..97cf83d 100644
--- a/test/CodeGen/SystemZ/frame-17.ll
+++ b/test/CodeGen/SystemZ/frame-17.ll
@@ -6,7 +6,7 @@
 ; 4-byte spill slot, rounded to 8 bytes.  The frame size should be exactly
 ; 160 + 8 * 8 = 232.
 define void @f1(float *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -232
 ; CHECK: std %f8, 224(%r15)
 ; CHECK: std %f9, 216(%r15)
@@ -70,7 +70,7 @@ define void @f1(float *%ptr) {
 
 ; Same for doubles, except that the full spill slot is used.
 define void @f2(double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -232
 ; CHECK: std %f8, 224(%r15)
 ; CHECK: std %f9, 216(%r15)
@@ -131,7 +131,7 @@ define void @f2(double *%ptr) {
 
 ; The long double case needs a 16-byte spill slot.
 define void @f3(fp128 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -240
 ; CHECK: std %f8, 232(%r15)
 ; CHECK: std %f9, 224(%r15)
diff --git a/test/CodeGen/SystemZ/frame-18.ll b/test/CodeGen/SystemZ/frame-18.ll
index a9977ed..57d6f7d 100644
--- a/test/CodeGen/SystemZ/frame-18.ll
+++ b/test/CodeGen/SystemZ/frame-18.ll
@@ -5,7 +5,7 @@
 ; We need to allocate a 4-byte spill slot, rounded to 8 bytes.  The frame
 ; size should be exactly 160 + 8 = 168.
 define void @f1(i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK: aghi %r15, -168
 ; CHECK-NOT: 160(%r15)
@@ -50,7 +50,7 @@ define void @f1(i32 *%ptr) {
 
 ; Same for i64, except that the full spill slot is used.
 define void @f2(i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK: aghi %r15, -168
 ; CHECK: stg [[REGISTER:%r[0-9]+]], 160(%r15)
diff --git a/test/CodeGen/SystemZ/insert-01.ll b/test/CodeGen/SystemZ/insert-01.ll
index 2ff9ff4..5f14b29 100644
--- a/test/CodeGen/SystemZ/insert-01.ll
+++ b/test/CodeGen/SystemZ/insert-01.ll
@@ -5,7 +5,7 @@
 ; Check a plain insertion with (or (and ... -0xff) (zext (load ....))).
 ; The whole sequence can be performed by IC.
 define i32 @f1(i32 %orig, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define i32 @f1(i32 %orig, i8 *%ptr) {
 
 ; Like f1, but with the operands reversed.
 define i32 @f2(i32 %orig, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -32,7 +32,7 @@ define i32 @f2(i32 %orig, i8 *%ptr) {
 ; Check a case where more bits than lower 8 are masked out of the
 ; register value.  We can use IC but must keep the original mask.
 define i32 @f3(i32 %orig, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: risbg %r2, %r2, 32, 182, 0
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -45,7 +45,7 @@ define i32 @f3(i32 %orig, i8 *%ptr) {
 
 ; Like f3, but with the operands reversed.
 define i32 @f4(i32 %orig, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: risbg %r2, %r2, 32, 182, 0
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i32 @f4(i32 %orig, i8 *%ptr) {
 
 ; Check a case where the low 8 bits are cleared by a shift left.
 define i32 @f5(i32 %orig, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sll %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f5(i32 %orig, i8 *%ptr) {
 
 ; Like f5, but with the operands reversed.
 define i32 @f6(i32 %orig, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sll %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i32 @f6(i32 %orig, i8 *%ptr) {
 
 ; Check insertions into a constant.
 define i32 @f7(i32 %orig, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lhi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -96,7 +96,7 @@ define i32 @f7(i32 %orig, i8 *%ptr) {
 
 ; Like f7, but with the operands reversed.
 define i32 @f8(i32 %orig, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lhi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define i32 @f8(i32 %orig, i8 *%ptr) {
 
 ; Check the high end of the IC range.
 define i32 @f9(i32 %orig, i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ic %r2, 4095(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -121,7 +121,7 @@ define i32 @f9(i32 %orig, i8 *%src) {
 
 ; Check the next byte up, which should use ICY instead of IC.
 define i32 @f10(i32 %orig, i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: icy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -134,7 +134,7 @@ define i32 @f10(i32 %orig, i8 *%src) {
 
 ; Check the high end of the ICY range.
 define i32 @f11(i32 %orig, i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: icy %r2, 524287(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -148,7 +148,7 @@ define i32 @f11(i32 %orig, i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f12(i32 %orig, i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -162,7 +162,7 @@ define i32 @f12(i32 %orig, i8 *%src) {
 
 ; Check the high end of the negative ICY range.
 define i32 @f13(i32 %orig, i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: icy %r2, -1(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -175,7 +175,7 @@ define i32 @f13(i32 %orig, i8 *%src) {
 
 ; Check the low end of the ICY range.
 define i32 @f14(i32 %orig, i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: icy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -189,7 +189,7 @@ define i32 @f14(i32 %orig, i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f15(i32 %orig, i8 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: agfi %r3, -524289
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -203,7 +203,7 @@ define i32 @f15(i32 %orig, i8 *%src) {
 
 ; Check that IC allows an index.
 define i32 @f16(i32 %orig, i8 *%src, i64 %index) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %ptr1 = getelementptr i8 *%src, i64 %index
@@ -217,7 +217,7 @@ define i32 @f16(i32 %orig, i8 *%src, i64 %index) {
 
 ; Check that ICY allows an index.
 define i32 @f17(i32 %orig, i8 *%src, i64 %index) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %ptr1 = getelementptr i8 *%src, i64 %index
diff --git a/test/CodeGen/SystemZ/insert-02.ll b/test/CodeGen/SystemZ/insert-02.ll
index e998014..05958a6 100644
--- a/test/CodeGen/SystemZ/insert-02.ll
+++ b/test/CodeGen/SystemZ/insert-02.ll
@@ -5,7 +5,7 @@
 ; Check a plain insertion with (or (and ... -0xff) (zext (load ....))).
 ; The whole sequence can be performed by IC.
 define i64 @f1(i64 %orig, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define i64 @f1(i64 %orig, i8 *%ptr) {
 
 ; Like f1, but with the operands reversed.
 define i64 @f2(i64 %orig, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -32,7 +32,7 @@ define i64 @f2(i64 %orig, i8 *%ptr) {
 ; Check a case where more bits than lower 8 are masked out of the
 ; register value.  We can use IC but must keep the original mask.
 define i64 @f3(i64 %orig, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: risbg %r2, %r2, 0, 182, 0
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -45,7 +45,7 @@ define i64 @f3(i64 %orig, i8 *%ptr) {
 
 ; Like f3, but with the operands reversed.
 define i64 @f4(i64 %orig, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: risbg %r2, %r2, 0, 182, 0
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i64 @f4(i64 %orig, i8 *%ptr) {
 
 ; Check a case where the low 8 bits are cleared by a shift left.
 define i64 @f5(i64 %orig, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sllg %r2, %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i64 @f5(i64 %orig, i8 *%ptr) {
 
 ; Like f5, but with the operands reversed.
 define i64 @f6(i64 %orig, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r2, %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f6(i64 %orig, i8 *%ptr) {
 
 ; Check insertions into a constant.
 define i64 @f7(i64 %orig, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lghi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -96,7 +96,7 @@ define i64 @f7(i64 %orig, i8 *%ptr) {
 
 ; Like f7, but with the operands reversed.
 define i64 @f8(i64 %orig, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lghi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define i64 @f8(i64 %orig, i8 *%ptr) {
 
 ; Check the high end of the IC range.
 define i64 @f9(i64 %orig, i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ic %r2, 4095(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -121,7 +121,7 @@ define i64 @f9(i64 %orig, i8 *%src) {
 
 ; Check the next byte up, which should use ICY instead of IC.
 define i64 @f10(i64 %orig, i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: icy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -134,7 +134,7 @@ define i64 @f10(i64 %orig, i8 *%src) {
 
 ; Check the high end of the ICY range.
 define i64 @f11(i64 %orig, i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: icy %r2, 524287(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -148,7 +148,7 @@ define i64 @f11(i64 %orig, i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f12(i64 %orig, i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -162,7 +162,7 @@ define i64 @f12(i64 %orig, i8 *%src) {
 
 ; Check the high end of the negative ICY range.
 define i64 @f13(i64 %orig, i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: icy %r2, -1(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -175,7 +175,7 @@ define i64 @f13(i64 %orig, i8 *%src) {
 
 ; Check the low end of the ICY range.
 define i64 @f14(i64 %orig, i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: icy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -189,7 +189,7 @@ define i64 @f14(i64 %orig, i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f15(i64 %orig, i8 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: agfi %r3, -524289
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -203,7 +203,7 @@ define i64 @f15(i64 %orig, i8 *%src) {
 
 ; Check that IC allows an index.
 define i64 @f16(i64 %orig, i8 *%src, i64 %index) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %ptr1 = getelementptr i8 *%src, i64 %index
@@ -217,7 +217,7 @@ define i64 @f16(i64 %orig, i8 *%src, i64 %index) {
 
 ; Check that ICY allows an index.
 define i64 @f17(i64 %orig, i8 *%src, i64 %index) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %ptr1 = getelementptr i8 *%src, i64 %index
diff --git a/test/CodeGen/SystemZ/insert-03.ll b/test/CodeGen/SystemZ/insert-03.ll
index 261eabd..c3c1ae3 100644
--- a/test/CodeGen/SystemZ/insert-03.ll
+++ b/test/CodeGen/SystemZ/insert-03.ll
@@ -5,7 +5,7 @@
 ; Check the lowest useful IILL value.  (We use NILL rather than IILL
 ; to clear 16 bits.)
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 1
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define i32 @f1(i32 %a) {
 
 ; Check a middle value.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 32769
 ; CHECK: br %r14
@@ -28,7 +28,7 @@ define i32 @f2(i32 %a) {
 ; Check the highest useful IILL value.  (We use OILL rather than IILL
 ; to set 16 bits.)
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 65534
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define i32 @f3(i32 %a) {
 
 ; Check the lowest useful IILH value.
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 1
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define i32 @f4(i32 %a) {
 
 ; Check a middle value.
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 32767
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define i32 @f5(i32 %a) {
 
 ; Check the highest useful IILH value.
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 65534
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/insert-04.ll b/test/CodeGen/SystemZ/insert-04.ll
index 07f88b9..5ce99df 100644
--- a/test/CodeGen/SystemZ/insert-04.ll
+++ b/test/CodeGen/SystemZ/insert-04.ll
@@ -5,7 +5,7 @@
 ; Check the lowest useful IILL value.  (We use NILL rather than IILL
 ; to clear 16 bits.)
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 1
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a) {
 
 ; Check a middle value.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 32769
 ; CHECK: br %r14
@@ -28,7 +28,7 @@ define i64 @f2(i64 %a) {
 ; Check the highest useful IILL value.  (We use OILL rather than IILL
 ; to set 16 bits.)
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 65534
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define i64 @f3(i64 %a) {
 
 ; Check the lowest useful IILH value.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 1
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define i64 @f4(i64 %a) {
 
 ; Check a middle value.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 32767
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the highest useful IILH value.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 65534
 ; CHECK: br %r14
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a) {
 
 ; Check the lowest useful IIHL value.
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: ni
 ; CHECK: iihl %r2, 1
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define i64 @f7(i64 %a) {
 
 ; Check a middle value.
 define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: ni
 ; CHECK: iihl %r2, 32767
 ; CHECK: br %r14
@@ -94,7 +94,7 @@ define i64 @f8(i64 %a) {
 
 ; Check the highest useful IIHL value.
 define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: ni
 ; CHECK: iihl %r2, 65534
 ; CHECK: br %r14
@@ -105,7 +105,7 @@ define i64 @f9(i64 %a) {
 
 ; Check the lowest useful IIHH value.
 define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: ni
 ; CHECK: iihh %r2, 1
 ; CHECK: br %r14
@@ -116,7 +116,7 @@ define i64 @f10(i64 %a) {
 
 ; Check a middle value.
 define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: ni
 ; CHECK: iihh %r2, 32767
 ; CHECK: br %r14
@@ -127,7 +127,7 @@ define i64 @f11(i64 %a) {
 
 ; Check the highest useful IIHH value.
 define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: ni
 ; CHECK: iihh %r2, 65534
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/insert-05.ll b/test/CodeGen/SystemZ/insert-05.ll
index da51676..b76859a 100644
--- a/test/CodeGen/SystemZ/insert-05.ll
+++ b/test/CodeGen/SystemZ/insert-05.ll
@@ -4,7 +4,7 @@
 
 ; Prefer LHI over IILF for signed 16-bit constants.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: lhi %r2, 1
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the LHI range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: lhi %r2, 32767
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define i64 @f2(i64 %a) {
 
 ; Check the next value up, which should use IILF instead.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: ni
 ; CHECK: iilf %r2, 32768
 ; CHECK: br %r14
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a) {
 
 ; Check a value in which the lower 16 bits are clear.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: ni
 ; CHECK: iilf %r2, 65536
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define i64 @f4(i64 %a) {
 
 ; Check the highest useful IILF value (-0x8001).
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: ni
 ; CHECK: iilf %r2, 4294934527
 ; CHECK: br %r14
@@ -59,7 +59,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the next value up, which should use LHI instead.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: ni
 ; CHECK: lhi %r2, -32768
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i64 @f6(i64 %a) {
 ; Check the highest useful LHI value.  (We use OILF for -1 instead, although
 ; LHI might be better there too.)
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: ni
 ; CHECK: lhi %r2, -2
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define i64 @f7(i64 %a) {
 ; Check that SRLG is still used if some of the high bits are known to be 0
 ; (and so might be removed from the mask).
 define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK-NEXT: iilf %r2, 32768
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f8(i64 %a) {
 
 ; Repeat f8 with addition, which is known to be equivalent to OR in this case.
 define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK-NEXT: iilf %r2, 32768
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define i64 @f9(i64 %a) {
 
 ; Repeat f8 with already-zero bits removed from the mask.
 define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK-NEXT: iilf %r2, 32768
 ; CHECK: br %r14
@@ -119,7 +119,7 @@ define i64 @f10(i64 %a) {
 
 ; Repeat f10 with addition, which is known to be equivalent to OR in this case.
 define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK-NEXT: iilf %r2, 32768
 ; CHECK: br %r14
@@ -131,7 +131,7 @@ define i64 @f11(i64 %a) {
 
 ; Check the lowest useful IIHF value.
 define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: ni
 ; CHECK: iihf %r2, 1
 ; CHECK: br %r14
@@ -142,7 +142,7 @@ define i64 @f12(i64 %a) {
 
 ; Check a value in which the lower 16 bits are clear.
 define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK-NOT: ni
 ; CHECK: iihf %r2, 2147483648
 ; CHECK: br %r14
@@ -153,7 +153,7 @@ define i64 @f13(i64 %a) {
 
 ; Check the highest useful IIHF value (0xfffffffe).
 define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: ni
 ; CHECK: iihf %r2, 4294967294
 ; CHECK: br %r14
@@ -165,7 +165,7 @@ define i64 @f14(i64 %a) {
 ; Check a case in which some of the low 32 bits are known to be clear,
 ; and so could be removed from the AND mask.
 define i64 @f15(i64 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: sllg %r2, %r2, 1
 ; CHECK-NEXT: iihf %r2, 1
 ; CHECK: br %r14
@@ -177,7 +177,7 @@ define i64 @f15(i64 %a) {
 
 ; Repeat f15 with the zero bits explicitly removed from the mask.
 define i64 @f16(i64 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: sllg %r2, %r2, 1
 ; CHECK-NEXT: iihf %r2, 1
 ; CHECK: br %r14
@@ -189,7 +189,7 @@ define i64 @f16(i64 %a) {
 
 ; Check concatenation of two i32s.
 define i64 @f17(i32 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: msr %r2, %r2
 ; CHECK-NEXT: iihf %r2, 1
 ; CHECK: br %r14
@@ -201,7 +201,7 @@ define i64 @f17(i32 %a) {
 
 ; Repeat f17 with the operands reversed.
 define i64 @f18(i32 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: msr %r2, %r2
 ; CHECK-NEXT: iihf %r2, 1
 ; CHECK: br %r14
@@ -213,7 +213,7 @@ define i64 @f18(i32 %a) {
 
 ; The truncation here isn't free; we need an explicit zero extension.
 define i64 @f19(i32 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: oihl %r2, 1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/insert-06.ll b/test/CodeGen/SystemZ/insert-06.ll
index 4a13ef4..8366b2c 100644
--- a/test/CodeGen/SystemZ/insert-06.ll
+++ b/test/CodeGen/SystemZ/insert-06.ll
@@ -4,7 +4,7 @@
 
 ; Insertion of an i32 can be done using LR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; ... and again with the operands reversed.
 define i64 @f2(i64 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -28,7 +28,7 @@ define i64 @f2(i64 %a, i32 %b) {
 
 ; Like f1, but with "in register" zero extension.
 define i64 @f3(i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define i64 @f3(i64 %a, i64 %b) {
 
 ; ... and again with the operands reversed.
 define i64 @f4(i64 %a, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -52,7 +52,7 @@ define i64 @f4(i64 %a, i64 %b) {
 
 ; Unary operations can be done directly into the low half.
 define i64 @f5(i64 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lcr %r2, %r3
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define i64 @f5(i64 %a, i32 %b) {
 
 ; ...likewise three-operand binary operations like RLL.
 define i64 @f6(i64 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: rll %r2, %r3, 1
 ; CHECK: br %r14
@@ -81,7 +81,7 @@ define i64 @f6(i64 %a, i32 %b) {
 ; Loads can be done directly into the low half.  The range of L is checked
 ; in the move tests.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: br %r14
@@ -94,7 +94,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; ...likewise extending loads.
 define i64 @f8(i64 %a, i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lb %r2, 0(%r3)
 ; CHECK: br %r14
@@ -110,7 +110,7 @@ define i64 @f8(i64 %a, i8 *%src) {
 ; that the upper half of one OR operand and the lower half of the other are
 ; both clear.
 define i64 @f9(i64 %a, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: sllg %r2, %r2, 32
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define i64 @f9(i64 %a, i32 %b) {
 
 ; ...and again with the operands reversed.
 define i64 @f10(i64 %a, i32 %b) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: sllg %r2, %r2, 32
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -134,7 +134,7 @@ define i64 @f10(i64 %a, i32 %b) {
 
 ; Like f9, but with "in register" zero extension.
 define i64 @f11(i64 %a, i64 %b) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   %shift = shl i64 %a, 32
@@ -145,7 +145,7 @@ define i64 @f11(i64 %a, i64 %b) {
 
 ; ...and again with the operands reversed.
 define i64 @f12(i64 %a, i64 %b) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   %shift = shl i64 %a, 32
@@ -156,7 +156,7 @@ define i64 @f12(i64 %a, i64 %b) {
 
 ; Like f9, but for larger shifts than 32.
 define i64 @f13(i64 %a, i32 %b) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: sllg %r2, %r2, 60
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-01.ll b/test/CodeGen/SystemZ/int-add-01.ll
index d12ac22..4114686 100644
--- a/test/CodeGen/SystemZ/int-add-01.ll
+++ b/test/CodeGen/SystemZ/int-add-01.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the AH range.
 define i32 @f1(i32 %lhs, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ah %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -16,7 +16,7 @@ define i32 @f1(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned AH range.
 define i32 @f2(i32 %lhs, i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ah %r2, 4094(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -28,7 +28,7 @@ define i32 @f2(i32 %lhs, i16 *%src) {
 
 ; Check the next halfword up, which should use AHY instead of AH.
 define i32 @f3(i32 %lhs, i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ahy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -40,7 +40,7 @@ define i32 @f3(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned AHY range.
 define i32 @f4(i32 %lhs, i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ahy %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -53,7 +53,7 @@ define i32 @f4(i32 %lhs, i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 %lhs, i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ah %r2, 0(%r3)
 ; CHECK: br %r14
@@ -66,7 +66,7 @@ define i32 @f5(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the negative aligned AHY range.
 define i32 @f6(i32 %lhs, i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ahy %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f6(i32 %lhs, i16 *%src) {
 
 ; Check the low end of the AHY range.
 define i32 @f7(i32 %lhs, i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ahy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -91,7 +91,7 @@ define i32 @f7(i32 %lhs, i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %lhs, i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524290
 ; CHECK: ah %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f8(i32 %lhs, i16 *%src) {
 
 ; Check that AH allows an index.
 define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ah %r2, 4094({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -118,7 +118,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
 
 ; Check that AHY allows an index.
 define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ahy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/int-add-02.ll b/test/CodeGen/SystemZ/int-add-02.ll
index bc434a6..0d4c8ce 100644
--- a/test/CodeGen/SystemZ/int-add-02.ll
+++ b/test/CodeGen/SystemZ/int-add-02.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Check AR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ar %r2, %r3
 ; CHECK: br %r14
   %add = add i32 %a, %b
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the A range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: a %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +25,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned A range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: a %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -36,7 +36,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use AY instead of A.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ay %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -47,7 +47,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned AY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ay %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -59,7 +59,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: a %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned AY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ay %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -82,7 +82,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the AY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ay %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -94,7 +94,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: a %r2, 0(%r3)
 ; CHECK: br %r14
@@ -106,7 +106,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that A allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: a %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -119,7 +119,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that AY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: ay %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -132,7 +132,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
 
 ; Check that additions of spilled values can use A rather than AR.
 define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: a %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-03.ll b/test/CodeGen/SystemZ/int-add-03.ll
index bfd163d..56000a8 100644
--- a/test/CodeGen/SystemZ/int-add-03.ll
+++ b/test/CodeGen/SystemZ/int-add-03.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check AGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: agfr %r2, %r3
 ; CHECK: br %r14
   %bext = sext i32 %b to i64
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check AGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: agf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -27,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned AGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -40,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: agf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -53,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned AGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the AGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -78,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: agf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that AGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -105,7 +105,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that additions of spilled values can use AGF rather than AGFR.
 define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: agf %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-04.ll b/test/CodeGen/SystemZ/int-add-04.ll
index 6c8e5cf..675e36b 100644
--- a/test/CodeGen/SystemZ/int-add-04.ll
+++ b/test/CodeGen/SystemZ/int-add-04.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check ALGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: algfr %r2, %r3
 ; CHECK: br %r14
   %bext = zext i32 %b to i64
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check ALGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: algf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -27,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned ALGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: algf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -40,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: algf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -53,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned ALGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: algf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the ALGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: algf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -78,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: algf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that ALGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: algf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -105,7 +105,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that additions of spilled values can use ALGF rather than ALGFR.
 define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: algf %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-05.ll b/test/CodeGen/SystemZ/int-add-05.ll
index ee840ac..4f39a2d 100644
--- a/test/CodeGen/SystemZ/int-add-05.ll
+++ b/test/CodeGen/SystemZ/int-add-05.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check AGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: agr %r2, %r3
 ; CHECK: br %r14
   %add = add i64 %a, %b
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check AG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ag %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -25,7 +25,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned AG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ag %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ag %r2, 0(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned AG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ag %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -60,7 +60,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the AG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ag %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: ag %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that AG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ag %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that additions of spilled values can use AG rather than AGR.
 define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: ag %r2, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-06.ll b/test/CodeGen/SystemZ/int-add-06.ll
index 3a9c698..142c755 100644
--- a/test/CodeGen/SystemZ/int-add-06.ll
+++ b/test/CodeGen/SystemZ/int-add-06.ll
@@ -4,7 +4,7 @@
 
 ; Check additions of 1.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ahi %r2, 1
 ; CHECK: br %r14
   %add = add i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the AHI range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ahi %r2, 32767
 ; CHECK: br %r14
   %add = add i32 %a, 32767
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; Check the next value up, which must use AFI instead.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi %r2, 32768
 ; CHECK: br %r14
   %add = add i32 %a, 32768
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Check the high end of the signed 32-bit range.
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi %r2, 2147483647
 ; CHECK: br %r14
   %add = add i32 %a, 2147483647
@@ -40,7 +40,7 @@ define i32 @f4(i32 %a) {
 
 ; Check the next value up, which is treated as a negative value.
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi %r2, -2147483648
 ; CHECK: br %r14
   %add = add i32 %a, 2147483648
@@ -49,7 +49,7 @@ define i32 @f5(i32 %a) {
 
 ; Check the high end of the negative AHI range.
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ahi %r2, -1
 ; CHECK: br %r14
   %add = add i32 %a, -1
@@ -58,7 +58,7 @@ define i32 @f6(i32 %a) {
 
 ; Check the low end of the AHI range.
 define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ahi %r2, -32768
 ; CHECK: br %r14
   %add = add i32 %a, -32768
@@ -67,7 +67,7 @@ define i32 @f7(i32 %a) {
 
 ; Check the next value down, which must use AFI instead.
 define i32 @f8(i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: afi %r2, -32769
 ; CHECK: br %r14
   %add = add i32 %a, -32769
@@ -76,7 +76,7 @@ define i32 @f8(i32 %a) {
 
 ; Check the low end of the signed 32-bit range.
 define i32 @f9(i32 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: afi %r2, -2147483648
 ; CHECK: br %r14
   %add = add i32 %a, -2147483648
@@ -85,7 +85,7 @@ define i32 @f9(i32 %a) {
 
 ; Check the next value down, which is treated as a positive value.
 define i32 @f10(i32 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: afi %r2, 2147483647
 ; CHECK: br %r14
   %add = add i32 %a, -2147483649
diff --git a/test/CodeGen/SystemZ/int-add-07.ll b/test/CodeGen/SystemZ/int-add-07.ll
index a065bb2..e9e0212 100644
--- a/test/CodeGen/SystemZ/int-add-07.ll
+++ b/test/CodeGen/SystemZ/int-add-07.ll
@@ -4,7 +4,7 @@
 
 ; Check additions of 1.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: {{aghi %r2, 1|la %r[0-5], 1\(%r2\)}}
 ; CHECK: br %r14
   %add = add i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the AGHI range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r2, 32767
 ; CHECK: br %r14
   %add = add i64 %a, 32767
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; Check the next value up, which must use AGFI instead.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: {{agfi %r2, 32768|lay %r[0-5], 32768\(%r2\)}}
 ; CHECK: br %r14
   %add = add i64 %a, 32768
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check the high end of the AGFI range.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r2, 2147483647
 ; CHECK: br %r14
   %add = add i64 %a, 2147483647
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a) {
 
 ; Check the next value up, which must use ALGFI instead.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: algfi %r2, 2147483648
 ; CHECK: br %r14
   %add = add i64 %a, 2147483648
@@ -49,7 +49,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the high end of the ALGFI range.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: algfi %r2, 4294967295
 ; CHECK: br %r14
   %add = add i64 %a, 4294967295
@@ -58,7 +58,7 @@ define i64 @f6(i64 %a) {
 
 ; Check the next value up, which must be loaded into a register first.
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llihl %r0, 1
 ; CHECK: agr
 ; CHECK: br %r14
@@ -68,7 +68,7 @@ define i64 @f7(i64 %a) {
 
 ; Check the high end of the negative AGHI range.
 define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, -1
 ; CHECK: br %r14
   %add = add i64 %a, -1
@@ -77,7 +77,7 @@ define i64 @f8(i64 %a) {
 
 ; Check the low end of the AGHI range.
 define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -32768
 ; CHECK: br %r14
   %add = add i64 %a, -32768
@@ -86,7 +86,7 @@ define i64 @f9(i64 %a) {
 
 ; Check the next value down, which must use AGFI instead.
 define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: {{agfi %r2, -32769|lay %r[0-5]+, -32769\(%r2\)}}
 ; CHECK: br %r14
   %add = add i64 %a, -32769
@@ -95,7 +95,7 @@ define i64 @f10(i64 %a) {
 
 ; Check the low end of the AGFI range.
 define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, -2147483648
 ; CHECK: br %r14
   %add = add i64 %a, -2147483648
@@ -104,7 +104,7 @@ define i64 @f11(i64 %a) {
 
 ; Check the next value down, which must use SLGFI instead.
 define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: slgfi %r2, 2147483649
 ; CHECK: br %r14
   %add = add i64 %a, -2147483649
@@ -113,7 +113,7 @@ define i64 @f12(i64 %a) {
 
 ; Check the low end of the SLGFI range.
 define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: slgfi %r2, 4294967295
 ; CHECK: br %r14
   %add = add i64 %a, -4294967295
@@ -122,7 +122,7 @@ define i64 @f13(i64 %a) {
 
 ; Check the next value down, which must use register addition instead.
 define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: llihf %r0, 4294967295
 ; CHECK: agr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-08.ll b/test/CodeGen/SystemZ/int-add-08.ll
index 0b8c01e..d645137 100644
--- a/test/CodeGen/SystemZ/int-add-08.ll
+++ b/test/CodeGen/SystemZ/int-add-08.ll
@@ -6,7 +6,7 @@ declare i128 *@foo()
 
 ; Test register addition.
 define void @f1(i128 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: algr
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -19,7 +19,7 @@ define void @f1(i128 *%ptr) {
 ; Test memory addition with no offset.  Making the load of %a volatile
 ; should force the memory operand to be %b.
 define void @f2(i128 *%aptr, i64 %addr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: alg {{%r[0-5]}}, 8(%r3)
 ; CHECK: alcg {{%r[0-5]}}, 0(%r3)
 ; CHECK: br %r14
@@ -33,7 +33,7 @@ define void @f2(i128 *%aptr, i64 %addr) {
 
 ; Test the highest aligned offset that is in range of both ALG and ALCG.
 define void @f3(i128 *%aptr, i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: alg {{%r[0-5]}}, 524280(%r3)
 ; CHECK: alcg {{%r[0-5]}}, 524272(%r3)
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define void @f3(i128 *%aptr, i64 %base) {
 
 ; Test the next doubleword up, which requires separate address logic for ALG.
 define void @f4(i128 *%aptr, i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgr [[BASE:%r[1-5]]], %r3
 ; CHECK: agfi [[BASE]], 524288
 ; CHECK: alg {{%r[0-5]}}, 0([[BASE]])
@@ -67,7 +67,7 @@ define void @f4(i128 *%aptr, i64 %base) {
 ; both instructions.  It would be better to create an anchor at 524288
 ; that both instructions can use, but that isn't implemented yet.
 define void @f5(i128 *%aptr, i64 %base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: alg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: br %r14
@@ -82,7 +82,7 @@ define void @f5(i128 *%aptr, i64 %base) {
 
 ; Test the lowest displacement that is in range of both ALG and ALCG.
 define void @f6(i128 *%aptr, i64 %base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: alg {{%r[0-5]}}, -524280(%r3)
 ; CHECK: alcg {{%r[0-5]}}, -524288(%r3)
 ; CHECK: br %r14
@@ -97,7 +97,7 @@ define void @f6(i128 *%aptr, i64 %base) {
 
 ; Test the next doubleword down, which is out of range of the ALCG.
 define void @f7(i128 *%aptr, i64 %base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: alg {{%r[0-5]}}, -524288(%r3)
 ; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: br %r14
@@ -113,7 +113,7 @@ define void @f7(i128 *%aptr, i64 %base) {
 ; Check that additions of spilled values can use ALG and ALCG rather than
 ; ALGR and ALCGR.
 define void @f8(i128 *%ptr0) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: alg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
 ; CHECK: alcg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
diff --git a/test/CodeGen/SystemZ/int-add-09.ll b/test/CodeGen/SystemZ/int-add-09.ll
index bfe6338..43136bd 100644
--- a/test/CodeGen/SystemZ/int-add-09.ll
+++ b/test/CodeGen/SystemZ/int-add-09.ll
@@ -5,7 +5,7 @@
 ; Check additions of 1.  The XOR ensures that we don't instead load the
 ; constant into a register and use memory addition.
 define void @f1(i128 *%aptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: algfi {{%r[0-5]}}, 1
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define void @f1(i128 *%aptr) {
 
 ; Check the high end of the ALGFI range.
 define void @f2(i128 *%aptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: algfi {{%r[0-5]}}, 4294967295
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define void @f2(i128 *%aptr) {
 
 ; Check the next value up, which must use register addition.
 define void @f3(i128 *%aptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: algr
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ define void @f3(i128 *%aptr) {
 
 ; Check addition of -1, which must also use register addition.
 define void @f4(i128 *%aptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: algr
 ; CHECK: alcgr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-10.ll b/test/CodeGen/SystemZ/int-add-10.ll
index 17cfdbe..66a275b 100644
--- a/test/CodeGen/SystemZ/int-add-10.ll
+++ b/test/CodeGen/SystemZ/int-add-10.ll
@@ -5,7 +5,7 @@
 ; Check register additions.  The XOR ensures that we don't instead zero-extend
 ; %b into a register and use memory addition.
 define void @f1(i128 *%aptr, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: algfr {{%r[0-5]}}, %r3
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -19,7 +19,7 @@ define void @f1(i128 *%aptr, i32 %b) {
 
 ; Like f1, but using an "in-register" extension.
 define void @f2(i128 *%aptr, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: algfr {{%r[0-5]}}, %r3
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define void @f2(i128 *%aptr, i64 %b) {
 ; Test register addition in cases where the second operand is zero extended
 ; from i64 rather than i32, but is later masked to i32 range.
 define void @f3(i128 *%aptr, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: algfr {{%r[0-5]}}, %r3
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define void @f3(i128 *%aptr, i64 %b) {
 
 ; Test ALGF with no offset.
 define void @f4(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: algf {{%r[0-5]}}, 0(%r3)
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define void @f4(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the high end of the ALGF range.
 define void @f5(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: algf {{%r[0-5]}}, 524284(%r3)
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -82,7 +82,7 @@ define void @f5(i128 *%aptr, i32 *%bsrc) {
 ; Check the next word up, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: algf {{%r[0-5]}}, 0(%r3)
 ; CHECK: alcgr
@@ -99,7 +99,7 @@ define void @f6(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the high end of the negative aligned ALGF range.
 define void @f7(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: algf {{%r[0-5]}}, -4(%r3)
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -115,7 +115,7 @@ define void @f7(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the low end of the ALGF range.
 define void @f8(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: algf {{%r[0-5]}}, -524288(%r3)
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define void @f8(i128 *%aptr, i32 *%bsrc) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: algf {{%r[0-5]}}, 0(%r3)
 ; CHECK: alcgr
@@ -149,7 +149,7 @@ define void @f9(i128 *%aptr, i32 *%bsrc) {
 
 ; Check that ALGF allows an index.
 define void @f10(i128 *%aptr, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: algf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %a = load i128 *%aptr
diff --git a/test/CodeGen/SystemZ/int-add-11.ll b/test/CodeGen/SystemZ/int-add-11.ll
index 47a776e..6c617ba 100644
--- a/test/CodeGen/SystemZ/int-add-11.ll
+++ b/test/CodeGen/SystemZ/int-add-11.ll
@@ -4,7 +4,7 @@
 
 ; Check additions of 1.
 define void @f1(i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: asi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i32 *%ptr) {
 
 ; Check the high end of the constant range.
 define void @f2(i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: asi 0(%r2), 127
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -27,7 +27,7 @@ define void @f2(i32 *%ptr) {
 ; Check the next constant up, which must use an addition and a store.
 ; Both L/AHI and LHI/A would be OK.
 define void @f3(i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: asi
 ; CHECK: st %r0, 0(%r2)
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define void @f3(i32 *%ptr) {
 
 ; Check the low end of the constant range.
 define void @f4(i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: asi 0(%r2), -128
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -50,7 +50,7 @@ define void @f4(i32 *%ptr) {
 
 ; Check the next value down, with the same comment as f3.
 define void @f5(i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: asi
 ; CHECK: st %r0, 0(%r2)
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define void @f5(i32 *%ptr) {
 
 ; Check the high end of the aligned ASI range.
 define void @f6(i32 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: asi 524284(%r2), 1
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%base, i64 131071
@@ -75,7 +75,7 @@ define void @f6(i32 *%base) {
 ; Check the next word up, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f7(i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: asi 0(%r2), 1
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define void @f7(i32 *%base) {
 
 ; Check the low end of the ASI range.
 define void @f8(i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: asi -524288(%r2), 1
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%base, i64 -131072
@@ -101,7 +101,7 @@ define void @f8(i32 *%base) {
 ; Check the next word down, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524292
 ; CHECK: asi 0(%r2), 1
 ; CHECK: br %r14
@@ -114,7 +114,7 @@ define void @f9(i32 *%base) {
 
 ; Check that ASI does not allow indices.
 define void @f10(i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r2, %r3
 ; CHECK: asi 4(%r2), 1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-12.ll b/test/CodeGen/SystemZ/int-add-12.ll
index ae1c1f7..ef4dc39 100644
--- a/test/CodeGen/SystemZ/int-add-12.ll
+++ b/test/CodeGen/SystemZ/int-add-12.ll
@@ -4,7 +4,7 @@
 
 ; Check additions of 1.
 define void @f1(i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: agsi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i64 *%ptr) {
 
 ; Check the high end of the constant range.
 define void @f2(i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: agsi 0(%r2), 127
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -27,7 +27,7 @@ define void @f2(i64 *%ptr) {
 ; Check the next constant up, which must use an addition and a store.
 ; Both LG/AGHI and LGHI/AG would be OK.
 define void @f3(i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: agsi
 ; CHECK: stg %r0, 0(%r2)
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define void @f3(i64 *%ptr) {
 
 ; Check the low end of the constant range.
 define void @f4(i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agsi 0(%r2), -128
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -50,7 +50,7 @@ define void @f4(i64 *%ptr) {
 
 ; Check the next value down, with the same comment as f3.
 define void @f5(i64 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: agsi
 ; CHECK: stg %r0, 0(%r2)
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define void @f5(i64 *%ptr) {
 
 ; Check the high end of the aligned AGSI range.
 define void @f6(i64 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agsi 524280(%r2), 1
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%base, i64 65535
@@ -75,7 +75,7 @@ define void @f6(i64 *%base) {
 ; Check the next doubleword up, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f7(i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: agsi 0(%r2), 1
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define void @f7(i64 *%base) {
 
 ; Check the low end of the AGSI range.
 define void @f8(i64 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agsi -524288(%r2), 1
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%base, i64 -65536
@@ -101,7 +101,7 @@ define void @f8(i64 *%base) {
 ; Check the next doubleword down, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i64 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524296
 ; CHECK: agsi 0(%r2), 1
 ; CHECK: br %r14
@@ -114,7 +114,7 @@ define void @f9(i64 *%base) {
 
 ; Check that AGSI does not allow indices.
 define void @f10(i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r2, %r3
 ; CHECK: agsi 8(%r2), 1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-01.ll b/test/CodeGen/SystemZ/int-cmp-01.ll
index aa432f0..dbfe0df 100644
--- a/test/CodeGen/SystemZ/int-cmp-01.ll
+++ b/test/CodeGen/SystemZ/int-cmp-01.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the CH range.
 define void @f1(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ch %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -18,7 +18,7 @@ define void @f1(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the high end of the aligned CH range.
 define void @f2(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ch %r2, 4094(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -32,7 +32,7 @@ define void @f2(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the next halfword up, which should use CHY instead of CH.
 define void @f3(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: chy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -46,7 +46,7 @@ define void @f3(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the high end of the aligned CHY range.
 define void @f4(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: chy %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -61,7 +61,7 @@ define void @f4(i32 %lhs, i16 *%src, i32 *%dst) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f5(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ch %r2, 0(%r3)
 ; CHECK: br %r14
@@ -76,7 +76,7 @@ define void @f5(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the high end of the negative aligned CHY range.
 define void @f6(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: chy %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -90,7 +90,7 @@ define void @f6(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the low end of the CHY range.
 define void @f7(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: chy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -105,7 +105,7 @@ define void @f7(i32 %lhs, i16 *%src, i32 *%dst) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524290
 ; CHECK: ch %r2, 0(%r3)
 ; CHECK: br %r14
@@ -120,7 +120,7 @@ define void @f8(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check that CH allows an index.
 define void @f9(i32 %lhs, i64 %base, i64 %index, i32 *%dst) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ch %r2, 4094({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
@@ -136,7 +136,7 @@ define void @f9(i32 %lhs, i64 %base, i64 %index, i32 *%dst) {
 
 ; Check that CHY allows an index.
 define void @f10(i32 %lhs, i64 %base, i64 %index, i32 *%dst) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: chy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
diff --git a/test/CodeGen/SystemZ/int-cmp-02.ll b/test/CodeGen/SystemZ/int-cmp-02.ll
index b98661e..455350b 100644
--- a/test/CodeGen/SystemZ/int-cmp-02.ll
+++ b/test/CodeGen/SystemZ/int-cmp-02.ll
@@ -4,7 +4,7 @@
 
 ; Check register comparison.
 define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: crjl %r2, %r3
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
 
 ; Check the low end of the C range.
 define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: c %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -28,7 +28,7 @@ define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
 
 ; Check the high end of the aligned C range.
 define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: c %r2, 4092(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -42,7 +42,7 @@ define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the next word up, which should use CY instead of C.
 define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cy %r2, 4096(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the high end of the aligned CY range.
 define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cy %r2, 524284(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -71,7 +71,7 @@ define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: c %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -86,7 +86,7 @@ define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the high end of the negative aligned CY range.
 define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cy %r2, -4(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -100,7 +100,7 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the low end of the CY range.
 define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cy %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -115,7 +115,7 @@ define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: c %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -130,7 +130,7 @@ define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check that C allows an index.
 define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: c %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -146,7 +146,7 @@ define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
 
 ; Check that CY allows an index.
 define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-03.ll b/test/CodeGen/SystemZ/int-cmp-03.ll
index bd802bc..2d679cf 100644
--- a/test/CodeGen/SystemZ/int-cmp-03.ll
+++ b/test/CodeGen/SystemZ/int-cmp-03.ll
@@ -4,7 +4,7 @@
 
 ; Check register comparison.
 define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -16,7 +16,7 @@ define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
 
 ; Check the low end of the CL range.
 define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cl %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -29,7 +29,7 @@ define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
 
 ; Check the high end of the aligned CL range.
 define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cl %r2, 4092(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the next word up, which should use CLY instead of CL.
 define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cly %r2, 4096(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -57,7 +57,7 @@ define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the high end of the aligned CLY range.
 define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cly %r2, 524284(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -72,7 +72,7 @@ define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cl %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -87,7 +87,7 @@ define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the high end of the negative aligned CLY range.
 define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cly %r2, -4(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -101,7 +101,7 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the low end of the CLY range.
 define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cly %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -116,7 +116,7 @@ define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: cl %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -131,7 +131,7 @@ define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check that CL allows an index.
 define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cl %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -147,7 +147,7 @@ define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
 
 ; Check that CLY allows an index.
 define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cly %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-04.ll b/test/CodeGen/SystemZ/int-cmp-04.ll
index d0625fb..54c4b5b 100644
--- a/test/CodeGen/SystemZ/int-cmp-04.ll
+++ b/test/CodeGen/SystemZ/int-cmp-04.ll
@@ -5,7 +5,7 @@
 
 ; Check CGH with no displacement.
 define void @f1(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -18,7 +18,7 @@ define void @f1(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check the high end of the aligned CGH range.
 define void @f2(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgh %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -33,7 +33,7 @@ define void @f2(i64 %lhs, i16 *%src, i64 *%dst) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f3(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define void @f3(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check the high end of the negative aligned CGH range.
 define void @f4(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cgh %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -62,7 +62,7 @@ define void @f4(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check the low end of the CGH range.
 define void @f5(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cgh %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -77,7 +77,7 @@ define void @f5(i64 %lhs, i16 *%src, i64 *%dst) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, -524290
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -92,7 +92,7 @@ define void @f6(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check that CGH allows an index.
 define void @f7(i64 %lhs, i64 %base, i64 %index, i64 *%dst) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cgh %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
diff --git a/test/CodeGen/SystemZ/int-cmp-05.ll b/test/CodeGen/SystemZ/int-cmp-05.ll
index d953ebf..36d12a5 100644
--- a/test/CodeGen/SystemZ/int-cmp-05.ll
+++ b/test/CodeGen/SystemZ/int-cmp-05.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check signed register comparison.
 define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgfr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -19,7 +19,7 @@ define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; Check unsigned register comparison, which can't use CGFR.
 define double @f2(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: cgfr
 ; CHECK: br %r14
   %i2 = sext i32 %unext to i64
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; Check register equality.
 define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cgfr %r2, %r3
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; Check register inequality.
 define double @f4(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cgfr %r2, %r3
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; Check signed comparisonn with memory.
 define double @f5(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -70,7 +70,7 @@ define double @f5(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check unsigned comparison with memory.
 define double @f6(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: cgf
 ; CHECK: br %r14
   %unext = load i32 *%ptr
@@ -82,7 +82,7 @@ define double @f6(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check memory equality.
 define double @f7(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -96,7 +96,7 @@ define double @f7(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check memory inequality.
 define double @f8(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -110,7 +110,7 @@ define double @f8(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check the high end of the aligned CGF range.
 define double @f9(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cgf %r2, 524284(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -126,7 +126,7 @@ define double @f9(double %a, double %b, i64 %i1, i32 *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f10(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -142,7 +142,7 @@ define double @f10(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check the high end of the negative aligned CGF range.
 define double @f11(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cgf %r2, -4(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -157,7 +157,7 @@ define double @f11(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check the low end of the CGF range.
 define double @f12(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cgf %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -173,7 +173,7 @@ define double @f12(double %a, double %b, i64 %i1, i32 *%base) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agfi %r3, -524292
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -189,7 +189,7 @@ define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check that CGF allows an index.
 define double @f14(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -206,7 +206,7 @@ define double @f14(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
 
 ; Check that comparisons of spilled values can use CGF rather than CGFR.
 define i64 @f15(i32 *%ptr0) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: cgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-06.ll b/test/CodeGen/SystemZ/int-cmp-06.ll
index f866631..cdd6114 100644
--- a/test/CodeGen/SystemZ/int-cmp-06.ll
+++ b/test/CodeGen/SystemZ/int-cmp-06.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check unsigned register comparison.
 define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -19,7 +19,7 @@ define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; ...and again with a different representation.
 define double @f2(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -32,7 +32,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 %unext) {
 
 ; Check signed register comparison, which can't use CLGFR.
 define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clgfr
 ; CHECK: br %r14
   %i2 = zext i32 %unext to i64
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; ...and again with a different representation
 define double @f4(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clgfr
 ; CHECK: br %r14
   %i2 = and i64 %unext, 4294967295
@@ -54,7 +54,7 @@ define double @f4(double %a, double %b, i64 %i1, i64 %unext) {
 
 ; Check register equality.
 define double @f5(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -67,7 +67,7 @@ define double @f5(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; ...and again with a different representation
 define double @f6(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -80,7 +80,7 @@ define double @f6(double %a, double %b, i64 %i1, i64 %unext) {
 
 ; Check register inequality.
 define double @f7(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -93,7 +93,7 @@ define double @f7(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; ...and again with a different representation
 define double @f8(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -106,7 +106,7 @@ define double @f8(double %a, double %b, i64 %i1, i64 %unext) {
 
 ; Check unsigned comparisonn with memory.
 define double @f9(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -120,7 +120,7 @@ define double @f9(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check signed comparison with memory.
 define double @f10(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clgf
 ; CHECK: br %r14
   %unext = load i32 *%ptr
@@ -132,7 +132,7 @@ define double @f10(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check memory equality.
 define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -146,7 +146,7 @@ define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check memory inequality.
 define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -160,7 +160,7 @@ define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check the high end of the aligned CLGF range.
 define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: clgf %r2, 524284(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -176,7 +176,7 @@ define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f14(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: agfi %r3, 524288
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -192,7 +192,7 @@ define double @f14(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check the high end of the negative aligned CLGF range.
 define double @f15(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: clgf %r2, -4(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -207,7 +207,7 @@ define double @f15(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check the low end of the CLGF range.
 define double @f16(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: clgf %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -223,7 +223,7 @@ define double @f16(double %a, double %b, i64 %i1, i32 *%base) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f17(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: agfi %r3, -524292
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -239,7 +239,7 @@ define double @f17(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check that CLGF allows an index.
 define double @f18(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: clgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -256,7 +256,7 @@ define double @f18(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
 
 ; Check that comparisons of spilled values can use CLGF rather than CLGFR.
 define i64 @f19(i32 *%ptr0) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: clgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-07.ll b/test/CodeGen/SystemZ/int-cmp-07.ll
index 48ccf5c..3308cb0 100644
--- a/test/CodeGen/SystemZ/int-cmp-07.ll
+++ b/test/CodeGen/SystemZ/int-cmp-07.ll
@@ -4,7 +4,7 @@
 
 ; Check CGR.
 define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgrjl %r2, %r3
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
 
 ; Check CG with no displacement.
 define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cg %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -28,7 +28,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
 
 ; Check the high end of the aligned CG range.
 define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cg %r2, 524280(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cg %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the high end of the negative aligned CG range.
 define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cg %r2, -8(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -72,7 +72,7 @@ define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the low end of the CG range.
 define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cg %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -87,7 +87,7 @@ define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: cg %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -102,7 +102,7 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check that CG allows an index.
 define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-08.ll b/test/CodeGen/SystemZ/int-cmp-08.ll
index b091ba6..e68a0fe 100644
--- a/test/CodeGen/SystemZ/int-cmp-08.ll
+++ b/test/CodeGen/SystemZ/int-cmp-08.ll
@@ -4,7 +4,7 @@
 
 ; Check CLGR.
 define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clgr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -16,7 +16,7 @@ define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
 
 ; Check CLG with no displacement.
 define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clg %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -29,7 +29,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
 
 ; Check the high end of the aligned CLG range.
 define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clg %r2, 524280(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: clg %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -59,7 +59,7 @@ define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the high end of the negative aligned CLG range.
 define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clg %r2, -8(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -73,7 +73,7 @@ define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the low end of the CLG range.
 define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clg %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -88,7 +88,7 @@ define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: clg %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -103,7 +103,7 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check that CLG allows an index.
 define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-09.ll b/test/CodeGen/SystemZ/int-cmp-09.ll
index 8fb0e7c..66c9d8d 100644
--- a/test/CodeGen/SystemZ/int-cmp-09.ll
+++ b/test/CodeGen/SystemZ/int-cmp-09.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i32 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cijl %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i32 %i1) {
 
 ; Check comparisons with 1.
 define double @f2(double %a, double %b, i32 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cijl %r2, 1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define double @f2(double %a, double %b, i32 %i1) {
 
 ; Check the high end of the CIJ range.
 define double @f3(double %a, double %b, i32 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cijl %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -37,7 +37,7 @@ define double @f3(double %a, double %b, i32 %i1) {
 
 ; Check the next value up, which must use CHI instead.
 define double @f4(double %a, double %b, i32 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: chi %r2, 128
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -49,7 +49,7 @@ define double @f4(double %a, double %b, i32 %i1) {
 
 ; Check the high end of the CHI range.
 define double @f5(double %a, double %b, i32 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: chi %r2, 32767
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -61,7 +61,7 @@ define double @f5(double %a, double %b, i32 %i1) {
 
 ; Check the next value up, which must use CFI.
 define double @f6(double %a, double %b, i32 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cfi %r2, 32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i32 %i1) {
 
 ; Check the high end of the signed 32-bit range.
 define double @f7(double %a, double %b, i32 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cfi %r2, 2147483647
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -85,7 +85,7 @@ define double @f7(double %a, double %b, i32 %i1) {
 
 ; Check the next value up, which should be treated as a negative value.
 define double @f8(double %a, double %b, i32 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cfi %r2, -2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -97,7 +97,7 @@ define double @f8(double %a, double %b, i32 %i1) {
 
 ; Check the high end of the negative CIJ range.
 define double @f9(double %a, double %b, i32 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cijl %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f9(double %a, double %b, i32 %i1) {
 
 ; Check the low end of the CIJ range.
 define double @f10(double %a, double %b, i32 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cijl %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -119,7 +119,7 @@ define double @f10(double %a, double %b, i32 %i1) {
 
 ; Check the next value down, which must use CHI instead.
 define double @f11(double %a, double %b, i32 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: chi %r2, -129
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -131,7 +131,7 @@ define double @f11(double %a, double %b, i32 %i1) {
 
 ; Check the low end of the CHI range.
 define double @f12(double %a, double %b, i32 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: chi %r2, -32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -143,7 +143,7 @@ define double @f12(double %a, double %b, i32 %i1) {
 
 ; Check the next value down, which must use CFI instead.
 define double @f13(double %a, double %b, i32 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cfi %r2, -32769
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -155,7 +155,7 @@ define double @f13(double %a, double %b, i32 %i1) {
 
 ; Check the low end of the signed 32-bit range.
 define double @f14(double %a, double %b, i32 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cfi %r2, -2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f14(double %a, double %b, i32 %i1) {
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f15(double %a, double %b, i32 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cfi %r2, 2147483647
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-10.ll b/test/CodeGen/SystemZ/int-cmp-10.ll
index 937b1bc..e30e014 100644
--- a/test/CodeGen/SystemZ/int-cmp-10.ll
+++ b/test/CodeGen/SystemZ/int-cmp-10.ll
@@ -5,7 +5,7 @@
 ; Check a value near the low end of the range.  We use CFI for comparisons
 ; with zero, or things that are equivalent to them.
 define double @f1(double %a, double %b, i32 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clfi %r2, 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i32 %i1) {
 
 ; Check a value near the high end of the range.
 define double @f2(double %a, double %b, i32 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clfi %r2, 4294967280
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-11.ll b/test/CodeGen/SystemZ/int-cmp-11.ll
index a0f598e..8dd2ebc 100644
--- a/test/CodeGen/SystemZ/int-cmp-11.ll
+++ b/test/CodeGen/SystemZ/int-cmp-11.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgijl %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i64 %i1) {
 
 ; Check comparisons with 1.
 define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgijl %r2, 1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define double @f2(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGIJ range.
 define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cgijl %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -37,7 +37,7 @@ define double @f3(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGHI instead.
 define double @f4(double %a, double %b, i64 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cghi %r2, 128
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -49,7 +49,7 @@ define double @f4(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGHI range.
 define double @f5(double %a, double %b, i64 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cghi %r2, 32767
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -61,7 +61,7 @@ define double @f5(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGFI.
 define double @f6(double %a, double %b, i64 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cgfi %r2, 32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGFI range.
 define double @f7(double %a, double %b, i64 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cgfi %r2, 2147483647
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -85,7 +85,7 @@ define double @f7(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use register comparison.
 define double @f8(double %a, double %b, i64 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cgrjl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -96,7 +96,7 @@ define double @f8(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the negative CGIJ range.
 define double @f9(double %a, double %b, i64 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cgijl %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define double @f9(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGIJ range.
 define double @f10(double %a, double %b, i64 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cgijl %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -118,7 +118,7 @@ define double @f10(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGHI instead.
 define double @f11(double %a, double %b, i64 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cghi %r2, -129
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -130,7 +130,7 @@ define double @f11(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGHI range.
 define double @f12(double %a, double %b, i64 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cghi %r2, -32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -142,7 +142,7 @@ define double @f12(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGFI instead.
 define double @f13(double %a, double %b, i64 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cgfi %r2, -32769
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -154,7 +154,7 @@ define double @f13(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGFI range.
 define double @f14(double %a, double %b, i64 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cgfi %r2, -2147483648
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -166,7 +166,7 @@ define double @f14(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use register comparison.
 define double @f15(double %a, double %b, i64 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cgrjl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-12.ll b/test/CodeGen/SystemZ/int-cmp-12.ll
index 74d16cc..f57f6ec 100644
--- a/test/CodeGen/SystemZ/int-cmp-12.ll
+++ b/test/CodeGen/SystemZ/int-cmp-12.ll
@@ -5,7 +5,7 @@
 ; Check a value near the low end of the range.  We use CGFI for comparisons
 ; with zero, or things that are equivalent to them.
 define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clgfi %r2, 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CLGFI range.
 define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clgfi %r2, 4294967295
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -29,7 +29,7 @@ define double @f2(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use a register comparison.
 define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clgr %r2,
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-13.ll b/test/CodeGen/SystemZ/int-cmp-13.ll
index 19bceec..53af0c8 100644
--- a/test/CodeGen/SystemZ/int-cmp-13.ll
+++ b/test/CodeGen/SystemZ/int-cmp-13.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgije %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGIJ range.
 define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgije %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define double @f2(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGHI instead.
 define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cghi %r2, 128
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -38,7 +38,7 @@ define double @f3(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGHI range.
 define double @f4(double %a, double %b, i64 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cghi %r2, 32767
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -50,7 +50,7 @@ define double @f4(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGFI.
 define double @f5(double %a, double %b, i64 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cgfi %r2, 32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -62,7 +62,7 @@ define double @f5(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGFI range.
 define double @f6(double %a, double %b, i64 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cgfi %r2, 2147483647
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -74,7 +74,7 @@ define double @f6(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which should use CLGFI instead.
 define double @f7(double %a, double %b, i64 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clgfi %r2, 2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CLGFI range.
 define double @f8(double %a, double %b, i64 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clgfi %r2, 4294967295
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -98,7 +98,7 @@ define double @f8(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use a register comparison.
 define double @f9(double %a, double %b, i64 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cgrje %r2,
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define double @f9(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the negative CGIJ range.
 define double @f10(double %a, double %b, i64 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cgije %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -120,7 +120,7 @@ define double @f10(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGIJ range.
 define double @f11(double %a, double %b, i64 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cgije %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -131,7 +131,7 @@ define double @f11(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGHI instead.
 define double @f12(double %a, double %b, i64 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cghi %r2, -129
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -143,7 +143,7 @@ define double @f12(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGHI range.
 define double @f13(double %a, double %b, i64 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cghi %r2, -32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -155,7 +155,7 @@ define double @f13(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGFI instead.
 define double @f14(double %a, double %b, i64 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cgfi %r2, -32769
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f14(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGFI range.
 define double @f15(double %a, double %b, i64 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cgfi %r2, -2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -179,7 +179,7 @@ define double @f15(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use register comparison.
 define double @f16(double %a, double %b, i64 %i1) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cgrje
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-14.ll b/test/CodeGen/SystemZ/int-cmp-14.ll
index 11b56ad..4dbd0ec 100644
--- a/test/CodeGen/SystemZ/int-cmp-14.ll
+++ b/test/CodeGen/SystemZ/int-cmp-14.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgijlh %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGIJ range.
 define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgijlh %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define double @f2(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGHI instead.
 define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cghi %r2, 128
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -38,7 +38,7 @@ define double @f3(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGHI range.
 define double @f4(double %a, double %b, i64 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cghi %r2, 32767
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -50,7 +50,7 @@ define double @f4(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGFI.
 define double @f5(double %a, double %b, i64 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cgfi %r2, 32768
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -62,7 +62,7 @@ define double @f5(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGFI range.
 define double @f6(double %a, double %b, i64 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cgfi %r2, 2147483647
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -74,7 +74,7 @@ define double @f6(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which should use CLGFI instead.
 define double @f7(double %a, double %b, i64 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clgfi %r2, 2147483648
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CLGFI range.
 define double @f8(double %a, double %b, i64 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clgfi %r2, 4294967295
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -98,7 +98,7 @@ define double @f8(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use a register comparison.
 define double @f9(double %a, double %b, i64 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cgrjlh %r2,
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define double @f9(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the negative CGIJ range.
 define double @f10(double %a, double %b, i64 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cgijlh %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -120,7 +120,7 @@ define double @f10(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGIJ range.
 define double @f11(double %a, double %b, i64 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cgijlh %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -131,7 +131,7 @@ define double @f11(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGHI instead.
 define double @f12(double %a, double %b, i64 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cghi %r2, -129
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -143,7 +143,7 @@ define double @f12(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGHI range.
 define double @f13(double %a, double %b, i64 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cghi %r2, -32768
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -155,7 +155,7 @@ define double @f13(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGFI instead.
 define double @f14(double %a, double %b, i64 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cgfi %r2, -32769
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f14(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGFI range.
 define double @f15(double %a, double %b, i64 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cgfi %r2, -2147483648
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -179,7 +179,7 @@ define double @f15(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use register comparison.
 define double @f16(double %a, double %b, i64 %i1) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cgrjlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-15.ll b/test/CodeGen/SystemZ/int-cmp-15.ll
index 1868c57..48a068e 100644
--- a/test/CodeGen/SystemZ/int-cmp-15.ll
+++ b/test/CodeGen/SystemZ/int-cmp-15.ll
@@ -4,7 +4,7 @@
 
 ; Check ordered comparisons near the low end of the unsigned 8-bit range.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check ordered comparisons near the high end of the unsigned 8-bit range.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -28,7 +28,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for negative bytes.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 
 ; ...and an alternative form.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -52,7 +52,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for non-negative bytes.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; ...and an alternative form.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -76,7 +76,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 
 ; Check equality comparisons at the low end of the signed 8-bit range.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check equality comparisons at the low end of the unsigned 8-bit range.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -100,7 +100,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check equality comparisons at the high end of the signed 8-bit range.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 
 ; Check equality comparisons at the high end of the unsigned 8-bit range.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -124,7 +124,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the CLI range.
 define double @f11(double %a, double %b, i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cli 4095(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -136,7 +136,7 @@ define double @f11(double %a, double %b, i8 *%src) {
 
 ; Check the next byte up, which should use CLIY instead of CLI.
 define double @f12(double %a, double %b, i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cliy 4096(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -148,7 +148,7 @@ define double @f12(double %a, double %b, i8 *%src) {
 
 ; Check the high end of the CLIY range.
 define double @f13(double %a, double %b, i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cliy 524287(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -161,7 +161,7 @@ define double @f13(double %a, double %b, i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f14(double %a, double %b, i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: agfi %r2, 524288
 ; CHECK: cli 0(%r2), 127
 ; CHECK: br %r14
@@ -174,7 +174,7 @@ define double @f14(double %a, double %b, i8 *%src) {
 
 ; Check the high end of the negative CLIY range.
 define double @f15(double %a, double %b, i8 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cliy -1(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -186,7 +186,7 @@ define double @f15(double %a, double %b, i8 *%src) {
 
 ; Check the low end of the CLIY range.
 define double @f16(double %a, double %b, i8 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cliy -524288(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -199,7 +199,7 @@ define double @f16(double %a, double %b, i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f17(double %a, double %b, i8 *%src) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: agfi %r2, -524289
 ; CHECK: cli 0(%r2), 127
 ; CHECK: br %r14
@@ -212,7 +212,7 @@ define double @f17(double %a, double %b, i8 *%src) {
 
 ; Check that CLI does not allow an index
 define double @f18(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: agr %r2, %r3
 ; CHECK: cli 4095(%r2), 127
 ; CHECK: br %r14
@@ -227,7 +227,7 @@ define double @f18(double %a, double %b, i64 %base, i64 %index) {
 
 ; Check that CLIY does not allow an index
 define double @f19(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: agr %r2, %r3
 ; CHECK: cliy 4096(%r2), 127
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-16.ll b/test/CodeGen/SystemZ/int-cmp-16.ll
index a2c9e87..be206d9 100644
--- a/test/CodeGen/SystemZ/int-cmp-16.ll
+++ b/test/CodeGen/SystemZ/int-cmp-16.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-17.ll b/test/CodeGen/SystemZ/int-cmp-17.ll
index 83e4d2d..3df4ecc 100644
--- a/test/CodeGen/SystemZ/int-cmp-17.ll
+++ b/test/CodeGen/SystemZ/int-cmp-17.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-18.ll b/test/CodeGen/SystemZ/int-cmp-18.ll
index 99cf68a..d03d6ac 100644
--- a/test/CodeGen/SystemZ/int-cmp-18.ll
+++ b/test/CodeGen/SystemZ/int-cmp-18.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-19.ll b/test/CodeGen/SystemZ/int-cmp-19.ll
index 4f84687..b5f0856 100644
--- a/test/CodeGen/SystemZ/int-cmp-19.ll
+++ b/test/CodeGen/SystemZ/int-cmp-19.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-20.ll b/test/CodeGen/SystemZ/int-cmp-20.ll
index eb21bd1..7ecde77 100644
--- a/test/CodeGen/SystemZ/int-cmp-20.ll
+++ b/test/CodeGen/SystemZ/int-cmp-20.ll
@@ -6,7 +6,7 @@
 ; Check unsigned comparison near the low end of the CLI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the low end of the CLI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -34,7 +34,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the high end of the CLI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the high end of the CLI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison above the high end of the CLI range, using zero
 ; extension.  The condition is always true.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -78,7 +78,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 ; unlikely to occur in practice, we don't bother optimizing the second case,
 ; and simply ignore CLI for this range.  First check the low end of the range.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -90,7 +90,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 
 ; ...and then the high end.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -103,7 +103,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the low end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -117,7 +117,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the low end of the CLI range, using sign
 ; extension.  This cannot use CLI.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -130,7 +130,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the high end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -144,7 +144,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the high end of the CLI range, using sign
 ; extension.  This cannot use CLI.
 define double @f11(double %a, double %b, i8 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -157,7 +157,7 @@ define double @f11(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison above the high end of the CLI range, using zero
 ; extension.  The condition is always true.
 define double @f12(double %a, double %b, i8 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -169,7 +169,7 @@ define double @f12(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for nonnegative values.
 define double @f13(double %a, double %b, i8 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -182,7 +182,7 @@ define double @f13(double %a, double %b, i8 *%ptr) {
 
 ; ...and another form
 define double @f14(double %a, double %b, i8 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -195,7 +195,7 @@ define double @f14(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for negative values.
 define double @f15(double %a, double %b, i8 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -208,7 +208,7 @@ define double @f15(double %a, double %b, i8 *%ptr) {
 
 ; ...and another form
 define double @f16(double %a, double %b, i8 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-21.ll b/test/CodeGen/SystemZ/int-cmp-21.ll
index 9f81ad8..ca9225d 100644
--- a/test/CodeGen/SystemZ/int-cmp-21.ll
+++ b/test/CodeGen/SystemZ/int-cmp-21.ll
@@ -6,7 +6,7 @@
 ; Check unsigned comparison near the low end of the CLI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the low end of the CLI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -34,7 +34,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the high end of the CLI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the high end of the CLI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison above the high end of the CLI range, using zero
 ; extension.  The condition is always true.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -78,7 +78,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 ; unlikely to occur in practice, we don't bother optimizing the second case,
 ; and simply ignore CLI for this range.  First check the low end of the range.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -90,7 +90,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 
 ; ...and then the high end.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -103,7 +103,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the low end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -117,7 +117,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the low end of the CLI range, using sign
 ; extension.  This cannot use CLI.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -130,7 +130,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the high end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -144,7 +144,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the high end of the CLI range, using sign
 ; extension.  This cannot use CLI.
 define double @f11(double %a, double %b, i8 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -157,7 +157,7 @@ define double @f11(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison above the high end of the CLI range, using zero
 ; extension.  The condition is always true.
 define double @f12(double %a, double %b, i8 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -169,7 +169,7 @@ define double @f12(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for nonnegative values.
 define double @f13(double %a, double %b, i8 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -182,7 +182,7 @@ define double @f13(double %a, double %b, i8 *%ptr) {
 
 ; ...and another form
 define double @f14(double %a, double %b, i8 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -195,7 +195,7 @@ define double @f14(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for negative values.
 define double @f15(double %a, double %b, i8 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -208,7 +208,7 @@ define double @f15(double %a, double %b, i8 *%ptr) {
 
 ; ...and another form
 define double @f16(double %a, double %b, i8 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-22.ll b/test/CodeGen/SystemZ/int-cmp-22.ll
index 7cecacb..ea16604 100644
--- a/test/CodeGen/SystemZ/int-cmp-22.ll
+++ b/test/CodeGen/SystemZ/int-cmp-22.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: chhsi 0(%r2), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 1.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: chhsi 0(%r2), 1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check a value near the high end of the signed 16-bit range.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: chhsi 0(%r2), 32766
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: chhsi 0(%r2), -1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check a value near the low end of the 16-bit signed range.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: chhsi 0(%r2), -32766
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the CHHSI range.
 define double @f6(double %a, double %b, i16 %i1, i16 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: chhsi 4094(%r3), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 %i1, i16 *%base) {
 
 ; Check the next halfword up, which needs separate address logic,
 define double @f7(double %a, double %b, i16 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: aghi %r2, 4096
 ; CHECK: chhsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -98,7 +98,7 @@ define double @f7(double %a, double %b, i16 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f8(double %a, double %b, i16 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, -2
 ; CHECK: chhsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -113,7 +113,7 @@ define double @f8(double %a, double %b, i16 *%base) {
 
 ; Check that CHHSI does not allow indices.
 define double @f9(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: chhsi 0({{%r[23]}}), 0
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-23.ll b/test/CodeGen/SystemZ/int-cmp-23.ll
index 2ca89c5..99fe74b 100644
--- a/test/CodeGen/SystemZ/int-cmp-23.ll
+++ b/test/CodeGen/SystemZ/int-cmp-23.ll
@@ -4,7 +4,7 @@
 
 ; Check a value near the low end of the unsigned 16-bit range.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check a value near the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the CLHHSI range.
 define double @f3(double %a, double %b, i16 %i1, i16 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 4094(%r3), 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 %i1, i16 *%base) {
 
 ; Check the next halfword up, which needs separate address logic,
 define double @f4(double %a, double %b, i16 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
@@ -59,7 +59,7 @@ define double @f4(double %a, double %b, i16 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f5(double %a, double %b, i16 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -2
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
@@ -74,7 +74,7 @@ define double @f5(double %a, double %b, i16 *%base) {
 
 ; Check that CLHHSI does not allow indices.
 define double @f6(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: clhhsi 0({{%r[23]}}), 1
 ; CHECK-NEXT: jh
diff --git a/test/CodeGen/SystemZ/int-cmp-24.ll b/test/CodeGen/SystemZ/int-cmp-24.ll
index 01cc7b3..1a8e587 100644
--- a/test/CodeGen/SystemZ/int-cmp-24.ll
+++ b/test/CodeGen/SystemZ/int-cmp-24.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the unsigned 16-bit range.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-25.ll b/test/CodeGen/SystemZ/int-cmp-25.ll
index 8ea8d6c..50803df 100644
--- a/test/CodeGen/SystemZ/int-cmp-25.ll
+++ b/test/CodeGen/SystemZ/int-cmp-25.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the unsigned 16-bit range.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-26.ll b/test/CodeGen/SystemZ/int-cmp-26.ll
index 9eb02f4..6077865 100644
--- a/test/CodeGen/SystemZ/int-cmp-26.ll
+++ b/test/CodeGen/SystemZ/int-cmp-26.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-27.ll b/test/CodeGen/SystemZ/int-cmp-27.ll
index 3a16e9e..3102f5c 100644
--- a/test/CodeGen/SystemZ/int-cmp-27.ll
+++ b/test/CodeGen/SystemZ/int-cmp-27.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-28.ll b/test/CodeGen/SystemZ/int-cmp-28.ll
index d40a95d..c3b9059 100644
--- a/test/CodeGen/SystemZ/int-cmp-28.ll
+++ b/test/CodeGen/SystemZ/int-cmp-28.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-29.ll b/test/CodeGen/SystemZ/int-cmp-29.ll
index 221bbcf..1b40d8c 100644
--- a/test/CodeGen/SystemZ/int-cmp-29.ll
+++ b/test/CodeGen/SystemZ/int-cmp-29.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-30.ll b/test/CodeGen/SystemZ/int-cmp-30.ll
index 507191b..6c9498c 100644
--- a/test/CodeGen/SystemZ/int-cmp-30.ll
+++ b/test/CodeGen/SystemZ/int-cmp-30.ll
@@ -6,7 +6,7 @@
 ; Check unsigned comparison near the low end of the CLHHSI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the low end of the CLHHSI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -34,7 +34,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the high end of the CLHHSI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the high end of the CLHHSI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison above the high end of the CLHHSI range, using zero
 ; extension.  The condition is always true.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -79,7 +79,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 ; and simply ignore CLHHSI for this range.  First check the low end of the
 ; range.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -91,7 +91,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 
 ; ...and then the high end.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -104,7 +104,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -118,7 +118,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: chhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -146,7 +146,7 @@ define double @f10(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f11(double %a, double %b, i16 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: chhsi 0(%r2), -2
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -160,7 +160,7 @@ define double @f11(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison above the high end of the CLHHSI range, using zero
 ; extension.  The condition is always true.
 define double @f12(double %a, double %b, i16 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -173,7 +173,7 @@ define double @f12(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CHHSI range, using sign
 ; extension.
 define double @f13(double %a, double %b, i16 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: chhsi 0(%r2), 32766
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -187,7 +187,7 @@ define double @f13(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison above the high end of the CHHSI range, using sign
 ; extension.  This condition is always true.
 define double @f14(double %a, double %b, i16 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -200,7 +200,7 @@ define double @f14(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CHHSI range, using sign
 ; extension.
 define double @f15(double %a, double %b, i16 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: chhsi 0(%r2), -32767
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -214,7 +214,7 @@ define double @f15(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison below the low end of the CHHSI range, using sign
 ; extension.  This condition is always true.
 define double @f16(double %a, double %b, i16 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-31.ll b/test/CodeGen/SystemZ/int-cmp-31.ll
index a70ce2b..21539f2 100644
--- a/test/CodeGen/SystemZ/int-cmp-31.ll
+++ b/test/CodeGen/SystemZ/int-cmp-31.ll
@@ -6,7 +6,7 @@
 ; Check unsigned comparison near the low end of the CLHHSI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the low end of the CLHHSI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -34,7 +34,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the high end of the CLHHSI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the high end of the CLHHSI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison above the high end of the CLHHSI range, using zero
 ; extension.  The condition is always true.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -79,7 +79,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 ; and simply ignore CLHHSI for this range.  First check the low end of the
 ; range.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -91,7 +91,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 
 ; ...and then the high end.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -104,7 +104,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -118,7 +118,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: chhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -146,7 +146,7 @@ define double @f10(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f11(double %a, double %b, i16 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: chhsi 0(%r2), -2
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -160,7 +160,7 @@ define double @f11(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison above the high end of the CLHHSI range, using zero
 ; extension.  The condition is always true.
 define double @f12(double %a, double %b, i16 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -173,7 +173,7 @@ define double @f12(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CHHSI range, using sign
 ; extension.
 define double @f13(double %a, double %b, i16 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: chhsi 0(%r2), 32766
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -187,7 +187,7 @@ define double @f13(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison above the high end of the CHHSI range, using sign
 ; extension.  This condition is always true.
 define double @f14(double %a, double %b, i16 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -200,7 +200,7 @@ define double @f14(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CHHSI range, using sign
 ; extension.
 define double @f15(double %a, double %b, i16 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: chhsi 0(%r2), -32767
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -214,7 +214,7 @@ define double @f15(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison below the low end of the CHHSI range, using sign
 ; extension.  This condition is always true.
 define double @f16(double %a, double %b, i16 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-32.ll b/test/CodeGen/SystemZ/int-cmp-32.ll
index f79182b..96398dd 100644
--- a/test/CodeGen/SystemZ/int-cmp-32.ll
+++ b/test/CodeGen/SystemZ/int-cmp-32.ll
@@ -4,7 +4,7 @@
 
 ; Check ordered comparisons with 0.
 define double @f1(double %a, double %b, i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: chsi 0(%r2), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with 1.
 define double @f2(double %a, double %b, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: chsi 0(%r2), 1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with the high end of the signed 16-bit range.
 define double @f3(double %a, double %b, i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: chsi 0(%r2), 32767
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value up, which can't use CHSI.
 define double @f4(double %a, double %b, i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -54,7 +54,7 @@ define double @f4(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with -1.
 define double @f5(double %a, double %b, i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: chsi 0(%r2), -1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -67,7 +67,7 @@ define double @f5(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with the low end of the 16-bit signed range.
 define double @f6(double %a, double %b, i32 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: chsi 0(%r2), -32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -80,7 +80,7 @@ define double @f6(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value down, which can't use CHSI.
 define double @f7(double %a, double %b, i32 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -91,7 +91,7 @@ define double @f7(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with 0.
 define double @f8(double %a, double %b, i32 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: chsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -104,7 +104,7 @@ define double @f8(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with 1.
 define double @f9(double %a, double %b, i32 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: chsi 0(%r2), 1
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -117,7 +117,7 @@ define double @f9(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with the high end of the signed 16-bit range.
 define double @f10(double %a, double %b, i32 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: chsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -130,7 +130,7 @@ define double @f10(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value up, which can't use CHSI.
 define double @f11(double %a, double %b, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -141,7 +141,7 @@ define double @f11(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with -1.
 define double @f12(double %a, double %b, i32 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: chsi 0(%r2), -1
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -154,7 +154,7 @@ define double @f12(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with the low end of the 16-bit signed range.
 define double @f13(double %a, double %b, i32 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: chsi 0(%r2), -32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f13(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f14(double %a, double %b, i32 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -178,7 +178,7 @@ define double @f14(double %a, double %b, i32 *%ptr) {
 
 ; Check the high end of the CHSI range.
 define double @f15(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: chsi 4092(%r3), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -192,7 +192,7 @@ define double @f15(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the next word up, which needs separate address logic,
 define double @f16(double %a, double %b, i32 *%base) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: aghi %r2, 4096
 ; CHECK: chsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -207,7 +207,7 @@ define double @f16(double %a, double %b, i32 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f17(double %a, double %b, i32 *%base) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: aghi %r2, -4
 ; CHECK: chsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -222,7 +222,7 @@ define double @f17(double %a, double %b, i32 *%base) {
 
 ; Check that CHSI does not allow indices.
 define double @f18(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: chsi 0({{%r[23]}}), 0
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-33.ll b/test/CodeGen/SystemZ/int-cmp-33.ll
index 2c1a26e..e5a653b 100644
--- a/test/CodeGen/SystemZ/int-cmp-33.ll
+++ b/test/CodeGen/SystemZ/int-cmp-33.ll
@@ -5,7 +5,7 @@
 ; Check ordered comparisons with a constant near the low end of the unsigned
 ; 16-bit range.
 define double @f1(double %a, double %b, i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clfhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clfhsi 0(%r2), 65535
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value up, which can't use CLFHSI.
 define double @f3(double %a, double %b, i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clfhsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i32 *%ptr) {
 ; Check equality comparisons with 32768, the lowest value for which
 ; we prefer CLFHSI to CHSI.
 define double @f4(double %a, double %b, i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clfhsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with the high end of the unsigned 16-bit range.
 define double @f5(double %a, double %b, i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clfhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value up, which can't use CLFHSI.
 define double @f6(double %a, double %b, i32 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: clfhsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -80,7 +80,7 @@ define double @f6(double %a, double %b, i32 *%ptr) {
 
 ; Check the high end of the CLFHSI range.
 define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clfhsi 4092(%r3), 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -94,7 +94,7 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the next word up, which needs separate address logic,
 define double @f8(double %a, double %b, i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, 4096
 ; CHECK: clfhsi 0(%r2), 1
 ; CHECK-NEXT: jh
@@ -109,7 +109,7 @@ define double @f8(double %a, double %b, i32 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f9(double %a, double %b, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -4
 ; CHECK: clfhsi 0(%r2), 1
 ; CHECK-NEXT: jh
@@ -124,7 +124,7 @@ define double @f9(double %a, double %b, i32 *%base) {
 
 ; Check that CLFHSI does not allow indices.
 define double @f10(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: clfhsi 0({{%r[23]}}), 1
 ; CHECK-NEXT: jh
diff --git a/test/CodeGen/SystemZ/int-cmp-34.ll b/test/CodeGen/SystemZ/int-cmp-34.ll
index ff0914a..53a5c76 100644
--- a/test/CodeGen/SystemZ/int-cmp-34.ll
+++ b/test/CodeGen/SystemZ/int-cmp-34.ll
@@ -4,7 +4,7 @@
 
 ; Check ordered comparisons with 0.
 define double @f1(double %a, double %b, i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cghsi 0(%r2), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with 1.
 define double @f2(double %a, double %b, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cghsi 0(%r2), 1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with the high end of the signed 16-bit range.
 define double @f3(double %a, double %b, i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cghsi 0(%r2), 32767
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value up, which can't use CGHSI.
 define double @f4(double %a, double %b, i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -54,7 +54,7 @@ define double @f4(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with -1.
 define double @f5(double %a, double %b, i64 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cghsi 0(%r2), -1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -67,7 +67,7 @@ define double @f5(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with the low end of the 16-bit signed range.
 define double @f6(double %a, double %b, i64 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cghsi 0(%r2), -32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -80,7 +80,7 @@ define double @f6(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f7(double %a, double %b, i64 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -91,7 +91,7 @@ define double @f7(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with 0.
 define double @f8(double %a, double %b, i64 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cghsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -104,7 +104,7 @@ define double @f8(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with 1.
 define double @f9(double %a, double %b, i64 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cghsi 0(%r2), 1
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -117,7 +117,7 @@ define double @f9(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with the high end of the signed 16-bit range.
 define double @f10(double %a, double %b, i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cghsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -130,7 +130,7 @@ define double @f10(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value up, which can't use CGHSI.
 define double @f11(double %a, double %b, i64 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -141,7 +141,7 @@ define double @f11(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with -1.
 define double @f12(double %a, double %b, i64 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cghsi 0(%r2), -1
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -154,7 +154,7 @@ define double @f12(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with the low end of the 16-bit signed range.
 define double @f13(double %a, double %b, i64 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cghsi 0(%r2), -32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f13(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f14(double %a, double %b, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -178,7 +178,7 @@ define double @f14(double %a, double %b, i64 *%ptr) {
 
 ; Check the high end of the CGHSI range.
 define double @f15(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cghsi 4088(%r3), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -192,7 +192,7 @@ define double @f15(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the next doubleword up, which needs separate address logic,
 define double @f16(double %a, double %b, i64 *%base) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: aghi %r2, 4096
 ; CHECK: cghsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -207,7 +207,7 @@ define double @f16(double %a, double %b, i64 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f17(double %a, double %b, i64 *%base) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: aghi %r2, -8
 ; CHECK: cghsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -222,7 +222,7 @@ define double @f17(double %a, double %b, i64 *%base) {
 
 ; Check that CGHSI does not allow indices.
 define double @f18(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: cghsi 0({{%r[23]}}), 0
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-35.ll b/test/CodeGen/SystemZ/int-cmp-35.ll
index b74d67e..539248a 100644
--- a/test/CodeGen/SystemZ/int-cmp-35.ll
+++ b/test/CodeGen/SystemZ/int-cmp-35.ll
@@ -5,7 +5,7 @@
 ; Check ordered comparisons with a constant near the low end of the unsigned
 ; 16-bit range.
 define double @f1(double %a, double %b, i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clghsi 0(%r2), 2
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clghsi 0(%r2), 65535
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value up, which can't use CLGHSI.
 define double @f3(double %a, double %b, i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i64 *%ptr) {
 ; Check equality comparisons with 32768, the lowest value for which
 ; we prefer CLGHSI to CGHSI.
 define double @f4(double %a, double %b, i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clghsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with the high end of the unsigned 16-bit range.
 define double @f5(double %a, double %b, i64 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clghsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value up, which can't use CLGHSI.
 define double @f6(double %a, double %b, i64 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: clghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -80,7 +80,7 @@ define double @f6(double %a, double %b, i64 *%ptr) {
 
 ; Check the high end of the CLGHSI range.
 define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clghsi 4088(%r3), 2
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -94,7 +94,7 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the next doubleword up, which needs separate address logic,
 define double @f8(double %a, double %b, i64 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, 4096
 ; CHECK: clghsi 0(%r2), 2
 ; CHECK-NEXT: jl
@@ -109,7 +109,7 @@ define double @f8(double %a, double %b, i64 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f9(double %a, double %b, i64 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -8
 ; CHECK: clghsi 0(%r2), 2
 ; CHECK-NEXT: jl
@@ -124,7 +124,7 @@ define double @f9(double %a, double %b, i64 *%base) {
 
 ; Check that CLGHSI does not allow indices.
 define double @f10(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: clghsi 0({{%r[23]}}), 2
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-36.ll b/test/CodeGen/SystemZ/int-cmp-36.ll
index df0e337..831b05f 100644
--- a/test/CodeGen/SystemZ/int-cmp-36.ll
+++ b/test/CodeGen/SystemZ/int-cmp-36.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparison.
 define i32 @f1(i32 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: chrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check unsigned comparison, which cannot use CHRL.
 define i32 @f2(i32 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: chrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i32 @f3(i32 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: chrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i32 @f4(i32 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: chrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i32 @f5(i32 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: ch %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-37.ll b/test/CodeGen/SystemZ/int-cmp-37.ll
index 272df71..97d210e 100644
--- a/test/CodeGen/SystemZ/int-cmp-37.ll
+++ b/test/CodeGen/SystemZ/int-cmp-37.ll
@@ -8,7 +8,7 @@
 
 ; Check unsigned comparison.
 define i32 @f1(i32 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check signed comparison.
 define i32 @f2(i32 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: clhrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i32 @f3(i32 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i32 @f4(i32 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i32 @f5(i32 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: llh [[VAL:%r[0-5]]], 0([[REG]])
 ; CHECK: clr %r2, [[VAL]]
diff --git a/test/CodeGen/SystemZ/int-cmp-38.ll b/test/CodeGen/SystemZ/int-cmp-38.ll
index 54f325e..d5a852c 100644
--- a/test/CodeGen/SystemZ/int-cmp-38.ll
+++ b/test/CodeGen/SystemZ/int-cmp-38.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparisons.
 define i32 @f1(i32 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: crl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ exit:
 
 ; Check unsigned comparisons.
 define i32 @f2(i32 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ exit:
 
 ; Check equality, which can use CRL or CLRL.
 define i32 @f3(i32 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: c{{l?}}rl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ exit:
 
 ; ...likewise inequality.
 define i32 @f4(i32 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: c{{l?}}rl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i32 @f5(i32 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: c %r2, 0([[REG]])
 ; CHECK-NEXT: jl
@@ -99,7 +99,7 @@ exit:
 
 ; Repeat f2 with an unaligned address.
 define i32 @f6(i32 %src1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cl %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-39.ll b/test/CodeGen/SystemZ/int-cmp-39.ll
index e99b240..d442058 100644
--- a/test/CodeGen/SystemZ/int-cmp-39.ll
+++ b/test/CodeGen/SystemZ/int-cmp-39.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparison.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cghrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check unsigned comparison, which cannot use CHRL.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: cghrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cghrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cghrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: cgh %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-40.ll b/test/CodeGen/SystemZ/int-cmp-40.ll
index 2d33c8f..6dab2db 100644
--- a/test/CodeGen/SystemZ/int-cmp-40.ll
+++ b/test/CodeGen/SystemZ/int-cmp-40.ll
@@ -8,7 +8,7 @@
 
 ; Check unsigned comparison.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check signed comparison.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: clghrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: llgh [[VAL:%r[0-5]]], 0([[REG]])
 ; CHECK: clgr %r2, [[VAL]]
diff --git a/test/CodeGen/SystemZ/int-cmp-41.ll b/test/CodeGen/SystemZ/int-cmp-41.ll
index f68638a..099681d 100644
--- a/test/CodeGen/SystemZ/int-cmp-41.ll
+++ b/test/CodeGen/SystemZ/int-cmp-41.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparison.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgfrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check unsigned comparison, which cannot use CHRL.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: cgfrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cgfrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cgfrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cgf %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-42.ll b/test/CodeGen/SystemZ/int-cmp-42.ll
index dd3cb4a..26a268d 100644
--- a/test/CodeGen/SystemZ/int-cmp-42.ll
+++ b/test/CodeGen/SystemZ/int-cmp-42.ll
@@ -8,7 +8,7 @@
 
 ; Check unsigned comparison.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clgfrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check signed comparison.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: clgfrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clgfrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clgfrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: clgf %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-43.ll b/test/CodeGen/SystemZ/int-cmp-43.ll
index 7d4adca..e5e1390 100644
--- a/test/CodeGen/SystemZ/int-cmp-43.ll
+++ b/test/CodeGen/SystemZ/int-cmp-43.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparisons.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ exit:
 
 ; Check unsigned comparisons.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clgrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ exit:
 
 ; Check equality, which can use CRL or CLRL.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: c{{l?}}grl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ exit:
 
 ; ...likewise inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: c{{l?}}grl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cg %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-const-01.ll b/test/CodeGen/SystemZ/int-const-01.ll
index e714e9d..e94c058 100644
--- a/test/CodeGen/SystemZ/int-const-01.ll
+++ b/test/CodeGen/SystemZ/int-const-01.ll
@@ -6,7 +6,7 @@ declare void @foo(i32, i32, i32, i32)
 
 ; Check 0.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r2, 0
 ; CHECK: br %r14
   ret i32 0
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Check the high end of the LHI range.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r2, 32767
 ; CHECK: br %r14
   ret i32 32767
@@ -22,7 +22,7 @@ define i32 @f2() {
 
 ; Check the next value up, which must use LLILL instead.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llill %r2, 32768
 ; CHECK: br %r14
   ret i32 32768
@@ -30,7 +30,7 @@ define i32 @f3() {
 
 ; Check the high end of the LLILL range.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llill %r2, 65535
 ; CHECK: br %r14
   ret i32 65535
@@ -38,7 +38,7 @@ define i32 @f4() {
 
 ; Check the first useful LLILH value, which is the next one up.
 define i32 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llilh %r2, 1
 ; CHECK: br %r14
   ret i32 65536
@@ -46,7 +46,7 @@ define i32 @f5() {
 
 ; Check the first useful IILF value, which is the next one up again.
 define i32 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: iilf %r2, 65537
 ; CHECK: br %r14
   ret i32 65537
@@ -54,7 +54,7 @@ define i32 @f6() {
 
 ; Check the high end of the LLILH range.
 define i32 @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llilh %r2, 65535
 ; CHECK: br %r14
   ret i32 -65536
@@ -62,7 +62,7 @@ define i32 @f7() {
 
 ; Check the next value up, which must use IILF.
 define i32 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: iilf %r2, 4294901761
 ; CHECK: br %r14
   ret i32 -65535
@@ -70,7 +70,7 @@ define i32 @f8() {
 
 ; Check the highest useful IILF value, 0xffff7fff
 define i32 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: iilf %r2, 4294934527
 ; CHECK: br %r14
   ret i32 -32769
@@ -78,7 +78,7 @@ define i32 @f9() {
 
 ; Check the next value up, which should use LHI.
 define i32 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lhi %r2, -32768
 ; CHECK: br %r14
   ret i32 -32768
@@ -86,7 +86,7 @@ define i32 @f10() {
 
 ; Check -1.
 define i32 @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lhi %r2, -1
 ; CHECK: br %r14
   ret i32 -1
@@ -94,7 +94,7 @@ define i32 @f11() {
 
 ; Check that constant loads are rematerialized.
 define i32 @f12() {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-DAG: lhi %r2, 42
 ; CHECK-DAG: llill %r3, 32768
 ; CHECK-DAG: llilh %r4, 1
diff --git a/test/CodeGen/SystemZ/int-const-02.ll b/test/CodeGen/SystemZ/int-const-02.ll
index ba143c7..e71abc6 100644
--- a/test/CodeGen/SystemZ/int-const-02.ll
+++ b/test/CodeGen/SystemZ/int-const-02.ll
@@ -6,7 +6,7 @@ declare void @foo(i64, i64, i64, i64)
 
 ; Check 0.
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lghi %r2, 0
 ; CHECK-NEXT: br %r14
   ret i64 0
@@ -14,7 +14,7 @@ define i64 @f1() {
 
 ; Check the high end of the LGHI range.
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lghi %r2, 32767
 ; CHECK-NEXT: br %r14
   ret i64 32767
@@ -22,7 +22,7 @@ define i64 @f2() {
 
 ; Check the next value up, which must use LLILL instead.
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llill %r2, 32768
 ; CHECK-NEXT: br %r14
   ret i64 32768
@@ -30,7 +30,7 @@ define i64 @f3() {
 
 ; Check the high end of the LLILL range.
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llill %r2, 65535
 ; CHECK-NEXT: br %r14
   ret i64 65535
@@ -38,7 +38,7 @@ define i64 @f4() {
 
 ; Check the first useful LLILH value, which is the next one up.
 define i64 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llilh %r2, 1
 ; CHECK-NEXT: br %r14
   ret i64 65536
@@ -46,7 +46,7 @@ define i64 @f5() {
 
 ; Check the first useful LGFI value, which is the next one up again.
 define i64 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgfi %r2, 65537
 ; CHECK-NEXT: br %r14
   ret i64 65537
@@ -54,7 +54,7 @@ define i64 @f6() {
 
 ; Check the high end of the LGFI range.
 define i64 @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgfi %r2, 2147483647
 ; CHECK-NEXT: br %r14
   ret i64 2147483647
@@ -62,7 +62,7 @@ define i64 @f7() {
 
 ; Check the next value up, which should use LLILH instead.
 define i64 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llilh %r2, 32768
 ; CHECK-NEXT: br %r14
   ret i64 2147483648
@@ -70,7 +70,7 @@ define i64 @f8() {
 
 ; Check the next value up again, which should use LLILF.
 define i64 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: llilf %r2, 2147483649
 ; CHECK-NEXT: br %r14
   ret i64 2147483649
@@ -78,7 +78,7 @@ define i64 @f9() {
 
 ; Check the high end of the LLILH range.
 define i64 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llilh %r2, 65535
 ; CHECK-NEXT: br %r14
   ret i64 4294901760
@@ -86,7 +86,7 @@ define i64 @f10() {
 
 ; Check the next value up, which must use LLILF.
 define i64 @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llilf %r2, 4294901761
 ; CHECK-NEXT: br %r14
   ret i64 4294901761
@@ -94,7 +94,7 @@ define i64 @f11() {
 
 ; Check the high end of the LLILF range.
 define i64 @f12() {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: llilf %r2, 4294967295
 ; CHECK-NEXT: br %r14
   ret i64 4294967295
@@ -102,7 +102,7 @@ define i64 @f12() {
 
 ; Check the lowest useful LLIHL value, which is the next one up.
 define i64 @f13() {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: br %r14
   ret i64 4294967296
@@ -110,7 +110,7 @@ define i64 @f13() {
 
 ; Check the next value up, which must use a combination of two instructions.
 define i64 @f14() {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oill %r2, 1
 ; CHECK-NEXT: br %r14
@@ -119,7 +119,7 @@ define i64 @f14() {
 
 ; Check the high end of the OILL range.
 define i64 @f15() {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oill %r2, 65535
 ; CHECK-NEXT: br %r14
@@ -128,7 +128,7 @@ define i64 @f15() {
 
 ; Check the next value up, which should use OILH instead.
 define i64 @f16() {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oilh %r2, 1
 ; CHECK-NEXT: br %r14
@@ -137,7 +137,7 @@ define i64 @f16() {
 
 ; Check the next value up again, which should use OILF.
 define i64 @f17() {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oilf %r2, 65537
 ; CHECK-NEXT: br %r14
@@ -146,7 +146,7 @@ define i64 @f17() {
 
 ; Check the high end of the OILH range.
 define i64 @f18() {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oilh %r2, 65535
 ; CHECK-NEXT: br %r14
@@ -155,7 +155,7 @@ define i64 @f18() {
 
 ; Check the high end of the OILF range.
 define i64 @f19() {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oilf %r2, 4294967295
 ; CHECK-NEXT: br %r14
@@ -164,7 +164,7 @@ define i64 @f19() {
 
 ; Check the high end of the LLIHL range.
 define i64 @f20() {
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK: llihl %r2, 65535
 ; CHECK-NEXT: br %r14
   ret i64 281470681743360
@@ -172,7 +172,7 @@ define i64 @f20() {
 
 ; Check the lowest useful LLIHH value, which is 1<<32 greater than the above.
 define i64 @f21() {
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK: llihh %r2, 1
 ; CHECK-NEXT: br %r14
   ret i64 281474976710656
@@ -180,7 +180,7 @@ define i64 @f21() {
 
 ; Check the lowest useful LLIHF value, which is 1<<32 greater again.
 define i64 @f22() {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK: llihf %r2, 65537
 ; CHECK-NEXT: br %r14
   ret i64 281479271677952
@@ -188,7 +188,7 @@ define i64 @f22() {
 
 ; Check the highest end of the LLIHH range.
 define i64 @f23() {
-; CHECK: f23:
+; CHECK-LABEL: f23:
 ; CHECK: llihh %r2, 65535
 ; CHECK-NEXT: br %r14
   ret i64 -281474976710656
@@ -196,7 +196,7 @@ define i64 @f23() {
 
 ; Check the next value up, which must use OILL too.
 define i64 @f24() {
-; CHECK: f24:
+; CHECK-LABEL: f24:
 ; CHECK: llihh %r2, 65535
 ; CHECK-NEXT: oill %r2, 1
 ; CHECK-NEXT: br %r14
@@ -205,7 +205,7 @@ define i64 @f24() {
 
 ; Check the high end of the LLIHF range.
 define i64 @f25() {
-; CHECK: f25:
+; CHECK-LABEL: f25:
 ; CHECK: llihf %r2, 4294967295
 ; CHECK-NEXT: br %r14
   ret i64 -4294967296
@@ -213,7 +213,7 @@ define i64 @f25() {
 
 ; Check -1.
 define i64 @f26() {
-; CHECK: f26:
+; CHECK-LABEL: f26:
 ; CHECK: lghi %r2, -1
 ; CHECK-NEXT: br %r14
   ret i64 -1
@@ -221,7 +221,7 @@ define i64 @f26() {
 
 ; Check the low end of the LGHI range.
 define i64 @f27() {
-; CHECK: f27:
+; CHECK-LABEL: f27:
 ; CHECK: lghi %r2, -32768
 ; CHECK-NEXT: br %r14
   ret i64 -32768
@@ -229,7 +229,7 @@ define i64 @f27() {
 
 ; Check the next value down, which must use LGFI instead.
 define i64 @f28() {
-; CHECK: f28:
+; CHECK-LABEL: f28:
 ; CHECK: lgfi %r2, -32769
 ; CHECK-NEXT: br %r14
   ret i64 -32769
@@ -237,7 +237,7 @@ define i64 @f28() {
 
 ; Check the low end of the LGFI range.
 define i64 @f29() {
-; CHECK: f29:
+; CHECK-LABEL: f29:
 ; CHECK: lgfi %r2, -2147483648
 ; CHECK-NEXT: br %r14
   ret i64 -2147483648
@@ -245,7 +245,7 @@ define i64 @f29() {
 
 ; Check the next value down, which needs a two-instruction sequence.
 define i64 @f30() {
-; CHECK: f30:
+; CHECK-LABEL: f30:
 ; CHECK: llihf %r2, 4294967295
 ; CHECK-NEXT: oilf %r2, 2147483647
 ; CHECK-NEXT: br %r14
@@ -254,7 +254,7 @@ define i64 @f30() {
 
 ; Check that constant loads are rematerialized.
 define i64 @f31() {
-; CHECK: f31:
+; CHECK-LABEL: f31:
 ; CHECK-DAG: lghi %r2, 42
 ; CHECK-DAG: lgfi %r3, 65537
 ; CHECK-DAG: llilf %r4, 2147483649
diff --git a/test/CodeGen/SystemZ/int-const-03.ll b/test/CodeGen/SystemZ/int-const-03.ll
index 807b7e4..78db963 100644
--- a/test/CodeGen/SystemZ/int-const-03.ll
+++ b/test/CodeGen/SystemZ/int-const-03.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the unsigned range.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: br %r14
   store i8 0, i8 *%ptr
@@ -13,7 +13,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check the high end of the signed range.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvi 0(%r2), 127
 ; CHECK: br %r14
   store i8 127, i8 *%ptr
@@ -22,7 +22,7 @@ define void @f2(i8 *%ptr) {
 
 ; Check the next value up.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: br %r14
   store i8 -128, i8 *%ptr
@@ -31,7 +31,7 @@ define void @f3(i8 *%ptr) {
 
 ; Check the high end of the unsigned range.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: br %r14
   store i8 255, i8 *%ptr
@@ -40,7 +40,7 @@ define void @f4(i8 *%ptr) {
 
 ; Check -1.
 define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: br %r14
   store i8 -1, i8 *%ptr
@@ -49,7 +49,7 @@ define void @f5(i8 *%ptr) {
 
 ; Check the low end of the signed range.
 define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: br %r14
   store i8 -128, i8 *%ptr
@@ -58,7 +58,7 @@ define void @f6(i8 *%ptr) {
 
 ; Check the next value down.
 define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvi 0(%r2), 127
 ; CHECK: br %r14
   store i8 -129, i8 *%ptr
@@ -67,7 +67,7 @@ define void @f7(i8 *%ptr) {
 
 ; Check the high end of the MVI range.
 define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: mvi 4095(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -77,7 +77,7 @@ define void @f8(i8 *%src) {
 
 ; Check the next byte up, which should use MVIY instead of MVI.
 define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mviy 4096(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -87,7 +87,7 @@ define void @f9(i8 *%src) {
 
 ; Check the high end of the MVIY range.
 define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mviy 524287(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -98,7 +98,7 @@ define void @f10(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, 524288
 ; CHECK: mvi 0(%r2), 42
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define void @f11(i8 *%src) {
 
 ; Check the high end of the negative MVIY range.
 define void @f12(i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mviy -1(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -119,7 +119,7 @@ define void @f12(i8 *%src) {
 
 ; Check the low end of the MVIY range.
 define void @f13(i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: mviy -524288(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -130,7 +130,7 @@ define void @f13(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f14(i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: agfi %r2, -524289
 ; CHECK: mvi 0(%r2), 42
 ; CHECK: br %r14
@@ -141,7 +141,7 @@ define void @f14(i8 *%src) {
 
 ; Check that MVI does not allow an index
 define void @f15(i64 %src, i64 %index) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: agr %r2, %r3
 ; CHECK: mvi 4095(%r2), 42
 ; CHECK: br %r14
@@ -154,7 +154,7 @@ define void @f15(i64 %src, i64 %index) {
 
 ; Check that MVIY does not allow an index
 define void @f16(i64 %src, i64 %index) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: agr %r2, %r3
 ; CHECK: mviy 4096(%r2), 42
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-const-04.ll b/test/CodeGen/SystemZ/int-const-04.ll
index 41c7306..c109faa 100644
--- a/test/CodeGen/SystemZ/int-const-04.ll
+++ b/test/CodeGen/SystemZ/int-const-04.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the unsigned range.
 define void @f1(i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvhhi 0(%r2), 0
 ; CHECK: br %r14
   store i16 0, i16 *%ptr
@@ -13,7 +13,7 @@ define void @f1(i16 *%ptr) {
 
 ; Check the high end of the signed range.
 define void @f2(i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvhhi 0(%r2), 32767
 ; CHECK: br %r14
   store i16 32767, i16 *%ptr
@@ -22,7 +22,7 @@ define void @f2(i16 *%ptr) {
 
 ; Check the next value up.
 define void @f3(i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvhhi 0(%r2), -32768
 ; CHECK: br %r14
   store i16 -32768, i16 *%ptr
@@ -31,7 +31,7 @@ define void @f3(i16 *%ptr) {
 
 ; Check the high end of the unsigned range.
 define void @f4(i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvhhi 0(%r2), -1
 ; CHECK: br %r14
   store i16 65535, i16 *%ptr
@@ -40,7 +40,7 @@ define void @f4(i16 *%ptr) {
 
 ; Check -1.
 define void @f5(i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvhhi 0(%r2), -1
 ; CHECK: br %r14
   store i16 -1, i16 *%ptr
@@ -49,7 +49,7 @@ define void @f5(i16 *%ptr) {
 
 ; Check the low end of the signed range.
 define void @f6(i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvhhi 0(%r2), -32768
 ; CHECK: br %r14
   store i16 -32768, i16 *%ptr
@@ -58,7 +58,7 @@ define void @f6(i16 *%ptr) {
 
 ; Check the next value down.
 define void @f7(i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvhhi 0(%r2), 32767
 ; CHECK: br %r14
   store i16 -32769, i16 *%ptr
@@ -67,7 +67,7 @@ define void @f7(i16 *%ptr) {
 
 ; Check the high end of the MVHHI range.
 define void @f8(i16 *%a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: mvhhi 4094(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%a, i64 2047
@@ -78,7 +78,7 @@ define void @f8(i16 *%a) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i16 *%a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mvhhi 0(%r2), 42
 ; CHECK: br %r14
@@ -89,7 +89,7 @@ define void @f9(i16 *%a) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f10(i16 *%a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: aghi %r2, -2
 ; CHECK: mvhhi 0(%r2), 42
 ; CHECK: br %r14
@@ -100,7 +100,7 @@ define void @f10(i16 *%a) {
 
 ; Check that MVHHI does not allow an index
 define void @f11(i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agr %r2, %r3
 ; CHECK: mvhhi 0(%r2), 42
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-const-05.ll b/test/CodeGen/SystemZ/int-const-05.ll
index b85fd6b..d0c8569 100644
--- a/test/CodeGen/SystemZ/int-const-05.ll
+++ b/test/CodeGen/SystemZ/int-const-05.ll
@@ -4,7 +4,7 @@
 
 ; Check moves of zero.
 define void @f1(i32 *%a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   store i32 0, i32 *%a
@@ -13,7 +13,7 @@ define void @f1(i32 *%a) {
 
 ; Check the high end of the signed 16-bit range.
 define void @f2(i32 *%a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvhi 0(%r2), 32767
 ; CHECK: br %r14
   store i32 32767, i32 *%a
@@ -22,7 +22,7 @@ define void @f2(i32 *%a) {
 
 ; Check the next value up, which can't use MVHI.
 define void @f3(i32 *%a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: mvhi
 ; CHECK: br %r14
   store i32 32768, i32 *%a
@@ -31,7 +31,7 @@ define void @f3(i32 *%a) {
 
 ; Check moves of -1.
 define void @f4(i32 *%a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvhi 0(%r2), -1
 ; CHECK: br %r14
   store i32 -1, i32 *%a
@@ -40,7 +40,7 @@ define void @f4(i32 *%a) {
 
 ; Check the low end of the MVHI range.
 define void @f5(i32 *%a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvhi 0(%r2), -32768
 ; CHECK: br %r14
   store i32 -32768, i32 *%a
@@ -49,7 +49,7 @@ define void @f5(i32 *%a) {
 
 ; Check the next value down, which can't use MVHI.
 define void @f6(i32 *%a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: mvhi
 ; CHECK: br %r14
   store i32 -32769, i32 *%a
@@ -58,7 +58,7 @@ define void @f6(i32 *%a) {
 
 ; Check the high end of the MVHI range.
 define void @f7(i32 *%a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvhi 4092(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%a, i64 1023
@@ -69,7 +69,7 @@ define void @f7(i32 *%a) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i32 *%a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mvhi 0(%r2), 42
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ define void @f8(i32 *%a) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f9(i32 *%a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -4
 ; CHECK: mvhi 0(%r2), 42
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define void @f9(i32 *%a) {
 
 ; Check that MVHI does not allow an index
 define void @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r2, %r3
 ; CHECK: mvhi 0(%r2), 42
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-const-06.ll b/test/CodeGen/SystemZ/int-const-06.ll
index 9f14347..12a555c 100644
--- a/test/CodeGen/SystemZ/int-const-06.ll
+++ b/test/CodeGen/SystemZ/int-const-06.ll
@@ -4,7 +4,7 @@
 
 ; Check moves of zero.
 define void @f1(i64 *%a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvghi 0(%r2), 0
 ; CHECK: br %r14
   store i64 0, i64 *%a
@@ -13,7 +13,7 @@ define void @f1(i64 *%a) {
 
 ; Check the high end of the signed 16-bit range.
 define void @f2(i64 *%a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvghi 0(%r2), 32767
 ; CHECK: br %r14
   store i64 32767, i64 *%a
@@ -22,7 +22,7 @@ define void @f2(i64 *%a) {
 
 ; Check the next value up, which can't use MVGHI.
 define void @f3(i64 *%a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: mvghi
 ; CHECK: br %r14
   store i64 32768, i64 *%a
@@ -31,7 +31,7 @@ define void @f3(i64 *%a) {
 
 ; Check moves of -1.
 define void @f4(i64 *%a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvghi 0(%r2), -1
 ; CHECK: br %r14
   store i64 -1, i64 *%a
@@ -40,7 +40,7 @@ define void @f4(i64 *%a) {
 
 ; Check the low end of the MVGHI range.
 define void @f5(i64 *%a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvghi 0(%r2), -32768
 ; CHECK: br %r14
   store i64 -32768, i64 *%a
@@ -49,7 +49,7 @@ define void @f5(i64 *%a) {
 
 ; Check the next value down, which can't use MVGHI.
 define void @f6(i64 *%a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: mvghi
 ; CHECK: br %r14
   store i64 -32769, i64 *%a
@@ -58,7 +58,7 @@ define void @f6(i64 *%a) {
 
 ; Check the high end of the MVGHI range.
 define void @f7(i64 *%a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvghi 4088(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%a, i64 511
@@ -69,7 +69,7 @@ define void @f7(i64 *%a) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i64 *%a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mvghi 0(%r2), 42
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ define void @f8(i64 *%a) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f9(i64 *%a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -8
 ; CHECK: mvghi 0(%r2), 42
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define void @f9(i64 *%a) {
 
 ; Check that MVGHI does not allow an index
 define void @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r2, %r3
 ; CHECK: mvghi 0(%r2), 42
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-conv-01.ll b/test/CodeGen/SystemZ/int-conv-01.ll
index 335cf75..e5c411c 100644
--- a/test/CodeGen/SystemZ/int-conv-01.ll
+++ b/test/CodeGen/SystemZ/int-conv-01.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lbr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i32 %a to i8
@@ -14,7 +14,7 @@ define i32 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lbr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i64 %a to i8
@@ -24,7 +24,7 @@ define i32 @f2(i64 %a) {
 
 ; Check LB with no displacement.
 define i32 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lb %r2, 0(%r2)
 ; CHECK: br %r14
   %byte = load i8 *%src
@@ -34,7 +34,7 @@ define i32 @f3(i8 *%src) {
 
 ; Check the high end of the LB range.
 define i32 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lb %r2, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -46,7 +46,7 @@ define i32 @f4(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lb %r2, 0(%r2)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i32 @f5(i8 *%src) {
 
 ; Check the high end of the negative LB range.
 define i32 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lb %r2, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -69,7 +69,7 @@ define i32 @f6(i8 *%src) {
 
 ; Check the low end of the LB range.
 define i32 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lb %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -81,7 +81,7 @@ define i32 @f7(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524289
 ; CHECK: lb %r2, 0(%r2)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i32 @f8(i8 *%src) {
 
 ; Check that LB allows an index
 define i32 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lb %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -107,7 +107,7 @@ define i32 @f9(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LBR.  We want
 ; to use LB if possible.
 define void @f10(i32 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lb {{%r[0-9]+}}, 16{{[37]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i32 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-02.ll b/test/CodeGen/SystemZ/int-conv-02.ll
index 05d1cd9..18cfd4a 100644
--- a/test/CodeGen/SystemZ/int-conv-02.ll
+++ b/test/CodeGen/SystemZ/int-conv-02.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llcr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i32 %a to i8
@@ -14,7 +14,7 @@ define i32 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llcr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i64 %a to i8
@@ -24,7 +24,7 @@ define i32 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llcr %r2, %r2
 ; CHECK: br %r14
   %ext = and i32 %a, 255
@@ -33,7 +33,7 @@ define i32 @f3(i32 %a) {
 
 ; Check LLC with no displacement.
 define i32 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llc %r2, 0(%r2)
 ; CHECK: br %r14
   %byte = load i8 *%src
@@ -43,7 +43,7 @@ define i32 @f4(i8 *%src) {
 
 ; Check the high end of the LLC range.
 define i32 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llc %r2, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -55,7 +55,7 @@ define i32 @f5(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llc %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i32 @f6(i8 *%src) {
 
 ; Check the high end of the negative LLC range.
 define i32 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llc %r2, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f7(i8 *%src) {
 
 ; Check the low end of the LLC range.
 define i32 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llc %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -90,7 +90,7 @@ define i32 @f8(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524289
 ; CHECK: llc %r2, 0(%r2)
 ; CHECK: br %r14
@@ -102,7 +102,7 @@ define i32 @f9(i8 *%src) {
 
 ; Check that LLC allows an index
 define i32 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llc %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -116,7 +116,7 @@ define i32 @f10(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LLCR.  We want
 ; to use LLC if possible.
 define void @f11(i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llc {{%r[0-9]+}}, 16{{[37]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i32 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-03.ll b/test/CodeGen/SystemZ/int-conv-03.ll
index e3a2cdd..cad9581 100644
--- a/test/CodeGen/SystemZ/int-conv-03.ll
+++ b/test/CodeGen/SystemZ/int-conv-03.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgbr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i32 %a to i8
@@ -14,7 +14,7 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgbr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i64 %a to i8
@@ -24,7 +24,7 @@ define i64 @f2(i64 %a) {
 
 ; Check LGB with no displacement.
 define i64 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgb %r2, 0(%r2)
 ; CHECK: br %r14
   %byte = load i8 *%src
@@ -34,7 +34,7 @@ define i64 @f3(i8 *%src) {
 
 ; Check the high end of the LGB range.
 define i64 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgb %r2, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -46,7 +46,7 @@ define i64 @f4(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lgb %r2, 0(%r2)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i64 @f5(i8 *%src) {
 
 ; Check the high end of the negative LGB range.
 define i64 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgb %r2, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -69,7 +69,7 @@ define i64 @f6(i8 *%src) {
 
 ; Check the low end of the LGB range.
 define i64 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgb %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -81,7 +81,7 @@ define i64 @f7(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524289
 ; CHECK: lgb %r2, 0(%r2)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i64 @f8(i8 *%src) {
 
 ; Check that LGB allows an index
 define i64 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lgb %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -107,7 +107,7 @@ define i64 @f9(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LGBR.  We want
 ; to use LGB if possible.
 define void @f10(i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lgb {{%r[0-9]+}}, 167(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i64 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-04.ll b/test/CodeGen/SystemZ/int-conv-04.ll
index c3d445a..1c6be7b 100644
--- a/test/CodeGen/SystemZ/int-conv-04.ll
+++ b/test/CodeGen/SystemZ/int-conv-04.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i32 %a to i8
@@ -14,7 +14,7 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i64 %a to i8
@@ -24,7 +24,7 @@ define i64 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: br %r14
   %ext = and i64 %a, 255
@@ -33,7 +33,7 @@ define i64 @f3(i64 %a) {
 
 ; Check LLGC with no displacement.
 define i64 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
   %byte = load i8 *%src
@@ -43,7 +43,7 @@ define i64 @f4(i8 *%src) {
 
 ; Check the high end of the LLGC range.
 define i64 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llgc %r2, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -55,7 +55,7 @@ define i64 @f5(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i64 @f6(i8 *%src) {
 
 ; Check the high end of the negative LLGC range.
 define i64 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llgc %r2, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -78,7 +78,7 @@ define i64 @f7(i8 *%src) {
 
 ; Check the low end of the LLGC range.
 define i64 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llgc %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -90,7 +90,7 @@ define i64 @f8(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524289
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
@@ -102,7 +102,7 @@ define i64 @f9(i8 *%src) {
 
 ; Check that LLGC allows an index
 define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llgc %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -116,7 +116,7 @@ define i64 @f10(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LLGCR.  We want
 ; to use LLGC if possible.
 define void @f11(i64 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llgc {{%r[0-9]+}}, 167(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i64 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-05.ll b/test/CodeGen/SystemZ/int-conv-05.ll
index b5f23af..5eade93 100644
--- a/test/CodeGen/SystemZ/int-conv-05.ll
+++ b/test/CodeGen/SystemZ/int-conv-05.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i32 %a to i16
@@ -14,7 +14,7 @@ define i32 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i64 %a to i16
@@ -24,7 +24,7 @@ define i32 @f2(i64 %a) {
 
 ; Check the low end of the LH range.
 define i32 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -34,7 +34,7 @@ define i32 @f3(i16 *%src) {
 
 ; Check the high end of the LH range.
 define i32 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lh %r2, 4094(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -45,7 +45,7 @@ define i32 @f4(i16 *%src) {
 
 ; Check the next halfword up, which needs LHY rather than LH.
 define i32 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lhy %r2, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -56,7 +56,7 @@ define i32 @f5(i16 *%src) {
 
 ; Check the high end of the LHY range.
 define i32 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lhy %r2, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -68,7 +68,7 @@ define i32 @f6(i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ define i32 @f7(i16 *%src) {
 
 ; Check the high end of the negative LHY range.
 define i32 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lhy %r2, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -91,7 +91,7 @@ define i32 @f8(i16 *%src) {
 
 ; Check the low end of the LHY range.
 define i32 @f9(i16 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lhy %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -103,7 +103,7 @@ define i32 @f9(i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f10(i16 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524290
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -115,7 +115,7 @@ define i32 @f10(i16 *%src) {
 
 ; Check that LH allows an index
 define i32 @f11(i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lh %r2, 4094(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -128,7 +128,7 @@ define i32 @f11(i64 %src, i64 %index) {
 
 ; Check that LH allows an index
 define i32 @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: lhy %r2, 4096(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -142,7 +142,7 @@ define i32 @f12(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LHR.  We want
 ; to use LH if possible.
 define void @f13(i32 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: lh {{%r[0-9]+}}, 16{{[26]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i32 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-06.ll b/test/CodeGen/SystemZ/int-conv-06.ll
index 90a142b..9c95bad 100644
--- a/test/CodeGen/SystemZ/int-conv-06.ll
+++ b/test/CodeGen/SystemZ/int-conv-06.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llhr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i32 %a to i16
@@ -14,7 +14,7 @@ define i32 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llhr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i64 %a to i16
@@ -24,7 +24,7 @@ define i32 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llhr %r2, %r2
 ; CHECK: br %r14
   %ext = and i32 %a, 65535
@@ -33,7 +33,7 @@ define i32 @f3(i32 %a) {
 
 ; Check LLH with no displacement.
 define i32 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llh %r2, 0(%r2)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -43,7 +43,7 @@ define i32 @f4(i16 *%src) {
 
 ; Check the high end of the LLH range.
 define i32 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llh %r2, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -55,7 +55,7 @@ define i32 @f5(i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i32 @f6(i16 *%src) {
 
 ; Check the high end of the negative LLH range.
 define i32 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llh %r2, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f7(i16 *%src) {
 
 ; Check the low end of the LLH range.
 define i32 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llh %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -90,7 +90,7 @@ define i32 @f8(i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i16 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524290
 ; CHECK: llh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -102,7 +102,7 @@ define i32 @f9(i16 *%src) {
 
 ; Check that LLH allows an index
 define i32 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llh %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -116,7 +116,7 @@ define i32 @f10(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LLHR.  We want
 ; to use LLH if possible.
 define void @f11(i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llh {{%r[0-9]+}}, 16{{[26]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i32 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-07.ll b/test/CodeGen/SystemZ/int-conv-07.ll
index 9b9df46..4b78c77 100644
--- a/test/CodeGen/SystemZ/int-conv-07.ll
+++ b/test/CodeGen/SystemZ/int-conv-07.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lghr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i64 %a to i16
@@ -14,7 +14,7 @@ define i64 @f1(i64 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lghr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i32 %a to i16
@@ -24,7 +24,7 @@ define i64 @f2(i32 %a) {
 
 ; Check LGH with no displacement.
 define i64 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgh %r2, 0(%r2)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -34,7 +34,7 @@ define i64 @f3(i16 *%src) {
 
 ; Check the high end of the LGH range.
 define i64 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgh %r2, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -46,7 +46,7 @@ define i64 @f4(i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lgh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i64 @f5(i16 *%src) {
 
 ; Check the high end of the negative LGH range.
 define i64 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgh %r2, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -69,7 +69,7 @@ define i64 @f6(i16 *%src) {
 
 ; Check the low end of the LGH range.
 define i64 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgh %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -81,7 +81,7 @@ define i64 @f7(i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524290
 ; CHECK: lgh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i64 @f8(i16 *%src) {
 
 ; Check that LGH allows an index.
 define i64 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lgh %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -107,7 +107,7 @@ define i64 @f9(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LGHR.  We want
 ; to use LGH if possible.
 define void @f10(i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lgh {{%r[0-9]+}}, 166(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i64 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-08.ll b/test/CodeGen/SystemZ/int-conv-08.ll
index 0616f1e..6b6cb67 100644
--- a/test/CodeGen/SystemZ/int-conv-08.ll
+++ b/test/CodeGen/SystemZ/int-conv-08.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llghr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i32 %a to i16
@@ -14,7 +14,7 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llghr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i64 %a to i16
@@ -24,7 +24,7 @@ define i64 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llghr %r2, %r2
 ; CHECK: br %r14
   %ext = and i64 %a, 65535
@@ -33,7 +33,7 @@ define i64 @f3(i64 %a) {
 
 ; Check LLGH with no displacement.
 define i64 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgh %r2, 0(%r2)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -43,7 +43,7 @@ define i64 @f4(i16 *%src) {
 
 ; Check the high end of the LLGH range.
 define i64 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llgh %r2, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -55,7 +55,7 @@ define i64 @f5(i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llgh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i64 @f6(i16 *%src) {
 
 ; Check the high end of the negative LLGH range.
 define i64 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llgh %r2, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i64 @f7(i16 *%src) {
 
 ; Check the low end of the LLGH range.
 define i64 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llgh %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -90,7 +90,7 @@ define i64 @f8(i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f9(i16 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524290
 ; CHECK: llgh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -102,7 +102,7 @@ define i64 @f9(i16 *%src) {
 
 ; Check that LLGH allows an index
 define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llgh %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -116,7 +116,7 @@ define i64 @f10(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LLGHR.  We want
 ; to use LLGH if possible.
 define void @f11(i64 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llgh {{%r[0-9]+}}, 166(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i64 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-09.ll b/test/CodeGen/SystemZ/int-conv-09.ll
index ab6c463..db4c333 100644
--- a/test/CodeGen/SystemZ/int-conv-09.ll
+++ b/test/CodeGen/SystemZ/int-conv-09.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgfr %r2, %r2
 ; CHECK: br %r14
   %ext = sext i32 %a to i64
@@ -13,7 +13,7 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgfr %r2, %r2
 ; CHECK: br %r14
   %word = trunc i64 %a to i32
@@ -23,7 +23,7 @@ define i64 @f2(i64 %a) {
 
 ; Check LGF with no displacement.
 define i64 @f3(i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgf %r2, 0(%r2)
 ; CHECK: br %r14
   %word = load i32 *%src
@@ -33,7 +33,7 @@ define i64 @f3(i32 *%src) {
 
 ; Check the high end of the LGF range.
 define i64 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgf %r2, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -45,7 +45,7 @@ define i64 @f4(i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lgf %r2, 0(%r2)
 ; CHECK: br %r14
@@ -57,7 +57,7 @@ define i64 @f5(i32 *%src) {
 
 ; Check the high end of the negative LGF range.
 define i64 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgf %r2, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -68,7 +68,7 @@ define i64 @f6(i32 *%src) {
 
 ; Check the low end of the LGF range.
 define i64 @f7(i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgf %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -80,7 +80,7 @@ define i64 @f7(i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524292
 ; CHECK: lgf %r2, 0(%r2)
 ; CHECK: br %r14
@@ -92,7 +92,7 @@ define i64 @f8(i32 *%src) {
 
 ; Check that LGF allows an index.
 define i64 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lgf %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -106,7 +106,7 @@ define i64 @f9(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LGFR.  We want
 ; to use LGF if possible.
 define void @f10(i64 *%ptr1, i32 *%ptr2) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i32 *%ptr2
diff --git a/test/CodeGen/SystemZ/int-conv-10.ll b/test/CodeGen/SystemZ/int-conv-10.ll
index 4b078f9..f2f71d9 100644
--- a/test/CodeGen/SystemZ/int-conv-10.ll
+++ b/test/CodeGen/SystemZ/int-conv-10.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llgfr %r2, %r2
 ; CHECK: br %r14
   %ext = zext i32 %a to i64
@@ -13,7 +13,7 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llgfr %r2, %r2
 ; CHECK: br %r14
   %word = trunc i64 %a to i32
@@ -23,7 +23,7 @@ define i64 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llgfr %r2, %r2
 ; CHECK: br %r14
   %ext = and i64 %a, 4294967295
@@ -32,7 +32,7 @@ define i64 @f3(i64 %a) {
 
 ; Check LLGF with no displacement.
 define i64 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgf %r2, 0(%r2)
 ; CHECK: br %r14
   %word = load i32 *%src
@@ -42,7 +42,7 @@ define i64 @f4(i32 *%src) {
 
 ; Check the high end of the LLGF range.
 define i64 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llgf %r2, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -54,7 +54,7 @@ define i64 @f5(i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llgf %r2, 0(%r2)
 ; CHECK: br %r14
@@ -66,7 +66,7 @@ define i64 @f6(i32 *%src) {
 
 ; Check the high end of the negative LLGF range.
 define i64 @f7(i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llgf %r2, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -77,7 +77,7 @@ define i64 @f7(i32 *%src) {
 
 ; Check the low end of the LLGF range.
 define i64 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llgf %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -89,7 +89,7 @@ define i64 @f8(i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f9(i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524292
 ; CHECK: llgf %r2, 0(%r2)
 ; CHECK: br %r14
@@ -101,7 +101,7 @@ define i64 @f9(i32 *%src) {
 
 ; Check that LLGF allows an index.
 define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llgf %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -115,7 +115,7 @@ define i64 @f10(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LLGFR.  We want
 ; to use LLGF if possible.
 define void @f11(i64 *%ptr1, i32 *%ptr2) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i32 *%ptr2
diff --git a/test/CodeGen/SystemZ/int-div-01.ll b/test/CodeGen/SystemZ/int-div-01.ll
index 9fa019b..2c21186 100644
--- a/test/CodeGen/SystemZ/int-div-01.ll
+++ b/test/CodeGen/SystemZ/int-div-01.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Test register division.  The result is in the second of the two registers.
 define void @f1(i32 *%dest, i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgfr %r1, %r3
 ; CHECK: dsgfr %r0, %r4
 ; CHECK: st %r1, 0(%r2)
@@ -18,7 +18,7 @@ define void @f1(i32 *%dest, i32 %a, i32 %b) {
 
 ; Test register remainder.  The result is in the first of the two registers.
 define void @f2(i32 *%dest, i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgfr %r1, %r3
 ; CHECK: dsgfr %r0, %r4
 ; CHECK: st %r0, 0(%r2)
@@ -30,7 +30,7 @@ define void @f2(i32 *%dest, i32 %a, i32 %b) {
 
 ; Test that division and remainder use a single instruction.
 define i32 @f3(i32 %dummy, i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: lgfr %r3, %r3
 ; CHECK-NOT: %r2
@@ -47,7 +47,7 @@ define i32 @f3(i32 %dummy, i32 %a, i32 %b) {
 ; Check that the sign extension of the dividend is elided when the argument
 ; is already sign-extended.
 define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgfr %r2, %r4
 ; CHECK-NOT: dsgfr
@@ -61,7 +61,7 @@ define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) {
 
 ; Test that memory dividends are loaded using sign extension (LGF).
 define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: lgf %r3, 0(%r3)
 ; CHECK-NOT: %r2
@@ -78,7 +78,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Test memory division with no displacement.
 define void @f6(i32 *%dest, i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgfr %r1, %r3
 ; CHECK: dsgf %r0, 0(%r4)
 ; CHECK: st %r1, 0(%r2)
@@ -91,7 +91,7 @@ define void @f6(i32 *%dest, i32 %a, i32 *%src) {
 
 ; Test memory remainder with no displacement.
 define void @f7(i32 *%dest, i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgfr %r1, %r3
 ; CHECK: dsgf %r0, 0(%r4)
 ; CHECK: st %r0, 0(%r2)
@@ -104,7 +104,7 @@ define void @f7(i32 *%dest, i32 %a, i32 *%src) {
 
 ; Test both memory division and memory remainder.
 define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
 ; CHECK: lgfr %r3, %r3
 ; CHECK-NOT: %r2
@@ -121,7 +121,7 @@ define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the high end of the DSGF range.
 define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dsgf %r2, 524284(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -133,7 +133,7 @@ define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
@@ -145,7 +145,7 @@ define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned DSGF range.
 define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: dsgf %r2, -4(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -156,7 +156,7 @@ define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the low end of the DSGF range.
 define i32 @f12(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dsgf %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -168,7 +168,7 @@ define i32 @f12(i32 %dummy, i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f13(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agfi %r4, -524292
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
@@ -180,7 +180,7 @@ define i32 @f13(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check that DSGF allows an index.
 define i32 @f14(i32 %dummy, i32 %a, i64 %src, i64 %index) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: dsgf %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -194,7 +194,7 @@ define i32 @f14(i32 %dummy, i32 %a, i64 %src, i64 %index) {
 ; Make sure that we still use DSGFR rather than DSGR in cases where
 ; a load and division cannot be combined.
 define void @f15(i32 *%dest, i32 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: l [[B:%r[0-9]+]], 0(%r3)
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: lgfr %r1, %r2
@@ -209,7 +209,7 @@ define void @f15(i32 *%dest, i32 *%src) {
 
 ; Check that divisions of spilled values can use DSGF rather than DSGFR.
 define i32 @f16(i32 *%ptr0) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: dsgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-div-02.ll b/test/CodeGen/SystemZ/int-div-02.ll
index b09172d..f3287a5 100644
--- a/test/CodeGen/SystemZ/int-div-02.ll
+++ b/test/CodeGen/SystemZ/int-div-02.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Test register division.  The result is in the second of the two registers.
 define void @f1(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -20,7 +20,7 @@ define void @f1(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
 
 ; Test register remainder.  The result is in the first of the two registers.
 define void @f2(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -34,7 +34,7 @@ define void @f2(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
 
 ; Test that division and remainder use a single instruction.
 define i32 @f3(i32 %dummy1, i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -50,7 +50,7 @@ define i32 @f3(i32 %dummy1, i32 %a, i32 %b) {
 
 ; Test memory division with no displacement.
 define void @f4(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -65,7 +65,7 @@ define void @f4(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
 
 ; Test memory remainder with no displacement.
 define void @f5(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -80,7 +80,7 @@ define void @f5(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
 
 ; Test both memory division and memory remainder.
 define i32 @f6(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -97,7 +97,7 @@ define i32 @f6(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the high end of the DL range.
 define i32 @f7(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: dl %r2, 524284(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -109,7 +109,7 @@ define i32 @f7(i32 %dummy, i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dl %r2, 0(%r4)
 ; CHECK: br %r14
@@ -121,7 +121,7 @@ define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned DL range.
 define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dl %r2, -4(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -132,7 +132,7 @@ define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the low end of the DL range.
 define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: dl %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -144,7 +144,7 @@ define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r4, -524292
 ; CHECK: dl %r2, 0(%r4)
 ; CHECK: br %r14
@@ -156,7 +156,7 @@ define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check that DL allows an index.
 define i32 @f12(i32 %dummy, i32 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dl %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -169,7 +169,7 @@ define i32 @f12(i32 %dummy, i32 %a, i64 %src, i64 %index) {
 
 ; Check that divisions of spilled values can use DL rather than DLR.
 define i32 @f13(i32 *%ptr0) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: dl {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-div-03.ll b/test/CodeGen/SystemZ/int-div-03.ll
index 652fddc..7c04090 100644
--- a/test/CodeGen/SystemZ/int-div-03.ll
+++ b/test/CodeGen/SystemZ/int-div-03.ll
@@ -7,7 +7,7 @@ declare i64 @foo()
 
 ; Test register division.  The result is in the second of the two registers.
 define void @f1(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgfr %r2, %r4
 ; CHECK: stg %r3, 0(%r5)
@@ -20,7 +20,7 @@ define void @f1(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
 
 ; Test register remainder.  The result is in the first of the two registers.
 define void @f2(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgfr %r2, %r4
 ; CHECK: stg %r2, 0(%r5)
@@ -33,7 +33,7 @@ define void @f2(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
 
 ; Test that division and remainder use a single instruction.
 define i64 @f3(i64 %dummy, i64 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgfr %r2, %r4
 ; CHECK: ogr %r2, %r3
@@ -48,7 +48,7 @@ define i64 @f3(i64 %dummy, i64 %a, i32 %b) {
 ; Test register division when the dividend is zero rather than sign extended.
 ; We can't use dsgfr here
 define void @f4(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: dsgfr
 ; CHECK: br %r14
   %bext = zext i32 %b to i64
@@ -59,7 +59,7 @@ define void @f4(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
 
 ; ...likewise remainder.
 define void @f5(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: dsgfr
 ; CHECK: br %r14
   %bext = zext i32 %b to i64
@@ -70,7 +70,7 @@ define void @f5(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
 
 ; Test memory division with no displacement.
 define void @f6(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: stg %r3, 0(%r5)
@@ -84,7 +84,7 @@ define void @f6(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
 
 ; Test memory remainder with no displacement.
 define void @f7(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: stg %r2, 0(%r5)
@@ -98,7 +98,7 @@ define void @f7(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
 
 ; Test both memory division and memory remainder.
 define i64 @f8(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK-NOT: {{dsgf|dsgfr}}
@@ -114,7 +114,7 @@ define i64 @f8(i64 %dummy, i64 %a, i32 *%src) {
 
 ; Check the high end of the DSGF range.
 define i64 @f9(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dsgf %r2, 524284(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -127,7 +127,7 @@ define i64 @f9(i64 %dummy, i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f10(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
@@ -140,7 +140,7 @@ define i64 @f10(i64 %dummy, i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned DSGF range.
 define i64 @f11(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: dsgf %r2, -4(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -152,7 +152,7 @@ define i64 @f11(i64 %dummy, i64 %a, i32 *%src) {
 
 ; Check the low end of the DSGF range.
 define i64 @f12(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dsgf %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -165,7 +165,7 @@ define i64 @f12(i64 %dummy, i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f13(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agfi %r4, -524292
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
@@ -178,7 +178,7 @@ define i64 @f13(i64 %dummy, i64 %a, i32 *%src) {
 
 ; Check that DSGF allows an index.
 define i64 @f14(i64 %dummy, i64 %a, i64 %src, i64 %index) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: dsgf %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -193,7 +193,7 @@ define i64 @f14(i64 %dummy, i64 %a, i64 %src, i64 %index) {
 ; Make sure that we still use DSGFR rather than DSGR in cases where
 ; a load and division cannot be combined.
 define void @f15(i64 *%dest, i32 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: l [[B:%r[0-9]+]], 0(%r3)
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: lgr %r1, %r2
diff --git a/test/CodeGen/SystemZ/int-div-04.ll b/test/CodeGen/SystemZ/int-div-04.ll
index b2710a1..87f1e10 100644
--- a/test/CodeGen/SystemZ/int-div-04.ll
+++ b/test/CodeGen/SystemZ/int-div-04.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Testg register division.  The result is in the second of the two registers.
 define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgr %r2, %r4
 ; CHECK: stg %r3, 0(%r5)
@@ -18,7 +18,7 @@ define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
 
 ; Testg register remainder.  The result is in the first of the two registers.
 define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgr %r2, %r4
 ; CHECK: stg %r2, 0(%r5)
@@ -30,7 +30,7 @@ define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
 
 ; Testg that division and remainder use a single instruction.
 define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgr %r2, %r4
 ; CHECK-NOT: dsgr
@@ -44,7 +44,7 @@ define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
 
 ; Testg memory division with no displacement.
 define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: stg %r3, 0(%r5)
@@ -57,7 +57,7 @@ define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 
 ; Testg memory remainder with no displacement.
 define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: stg %r2, 0(%r5)
@@ -70,7 +70,7 @@ define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 
 ; Testg both memory division and memory remainder.
 define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK-NOT: {{dsg|dsgr}}
@@ -85,7 +85,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the DSG range.
 define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: dsg %r2, 524280(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -97,7 +97,7 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned DSG range.
 define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dsg %r2, -8(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -120,7 +120,7 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the low end of the DSG range.
 define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: dsg %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -132,7 +132,7 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r4, -524296
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -144,7 +144,7 @@ define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check that DSG allows an index.
 define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dsg %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -157,7 +157,7 @@ define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
 
 ; Check that divisions of spilled values can use DSG rather than DSGR.
 define i64 @f13(i64 *%ptr0) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: dsg {{%r[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-div-05.ll b/test/CodeGen/SystemZ/int-div-05.ll
index 3141503..8179830 100644
--- a/test/CodeGen/SystemZ/int-div-05.ll
+++ b/test/CodeGen/SystemZ/int-div-05.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Testg register division.  The result is in the second of the two registers.
 define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -20,7 +20,7 @@ define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
 
 ; Testg register remainder.  The result is in the first of the two registers.
 define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -34,7 +34,7 @@ define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
 
 ; Testg that division and remainder use a single instruction.
 define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -50,7 +50,7 @@ define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
 
 ; Testg memory division with no displacement.
 define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -65,7 +65,7 @@ define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 
 ; Testg memory remainder with no displacement.
 define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -80,7 +80,7 @@ define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 
 ; Testg both memory division and memory remainder.
 define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -97,7 +97,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the DLG range.
 define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: dlg %r2, 524280(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -109,7 +109,7 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -121,7 +121,7 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned DLG range.
 define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dlg %r2, -8(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -132,7 +132,7 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the low end of the DLG range.
 define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: dlg %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -144,7 +144,7 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r4, -524296
 ; CHECK: dlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -156,7 +156,7 @@ define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check that DLG allows an index.
 define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dlg %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -169,7 +169,7 @@ define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
 
 ; Check that divisions of spilled values can use DLG rather than DLGR.
 define i64 @f13(i64 *%ptr0) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: dlg {{%r[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-move-01.ll b/test/CodeGen/SystemZ/int-move-01.ll
index ae890ad..038e688 100644
--- a/test/CodeGen/SystemZ/int-move-01.ll
+++ b/test/CodeGen/SystemZ/int-move-01.ll
@@ -4,7 +4,7 @@
 
 ; Test 8-bit moves, which should get promoted to i32.
 define i8 @f1(i8 %a, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   ret i8 %b
@@ -12,7 +12,7 @@ define i8 @f1(i8 %a, i8 %b) {
 
 ; Test 16-bit moves, which again should get promoted to i32.
 define i16 @f2(i16 %a, i16 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   ret i16 %b
@@ -20,7 +20,7 @@ define i16 @f2(i16 %a, i16 %b) {
 
 ; Test 32-bit moves.
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   ret i32 %b
@@ -28,7 +28,7 @@ define i32 @f3(i32 %a, i32 %b) {
 
 ; Test 64-bit moves.
 define i64 @f4(i64 %a, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   ret i64 %b
diff --git a/test/CodeGen/SystemZ/int-move-02.ll b/test/CodeGen/SystemZ/int-move-02.ll
index 467e22d..5fc0843 100644
--- a/test/CodeGen/SystemZ/int-move-02.ll
+++ b/test/CodeGen/SystemZ/int-move-02.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the L range.
 define i32 @f1(i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: br %r14
   %val = load i32 *%src
@@ -13,7 +13,7 @@ define i32 @f1(i32 *%src) {
 
 ; Check the high end of the aligned L range.
 define i32 @f2(i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -23,7 +23,7 @@ define i32 @f2(i32 *%src) {
 
 ; Check the next word up, which should use LY instead of L.
 define i32 @f3(i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ly %r2, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -33,7 +33,7 @@ define i32 @f3(i32 *%src) {
 
 ; Check the high end of the aligned LY range.
 define i32 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ly %r2, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -44,7 +44,7 @@ define i32 @f4(i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define i32 @f5(i32 *%src) {
 
 ; Check the high end of the negative aligned LY range.
 define i32 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ly %r2, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i32 @f6(i32 *%src) {
 
 ; Check the low end of the LY range.
 define i32 @f7(i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ly %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -76,7 +76,7 @@ define i32 @f7(i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524292
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define i32 @f8(i32 *%src) {
 
 ; Check that L allows an index.
 define i32 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: l %r2, 4095({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define i32 @f9(i64 %src, i64 %index) {
 
 ; Check that LY allows an index.
 define i32 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ly %r2, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/int-move-03.ll b/test/CodeGen/SystemZ/int-move-03.ll
index 97c70a2..2894512 100644
--- a/test/CodeGen/SystemZ/int-move-03.ll
+++ b/test/CodeGen/SystemZ/int-move-03.ll
@@ -4,7 +4,7 @@
 
 ; Check LG with no displacement.
 define i64 @f1(i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: br %r14
   %val = load i64 *%src
@@ -13,7 +13,7 @@ define i64 @f1(i64 *%src) {
 
 ; Check the high end of the aligned LG range.
 define i64 @f2(i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -24,7 +24,7 @@ define i64 @f2(i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f3(i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define i64 @f3(i64 *%src) {
 
 ; Check the high end of the negative aligned LG range.
 define i64 @f4(i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lg %r2, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -45,7 +45,7 @@ define i64 @f4(i64 *%src) {
 
 ; Check the low end of the LG range.
 define i64 @f5(i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lg %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -56,7 +56,7 @@ define i64 @f5(i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524296
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i64 @f6(i64 *%src) {
 
 ; Check that LG allows an index.
 define i64 @f7(i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lg %r2, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/int-move-04.ll b/test/CodeGen/SystemZ/int-move-04.ll
index 9736657..d97ed2f 100644
--- a/test/CodeGen/SystemZ/int-move-04.ll
+++ b/test/CodeGen/SystemZ/int-move-04.ll
@@ -4,7 +4,7 @@
 
 ; Test an i8 store, which should get converted into an i32 truncation.
 define void @f1(i8 *%dst, i8 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   store i8 %val, i8 *%dst
@@ -13,7 +13,7 @@ define void @f1(i8 *%dst, i8 %val) {
 
 ; Test an i32 truncating store.
 define void @f2(i8 *%dst, i32 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   %trunc = trunc i32 %val to i8
@@ -23,7 +23,7 @@ define void @f2(i8 *%dst, i32 %val) {
 
 ; Test an i64 truncating store.
 define void @f3(i8 *%dst, i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   %trunc = trunc i64 %val to i8
@@ -33,7 +33,7 @@ define void @f3(i8 *%dst, i64 %val) {
 
 ; Check the high end of the STC range.
 define void @f4(i8 *%dst, i8 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stc %r3, 4095(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 4095
@@ -43,7 +43,7 @@ define void @f4(i8 *%dst, i8 %val) {
 
 ; Check the next byte up, which should use STCY instead of STC.
 define void @f5(i8 *%dst, i8 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stcy %r3, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 4096
@@ -53,7 +53,7 @@ define void @f5(i8 *%dst, i8 %val) {
 
 ; Check the high end of the STCY range.
 define void @f6(i8 *%dst, i8 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: stcy %r3, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 524287
@@ -64,7 +64,7 @@ define void @f6(i8 *%dst, i8 %val) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f7(i8 *%dst, i8 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f7(i8 *%dst, i8 %val) {
 
 ; Check the high end of the negative STCY range.
 define void @f8(i8 *%dst, i8 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: stcy %r3, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 -1
@@ -85,7 +85,7 @@ define void @f8(i8 *%dst, i8 %val) {
 
 ; Check the low end of the STCY range.
 define void @f9(i8 *%dst, i8 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: stcy %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 -524288
@@ -96,7 +96,7 @@ define void @f9(i8 *%dst, i8 %val) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f10(i8 *%dst, i8 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524289
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define void @f10(i8 *%dst, i8 %val) {
 
 ; Check that STC allows an index.
 define void @f11(i64 %dst, i64 %index, i8 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: stc %r4, 4095(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
@@ -119,7 +119,7 @@ define void @f11(i64 %dst, i64 %index, i8 %val) {
 
 ; Check that STCY allows an index.
 define void @f12(i64 %dst, i64 %index, i8 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: stcy %r4, 4096(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
diff --git a/test/CodeGen/SystemZ/int-move-05.ll b/test/CodeGen/SystemZ/int-move-05.ll
index f61477e..c21b88a 100644
--- a/test/CodeGen/SystemZ/int-move-05.ll
+++ b/test/CodeGen/SystemZ/int-move-05.ll
@@ -4,7 +4,7 @@
 
 ; Test an i16 store, which should get converted into an i32 truncation.
 define void @f1(i16 *%dst, i16 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
   store i16 %val, i16 *%dst
@@ -13,7 +13,7 @@ define void @f1(i16 *%dst, i16 %val) {
 
 ; Test an i32 truncating store.
 define void @f2(i16 *%dst, i32 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
   %trunc = trunc i32 %val to i16
@@ -23,7 +23,7 @@ define void @f2(i16 *%dst, i32 %val) {
 
 ; Test an i64 truncating store.
 define void @f3(i16 *%dst, i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
   %trunc = trunc i64 %val to i16
@@ -33,7 +33,7 @@ define void @f3(i16 *%dst, i64 %val) {
 
 ; Check the high end of the STH range.
 define void @f4(i16 *%dst, i16 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sth %r3, 4094(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 2047
@@ -43,7 +43,7 @@ define void @f4(i16 *%dst, i16 %val) {
 
 ; Check the next halfword up, which should use STHY instead of STH.
 define void @f5(i16 *%dst, i16 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sthy %r3, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 2048
@@ -53,7 +53,7 @@ define void @f5(i16 *%dst, i16 %val) {
 
 ; Check the high end of the aligned STHY range.
 define void @f6(i16 *%dst, i16 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sthy %r3, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 262143
@@ -64,7 +64,7 @@ define void @f6(i16 *%dst, i16 %val) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f7(i16 *%dst, i16 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f7(i16 *%dst, i16 %val) {
 
 ; Check the high end of the negative aligned STHY range.
 define void @f8(i16 *%dst, i16 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sthy %r3, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 -1
@@ -85,7 +85,7 @@ define void @f8(i16 *%dst, i16 %val) {
 
 ; Check the low end of the STHY range.
 define void @f9(i16 *%dst, i16 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: sthy %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 -262144
@@ -96,7 +96,7 @@ define void @f9(i16 *%dst, i16 %val) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f10(i16 *%dst, i16 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524290
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define void @f10(i16 *%dst, i16 %val) {
 
 ; Check that STH allows an index.
 define void @f11(i64 %dst, i64 %index, i16 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sth %r4, 4094({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
@@ -119,7 +119,7 @@ define void @f11(i64 %dst, i64 %index, i16 %val) {
 
 ; Check that STHY allows an index.
 define void @f12(i64 %dst, i64 %index, i16 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: sthy %r4, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
diff --git a/test/CodeGen/SystemZ/int-move-06.ll b/test/CodeGen/SystemZ/int-move-06.ll
index 5b35a32..b8c6f53 100644
--- a/test/CodeGen/SystemZ/int-move-06.ll
+++ b/test/CodeGen/SystemZ/int-move-06.ll
@@ -4,7 +4,7 @@
 
 ; Test an i32 store.
 define void @f1(i32 *%dst, i32 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: br %r14
   store i32 %val, i32 *%dst
@@ -20,7 +20,7 @@ define void @f2(i32 *%dst, i64 %val) {
 
 ; Check the high end of the aligned ST range.
 define void @f3(i32 *%dst, i32 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: st %r3, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 1023
@@ -30,7 +30,7 @@ define void @f3(i32 *%dst, i32 %val) {
 
 ; Check the next word up, which should use STY instead of ST.
 define void @f4(i32 *%dst, i32 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sty %r3, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 1024
@@ -40,7 +40,7 @@ define void @f4(i32 *%dst, i32 %val) {
 
 ; Check the high end of the aligned STY range.
 define void @f5(i32 *%dst, i32 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sty %r3, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 131071
@@ -51,7 +51,7 @@ define void @f5(i32 *%dst, i32 %val) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i32 *%dst, i32 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define void @f6(i32 *%dst, i32 %val) {
 
 ; Check the high end of the negative aligned STY range.
 define void @f7(i32 *%dst, i32 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sty %r3, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 -1
@@ -72,7 +72,7 @@ define void @f7(i32 *%dst, i32 %val) {
 
 ; Check the low end of the STY range.
 define void @f8(i32 *%dst, i32 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sty %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 -131072
@@ -83,7 +83,7 @@ define void @f8(i32 *%dst, i32 %val) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i32 *%dst, i32 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524292
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: br %r14
@@ -94,7 +94,7 @@ define void @f9(i32 *%dst, i32 %val) {
 
 ; Check that ST allows an index.
 define void @f10(i64 %dst, i64 %index, i32 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: st %r4, 4095(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
@@ -106,7 +106,7 @@ define void @f10(i64 %dst, i64 %index, i32 %val) {
 
 ; Check that STY allows an index.
 define void @f11(i64 %dst, i64 %index, i32 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sty %r4, 4096(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
diff --git a/test/CodeGen/SystemZ/int-move-07.ll b/test/CodeGen/SystemZ/int-move-07.ll
index ab21ab0..5cac1e5 100644
--- a/test/CodeGen/SystemZ/int-move-07.ll
+++ b/test/CodeGen/SystemZ/int-move-07.ll
@@ -4,7 +4,7 @@
 
 ; Check STG with no displacement.
 define void @f1(i64 *%dst, i64 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
   store i64 %val, i64 *%dst
@@ -13,7 +13,7 @@ define void @f1(i64 *%dst, i64 %val) {
 
 ; Check the high end of the aligned STG range.
 define void @f2(i64 *%dst, i64 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stg %r3, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 65535
@@ -24,7 +24,7 @@ define void @f2(i64 *%dst, i64 %val) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f3(i64 *%dst, i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define void @f3(i64 *%dst, i64 %val) {
 
 ; Check the high end of the negative aligned STG range.
 define void @f4(i64 *%dst, i64 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stg %r3, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 -1
@@ -45,7 +45,7 @@ define void @f4(i64 *%dst, i64 %val) {
 
 ; Check the low end of the STG range.
 define void @f5(i64 *%dst, i64 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stg %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 -65536
@@ -56,7 +56,7 @@ define void @f5(i64 *%dst, i64 %val) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 *%dst, i64 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524296
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define void @f6(i64 *%dst, i64 %val) {
 
 ; Check that STG allows an index.
 define void @f7(i64 %dst, i64 %index, i64 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: stg %r4, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
diff --git a/test/CodeGen/SystemZ/int-move-08.ll b/test/CodeGen/SystemZ/int-move-08.ll
index e6022aa..f16dd8e 100644
--- a/test/CodeGen/SystemZ/int-move-08.ll
+++ b/test/CodeGen/SystemZ/int-move-08.ll
@@ -13,7 +13,7 @@
 
 ; Check sign-extending loads from i16.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhrl %r2, gsrc16
 ; CHECK: br %r14
   %val = load i16 *@gsrc16
@@ -23,7 +23,7 @@ define i32 @f1() {
 
 ; Check zero-extending loads from i16.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llhrl %r2, gsrc16
 ; CHECK: br %r14
   %val = load i16 *@gsrc16
@@ -33,7 +33,7 @@ define i32 @f2() {
 
 ; Check truncating 16-bit stores.
 define void @f3(i32 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sthrl %r2, gdst16
 ; CHECK: br %r14
   %half = trunc i32 %val to i16
@@ -43,7 +43,7 @@ define void @f3(i32 %val) {
 
 ; Check plain loads and stores.
 define void @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lrl %r0, gsrc32
 ; CHECK: strl %r0, gdst32
 ; CHECK: br %r14
@@ -54,7 +54,7 @@ define void @f4() {
 
 ; Repeat f1 with an unaligned variable.
 define i32 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
 ; CHECK: lh %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define i32 @f5() {
 
 ; Repeat f2 with an unaligned variable.
 define i32 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
 ; CHECK: llh %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -76,7 +76,7 @@ define i32 @f6() {
 
 ; Repeat f3 with an unaligned variable.
 define void @f7(i32 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgrl [[REG:%r[0-5]]], gdst16u
 ; CHECK: sth %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define void @f7(i32 %val) {
 
 ; Repeat f4 with unaligned variables.
 define void @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: l [[VAL:%r[0-5]]], 0([[REG]])
 ; CHECK: larl [[REG:%r[0-5]]], gdst32u
diff --git a/test/CodeGen/SystemZ/int-move-09.ll b/test/CodeGen/SystemZ/int-move-09.ll
index 9167405..b5c9cb1 100644
--- a/test/CodeGen/SystemZ/int-move-09.ll
+++ b/test/CodeGen/SystemZ/int-move-09.ll
@@ -17,7 +17,7 @@
 
 ; Check sign-extending loads from i16.
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lghrl %r2, gsrc16
 ; CHECK: br %r14
   %val = load i16 *@gsrc16
@@ -27,7 +27,7 @@ define i64 @f1() {
 
 ; Check zero-extending loads from i16.
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llghrl %r2, gsrc16
 ; CHECK: br %r14
   %val = load i16 *@gsrc16
@@ -37,7 +37,7 @@ define i64 @f2() {
 
 ; Check sign-extending loads from i32.
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgfrl %r2, gsrc32
 ; CHECK: br %r14
   %val = load i32 *@gsrc32
@@ -47,7 +47,7 @@ define i64 @f3() {
 
 ; Check zero-extending loads from i32.
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgfrl %r2, gsrc32
 ; CHECK: br %r14
   %val = load i32 *@gsrc32
@@ -57,7 +57,7 @@ define i64 @f4() {
 
 ; Check truncating 16-bit stores.
 define void @f5(i64 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sthrl %r2, gdst16
 ; CHECK: br %r14
   %half = trunc i64 %val to i16
@@ -67,7 +67,7 @@ define void @f5(i64 %val) {
 
 ; Check truncating 32-bit stores.
 define void @f6(i64 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: strl %r2, gdst32
 ; CHECK: br %r14
   %word = trunc i64 %val to i32
@@ -77,7 +77,7 @@ define void @f6(i64 %val) {
 
 ; Check plain loads and stores.
 define void @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgrl %r0, gsrc64
 ; CHECK: stgrl %r0, gdst64
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define void @f7() {
 
 ; Repeat f1 with an unaligned variable.
 define i64 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
 ; CHECK: lgh %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -99,7 +99,7 @@ define i64 @f8() {
 
 ; Repeat f2 with an unaligned variable.
 define i64 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
 ; CHECK: llgh %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -110,7 +110,7 @@ define i64 @f9() {
 
 ; Repeat f3 with an unaligned variable.
 define i64 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: lgf %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -121,7 +121,7 @@ define i64 @f10() {
 
 ; Repeat f4 with an unaligned variable.
 define i64 @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: llgf %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define i64 @f11() {
 
 ; Repeat f5 with an unaligned variable.
 define void @f12(i64 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: lgrl [[REG:%r[0-5]]], gdst16u@GOT
 ; CHECK: sth %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -143,7 +143,7 @@ define void @f12(i64 %val) {
 
 ; Repeat f6 with an unaligned variable.
 define void @f13(i64 %val) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: larl [[REG:%r[0-5]]], gdst32u
 ; CHECK: st %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -154,7 +154,7 @@ define void @f13(i64 %val) {
 
 ; Repeat f7 with unaligned variables.
 define void @f14() {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc64u
 ; CHECK: lg [[VAL:%r[0-5]]], 0([[REG]])
 ; CHECK: larl [[REG:%r[0-5]]], gdst64u
diff --git a/test/CodeGen/SystemZ/int-mul-01.ll b/test/CodeGen/SystemZ/int-mul-01.ll
index e1246e2..d5f7155 100644
--- a/test/CodeGen/SystemZ/int-mul-01.ll
+++ b/test/CodeGen/SystemZ/int-mul-01.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the MH range.
 define i32 @f1(i32 %lhs, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mh %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -16,7 +16,7 @@ define i32 @f1(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned MH range.
 define i32 @f2(i32 %lhs, i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mh %r2, 4094(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -28,7 +28,7 @@ define i32 @f2(i32 %lhs, i16 *%src) {
 
 ; Check the next halfword up, which should use MHY instead of MH.
 define i32 @f3(i32 %lhs, i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mhy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -40,7 +40,7 @@ define i32 @f3(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned MHY range.
 define i32 @f4(i32 %lhs, i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mhy %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -53,7 +53,7 @@ define i32 @f4(i32 %lhs, i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 %lhs, i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: mh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -66,7 +66,7 @@ define i32 @f5(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the negative aligned MHY range.
 define i32 @f6(i32 %lhs, i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mhy %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f6(i32 %lhs, i16 *%src) {
 
 ; Check the low end of the MHY range.
 define i32 @f7(i32 %lhs, i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mhy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -91,7 +91,7 @@ define i32 @f7(i32 %lhs, i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %lhs, i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524290
 ; CHECK: mh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f8(i32 %lhs, i16 *%src) {
 
 ; Check that MH allows an index.
 define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mh %r2, 4094({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -118,7 +118,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
 
 ; Check that MHY allows an index.
 define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mhy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/int-mul-02.ll b/test/CodeGen/SystemZ/int-mul-02.ll
index 72990a7..d002a7f 100644
--- a/test/CodeGen/SystemZ/int-mul-02.ll
+++ b/test/CodeGen/SystemZ/int-mul-02.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Check MSR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msr %r2, %r3
 ; CHECK: br %r14
   %mul = mul i32 %a, %b
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the MS range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ms %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +25,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned MS range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ms %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -36,7 +36,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use MSY instead of MS.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: msy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -47,7 +47,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned MSY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msy %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -59,7 +59,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ms %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned MSY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: msy %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -82,7 +82,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the MSY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: msy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -94,7 +94,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: ms %r2, 0(%r3)
 ; CHECK: br %r14
@@ -106,7 +106,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that MS allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ms %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -119,7 +119,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that MSY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: msy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -132,7 +132,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
 
 ; Check that multiplications of spilled values can use MS rather than MSR.
 define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: ms %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-mul-03.ll b/test/CodeGen/SystemZ/int-mul-03.ll
index f027bd0..df18050 100644
--- a/test/CodeGen/SystemZ/int-mul-03.ll
+++ b/test/CodeGen/SystemZ/int-mul-03.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check MSGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msgfr %r2, %r3
 ; CHECK: br %r14
   %bext = sext i32 %b to i64
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check MSGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: msgf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -27,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned MSGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: msgf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -40,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: msgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -53,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned MSGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msgf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the MSGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: msgf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -78,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: msgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that MSGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: msgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -105,7 +105,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that multiplications of spilled values can use MSGF rather than MSGFR.
 define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: msgf %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-mul-04.ll b/test/CodeGen/SystemZ/int-mul-04.ll
index b37b043..183a9a7 100644
--- a/test/CodeGen/SystemZ/int-mul-04.ll
+++ b/test/CodeGen/SystemZ/int-mul-04.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check MSGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msgr %r2, %r3
 ; CHECK: br %r14
   %mul = mul i64 %a, %b
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check MSG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: msg %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -25,7 +25,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned MSG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: msg %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: msg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned MSG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msg %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -60,7 +60,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the MSG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: msg %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: msg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that MSG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: msg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that multiplications of spilled values can use MSG rather than MSGR.
 define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: msg %r2, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-mul-05.ll b/test/CodeGen/SystemZ/int-mul-05.ll
index 5e4031b..93f140d 100644
--- a/test/CodeGen/SystemZ/int-mul-05.ll
+++ b/test/CodeGen/SystemZ/int-mul-05.ll
@@ -4,7 +4,7 @@
 
 ; Check multiplication by 2, which should use shifts.
 define i32 @f1(i32 %a, i32 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sll %r2, 1
 ; CHECK: br %r14
   %mul = mul i32 %a, 2
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a, i32 *%dest) {
 
 ; Check multiplication by 3.
 define i32 @f2(i32 %a, i32 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mhi %r2, 3
 ; CHECK: br %r14
   %mul = mul i32 %a, 3
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a, i32 *%dest) {
 
 ; Check the high end of the MHI range.
 define i32 @f3(i32 %a, i32 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mhi %r2, 32767
 ; CHECK: br %r14
   %mul = mul i32 %a, 32767
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a, i32 *%dest) {
 
 ; Check the next value up, which should use shifts.
 define i32 @f4(i32 %a, i32 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sll %r2, 15
 ; CHECK: br %r14
   %mul = mul i32 %a, 32768
@@ -40,7 +40,7 @@ define i32 @f4(i32 %a, i32 *%dest) {
 
 ; Check the next value up again, which can use MSFI.
 define i32 @f5(i32 %a, i32 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msfi %r2, 32769
 ; CHECK: br %r14
   %mul = mul i32 %a, 32769
@@ -49,7 +49,7 @@ define i32 @f5(i32 %a, i32 *%dest) {
 
 ; Check the high end of the MSFI range.
 define i32 @f6(i32 %a, i32 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: msfi %r2, 2147483647
 ; CHECK: br %r14
   %mul = mul i32 %a, 2147483647
@@ -58,7 +58,7 @@ define i32 @f6(i32 %a, i32 *%dest) {
 
 ; Check the next value up, which should use shifts.
 define i32 @f7(i32 %a, i32 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sll %r2, 31
 ; CHECK: br %r14
   %mul = mul i32 %a, 2147483648
@@ -67,7 +67,7 @@ define i32 @f7(i32 %a, i32 *%dest) {
 
 ; Check the next value up again, which is treated as a negative value.
 define i32 @f8(i32 %a, i32 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: msfi %r2, -2147483647
 ; CHECK: br %r14
   %mul = mul i32 %a, 2147483649
@@ -76,7 +76,7 @@ define i32 @f8(i32 %a, i32 *%dest) {
 
 ; Check multiplication by -1, which is a negation.
 define i32 @f9(i32 %a, i32 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lcr %r2, %r2
 ; CHECK: br %r14
   %mul = mul i32 %a, -1
@@ -85,7 +85,7 @@ define i32 @f9(i32 %a, i32 *%dest) {
 
 ; Check multiplication by -2, which should use shifts.
 define i32 @f10(i32 %a, i32 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: sll %r2, 1
 ; CHECK: lcr %r2, %r2
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i32 @f10(i32 %a, i32 *%dest) {
 
 ; Check multiplication by -3.
 define i32 @f11(i32 %a, i32 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: mhi %r2, -3
 ; CHECK: br %r14
   %mul = mul i32 %a, -3
@@ -104,7 +104,7 @@ define i32 @f11(i32 %a, i32 *%dest) {
 
 ; Check the lowest useful MHI value.
 define i32 @f12(i32 %a, i32 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mhi %r2, -32767
 ; CHECK: br %r14
   %mul = mul i32 %a, -32767
@@ -113,7 +113,7 @@ define i32 @f12(i32 %a, i32 *%dest) {
 
 ; Check the next value down, which should use shifts.
 define i32 @f13(i32 %a, i32 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: sll %r2, 15
 ; CHECK: lcr %r2, %r2
 ; CHECK: br %r14
@@ -123,7 +123,7 @@ define i32 @f13(i32 %a, i32 *%dest) {
 
 ; Check the next value down again, which can use MSFI.
 define i32 @f14(i32 %a, i32 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: msfi %r2, -32769
 ; CHECK: br %r14
   %mul = mul i32 %a, -32769
@@ -132,7 +132,7 @@ define i32 @f14(i32 %a, i32 *%dest) {
 
 ; Check the lowest useful MSFI value.
 define i32 @f15(i32 %a, i32 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: msfi %r2, -2147483647
 ; CHECK: br %r14
   %mul = mul i32 %a, -2147483647
@@ -141,7 +141,7 @@ define i32 @f15(i32 %a, i32 *%dest) {
 
 ; Check the next value down, which should use shifts.
 define i32 @f16(i32 %a, i32 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: sll %r2, 31
 ; CHECK-NOT: lcr
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define i32 @f16(i32 %a, i32 *%dest) {
 
 ; Check the next value down again, which is treated as a positive value.
 define i32 @f17(i32 %a, i32 *%dest) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: msfi %r2, 2147483647
 ; CHECK: br %r14
   %mul = mul i32 %a, -2147483649
diff --git a/test/CodeGen/SystemZ/int-mul-06.ll b/test/CodeGen/SystemZ/int-mul-06.ll
index a354605..ae9f9c6 100644
--- a/test/CodeGen/SystemZ/int-mul-06.ll
+++ b/test/CodeGen/SystemZ/int-mul-06.ll
@@ -4,7 +4,7 @@
 
 ; Check multiplication by 2, which should use shifts.
 define i64 @f1(i64 %a, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg %r2, %r2, 1
 ; CHECK: br %r14
   %mul = mul i64 %a, 2
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a, i64 *%dest) {
 
 ; Check multiplication by 3.
 define i64 @f2(i64 %a, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mghi %r2, 3
 ; CHECK: br %r14
   %mul = mul i64 %a, 3
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a, i64 *%dest) {
 
 ; Check the high end of the MGHI range.
 define i64 @f3(i64 %a, i64 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mghi %r2, 32767
 ; CHECK: br %r14
   %mul = mul i64 %a, 32767
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a, i64 *%dest) {
 
 ; Check the next value up, which should use shifts.
 define i64 @f4(i64 %a, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sllg %r2, %r2, 15
 ; CHECK: br %r14
   %mul = mul i64 %a, 32768
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a, i64 *%dest) {
 
 ; Check the next value up again, which can use MSGFI.
 define i64 @f5(i64 %a, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msgfi %r2, 32769
 ; CHECK: br %r14
   %mul = mul i64 %a, 32769
@@ -49,7 +49,7 @@ define i64 @f5(i64 %a, i64 *%dest) {
 
 ; Check the high end of the MSGFI range.
 define i64 @f6(i64 %a, i64 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: msgfi %r2, 2147483647
 ; CHECK: br %r14
   %mul = mul i64 %a, 2147483647
@@ -58,7 +58,7 @@ define i64 @f6(i64 %a, i64 *%dest) {
 
 ; Check the next value up, which should use shifts.
 define i64 @f7(i64 %a, i64 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r2, %r2, 31
 ; CHECK: br %r14
   %mul = mul i64 %a, 2147483648
@@ -67,7 +67,7 @@ define i64 @f7(i64 %a, i64 *%dest) {
 
 ; Check the next value up again, which cannot use a constant multiplicatoin.
 define i64 @f8(i64 %a, i64 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: msgfi
 ; CHECK: br %r14
   %mul = mul i64 %a, 2147483649
@@ -76,7 +76,7 @@ define i64 @f8(i64 %a, i64 *%dest) {
 
 ; Check multiplication by -1, which is a negation.
 define i64 @f9(i64 %a, i64 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lcgr {{%r[0-5]}}, %r2
 ; CHECK: br %r14
   %mul = mul i64 %a, -1
@@ -85,7 +85,7 @@ define i64 @f9(i64 %a, i64 *%dest) {
 
 ; Check multiplication by -2, which should use shifts.
 define i64 @f10(i64 %a, i64 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 1
 ; CHECK: lcgr %r2, [[SHIFTED]]
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f10(i64 %a, i64 *%dest) {
 
 ; Check multiplication by -3.
 define i64 @f11(i64 %a, i64 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: mghi %r2, -3
 ; CHECK: br %r14
   %mul = mul i64 %a, -3
@@ -104,7 +104,7 @@ define i64 @f11(i64 %a, i64 *%dest) {
 
 ; Check the lowest useful MGHI value.
 define i64 @f12(i64 %a, i64 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mghi %r2, -32767
 ; CHECK: br %r14
   %mul = mul i64 %a, -32767
@@ -113,7 +113,7 @@ define i64 @f12(i64 %a, i64 *%dest) {
 
 ; Check the next value down, which should use shifts.
 define i64 @f13(i64 %a, i64 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 15
 ; CHECK: lcgr %r2, [[SHIFTED]]
 ; CHECK: br %r14
@@ -123,7 +123,7 @@ define i64 @f13(i64 %a, i64 *%dest) {
 
 ; Check the next value down again, which can use MSGFI.
 define i64 @f14(i64 %a, i64 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: msgfi %r2, -32769
 ; CHECK: br %r14
   %mul = mul i64 %a, -32769
@@ -132,7 +132,7 @@ define i64 @f14(i64 %a, i64 *%dest) {
 
 ; Check the lowest useful MSGFI value.
 define i64 @f15(i64 %a, i64 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: msgfi %r2, -2147483647
 ; CHECK: br %r14
   %mul = mul i64 %a, -2147483647
@@ -141,7 +141,7 @@ define i64 @f15(i64 %a, i64 *%dest) {
 
 ; Check the next value down, which should use shifts.
 define i64 @f16(i64 %a, i64 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 31
 ; CHECK: lcgr %r2, [[SHIFTED]]
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define i64 @f16(i64 %a, i64 *%dest) {
 
 ; Check the next value down again, which cannot use constant multiplication
 define i64 @f17(i64 %a, i64 *%dest) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK-NOT: msgfi
 ; CHECK: br %r14
   %mul = mul i64 %a, -2147483649
diff --git a/test/CodeGen/SystemZ/int-mul-07.ll b/test/CodeGen/SystemZ/int-mul-07.ll
index 2459cc3..874f43d 100644
--- a/test/CodeGen/SystemZ/int-mul-07.ll
+++ b/test/CodeGen/SystemZ/int-mul-07.ll
@@ -7,7 +7,7 @@
 
 ; Check zero-extended multiplication in which only the high part is used.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msgr
 ; CHECK: br %r14
   %ax = zext i32 %a to i64
@@ -20,7 +20,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check sign-extended multiplication in which only the high part is used.
 define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: msgfr
 ; CHECK: br %r14
   %ax = sext i32 %a to i64
@@ -34,7 +34,7 @@ define i32 @f2(i32 %a, i32 %b) {
 ; Check zero-extended multiplication in which the result is split into
 ; high and low halves.
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: msgr
 ; CHECK: br %r14
   %ax = zext i32 %a to i64
@@ -50,7 +50,7 @@ define i32 @f3(i32 %a, i32 %b) {
 ; Check sign-extended multiplication in which the result is split into
 ; high and low halves.
 define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: msgfr
 ; CHECK: br %r14
   %ax = sext i32 %a to i64
diff --git a/test/CodeGen/SystemZ/int-mul-08.ll b/test/CodeGen/SystemZ/int-mul-08.ll
index e06cfc2..a245760 100644
--- a/test/CodeGen/SystemZ/int-mul-08.ll
+++ b/test/CodeGen/SystemZ/int-mul-08.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check zero-extended multiplication in which only the high part is used.
 define i64 @f1(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: mlgr %r2, %r4
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define i64 @f1(i64 %dummy, i64 %a, i64 %b) {
 ; Check sign-extended multiplication in which only the high part is used.
 ; This needs a rather convoluted sequence.
 define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mlgr
 ; CHECK: agr
 ; CHECK: agr
@@ -37,7 +37,7 @@ define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
 ; Check zero-extended multiplication in which only part of the high half
 ; is used.
 define i64 @f3(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: mlgr %r2, %r4
 ; CHECK: srlg %r2, %r2, 3
@@ -53,7 +53,7 @@ define i64 @f3(i64 %dummy, i64 %a, i64 %b) {
 ; Check zero-extended multiplication in which the result is split into
 ; high and low halves.
 define i64 @f4(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: mlgr %r2, %r4
 ; CHECK: ogr %r2, %r3
@@ -70,7 +70,7 @@ define i64 @f4(i64 %dummy, i64 %a, i64 %b) {
 
 ; Check division by a constant, which should use multiplication instead.
 define i64 @f5(i64 %dummy, i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mlgr %r2,
 ; CHECK: srlg %r2, %r2,
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ define i64 @f5(i64 %dummy, i64 %a) {
 
 ; Check MLG with no displacement.
 define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: mlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned MLG range.
 define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mlg %r2, 524280(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -111,7 +111,7 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword up, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, 524288
 ; CHECK: mlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -127,7 +127,7 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned MLG range.
 define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mlg %r2, -8(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -142,7 +142,7 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the low end of the MLG range.
 define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mlg %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -158,7 +158,7 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f11(i64 *%dest, i64 %a, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r4, -524296
 ; CHECK: mlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -174,7 +174,7 @@ define i64 @f11(i64 *%dest, i64 %a, i64 *%src) {
 
 ; Check that MLG allows an index.
 define i64 @f12(i64 *%dest, i64 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mlg %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -191,7 +191,7 @@ define i64 @f12(i64 *%dest, i64 %a, i64 %src, i64 %index) {
 
 ; Check that multiplications of spilled values can use MLG rather than MLGR.
 define i64 @f13(i64 *%ptr0) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mlg {{%r[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-neg-01.ll b/test/CodeGen/SystemZ/int-neg-01.ll
index 6114f4e..a342fa7 100644
--- a/test/CodeGen/SystemZ/int-neg-01.ll
+++ b/test/CodeGen/SystemZ/int-neg-01.ll
@@ -4,7 +4,7 @@
 
 ; Test i32->i32 negation.
 define i32 @f1(i32 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lcr %r2, %r2
 ; CHECK: br %r14
   %neg = sub i32 0, %val
@@ -13,7 +13,7 @@ define i32 @f1(i32 %val) {
 
 ; Test i32->i64 negation.
 define i64 @f2(i32 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lcgfr %r2, %r2
 ; CHECK: br %r14
   %ext = sext i32 %val to i64
@@ -23,7 +23,7 @@ define i64 @f2(i32 %val) {
 
 ; Test i32->i64 negation that uses an "in-register" form of sign extension.
 define i64 @f3(i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lcgfr %r2, %r2
 ; CHECK: br %r14
   %trunc = trunc i64 %val to i32
@@ -34,7 +34,7 @@ define i64 @f3(i64 %val) {
 
 ; Test i64 negation.
 define i64 @f4(i64 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lcgr %r2, %r2
 ; CHECK: br %r14
   %neg = sub i64 0, %val
diff --git a/test/CodeGen/SystemZ/int-sub-01.ll b/test/CodeGen/SystemZ/int-sub-01.ll
index 96ce361..ac3a5ff 100644
--- a/test/CodeGen/SystemZ/int-sub-01.ll
+++ b/test/CodeGen/SystemZ/int-sub-01.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Check SR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sr %r2, %r3
 ; CHECK: br %r14
   %sub = sub i32 %a, %b
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the S range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +25,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned S range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: s %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -36,7 +36,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use SY instead of S.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -47,7 +47,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned SY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sy %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -59,7 +59,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned SY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sy %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -82,7 +82,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the SY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -94,7 +94,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: br %r14
@@ -106,7 +106,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that S allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: s %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -119,7 +119,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that SY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -132,7 +132,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
 
 ; Check that subtractions of spilled values can use S rather than SR.
 define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: s %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-sub-02.ll b/test/CodeGen/SystemZ/int-sub-02.ll
index 99d1c7b..a1c5ec5 100644
--- a/test/CodeGen/SystemZ/int-sub-02.ll
+++ b/test/CodeGen/SystemZ/int-sub-02.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check SGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sgfr %r2, %r3
 ; CHECK: br %r14
   %bext = sext i32 %b to i64
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check SGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sgf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -27,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned SGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sgf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -40,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: sgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -53,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned SGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sgf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the SGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sgf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -78,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: sgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that SGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -105,7 +105,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that subtractions of spilled values can use SGF rather than SGFR.
 define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: sgf %r2, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-sub-03.ll b/test/CodeGen/SystemZ/int-sub-03.ll
index 4904017..44edd84 100644
--- a/test/CodeGen/SystemZ/int-sub-03.ll
+++ b/test/CodeGen/SystemZ/int-sub-03.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check SLGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: slgfr %r2, %r3
 ; CHECK: br %r14
   %bext = zext i32 %b to i64
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check SLGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: slgf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -27,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned SLGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: slgf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -40,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: slgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -53,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned SLGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: slgf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the SLGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: slgf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -78,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: slgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that SLGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: slgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -105,7 +105,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that subtractions of spilled values can use SLGF rather than SLGFR.
 define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: slgf %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-sub-04.ll b/test/CodeGen/SystemZ/int-sub-04.ll
index 554f7f6..9547756 100644
--- a/test/CodeGen/SystemZ/int-sub-04.ll
+++ b/test/CodeGen/SystemZ/int-sub-04.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check SGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sgr %r2, %r3
 ; CHECK: br %r14
   %sub = sub i64 %a, %b
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check SG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -25,7 +25,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned SG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sg %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned SG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sg %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -60,7 +60,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the SG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sg %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that SG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that subtractions of spilled values can use SG rather than SGR.
 define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: sg %r2, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-sub-05.ll b/test/CodeGen/SystemZ/int-sub-05.ll
index 5d95e79..9ec66d0 100644
--- a/test/CodeGen/SystemZ/int-sub-05.ll
+++ b/test/CodeGen/SystemZ/int-sub-05.ll
@@ -6,7 +6,7 @@ declare i128 *@foo()
 
 ; Test register addition.
 define void @f1(i128 *%ptr, i64 %high, i64 %low) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: slgr {{%r[0-5]}}, %r4
 ; CHECK: slbgr {{%r[0-5]}}, %r3
 ; CHECK: br %r14
@@ -22,7 +22,7 @@ define void @f1(i128 *%ptr, i64 %high, i64 %low) {
 
 ; Test memory addition with no offset.
 define void @f2(i64 %addr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: slg {{%r[0-5]}}, 8(%r2)
 ; CHECK: slbg {{%r[0-5]}}, 0(%r2)
 ; CHECK: br %r14
@@ -37,7 +37,7 @@ define void @f2(i64 %addr) {
 
 ; Test the highest aligned offset that is in range of both SLG and SLBG.
 define void @f3(i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: slg {{%r[0-5]}}, 524280(%r2)
 ; CHECK: slbg {{%r[0-5]}}, 524272(%r2)
 ; CHECK: br %r14
@@ -53,7 +53,7 @@ define void @f3(i64 %base) {
 
 ; Test the next doubleword up, which requires separate address logic for SLG.
 define void @f4(i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgr [[BASE:%r[1-5]]], %r2
 ; CHECK: agfi [[BASE]], 524288
 ; CHECK: slg {{%r[0-5]}}, 0([[BASE]])
@@ -73,7 +73,7 @@ define void @f4(i64 %base) {
 ; both instructions.  It would be better to create an anchor at 524288
 ; that both instructions can use, but that isn't implemented yet.
 define void @f5(i64 %base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: slg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: slbg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: br %r14
@@ -89,7 +89,7 @@ define void @f5(i64 %base) {
 
 ; Test the lowest displacement that is in range of both SLG and SLBG.
 define void @f6(i64 %base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: slg {{%r[0-5]}}, -524280(%r2)
 ; CHECK: slbg {{%r[0-5]}}, -524288(%r2)
 ; CHECK: br %r14
@@ -105,7 +105,7 @@ define void @f6(i64 %base) {
 
 ; Test the next doubleword down, which is out of range of the SLBG.
 define void @f7(i64 %base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: slg {{%r[0-5]}}, -524288(%r2)
 ; CHECK: slbg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define void @f7(i64 %base) {
 ; Check that subtractions of spilled values can use SLG and SLBG rather than
 ; SLGR and SLBGR.
 define void @f8(i128 *%ptr0) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: slg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
 ; CHECK: slbg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
diff --git a/test/CodeGen/SystemZ/int-sub-06.ll b/test/CodeGen/SystemZ/int-sub-06.ll
index 0e04d51..395d584 100644
--- a/test/CodeGen/SystemZ/int-sub-06.ll
+++ b/test/CodeGen/SystemZ/int-sub-06.ll
@@ -5,7 +5,7 @@
 ; Check register additions.  The XOR ensures that we don't instead zero-extend
 ; %b into a register and use memory addition.
 define void @f1(i128 *%aptr, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: slgfr {{%r[0-5]}}, %r3
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -19,7 +19,7 @@ define void @f1(i128 *%aptr, i32 %b) {
 
 ; Like f1, but using an "in-register" extension.
 define void @f2(i128 *%aptr, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: slgfr {{%r[0-5]}}, %r3
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define void @f2(i128 *%aptr, i64 %b) {
 ; Test register addition in cases where the second operand is zero extended
 ; from i64 rather than i32, but is later masked to i32 range.
 define void @f3(i128 *%aptr, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: slgfr {{%r[0-5]}}, %r3
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define void @f3(i128 *%aptr, i64 %b) {
 
 ; Test SLGF with no offset.
 define void @f4(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: slgf {{%r[0-5]}}, 0(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define void @f4(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the high end of the SLGF range.
 define void @f5(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: slgf {{%r[0-5]}}, 524284(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -82,7 +82,7 @@ define void @f5(i128 *%aptr, i32 *%bsrc) {
 ; Check the next word up, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: slgf {{%r[0-5]}}, 0(%r3)
 ; CHECK: slbgr
@@ -99,7 +99,7 @@ define void @f6(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the high end of the negative aligned SLGF range.
 define void @f7(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: slgf {{%r[0-5]}}, -4(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -115,7 +115,7 @@ define void @f7(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the low end of the SLGF range.
 define void @f8(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: slgf {{%r[0-5]}}, -524288(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define void @f8(i128 *%aptr, i32 *%bsrc) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: slgf {{%r[0-5]}}, 0(%r3)
 ; CHECK: slbgr
@@ -149,7 +149,7 @@ define void @f9(i128 *%aptr, i32 *%bsrc) {
 
 ; Check that SLGF allows an index.
 define void @f10(i128 *%aptr, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: slgf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %a = load i128 *%aptr
diff --git a/test/CodeGen/SystemZ/int-sub-07.ll b/test/CodeGen/SystemZ/int-sub-07.ll
index 9bf5ed9..5c1f42c 100644
--- a/test/CodeGen/SystemZ/int-sub-07.ll
+++ b/test/CodeGen/SystemZ/int-sub-07.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the SH range.
 define i32 @f1(i32 %lhs, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sh %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -16,7 +16,7 @@ define i32 @f1(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned SH range.
 define i32 @f2(i32 %lhs, i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sh %r2, 4094(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -28,7 +28,7 @@ define i32 @f2(i32 %lhs, i16 *%src) {
 
 ; Check the next halfword up, which should use SHY instead of SH.
 define i32 @f3(i32 %lhs, i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: shy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -40,7 +40,7 @@ define i32 @f3(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned SHY range.
 define i32 @f4(i32 %lhs, i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: shy %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -53,7 +53,7 @@ define i32 @f4(i32 %lhs, i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 %lhs, i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: sh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -66,7 +66,7 @@ define i32 @f5(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the negative aligned SHY range.
 define i32 @f6(i32 %lhs, i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: shy %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f6(i32 %lhs, i16 *%src) {
 
 ; Check the low end of the SHY range.
 define i32 @f7(i32 %lhs, i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: shy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -91,7 +91,7 @@ define i32 @f7(i32 %lhs, i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %lhs, i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524290
 ; CHECK: sh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f8(i32 %lhs, i16 *%src) {
 
 ; Check that SH allows an index.
 define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: sh %r2, 4094({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %sub1 = add i64 %src, %index
@@ -118,7 +118,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
 
 ; Check that SHY allows an index.
 define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: shy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %sub1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/la-01.ll b/test/CodeGen/SystemZ/la-01.ll
index 1ebe109..31d2041 100644
--- a/test/CodeGen/SystemZ/la-01.ll
+++ b/test/CodeGen/SystemZ/la-01.ll
@@ -19,7 +19,7 @@ declare void @foo(i32 *)
 
 ; Test a load of a fully-aligned external variable.
 define i32 *@f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl %r2, e4
 ; CHECK-NEXT: br %r14
   ret i32 *@e4
@@ -27,7 +27,7 @@ define i32 *@f1() {
 
 ; Test a load of a fully-aligned local variable.
 define i32 *@f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: larl %r2, d4
 ; CHECK-NEXT: br %r14
   ret i32 *@d4
@@ -35,7 +35,7 @@ define i32 *@f2() {
 
 ; Test a load of a 2-byte-aligned external variable.
 define i32 *@f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: larl %r2, e2
 ; CHECK-NEXT: br %r14
   ret i32 *@e2
@@ -43,7 +43,7 @@ define i32 *@f3() {
 
 ; Test a load of a 2-byte-aligned local variable.
 define i32 *@f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: larl %r2, d2
 ; CHECK-NEXT: br %r14
   ret i32 *@d2
@@ -51,7 +51,7 @@ define i32 *@f4() {
 
 ; Test a load of an unaligned external variable, which must go via the GOT.
 define i32 *@f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl %r2, e1@GOT
 ; CHECK-NEXT: br %r14
   ret i32 *@e1
@@ -59,7 +59,7 @@ define i32 *@f5() {
 
 ; Test a load of an unaligned local variable, which must go via the GOT.
 define i32 *@f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgrl %r2, d1@GOT
 ; CHECK-NEXT: br %r14
   ret i32 *@d1
@@ -67,7 +67,7 @@ define i32 *@f6() {
 
 ; Test a load of an external function.
 define void() *@f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: larl %r2, ef
 ; CHECK-NEXT: br %r14
   ret void() *@ef
@@ -75,7 +75,7 @@ define void() *@f7() {
 
 ; Test a load of a local function.
 define void() *@f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: larl %r2, df
 ; CHECK-NEXT: br %r14
   ret void() *@df
@@ -83,7 +83,7 @@ define void() *@f8() {
 
 ; Test that LARL can be rematerialized.
 define i32 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: larl %r2, d2
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: larl %r2, d2
diff --git a/test/CodeGen/SystemZ/la-02.ll b/test/CodeGen/SystemZ/la-02.ll
index 4c5374a..d7362d6 100644
--- a/test/CodeGen/SystemZ/la-02.ll
+++ b/test/CodeGen/SystemZ/la-02.ll
@@ -23,7 +23,7 @@ define hidden void @hf() {
 ; Test loads of external variables.  There is no guarantee that the
 ; variable will be in range of LARL.
 define i32 *@f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgrl %r2, ev@GOT
 ; CHECK: br %r14
   ret i32 *@ev
@@ -31,7 +31,7 @@ define i32 *@f1() {
 
 ; ...likewise locally-defined normal-visibility variables.
 define i32 *@f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgrl %r2, dv@GOT
 ; CHECK: br %r14
   ret i32 *@dv
@@ -39,7 +39,7 @@ define i32 *@f2() {
 
 ; ...likewise protected variables.
 define i32 *@f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgrl %r2, pv@GOT
 ; CHECK: br %r14
   ret i32 *@pv
@@ -47,7 +47,7 @@ define i32 *@f3() {
 
 ; ...likewise hidden variables.
 define i32 *@f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgrl %r2, hv@GOT
 ; CHECK: br %r14
   ret i32 *@hv
@@ -56,7 +56,7 @@ define i32 *@f4() {
 ; Check loads of external functions.  This could use LARL, but we don't have
 ; code to detect that yet.
 define void() *@f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl %r2, ef@GOT
 ; CHECK: br %r14
   ret void() *@ef
@@ -64,7 +64,7 @@ define void() *@f5() {
 
 ; ...likewise locally-defined normal-visibility functions.
 define void() *@f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgrl %r2, df@GOT
 ; CHECK: br %r14
   ret void() *@df
@@ -72,7 +72,7 @@ define void() *@f6() {
 
 ; ...likewise protected functions.
 define void() *@f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgrl %r2, pf@GOT
 ; CHECK: br %r14
   ret void() *@pf
@@ -80,7 +80,7 @@ define void() *@f7() {
 
 ; ...likewise hidden functions.
 define void() *@f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lgrl %r2, hf@GOT
 ; CHECK: br %r14
   ret void() *@hf
diff --git a/test/CodeGen/SystemZ/la-03.ll b/test/CodeGen/SystemZ/la-03.ll
index 9449b2b..1ff3fef 100644
--- a/test/CodeGen/SystemZ/la-03.ll
+++ b/test/CodeGen/SystemZ/la-03.ll
@@ -20,7 +20,7 @@ define hidden void @hf() {
 
 ; Test loads of external variables, which must go via the GOT.
 define i32 *@f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgrl %r2, ev@GOT
 ; CHECK: br %r14
   ret i32 *@ev
@@ -29,7 +29,7 @@ define i32 *@f1() {
 ; Check loads of locally-defined normal-visibility variables, which might
 ; be overridden.  The load must go via the GOT.
 define i32 *@f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgrl %r2, dv@GOT
 ; CHECK: br %r14
   ret i32 *@dv
@@ -38,7 +38,7 @@ define i32 *@f2() {
 ; Check loads of protected variables, which in the small code model
 ; must be in range of LARL.
 define i32 *@f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: larl %r2, pv
 ; CHECK: br %r14
   ret i32 *@pv
@@ -46,7 +46,7 @@ define i32 *@f3() {
 
 ; ...likewise hidden variables.
 define i32 *@f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: larl %r2, hv
 ; CHECK: br %r14
   ret i32 *@hv
@@ -54,7 +54,7 @@ define i32 *@f4() {
 
 ; Like f1, but for functions.
 define void() *@f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl %r2, ef@GOT
 ; CHECK: br %r14
   ret void() *@ef
@@ -62,7 +62,7 @@ define void() *@f5() {
 
 ; Like f2, but for functions.
 define void() *@f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgrl %r2, df@GOT
 ; CHECK: br %r14
   ret void() *@df
@@ -70,7 +70,7 @@ define void() *@f6() {
 
 ; Like f3, but for functions.
 define void() *@f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: larl %r2, pf
 ; CHECK: br %r14
   ret void() *@pf
@@ -78,7 +78,7 @@ define void() *@f7() {
 
 ; Like f4, but for functions.
 define void() *@f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: larl %r2, hf
 ; CHECK: br %r14
   ret void() *@hf
diff --git a/test/CodeGen/SystemZ/la-04.ll b/test/CodeGen/SystemZ/la-04.ll
index 4c36364..4d47308 100644
--- a/test/CodeGen/SystemZ/la-04.ll
+++ b/test/CodeGen/SystemZ/la-04.ll
@@ -4,7 +4,7 @@
 
 ; Do some arbitrary work and return the address of the following label.
 define i8 *@f1(i8 *%addr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvi 0(%r2), 1
 ; CHECK: [[LABEL:\.L.*]]:
 ; CHECK: larl %r2, [[LABEL]]
diff --git a/test/CodeGen/SystemZ/memcpy-01.ll b/test/CodeGen/SystemZ/memcpy-01.ll
index 2985b03..7cb58b3 100644
--- a/test/CodeGen/SystemZ/memcpy-01.ll
+++ b/test/CodeGen/SystemZ/memcpy-01.ll
@@ -6,7 +6,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8 *nocapture, i8 *nocapture, i32, i32,
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8 *nocapture, i8 *nocapture, i64, i32, i1) nounwind
 
 define void @f1(i8 *%dest, i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK-NOT: %r3
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define void @f1(i8 *%dest, i8 *%src) {
 }
 
 define void @f2(i8 *%dest, i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK-NOT: %r3
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define void @f2(i8 *%dest, i8 *%src) {
 }
 
 define void @f3(i8 *%dest, i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvc 0(1,%r2), 0(%r3)
 ; CHECK: br %r14
   call void @llvm.memcpy.p0i8.p0i8.i32(i8 *%dest, i8 *%src, i32 1, i32 1,
@@ -35,7 +35,7 @@ define void @f3(i8 *%dest, i8 *%src) {
 }
 
 define void @f4(i8 *%dest, i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvc 0(1,%r2), 0(%r3)
 ; CHECK: br %r14
   call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 1, i32 1,
@@ -44,7 +44,7 @@ define void @f4(i8 *%dest, i8 *%src) {
 }
 
 define void @f5(i8 *%dest, i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvc 0(256,%r2), 0(%r3)
 ; CHECK: br %r14
   call void @llvm.memcpy.p0i8.p0i8.i32(i8 *%dest, i8 *%src, i32 256, i32 1,
@@ -53,7 +53,7 @@ define void @f5(i8 *%dest, i8 *%src) {
 }
 
 define void @f6(i8 *%dest, i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvc 0(256,%r2), 0(%r3)
 ; CHECK: br %r14
   call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 256, i32 1,
@@ -64,7 +64,7 @@ define void @f6(i8 *%dest, i8 *%src) {
 ; 257 bytes is too big for a single MVC.  For now expect none, so that
 ; the test fails and gets updated when large copies are implemented.
 define void @f7(i8 *%dest, i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memcpy.p0i8.p0i8.i32(i8 *%dest, i8 *%src, i32 257, i32 1,
@@ -73,7 +73,7 @@ define void @f7(i8 *%dest, i8 *%src) {
 }
 
 define void @f8(i8 *%dest, i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 257, i32 1,
diff --git a/test/CodeGen/SystemZ/memcpy-02.ll b/test/CodeGen/SystemZ/memcpy-02.ll
index 0b576a7..83b2cd8 100644
--- a/test/CodeGen/SystemZ/memcpy-02.ll
+++ b/test/CodeGen/SystemZ/memcpy-02.ll
@@ -10,7 +10,7 @@
 
 ; Test the simple i8 case.
 define void @f1(i8 *%ptr1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i8 *%ptr1, i64 1
@@ -21,7 +21,7 @@ define void @f1(i8 *%ptr1) {
 
 ; Test i8 cases where the value is zero-extended to 32 bits.
 define void @f2(i8 *%ptr1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i8 *%ptr1, i64 1
@@ -34,7 +34,7 @@ define void @f2(i8 *%ptr1) {
 
 ; Test i8 cases where the value is zero-extended to 64 bits.
 define void @f3(i8 *%ptr1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i8 *%ptr1, i64 1
@@ -47,7 +47,7 @@ define void @f3(i8 *%ptr1) {
 
 ; Test i8 cases where the value is sign-extended to 32 bits.
 define void @f4(i8 *%ptr1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i8 *%ptr1, i64 1
@@ -60,7 +60,7 @@ define void @f4(i8 *%ptr1) {
 
 ; Test i8 cases where the value is sign-extended to 64 bits.
 define void @f5(i8 *%ptr1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i8 *%ptr1, i64 1
@@ -73,7 +73,7 @@ define void @f5(i8 *%ptr1) {
 
 ; Test the simple i16 case.
 define void @f6(i16 *%ptr1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i16 *%ptr1, i64 1
@@ -84,7 +84,7 @@ define void @f6(i16 *%ptr1) {
 
 ; Test i16 cases where the value is zero-extended to 32 bits.
 define void @f7(i16 *%ptr1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i16 *%ptr1, i64 1
@@ -97,7 +97,7 @@ define void @f7(i16 *%ptr1) {
 
 ; Test i16 cases where the value is zero-extended to 64 bits.
 define void @f8(i16 *%ptr1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i16 *%ptr1, i64 1
@@ -110,7 +110,7 @@ define void @f8(i16 *%ptr1) {
 
 ; Test i16 cases where the value is sign-extended to 32 bits.
 define void @f9(i16 *%ptr1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i16 *%ptr1, i64 1
@@ -123,7 +123,7 @@ define void @f9(i16 *%ptr1) {
 
 ; Test i16 cases where the value is sign-extended to 64 bits.
 define void @f10(i16 *%ptr1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i16 *%ptr1, i64 1
@@ -136,7 +136,7 @@ define void @f10(i16 *%ptr1) {
 
 ; Test the simple i32 case.
 define void @f11(i32 *%ptr1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i32 *%ptr1, i64 1
@@ -147,7 +147,7 @@ define void @f11(i32 *%ptr1) {
 
 ; Test i32 cases where the value is zero-extended to 64 bits.
 define void @f12(i32 *%ptr1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i32 *%ptr1, i64 1
@@ -160,7 +160,7 @@ define void @f12(i32 *%ptr1) {
 
 ; Test i32 cases where the value is sign-extended to 64 bits.
 define void @f13(i32 *%ptr1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i32 *%ptr1, i64 1
@@ -173,7 +173,7 @@ define void @f13(i32 *%ptr1) {
 
 ; Test the i64 case.
 define void @f14(i64 *%ptr1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: mvc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i64 *%ptr1, i64 1
@@ -184,7 +184,7 @@ define void @f14(i64 *%ptr1) {
 
 ; Test the f32 case.
 define void @f15(float *%ptr1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr float *%ptr1, i64 1
@@ -195,7 +195,7 @@ define void @f15(float *%ptr1) {
 
 ; Test the f64 case.
 define void @f16(double *%ptr1) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: mvc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr double *%ptr1, i64 1
@@ -206,7 +206,7 @@ define void @f16(double *%ptr1) {
 
 ; Test the f128 case.
 define void @f17(fp128 *%ptr1) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: mvc 16(16,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr fp128 *%ptr1, i64 1
@@ -217,7 +217,7 @@ define void @f17(fp128 *%ptr1) {
 
 ; Make sure that we don't use MVC if the load is volatile.
 define void @f18(i64 *%ptr1) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %ptr2 = getelementptr i64 *%ptr1, i64 1
@@ -228,7 +228,7 @@ define void @f18(i64 *%ptr1) {
 
 ; ...likewise the store.
 define void @f19(i64 *%ptr1) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %ptr2 = getelementptr i64 *%ptr1, i64 1
@@ -240,7 +240,7 @@ define void @f19(i64 *%ptr1) {
 ; Test that MVC is used for aligned loads and stores, even if there is
 ; no way of telling whether they alias.
 define void @f20(i64 *%ptr1, i64 *%ptr2) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK: mvc 0(8,%r3), 0(%r2)
 ; CHECK: br %r14
   %val = load i64 *%ptr1
@@ -250,7 +250,7 @@ define void @f20(i64 *%ptr1, i64 *%ptr2) {
 
 ; ...but if the loads aren't aligned, we can't be sure.
 define void @f21(i64 *%ptr1, i64 *%ptr2) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %val = load i64 *%ptr1, align 2
@@ -260,7 +260,7 @@ define void @f21(i64 *%ptr1, i64 *%ptr2) {
 
 ; Test a case where there is definite overlap.
 define void @f22(i64 %base) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %add = add i64 %base, 1
@@ -273,7 +273,7 @@ define void @f22(i64 %base) {
 
 ; Test that we can use MVC for global addresses for i8.
 define void @f23(i8 *%ptr) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
 ; CHECK: larl [[REG:%r[0-5]]], g1
 ; CHECK: mvc 0(1,%r2), 0([[REG]])
 ; CHECK: br %r14
@@ -284,7 +284,7 @@ define void @f23(i8 *%ptr) {
 
 ; ...and again with the global on the store.
 define void @f24(i8 *%ptr) {
-; CHECK: f24:
+; CHECK-LABEL: f24:
 ; CHECK: larl [[REG:%r[0-5]]], g1
 ; CHECK: mvc 0(1,[[REG]]), 0(%r2)
 ; CHECK: br %r14
@@ -295,7 +295,7 @@ define void @f24(i8 *%ptr) {
 
 ; Test that we use LHRL for i16.
 define void @f25(i16 *%ptr) {
-; CHECK: f25:
+; CHECK-LABEL: f25:
 ; CHECK: lhrl [[REG:%r[0-5]]], g2
 ; CHECK: sth [[REG]], 0(%r2)
 ; CHECK: br %r14
@@ -306,7 +306,7 @@ define void @f25(i16 *%ptr) {
 
 ; ...likewise STHRL.
 define void @f26(i16 *%ptr) {
-; CHECK: f26:
+; CHECK-LABEL: f26:
 ; CHECK: lh [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: sthrl [[REG]], g2
 ; CHECK: br %r14
@@ -317,7 +317,7 @@ define void @f26(i16 *%ptr) {
 
 ; Test that we use LRL for i32.
 define void @f27(i32 *%ptr) {
-; CHECK: f27:
+; CHECK-LABEL: f27:
 ; CHECK: lrl [[REG:%r[0-5]]], g3
 ; CHECK: st [[REG]], 0(%r2)
 ; CHECK: br %r14
@@ -328,7 +328,7 @@ define void @f27(i32 *%ptr) {
 
 ; ...likewise STRL.
 define void @f28(i32 *%ptr) {
-; CHECK: f28:
+; CHECK-LABEL: f28:
 ; CHECK: l [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: strl [[REG]], g3
 ; CHECK: br %r14
@@ -339,7 +339,7 @@ define void @f28(i32 *%ptr) {
 
 ; Test that we use LGRL for i64.
 define void @f29(i64 *%ptr) {
-; CHECK: f29:
+; CHECK-LABEL: f29:
 ; CHECK: lgrl [[REG:%r[0-5]]], g4
 ; CHECK: stg [[REG]], 0(%r2)
 ; CHECK: br %r14
@@ -350,7 +350,7 @@ define void @f29(i64 *%ptr) {
 
 ; ...likewise STGRL.
 define void @f30(i64 *%ptr) {
-; CHECK: f30:
+; CHECK-LABEL: f30:
 ; CHECK: lg [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: stgrl [[REG]], g4
 ; CHECK: br %r14
@@ -361,7 +361,7 @@ define void @f30(i64 *%ptr) {
 
 ; Test that we can use MVC for global addresses for fp128.
 define void @f31(fp128 *%ptr) {
-; CHECK: f31:
+; CHECK-LABEL: f31:
 ; CHECK: larl [[REG:%r[0-5]]], g5
 ; CHECK: mvc 0(16,%r2), 0([[REG]])
 ; CHECK: br %r14
@@ -372,7 +372,7 @@ define void @f31(fp128 *%ptr) {
 
 ; ...and again with the global on the store.
 define void @f32(fp128 *%ptr) {
-; CHECK: f32:
+; CHECK-LABEL: f32:
 ; CHECK: larl [[REG:%r[0-5]]], g5
 ; CHECK: mvc 0(16,[[REG]]), 0(%r2)
 ; CHECK: br %r14
@@ -383,7 +383,7 @@ define void @f32(fp128 *%ptr) {
 
 ; Test a case where offset disambiguation is enough.
 define void @f33(i64 *%ptr1) {
-; CHECK: f33:
+; CHECK-LABEL: f33:
 ; CHECK: mvc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i64 *%ptr1, i64 1
@@ -394,7 +394,7 @@ define void @f33(i64 *%ptr1) {
 
 ; Test f21 in cases where TBAA tells us there is no alias.
 define void @f34(i64 *%ptr1, i64 *%ptr2) {
-; CHECK: f34:
+; CHECK-LABEL: f34:
 ; CHECK: mvc 0(8,%r3), 0(%r2)
 ; CHECK: br %r14
   %val = load i64 *%ptr1, align 2, !tbaa !1
@@ -404,7 +404,7 @@ define void @f34(i64 *%ptr1, i64 *%ptr2) {
 
 ; Test f21 in cases where TBAA is present but doesn't help.
 define void @f35(i64 *%ptr1, i64 *%ptr2) {
-; CHECK: f35:
+; CHECK-LABEL: f35:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %val = load i64 *%ptr1, align 2, !tbaa !1
diff --git a/test/CodeGen/SystemZ/memset-01.ll b/test/CodeGen/SystemZ/memset-01.ll
index 1592318..b272a5b 100644
--- a/test/CodeGen/SystemZ/memset-01.ll
+++ b/test/CodeGen/SystemZ/memset-01.ll
@@ -7,7 +7,7 @@ declare void @llvm.memset.p0i8.i64(i8 *nocapture, i8, i64, i32, i1) nounwind
 
 ; No bytes, i32 version.
 define void @f1(i8 *%dest, i8 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK-NOT: %r3
 ; CHECK: br %r14
@@ -17,7 +17,7 @@ define void @f1(i8 *%dest, i8 %val) {
 
 ; No bytes, i64 version.
 define void @f2(i8 *%dest, i8 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK-NOT: %r3
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ define void @f2(i8 *%dest, i8 %val) {
 
 ; 1 byte, i32 version.
 define void @f3(i8 *%dest, i8 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 %val, i32 1, i32 1, i1 false)
@@ -36,7 +36,7 @@ define void @f3(i8 *%dest, i8 %val) {
 
 ; 1 byte, i64 version.
 define void @f4(i8 *%dest, i8 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 %val, i64 1, i32 1, i1 false)
@@ -45,7 +45,7 @@ define void @f4(i8 *%dest, i8 %val) {
 
 ; 2 bytes, i32 version.
 define void @f5(i8 *%dest, i8 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-DAG: stc %r3, 0(%r2)
 ; CHECK-DAG: stc %r3, 1(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define void @f5(i8 *%dest, i8 %val) {
 
 ; 2 bytes, i64 version.
 define void @f6(i8 *%dest, i8 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-DAG: stc %r3, 0(%r2)
 ; CHECK-DAG: stc %r3, 1(%r2)
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define void @f6(i8 *%dest, i8 %val) {
 
 ; 3 bytes, i32 version.
 define void @f7(i8 *%dest, i8 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: mvc 1(2,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f7(i8 *%dest, i8 %val) {
 
 ; 3 bytes, i64 version.
 define void @f8(i8 *%dest, i8 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: mvc 1(2,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -85,7 +85,7 @@ define void @f8(i8 *%dest, i8 %val) {
 
 ; 257 bytes, i32 version.
 define void @f9(i8 *%dest, i8 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define void @f9(i8 *%dest, i8 %val) {
 
 ; 257 bytes, i64 version.
 define void @f10(i8 *%dest, i8 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define void @f10(i8 *%dest, i8 %val) {
 ; For now expect none, so that the test fails and gets updated when
 ; large copies are implemented.
 define void @f11(i8 *%dest, i8 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 %val, i32 258, i32 1, i1 false)
@@ -116,7 +116,7 @@ define void @f11(i8 *%dest, i8 %val) {
 
 ; 258 bytes, i64 version, with the same comments as above.
 define void @f12(i8 *%dest, i8 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 %val, i64 258, i32 1, i1 false)
diff --git a/test/CodeGen/SystemZ/memset-02.ll b/test/CodeGen/SystemZ/memset-02.ll
index c2c45fb..b74d907 100644
--- a/test/CodeGen/SystemZ/memset-02.ll
+++ b/test/CodeGen/SystemZ/memset-02.ll
@@ -7,7 +7,7 @@ declare void @llvm.memset.p0i8.i64(i8 *nocapture, i8, i64, i32, i1) nounwind
 
 ; No bytes, i32 version.
 define void @f1(i8 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 0, i32 1, i1 false)
@@ -16,7 +16,7 @@ define void @f1(i8 *%dest) {
 
 ; No bytes, i64 version.
 define void @f2(i8 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 0, i32 1, i1 false)
@@ -25,7 +25,7 @@ define void @f2(i8 *%dest) {
 
 ; 1 byte, i32 version.
 define void @f3(i8 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 1, i32 1, i1 false)
@@ -34,7 +34,7 @@ define void @f3(i8 *%dest) {
 
 ; 1 byte, i64 version.
 define void @f4(i8 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 1, i32 1, i1 false)
@@ -43,7 +43,7 @@ define void @f4(i8 *%dest) {
 
 ; 2 bytes, i32 version.
 define void @f5(i8 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvhhi 0(%r2), -32640
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 2, i32 1, i1 false)
@@ -52,7 +52,7 @@ define void @f5(i8 *%dest) {
 
 ; 2 bytes, i64 version.
 define void @f6(i8 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvhhi 0(%r2), -32640
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 2, i32 1, i1 false)
@@ -61,7 +61,7 @@ define void @f6(i8 *%dest) {
 
 ; 3 bytes, i32 version.
 define void @f7(i8 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-DAG: mvhhi 0(%r2), -32640
 ; CHECK-DAG: mvi 2(%r2), 128
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define void @f7(i8 *%dest) {
 
 ; 3 bytes, i64 version.
 define void @f8(i8 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-DAG: mvhhi 0(%r2), -32640
 ; CHECK-DAG: mvi 2(%r2), 128
 ; CHECK: br %r14
@@ -81,7 +81,7 @@ define void @f8(i8 *%dest) {
 
 ; 4 bytes, i32 version.
 define void @f9(i8 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: iilf [[REG:%r[0-5]]], 2155905152
 ; CHECK: st [[REG]], 0(%r2)
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define void @f9(i8 *%dest) {
 
 ; 4 bytes, i64 version.
 define void @f10(i8 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: iilf [[REG:%r[0-5]]], 2155905152
 ; CHECK: st [[REG]], 0(%r2)
 ; CHECK: br %r14
@@ -101,7 +101,7 @@ define void @f10(i8 *%dest) {
 
 ; 5 bytes, i32 version.
 define void @f11(i8 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: mvc 1(4,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -111,7 +111,7 @@ define void @f11(i8 *%dest) {
 
 ; 5 bytes, i64 version.
 define void @f12(i8 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: mvc 1(4,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -121,7 +121,7 @@ define void @f12(i8 *%dest) {
 
 ; 257 bytes, i32 version.
 define void @f13(i8 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -131,7 +131,7 @@ define void @f13(i8 *%dest) {
 
 ; 257 bytes, i64 version.
 define void @f14(i8 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -143,7 +143,7 @@ define void @f14(i8 *%dest) {
 ; For now expect none, so that the test fails and gets updated when
 ; large copies are implemented.
 define void @f15(i8 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 258, i32 1, i1 false)
@@ -152,7 +152,7 @@ define void @f15(i8 *%dest) {
 
 ; 258 bytes, i64 version, with the same comments as above.
 define void @f16(i8 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 258, i32 1, i1 false)
diff --git a/test/CodeGen/SystemZ/memset-03.ll b/test/CodeGen/SystemZ/memset-03.ll
index b18cca4..1d48f1a 100644
--- a/test/CodeGen/SystemZ/memset-03.ll
+++ b/test/CodeGen/SystemZ/memset-03.ll
@@ -7,7 +7,7 @@ declare void @llvm.memset.p0i8.i64(i8 *nocapture, i8, i64, i32, i1) nounwind
 
 ; No bytes, i32 version.
 define void @f1(i8 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 0, i32 1, i1 false)
@@ -16,7 +16,7 @@ define void @f1(i8 *%dest) {
 
 ; No bytes, i64 version.
 define void @f2(i8 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 0, i32 1, i1 false)
@@ -25,7 +25,7 @@ define void @f2(i8 *%dest) {
 
 ; 1 byte, i32 version.
 define void @f3(i8 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 1, i32 1, i1 false)
@@ -34,7 +34,7 @@ define void @f3(i8 *%dest) {
 
 ; 1 byte, i64 version.
 define void @f4(i8 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 1, i32 1, i1 false)
@@ -43,7 +43,7 @@ define void @f4(i8 *%dest) {
 
 ; 2 bytes, i32 version.
 define void @f5(i8 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvhhi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 2, i32 1, i1 false)
@@ -52,7 +52,7 @@ define void @f5(i8 *%dest) {
 
 ; 2 bytes, i64 version.
 define void @f6(i8 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvhhi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 2, i32 1, i1 false)
@@ -61,7 +61,7 @@ define void @f6(i8 *%dest) {
 
 ; 3 bytes, i32 version.
 define void @f7(i8 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-DAG: mvhhi 0(%r2), 0
 ; CHECK-DAG: mvi 2(%r2), 0
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define void @f7(i8 *%dest) {
 
 ; 3 bytes, i64 version.
 define void @f8(i8 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-DAG: mvhhi 0(%r2), 0
 ; CHECK-DAG: mvi 2(%r2), 0
 ; CHECK: br %r14
@@ -81,7 +81,7 @@ define void @f8(i8 *%dest) {
 
 ; 4 bytes, i32 version.
 define void @f9(i8 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 4, i32 1, i1 false)
@@ -90,7 +90,7 @@ define void @f9(i8 *%dest) {
 
 ; 4 bytes, i64 version.
 define void @f10(i8 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 4, i32 1, i1 false)
@@ -99,7 +99,7 @@ define void @f10(i8 *%dest) {
 
 ; 5 bytes, i32 version.
 define void @f11(i8 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-DAG: mvhi 0(%r2), 0
 ; CHECK-DAG: mvi 4(%r2), 0
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define void @f11(i8 *%dest) {
 
 ; 5 bytes, i64 version.
 define void @f12(i8 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-DAG: mvhi 0(%r2), 0
 ; CHECK-DAG: mvi 4(%r2), 0
 ; CHECK: br %r14
@@ -119,7 +119,7 @@ define void @f12(i8 *%dest) {
 
 ; 6 bytes, i32 version.
 define void @f13(i8 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK-DAG: mvhi 0(%r2), 0
 ; CHECK-DAG: mvhhi 4(%r2), 0
 ; CHECK: br %r14
@@ -129,7 +129,7 @@ define void @f13(i8 *%dest) {
 
 ; 6 bytes, i64 version.
 define void @f14(i8 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-DAG: mvhi 0(%r2), 0
 ; CHECK-DAG: mvhhi 4(%r2), 0
 ; CHECK: br %r14
@@ -139,7 +139,7 @@ define void @f14(i8 *%dest) {
 
 ; 7 bytes, i32 version.
 define void @f15(i8 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(6,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -149,7 +149,7 @@ define void @f15(i8 *%dest) {
 
 ; 7 bytes, i64 version.
 define void @f16(i8 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(6,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -159,7 +159,7 @@ define void @f16(i8 *%dest) {
 
 ; 8 bytes, i32 version.
 define void @f17(i8 *%dest) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: mvghi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 8, i32 1, i1 false)
@@ -168,7 +168,7 @@ define void @f17(i8 *%dest) {
 
 ; 8 bytes, i64 version.
 define void @f18(i8 *%dest) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: mvghi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 8, i32 1, i1 false)
@@ -177,7 +177,7 @@ define void @f18(i8 *%dest) {
 
 ; 9 bytes, i32 version.
 define void @f19(i8 *%dest) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvi 8(%r2), 0
 ; CHECK: br %r14
@@ -187,7 +187,7 @@ define void @f19(i8 *%dest) {
 
 ; 9 bytes, i64 version.
 define void @f20(i8 *%dest) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvi 8(%r2), 0
 ; CHECK: br %r14
@@ -197,7 +197,7 @@ define void @f20(i8 *%dest) {
 
 ; 10 bytes, i32 version.
 define void @f21(i8 *%dest) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvhhi 8(%r2), 0
 ; CHECK: br %r14
@@ -207,7 +207,7 @@ define void @f21(i8 *%dest) {
 
 ; 10 bytes, i64 version.
 define void @f22(i8 *%dest) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvhhi 8(%r2), 0
 ; CHECK: br %r14
@@ -217,7 +217,7 @@ define void @f22(i8 *%dest) {
 
 ; 11 bytes, i32 version.
 define void @f23(i8 *%dest) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(10,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -227,7 +227,7 @@ define void @f23(i8 *%dest) {
 
 ; 11 bytes, i64 version.
 define void @f24(i8 *%dest) {
-; CHECK: f24:
+; CHECK-LABEL: f24:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(10,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -237,7 +237,7 @@ define void @f24(i8 *%dest) {
 
 ; 12 bytes, i32 version.
 define void @f25(i8 *%dest) {
-; CHECK: f25:
+; CHECK-LABEL: f25:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvhi 8(%r2), 0
 ; CHECK: br %r14
@@ -247,7 +247,7 @@ define void @f25(i8 *%dest) {
 
 ; 12 bytes, i64 version.
 define void @f26(i8 *%dest) {
-; CHECK: f26:
+; CHECK-LABEL: f26:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvhi 8(%r2), 0
 ; CHECK: br %r14
@@ -257,7 +257,7 @@ define void @f26(i8 *%dest) {
 
 ; 13 bytes, i32 version.
 define void @f27(i8 *%dest) {
-; CHECK: f27:
+; CHECK-LABEL: f27:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(12,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -267,7 +267,7 @@ define void @f27(i8 *%dest) {
 
 ; 13 bytes, i64 version.
 define void @f28(i8 *%dest) {
-; CHECK: f28:
+; CHECK-LABEL: f28:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(12,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -277,7 +277,7 @@ define void @f28(i8 *%dest) {
 
 ; 14 bytes, i32 version.
 define void @f29(i8 *%dest) {
-; CHECK: f29:
+; CHECK-LABEL: f29:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(13,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -287,7 +287,7 @@ define void @f29(i8 *%dest) {
 
 ; 14 bytes, i64 version.
 define void @f30(i8 *%dest) {
-; CHECK: f30:
+; CHECK-LABEL: f30:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(13,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -297,7 +297,7 @@ define void @f30(i8 *%dest) {
 
 ; 15 bytes, i32 version.
 define void @f31(i8 *%dest) {
-; CHECK: f31:
+; CHECK-LABEL: f31:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(14,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -307,7 +307,7 @@ define void @f31(i8 *%dest) {
 
 ; 15 bytes, i64 version.
 define void @f32(i8 *%dest) {
-; CHECK: f32:
+; CHECK-LABEL: f32:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(14,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -317,7 +317,7 @@ define void @f32(i8 *%dest) {
 
 ; 16 bytes, i32 version.
 define void @f33(i8 *%dest) {
-; CHECK: f33:
+; CHECK-LABEL: f33:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvghi 8(%r2), 0
 ; CHECK: br %r14
@@ -327,7 +327,7 @@ define void @f33(i8 *%dest) {
 
 ; 16 bytes, i64 version.
 define void @f34(i8 *%dest) {
-; CHECK: f34:
+; CHECK-LABEL: f34:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvghi 8(%r2), 0
 ; CHECK: br %r14
@@ -337,7 +337,7 @@ define void @f34(i8 *%dest) {
 
 ; 17 bytes, i32 version.
 define void @f35(i8 *%dest) {
-; CHECK: f35:
+; CHECK-LABEL: f35:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(16,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -347,7 +347,7 @@ define void @f35(i8 *%dest) {
 
 ; 17 bytes, i64 version.
 define void @f36(i8 *%dest) {
-; CHECK: f36:
+; CHECK-LABEL: f36:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(16,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -357,7 +357,7 @@ define void @f36(i8 *%dest) {
 
 ; 257 bytes, i32 version.
 define void @f37(i8 *%dest) {
-; CHECK: f37:
+; CHECK-LABEL: f37:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -367,7 +367,7 @@ define void @f37(i8 *%dest) {
 
 ; 257 bytes, i64 version.
 define void @f38(i8 *%dest) {
-; CHECK: f38:
+; CHECK-LABEL: f38:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -379,7 +379,7 @@ define void @f38(i8 *%dest) {
 ; For now expect none, so that the test fails and gets updated when
 ; large copies are implemented.
 define void @f39(i8 *%dest) {
-; CHECK: f39:
+; CHECK-LABEL: f39:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 258, i32 1, i1 false)
@@ -388,7 +388,7 @@ define void @f39(i8 *%dest) {
 
 ; 258 bytes, i64 version, with the same comments as above.
 define void @f40(i8 *%dest) {
-; CHECK: f40:
+; CHECK-LABEL: f40:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 258, i32 1, i1 false)
diff --git a/test/CodeGen/SystemZ/memset-04.ll b/test/CodeGen/SystemZ/memset-04.ll
index 679e21f..9288692 100644
--- a/test/CodeGen/SystemZ/memset-04.ll
+++ b/test/CodeGen/SystemZ/memset-04.ll
@@ -7,7 +7,7 @@ declare void @llvm.memset.p0i8.i64(i8 *nocapture, i8, i64, i32, i1) nounwind
 
 ; No bytes, i32 version.
 define void @f1(i8 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 0, i32 1, i1 false)
@@ -16,7 +16,7 @@ define void @f1(i8 *%dest) {
 
 ; No bytes, i64 version.
 define void @f2(i8 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 0, i32 1, i1 false)
@@ -25,7 +25,7 @@ define void @f2(i8 *%dest) {
 
 ; 1 byte, i32 version.
 define void @f3(i8 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 1, i32 1, i1 false)
@@ -34,7 +34,7 @@ define void @f3(i8 *%dest) {
 
 ; 1 byte, i64 version.
 define void @f4(i8 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 1, i32 1, i1 false)
@@ -43,7 +43,7 @@ define void @f4(i8 *%dest) {
 
 ; 2 bytes, i32 version.
 define void @f5(i8 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvhhi 0(%r2), -1
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 2, i32 1, i1 false)
@@ -52,7 +52,7 @@ define void @f5(i8 *%dest) {
 
 ; 2 bytes, i64 version.
 define void @f6(i8 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvhhi 0(%r2), -1
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 2, i32 1, i1 false)
@@ -61,7 +61,7 @@ define void @f6(i8 *%dest) {
 
 ; 3 bytes, i32 version.
 define void @f7(i8 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-DAG: mvhhi 0(%r2), -1
 ; CHECK-DAG: mvi 2(%r2), 255
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define void @f7(i8 *%dest) {
 
 ; 3 bytes, i64 version.
 define void @f8(i8 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-DAG: mvhhi 0(%r2), -1
 ; CHECK-DAG: mvi 2(%r2), 255
 ; CHECK: br %r14
@@ -81,7 +81,7 @@ define void @f8(i8 *%dest) {
 
 ; 4 bytes, i32 version.
 define void @f9(i8 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mvhi 0(%r2), -1
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 4, i32 1, i1 false)
@@ -90,7 +90,7 @@ define void @f9(i8 *%dest) {
 
 ; 4 bytes, i64 version.
 define void @f10(i8 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mvhi 0(%r2), -1
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 4, i32 1, i1 false)
@@ -99,7 +99,7 @@ define void @f10(i8 *%dest) {
 
 ; 5 bytes, i32 version.
 define void @f11(i8 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-DAG: mvhi 0(%r2), -1
 ; CHECK-DAG: mvi 4(%r2), 255
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define void @f11(i8 *%dest) {
 
 ; 5 bytes, i64 version.
 define void @f12(i8 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-DAG: mvhi 0(%r2), -1
 ; CHECK-DAG: mvi 4(%r2), 255
 ; CHECK: br %r14
@@ -119,7 +119,7 @@ define void @f12(i8 *%dest) {
 
 ; 6 bytes, i32 version.
 define void @f13(i8 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK-DAG: mvhi 0(%r2), -1
 ; CHECK-DAG: mvhhi 4(%r2), -1
 ; CHECK: br %r14
@@ -129,7 +129,7 @@ define void @f13(i8 *%dest) {
 
 ; 6 bytes, i64 version.
 define void @f14(i8 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-DAG: mvhi 0(%r2), -1
 ; CHECK-DAG: mvhhi 4(%r2), -1
 ; CHECK: br %r14
@@ -139,7 +139,7 @@ define void @f14(i8 *%dest) {
 
 ; 7 bytes, i32 version.
 define void @f15(i8 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(6,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -149,7 +149,7 @@ define void @f15(i8 *%dest) {
 
 ; 7 bytes, i64 version.
 define void @f16(i8 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(6,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -159,7 +159,7 @@ define void @f16(i8 *%dest) {
 
 ; 8 bytes, i32 version.
 define void @f17(i8 *%dest) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: mvghi 0(%r2), -1
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 8, i32 1, i1 false)
@@ -168,7 +168,7 @@ define void @f17(i8 *%dest) {
 
 ; 8 bytes, i64 version.
 define void @f18(i8 *%dest) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: mvghi 0(%r2), -1
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 8, i32 1, i1 false)
@@ -177,7 +177,7 @@ define void @f18(i8 *%dest) {
 
 ; 9 bytes, i32 version.
 define void @f19(i8 *%dest) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvi 8(%r2), 255
 ; CHECK: br %r14
@@ -187,7 +187,7 @@ define void @f19(i8 *%dest) {
 
 ; 9 bytes, i64 version.
 define void @f20(i8 *%dest) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvi 8(%r2), 255
 ; CHECK: br %r14
@@ -197,7 +197,7 @@ define void @f20(i8 *%dest) {
 
 ; 10 bytes, i32 version.
 define void @f21(i8 *%dest) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvhhi 8(%r2), -1
 ; CHECK: br %r14
@@ -207,7 +207,7 @@ define void @f21(i8 *%dest) {
 
 ; 10 bytes, i64 version.
 define void @f22(i8 *%dest) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvhhi 8(%r2), -1
 ; CHECK: br %r14
@@ -217,7 +217,7 @@ define void @f22(i8 *%dest) {
 
 ; 11 bytes, i32 version.
 define void @f23(i8 *%dest) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(10,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -227,7 +227,7 @@ define void @f23(i8 *%dest) {
 
 ; 11 bytes, i64 version.
 define void @f24(i8 *%dest) {
-; CHECK: f24:
+; CHECK-LABEL: f24:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(10,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -237,7 +237,7 @@ define void @f24(i8 *%dest) {
 
 ; 12 bytes, i32 version.
 define void @f25(i8 *%dest) {
-; CHECK: f25:
+; CHECK-LABEL: f25:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvhi 8(%r2), -1
 ; CHECK: br %r14
@@ -247,7 +247,7 @@ define void @f25(i8 *%dest) {
 
 ; 12 bytes, i64 version.
 define void @f26(i8 *%dest) {
-; CHECK: f26:
+; CHECK-LABEL: f26:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvhi 8(%r2), -1
 ; CHECK: br %r14
@@ -257,7 +257,7 @@ define void @f26(i8 *%dest) {
 
 ; 13 bytes, i32 version.
 define void @f27(i8 *%dest) {
-; CHECK: f27:
+; CHECK-LABEL: f27:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(12,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -267,7 +267,7 @@ define void @f27(i8 *%dest) {
 
 ; 13 bytes, i64 version.
 define void @f28(i8 *%dest) {
-; CHECK: f28:
+; CHECK-LABEL: f28:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(12,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -277,7 +277,7 @@ define void @f28(i8 *%dest) {
 
 ; 14 bytes, i32 version.
 define void @f29(i8 *%dest) {
-; CHECK: f29:
+; CHECK-LABEL: f29:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(13,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -287,7 +287,7 @@ define void @f29(i8 *%dest) {
 
 ; 14 bytes, i64 version.
 define void @f30(i8 *%dest) {
-; CHECK: f30:
+; CHECK-LABEL: f30:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(13,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -297,7 +297,7 @@ define void @f30(i8 *%dest) {
 
 ; 15 bytes, i32 version.
 define void @f31(i8 *%dest) {
-; CHECK: f31:
+; CHECK-LABEL: f31:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(14,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -307,7 +307,7 @@ define void @f31(i8 *%dest) {
 
 ; 15 bytes, i64 version.
 define void @f32(i8 *%dest) {
-; CHECK: f32:
+; CHECK-LABEL: f32:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(14,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -317,7 +317,7 @@ define void @f32(i8 *%dest) {
 
 ; 16 bytes, i32 version.
 define void @f33(i8 *%dest) {
-; CHECK: f33:
+; CHECK-LABEL: f33:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvghi 8(%r2), -1
 ; CHECK: br %r14
@@ -327,7 +327,7 @@ define void @f33(i8 *%dest) {
 
 ; 16 bytes, i64 version.
 define void @f34(i8 *%dest) {
-; CHECK: f34:
+; CHECK-LABEL: f34:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvghi 8(%r2), -1
 ; CHECK: br %r14
@@ -337,7 +337,7 @@ define void @f34(i8 *%dest) {
 
 ; 17 bytes, i32 version.
 define void @f35(i8 *%dest) {
-; CHECK: f35:
+; CHECK-LABEL: f35:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(16,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -347,7 +347,7 @@ define void @f35(i8 *%dest) {
 
 ; 17 bytes, i64 version.
 define void @f36(i8 *%dest) {
-; CHECK: f36:
+; CHECK-LABEL: f36:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(16,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -357,7 +357,7 @@ define void @f36(i8 *%dest) {
 
 ; 257 bytes, i32 version.
 define void @f37(i8 *%dest) {
-; CHECK: f37:
+; CHECK-LABEL: f37:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -367,7 +367,7 @@ define void @f37(i8 *%dest) {
 
 ; 257 bytes, i64 version.
 define void @f38(i8 *%dest) {
-; CHECK: f38:
+; CHECK-LABEL: f38:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -379,7 +379,7 @@ define void @f38(i8 *%dest) {
 ; For now expect none, so that the test fails and gets updated when
 ; large copies are implemented.
 define void @f39(i8 *%dest) {
-; CHECK: f39:
+; CHECK-LABEL: f39:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 258, i32 1, i1 false)
@@ -388,7 +388,7 @@ define void @f39(i8 *%dest) {
 
 ; 258 bytes, i64 version, with the same comments as above.
 define void @f40(i8 *%dest) {
-; CHECK: f40:
+; CHECK-LABEL: f40:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 258, i32 1, i1 false)
diff --git a/test/CodeGen/SystemZ/or-01.ll b/test/CodeGen/SystemZ/or-01.ll
index ab869c7..ee0a392 100644
--- a/test/CodeGen/SystemZ/or-01.ll
+++ b/test/CodeGen/SystemZ/or-01.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Check OR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: or %r2, %r3
 ; CHECK: br %r14
   %or = or i32 %a, %b
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the O range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: o %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +25,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned O range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: o %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -36,7 +36,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use OY instead of O.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -47,7 +47,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned OY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oy %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -59,7 +59,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: o %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned OY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oy %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -82,7 +82,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the OY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -94,7 +94,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: o %r2, 0(%r3)
 ; CHECK: br %r14
@@ -106,7 +106,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that O allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: o %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -119,7 +119,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that OY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: oy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -132,7 +132,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
 
 ; Check that ORs of spilled values can use O rather than OR.
 define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: o %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/or-02.ll b/test/CodeGen/SystemZ/or-02.ll
index 377a3e6..267be20 100644
--- a/test/CodeGen/SystemZ/or-02.ll
+++ b/test/CodeGen/SystemZ/or-02.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful OILL value.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: oill %r2, 1
 ; CHECK: br %r14
   %or = or i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the OILL range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: oill %r2, 65535
 ; CHECK: br %r14
   %or = or i32 %a, 65535
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; Check the lowest useful OILH range, which is the next value up.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oilh %r2, 1
 ; CHECK: br %r14
   %or = or i32 %a, 65536
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Check the lowest useful OILF value, which is the next value up again.
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilf %r2, 65537
 ; CHECK: br %r14
   %or = or i32 %a, 65537
@@ -40,7 +40,7 @@ define i32 @f4(i32 %a) {
 
 ; Check the high end of the OILH range.
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilh %r2, 65535
 ; CHECK: br %r14
   %or = or i32 %a, -65536
@@ -49,7 +49,7 @@ define i32 @f5(i32 %a) {
 
 ; Check the next value up, which must use OILF instead.
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilf %r2, 4294901761
 ; CHECK: br %r14
   %or = or i32 %a, -65535
@@ -58,7 +58,7 @@ define i32 @f6(i32 %a) {
 
 ; Check the highest useful OILF value.
 define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oilf %r2, 4294967294
 ; CHECK: br %r14
   %or = or i32 %a, -2
diff --git a/test/CodeGen/SystemZ/or-03.ll b/test/CodeGen/SystemZ/or-03.ll
index cf85b0a..3e37367 100644
--- a/test/CodeGen/SystemZ/or-03.ll
+++ b/test/CodeGen/SystemZ/or-03.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check OGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ogr %r2, %r3
 ; CHECK: br %r14
   %or = or i64 %a, %b
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check OG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: og %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -25,7 +25,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned OG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: og %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: og %r2, 0(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned OG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: og %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -60,7 +60,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the OG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: og %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: og %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that OG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: og %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that ORs of spilled values can use OG rather than OGR.
 define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: og %r2, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/or-04.ll b/test/CodeGen/SystemZ/or-04.ll
index a827842..87a30d5 100644
--- a/test/CodeGen/SystemZ/or-04.ll
+++ b/test/CodeGen/SystemZ/or-04.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful OILL value.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: oill %r2, 1
 ; CHECK: br %r14
   %or = or i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the OILL range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: oill %r2, 65535
 ; CHECK: br %r14
   %or = or i64 %a, 65535
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; Check the lowest useful OILH value, which is the next value up.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oilh %r2, 1
 ; CHECK: br %r14
   %or = or i64 %a, 65536
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check the lowest useful OILF value, which is the next value up again.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilf %r2, 4294901759
 ; CHECK: br %r14
   %or = or i64 %a, 4294901759
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a) {
 
 ; Check the high end of the OILH range.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilh %r2, 65535
 ; CHECK: br %r14
   %or = or i64 %a, 4294901760
@@ -49,7 +49,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the high end of the OILF range.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilf %r2, 4294967295
 ; CHECK: br %r14
   %or = or i64 %a, 4294967295
@@ -58,7 +58,7 @@ define i64 @f6(i64 %a) {
 
 ; Check the lowest useful OIHL value, which is the next value up.
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oihl %r2, 1
 ; CHECK: br %r14
   %or = or i64 %a, 4294967296
@@ -67,7 +67,7 @@ define i64 @f7(i64 %a) {
 
 ; Check the next value up again, which must use two ORs.
 define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oihl %r2, 1
 ; CHECK: oill %r2, 1
 ; CHECK: br %r14
@@ -77,7 +77,7 @@ define i64 @f8(i64 %a) {
 
 ; Check the high end of the OILL range.
 define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: oihl %r2, 1
 ; CHECK: oill %r2, 65535
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define i64 @f9(i64 %a) {
 
 ; Check the next value up, which must use OILH
 define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: oihl %r2, 1
 ; CHECK: oilh %r2, 1
 ; CHECK: br %r14
@@ -97,7 +97,7 @@ define i64 @f10(i64 %a) {
 
 ; Check the next value up again, which must use OILF
 define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: oihl %r2, 1
 ; CHECK: oilf %r2, 65537
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define i64 @f11(i64 %a) {
 
 ; Check the high end of the OIHL range.
 define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: oihl %r2, 65535
 ; CHECK: br %r14
   %or = or i64 %a, 281470681743360
@@ -117,7 +117,7 @@ define i64 @f12(i64 %a) {
 ; Check a combination of the high end of the OIHL range and the high end
 ; of the OILF range.
 define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: oihl %r2, 65535
 ; CHECK: oilf %r2, 4294967295
 ; CHECK: br %r14
@@ -127,7 +127,7 @@ define i64 @f13(i64 %a) {
 
 ; Check the lowest useful OIHH value.
 define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: oihh %r2, 1
 ; CHECK: br %r14
   %or = or i64 %a, 281474976710656
@@ -136,7 +136,7 @@ define i64 @f14(i64 %a) {
 
 ; Check the next value up, which needs two ORs.
 define i64 @f15(i64 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: oihh %r2, 1
 ; CHECK: oill %r2, 1
 ; CHECK: br %r14
@@ -146,7 +146,7 @@ define i64 @f15(i64 %a) {
 
 ; Check the lowest useful OIHF value.
 define i64 @f16(i64 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: oihf %r2, 65537
 ; CHECK: br %r14
   %or = or i64 %a, 281479271677952
@@ -155,7 +155,7 @@ define i64 @f16(i64 %a) {
 
 ; Check the high end of the OIHH range.
 define i64 @f17(i64 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: oihh %r2, 65535
 ; CHECK: br %r14
   %or = or i64 %a, 18446462598732840960
@@ -164,7 +164,7 @@ define i64 @f17(i64 %a) {
 
 ; Check the high end of the OIHF range.
 define i64 @f18(i64 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: oihf %r2, 4294967295
 ; CHECK: br %r14
   %or = or i64 %a, -4294967296
@@ -173,7 +173,7 @@ define i64 @f18(i64 %a) {
 
 ; Check the highest useful OR value.
 define i64 @f19(i64 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: oihf %r2, 4294967295
 ; CHECK: oilf %r2, 4294967294
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/or-05.ll b/test/CodeGen/SystemZ/or-05.ll
index 9b6c10d..d905891 100644
--- a/test/CodeGen/SystemZ/or-05.ll
+++ b/test/CodeGen/SystemZ/or-05.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful constant, expressed as a signed integer.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: oi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a signed integer.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -26,7 +26,7 @@ define void @f2(i8 *%ptr) {
 
 ; Check the lowest useful constant, expressed as an unsigned integer.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -37,7 +37,7 @@ define void @f3(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a unsigned integer.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -48,7 +48,7 @@ define void @f4(i8 *%ptr) {
 
 ; Check the high end of the OI range.
 define void @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oi 4095(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -60,7 +60,7 @@ define void @f5(i8 *%src) {
 
 ; Check the next byte up, which should use OIY instead of OI.
 define void @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oiy 4096(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -72,7 +72,7 @@ define void @f6(i8 *%src) {
 
 ; Check the high end of the OIY range.
 define void @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oiy 524287(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -85,7 +85,7 @@ define void @f7(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, 524288
 ; CHECK: oi 0(%r2), 127
 ; CHECK: br %r14
@@ -98,7 +98,7 @@ define void @f8(i8 *%src) {
 
 ; Check the high end of the negative OIY range.
 define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: oiy -1(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -110,7 +110,7 @@ define void @f9(i8 *%src) {
 
 ; Check the low end of the OIY range.
 define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: oiy -524288(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -123,7 +123,7 @@ define void @f10(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, -524289
 ; CHECK: oi 0(%r2), 127
 ; CHECK: br %r14
@@ -136,7 +136,7 @@ define void @f11(i8 *%src) {
 
 ; Check that OI does not allow an index
 define void @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agr %r2, %r3
 ; CHECK: oi 4095(%r2), 127
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define void @f12(i64 %src, i64 %index) {
 
 ; Check that OIY does not allow an index
 define void @f13(i64 %src, i64 %index) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agr %r2, %r3
 ; CHECK: oiy 4096(%r2), 127
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/or-06.ll b/test/CodeGen/SystemZ/or-06.ll
index a24a18a..0a865d3 100644
--- a/test/CodeGen/SystemZ/or-06.ll
+++ b/test/CodeGen/SystemZ/or-06.ll
@@ -5,7 +5,7 @@
 
 ; Zero extension to 32 bits, negative constant.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -18,7 +18,7 @@ define void @f1(i8 *%ptr) {
 
 ; Zero extension to 64 bits, negative constant.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -31,7 +31,7 @@ define void @f2(i8 *%ptr) {
 
 ; Zero extension to 32 bits, positive constant.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define void @f3(i8 *%ptr) {
 
 ; Zero extension to 64 bits, positive constant.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -57,7 +57,7 @@ define void @f4(i8 *%ptr) {
 
 ; Sign extension to 32 bits, negative constant.
 define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -70,7 +70,7 @@ define void @f5(i8 *%ptr) {
 
 ; Sign extension to 64 bits, negative constant.
 define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -83,7 +83,7 @@ define void @f6(i8 *%ptr) {
 
 ; Sign extension to 32 bits, positive constant.
 define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -96,7 +96,7 @@ define void @f7(i8 *%ptr) {
 
 ; Sign extension to 64 bits, positive constant.
 define void @f8(i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/risbg-01.ll b/test/CodeGen/SystemZ/risbg-01.ll
index 178fa4f..f5aeaf1 100644
--- a/test/CodeGen/SystemZ/risbg-01.ll
+++ b/test/CodeGen/SystemZ/risbg-01.ll
@@ -4,7 +4,7 @@
 
 ; Test an extraction of bit 0 from a right-shifted value.
 define i32 @f1(i32 %foo) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: risbg %r2, %r2, 63, 191, 54
 ; CHECK: br %r14
   %shr = lshr i32 %foo, 10
@@ -14,7 +14,7 @@ define i32 @f1(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f2(i64 %foo) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: risbg %r2, %r2, 63, 191, 54
 ; CHECK: br %r14
   %shr = lshr i64 %foo, 10
@@ -24,7 +24,7 @@ define i64 @f2(i64 %foo) {
 
 ; Test an extraction of other bits from a right-shifted value.
 define i32 @f3(i32 %foo) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: risbg %r2, %r2, 60, 189, 42
 ; CHECK: br %r14
   %shr = lshr i32 %foo, 22
@@ -34,7 +34,7 @@ define i32 @f3(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f4(i64 %foo) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: risbg %r2, %r2, 60, 189, 42
 ; CHECK: br %r14
   %shr = lshr i64 %foo, 22
@@ -45,7 +45,7 @@ define i64 @f4(i64 %foo) {
 ; Test an extraction of most bits from a right-shifted value.
 ; The range should be reduced to exclude the zeroed high bits.
 define i32 @f5(i32 %foo) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: risbg %r2, %r2, 34, 188, 62
 ; CHECK: br %r14
   %shr = lshr i32 %foo, 2
@@ -55,7 +55,7 @@ define i32 @f5(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f6(i64 %foo) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: risbg %r2, %r2, 2, 188, 62
 ; CHECK: br %r14
   %shr = lshr i64 %foo, 2
@@ -66,7 +66,7 @@ define i64 @f6(i64 %foo) {
 ; Try the next value up (mask ....1111001).  The mask itself is suitable
 ; for RISBG, but the shift is still needed.
 define i32 @f7(i32 %foo) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: srl %r2, 2
 ; CHECK: risbg %r2, %r2, 63, 188, 0
 ; CHECK: br %r14
@@ -77,7 +77,7 @@ define i32 @f7(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f8(i64 %foo) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: srlg [[REG:%r[0-5]]], %r2, 2
 ; CHECK: risbg %r2, [[REG]], 63, 188, 0
 ; CHECK: br %r14
@@ -89,7 +89,7 @@ define i64 @f8(i64 %foo) {
 ; Test an extraction of bits from a left-shifted value.  The range should
 ; be reduced to exclude the zeroed low bits.
 define i32 @f9(i32 %foo) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: risbg %r2, %r2, 56, 189, 2
 ; CHECK: br %r14
   %shr = shl i32 %foo, 2
@@ -99,7 +99,7 @@ define i32 @f9(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f10(i64 %foo) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: risbg %r2, %r2, 56, 189, 2
 ; CHECK: br %r14
   %shr = shl i64 %foo, 2
@@ -110,7 +110,7 @@ define i64 @f10(i64 %foo) {
 ; Try a wrap-around mask (mask ....111100001111).  The mask itself is suitable
 ; for RISBG, but the shift is still needed.
 define i32 @f11(i32 %foo) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sll %r2, 2
 ; CHECK: risbg %r2, %r2, 60, 183, 0
 ; CHECK: br %r14
@@ -121,7 +121,7 @@ define i32 @f11(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f12(i64 %foo) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: sllg [[REG:%r[0-5]]], %r2, 2
 ; CHECK: risbg %r2, [[REG]], 60, 183, 0
 ; CHECK: br %r14
@@ -134,7 +134,7 @@ define i64 @f12(i64 %foo) {
 ; This is equivalent to the lshr case, because the bits from the
 ; shl are not used.
 define i32 @f13(i32 %foo) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: risbg %r2, %r2, 56, 188, 46
 ; CHECK: br %r14
   %parta = shl i32 %foo, 14
@@ -146,7 +146,7 @@ define i32 @f13(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f14(i64 %foo) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: risbg %r2, %r2, 56, 188, 14
 ; CHECK: br %r14
   %parta = shl i64 %foo, 14
@@ -158,7 +158,7 @@ define i64 @f14(i64 %foo) {
 
 ; Try a case in which only the bits from the shl are used.
 define i32 @f15(i32 %foo) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: risbg %r2, %r2, 47, 177, 14
 ; CHECK: br %r14
   %parta = shl i32 %foo, 14
@@ -170,7 +170,7 @@ define i32 @f15(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f16(i64 %foo) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: risbg %r2, %r2, 47, 177, 14
 ; CHECK: br %r14
   %parta = shl i64 %foo, 14
@@ -184,7 +184,7 @@ define i64 @f16(i64 %foo) {
 ; This needs a separate shift (although RISBLG would be better
 ; if supported).
 define i32 @f17(i32 %foo) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: rll [[REG:%r[0-5]]], %r2, 4
 ; CHECK: risbg %r2, [[REG]], 57, 190, 0
 ; CHECK: br %r14
@@ -197,7 +197,7 @@ define i32 @f17(i32 %foo) {
 
 ; ...and for i64, where RISBG should do the rotate too.
 define i64 @f18(i64 %foo) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: risbg %r2, %r2, 57, 190, 4
 ; CHECK: br %r14
   %parta = shl i64 %foo, 4
@@ -210,7 +210,7 @@ define i64 @f18(i64 %foo) {
 ; Test an arithmetic shift right in which some of the sign bits are kept.
 ; The SRA is still needed.
 define i32 @f19(i32 %foo) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: sra %r2, 28
 ; CHECK: risbg %r2, %r2, 59, 190, 0
 ; CHECK: br %r14
@@ -221,7 +221,7 @@ define i32 @f19(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f20(i64 %foo) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK: srag [[REG:%r[0-5]]], %r2, 60
 ; CHECK: risbg %r2, [[REG]], 59, 190, 0
 ; CHECK: br %r14
@@ -234,7 +234,7 @@ define i64 @f20(i64 %foo) {
 ; Introduce a second use of %shr so that the ashr doesn't decompose to
 ; an lshr.
 define i32 @f21(i32 %foo, i32 *%dest) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK: risbg %r2, %r2, 60, 190, 36
 ; CHECK: br %r14
   %shr = ashr i32 %foo, 28
@@ -245,7 +245,7 @@ define i32 @f21(i32 %foo, i32 *%dest) {
 
 ; ...and again with i64.
 define i64 @f22(i64 %foo, i64 *%dest) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK: risbg %r2, %r2, 60, 190, 4
 ; CHECK: br %r14
   %shr = ashr i64 %foo, 60
@@ -257,7 +257,7 @@ define i64 @f22(i64 %foo, i64 *%dest) {
 ; Check that we use RISBG for shifted values even if the AND is a
 ; natural zero extension.
 define i64 @f23(i64 %foo) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
 ; CHECK: risbg %r2, %r2, 56, 191, 62
 ; CHECK: br %r14
   %shr = lshr i64 %foo, 2
diff --git a/test/CodeGen/SystemZ/shift-01.ll b/test/CodeGen/SystemZ/shift-01.ll
index e5a459a..5dab36b 100644
--- a/test/CodeGen/SystemZ/shift-01.ll
+++ b/test/CodeGen/SystemZ/shift-01.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SLL range.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sll %r2, 1
 ; CHECK: br %r14
   %shift = shl i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the defined SLL range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sll %r2, 31
 ; CHECK: br %r14
   %shift = shl i32 %a, 31
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: sll %r2, 32
 ; CHECK: br %r14
   %shift = shl i32 %a, 32
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Make sure that we don't generate negative shift amounts.
 define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: sll %r2, -1{{.*}}
 ; CHECK: br %r14
   %sub = sub i32 %amt, 1
@@ -41,7 +41,7 @@ define i32 @f4(i32 %a, i32 %amt) {
 
 ; Check variable shifts.
 define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sll %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = shl i32 %a, %amt
@@ -50,7 +50,7 @@ define i32 @f5(i32 %a, i32 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i32 @f6(i32 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sll %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -60,7 +60,7 @@ define i32 @f6(i32 %a, i32 %amt) {
 
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sll %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -72,7 +72,7 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sll %r2, 4095(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 4095
@@ -82,7 +82,7 @@ define i32 @f8(i32 %a, i32 %amt) {
 
 ; Check the next value up.  Again, we could mask the amount instead.
 define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ahi %r3, 4096
 ; CHECK: sll %r2, 0(%r3)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i32 @f9(i32 %a, i32 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f10(i32 %a, i32 %b, i32 %c) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ar {{%r3, %r4|%r4, %r3}}
 ; CHECK: sll %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f11(i32 %a, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: sll %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-02.ll b/test/CodeGen/SystemZ/shift-02.ll
index 38093a8..27e73cd 100644
--- a/test/CodeGen/SystemZ/shift-02.ll
+++ b/test/CodeGen/SystemZ/shift-02.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SRL range.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: srl %r2, 1
 ; CHECK: br %r14
   %shift = lshr i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the defined SRL range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: srl %r2, 31
 ; CHECK: br %r14
   %shift = lshr i32 %a, 31
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: srl %r2, 32
 ; CHECK: br %r14
   %shift = lshr i32 %a, 32
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Make sure that we don't generate negative shift amounts.
 define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: srl %r2, -1{{.*}}
 ; CHECK: br %r14
   %sub = sub i32 %amt, 1
@@ -41,7 +41,7 @@ define i32 @f4(i32 %a, i32 %amt) {
 
 ; Check variable shifts.
 define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: srl %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = lshr i32 %a, %amt
@@ -50,7 +50,7 @@ define i32 @f5(i32 %a, i32 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i32 @f6(i32 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: srl %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -60,7 +60,7 @@ define i32 @f6(i32 %a, i32 %amt) {
 
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: srl %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -72,7 +72,7 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: srl %r2, 4095(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 4095
@@ -82,7 +82,7 @@ define i32 @f8(i32 %a, i32 %amt) {
 
 ; Check the next value up.  Again, we could mask the amount instead.
 define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ahi %r3, 4096
 ; CHECK: srl %r2, 0(%r3)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i32 @f9(i32 %a, i32 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f10(i32 %a, i32 %b, i32 %c) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ar {{%r3, %r4|%r4, %r3}}
 ; CHECK: srl %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f11(i32 %a, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: srl %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-03.ll b/test/CodeGen/SystemZ/shift-03.ll
index ca510f3..c45ae48 100644
--- a/test/CodeGen/SystemZ/shift-03.ll
+++ b/test/CodeGen/SystemZ/shift-03.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SRA range.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sra %r2, 1
 ; CHECK: br %r14
   %shift = ashr i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the defined SRA range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sra %r2, 31
 ; CHECK: br %r14
   %shift = ashr i32 %a, 31
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: sra %r2, 32
 ; CHECK: br %r14
   %shift = ashr i32 %a, 32
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Make sure that we don't generate negative shift amounts.
 define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: sra %r2, -1{{.*}}
 ; CHECK: br %r14
   %sub = sub i32 %amt, 1
@@ -41,7 +41,7 @@ define i32 @f4(i32 %a, i32 %amt) {
 
 ; Check variable shifts.
 define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sra %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = ashr i32 %a, %amt
@@ -50,7 +50,7 @@ define i32 @f5(i32 %a, i32 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i32 @f6(i32 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sra %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -60,7 +60,7 @@ define i32 @f6(i32 %a, i32 %amt) {
 
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sra %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -72,7 +72,7 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sra %r2, 4095(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 4095
@@ -82,7 +82,7 @@ define i32 @f8(i32 %a, i32 %amt) {
 
 ; Check the next value up.  Again, we could mask the amount instead.
 define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ahi %r3, 4096
 ; CHECK: sra %r2, 0(%r3)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i32 @f9(i32 %a, i32 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f10(i32 %a, i32 %b, i32 %c) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ar {{%r3, %r4|%r4, %r3}}
 ; CHECK: sra %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f11(i32 %a, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: sra %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-04.ll b/test/CodeGen/SystemZ/shift-04.ll
index 0146a86..04b39d0 100644
--- a/test/CodeGen/SystemZ/shift-04.ll
+++ b/test/CodeGen/SystemZ/shift-04.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the RLL range.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: rll %r2, %r2, 1
 ; CHECK: br %r14
   %parta = shl i32 %a, 1
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the defined RLL range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: rll %r2, %r2, 31
 ; CHECK: br %r14
   %parta = shl i32 %a, 31
@@ -26,7 +26,7 @@ define i32 @f2(i32 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: rll
 ; CHECK: br %r14
   %parta = shl i32 %a, 32
@@ -37,7 +37,7 @@ define i32 @f3(i32 %a) {
 
 ; Check variable shifts.
 define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: rll %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %amtb = sub i32 32, %amt
@@ -49,7 +49,7 @@ define i32 @f4(i32 %a, i32 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: rll %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -62,7 +62,7 @@ define i32 @f5(i32 %a, i32 %amt) {
 
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f6(i32 %a, i64 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: rll %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -76,7 +76,7 @@ define i32 @f6(i32 %a, i64 %amt) {
 
 ; ...and again with a different truncation representation.
 define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: rll %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -92,7 +92,7 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: rll %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 524287
@@ -106,7 +106,7 @@ define i32 @f8(i32 %a, i32 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: afi %r3, 524288
 ; CHECK: rll %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -120,7 +120,7 @@ define i32 @f9(i32 %a, i32 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i32 @f10(i32 %a, i32 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: rll %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %suba = sub i32 %amt, 1
@@ -134,7 +134,7 @@ define i32 @f10(i32 %a, i32 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i32 @f11(i32 %a, i32 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: rll %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %suba = sub i32 %amt, 524288
@@ -148,7 +148,7 @@ define i32 @f11(i32 %a, i32 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i32 @f12(i32 %a, i32 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: afi %r3, -524289
 ; CHECK: rll %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -162,7 +162,7 @@ define i32 @f12(i32 %a, i32 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f13(i32 %a, i32 %b, i32 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: ar {{%r3, %r4|%r4, %r3}}
 ; CHECK: rll %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -176,7 +176,7 @@ define i32 @f13(i32 %a, i32 %b, i32 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f14(i32 %a, i32 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: rll %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-05.ll b/test/CodeGen/SystemZ/shift-05.ll
index 8c0ca93..833b2fb 100644
--- a/test/CodeGen/SystemZ/shift-05.ll
+++ b/test/CodeGen/SystemZ/shift-05.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SLLG range.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg %r2, %r2, 1
 ; CHECK: br %r14
   %shift = shl i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the defined SLLG range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg %r2, %r2, 63
 ; CHECK: br %r14
   %shift = shl i64 %a, 63
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: sllg
 ; CHECK: br %r14
   %shift = shl i64 %a, 64
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = shl i64 %a, %amt
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a, i64 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -50,7 +50,7 @@ define i64 @f5(i64 %a, i64 %amt) {
 
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -61,7 +61,7 @@ define i64 @f6(i64 %a, i32 %amt) {
 
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -73,7 +73,7 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 524287
@@ -84,7 +84,7 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: a{{g?}}fi %r3, 524288
 ; CHECK: sllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f9(i64 %a, i64 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: sllg %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 1
@@ -106,7 +106,7 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sllg %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 524288
@@ -117,7 +117,7 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: a{{g?}}fi %r3, -524289
 ; CHECK: sllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -128,7 +128,7 @@ define i64 @f12(i64 %a, i64 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
 ; CHECK: sllg %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -139,7 +139,7 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: sllg %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-06.ll b/test/CodeGen/SystemZ/shift-06.ll
index 5f600b4..74cae12 100644
--- a/test/CodeGen/SystemZ/shift-06.ll
+++ b/test/CodeGen/SystemZ/shift-06.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SRLG range.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK: br %r14
   %shift = lshr i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the defined SRLG range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: srlg %r2, %r2, 63
 ; CHECK: br %r14
   %shift = lshr i64 %a, 63
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: srlg
 ; CHECK: br %r14
   %shift = lshr i64 %a, 64
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: srlg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = lshr i64 %a, %amt
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a, i64 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: srlg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -50,7 +50,7 @@ define i64 @f5(i64 %a, i64 %amt) {
 
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: srlg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -61,7 +61,7 @@ define i64 @f6(i64 %a, i32 %amt) {
 
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: srlg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -73,7 +73,7 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: srlg %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 524287
@@ -84,7 +84,7 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: a{{g?}}fi %r3, 524288
 ; CHECK: srlg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f9(i64 %a, i64 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: srlg %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 1
@@ -106,7 +106,7 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: srlg %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 524288
@@ -117,7 +117,7 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: a{{g?}}fi %r3, -524289
 ; CHECK: srlg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -128,7 +128,7 @@ define i64 @f12(i64 %a, i64 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
 ; CHECK: srlg %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -139,7 +139,7 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: srlg %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-07.ll b/test/CodeGen/SystemZ/shift-07.ll
index ef583e8..712849d 100644
--- a/test/CodeGen/SystemZ/shift-07.ll
+++ b/test/CodeGen/SystemZ/shift-07.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SRAG range.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: srag %r2, %r2, 1
 ; CHECK: br %r14
   %shift = ashr i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the defined SRAG range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: srag %r2, %r2, 63
 ; CHECK: br %r14
   %shift = ashr i64 %a, 63
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: srag
 ; CHECK: br %r14
   %shift = ashr i64 %a, 64
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: srag %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = ashr i64 %a, %amt
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a, i64 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: srag %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -50,7 +50,7 @@ define i64 @f5(i64 %a, i64 %amt) {
 
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: srag %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -61,7 +61,7 @@ define i64 @f6(i64 %a, i32 %amt) {
 
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: srag %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -73,7 +73,7 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: srag %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 524287
@@ -84,7 +84,7 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: a{{g?}}fi %r3, 524288
 ; CHECK: srag %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f9(i64 %a, i64 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: srag %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 1
@@ -106,7 +106,7 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: srag %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 524288
@@ -117,7 +117,7 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: a{{g?}}fi %r3, -524289
 ; CHECK: srag %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -128,7 +128,7 @@ define i64 @f12(i64 %a, i64 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
 ; CHECK: srag %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -139,7 +139,7 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: srag %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-08.ll b/test/CodeGen/SystemZ/shift-08.ll
index 0688a06..47283b5 100644
--- a/test/CodeGen/SystemZ/shift-08.ll
+++ b/test/CodeGen/SystemZ/shift-08.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the RLLG range.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: rllg %r2, %r2, 1
 ; CHECK: br %r14
   %parta = shl i64 %a, 1
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the defined RLLG range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: rllg %r2, %r2, 63
 ; CHECK: br %r14
   %parta = shl i64 %a, 63
@@ -26,7 +26,7 @@ define i64 @f2(i64 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: rllg
 ; CHECK: br %r14
   %parta = shl i64 %a, 64
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a) {
 
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: rllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %amtb = sub i64 64, %amt
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: rllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -62,7 +62,7 @@ define i64 @f5(i64 %a, i64 %amt) {
 
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: rllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -77,7 +77,7 @@ define i64 @f6(i64 %a, i32 %amt) {
 
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: rllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -93,7 +93,7 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: rllg %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 524287
@@ -107,7 +107,7 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: a{{g?}}fi %r3, 524288
 ; CHECK: rllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -121,7 +121,7 @@ define i64 @f9(i64 %a, i64 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: rllg %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %suba = sub i64 %amt, 1
@@ -135,7 +135,7 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: rllg %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %suba = sub i64 %amt, 524288
@@ -149,7 +149,7 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: a{{g?}}fi %r3, -524289
 ; CHECK: rllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -163,7 +163,7 @@ define i64 @f12(i64 %a, i64 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
 ; CHECK: rllg %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -177,7 +177,7 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: rllg %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/spill-01.ll b/test/CodeGen/SystemZ/spill-01.ll
index d48e982..9de89d6 100644
--- a/test/CodeGen/SystemZ/spill-01.ll
+++ b/test/CodeGen/SystemZ/spill-01.ll
@@ -28,7 +28,7 @@ declare void @foo()
 
 ; This function shouldn't spill anything
 define void @f1(i32 *%ptr0) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg
 ; CHECK: aghi %r15, -160
 ; CHECK-NOT: %r15
@@ -67,7 +67,7 @@ define void @f1(i32 *%ptr0) {
 ; Test a case where at least one i32 load and at least one i32 store
 ; need spills.
 define void @f2(i32 *%ptr0) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvc [[OFFSET1:16[04]]](4,%r15), [[OFFSET2:[0-9]+]]({{%r[0-9]+}})
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mvc [[OFFSET2]](4,{{%r[0-9]+}}), [[OFFSET1]](%r15)
@@ -109,7 +109,7 @@ define void @f2(i32 *%ptr0) {
 ; Test a case where at least one i64 load and at least one i64 store
 ; need spills.
 define void @f3(i64 *%ptr0) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvc 160(8,%r15), [[OFFSET:[0-9]+]]({{%r[0-9]+}})
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mvc [[OFFSET]](8,{{%r[0-9]+}}), 160(%r15)
@@ -154,7 +154,7 @@ define void @f3(i64 *%ptr0) {
 ; (and are at the time of writing), but it would really be better to use
 ; MVC for all 10.
 define void @f4(float *%ptr0) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvc [[OFFSET1:16[04]]](4,%r15), [[OFFSET2:[0-9]+]]({{%r[0-9]+}})
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mvc [[OFFSET2]](4,{{%r[0-9]+}}), [[OFFSET1]](%r15)
@@ -198,7 +198,7 @@ define void @f4(float *%ptr0) {
 
 ; Similarly for f64.
 define void @f5(double *%ptr0) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvc 160(8,%r15), [[OFFSET:[0-9]+]]({{%r[0-9]+}})
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mvc [[OFFSET]](8,{{%r[0-9]+}}), 160(%r15)
@@ -242,7 +242,7 @@ define void @f5(double *%ptr0) {
 
 ; Repeat f2 with atomic accesses.  We shouldn't use MVC here.
 define void @f6(i32 *%ptr0) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %ptr1 = getelementptr i32 *%ptr0, i64 2
@@ -281,7 +281,7 @@ define void @f6(i32 *%ptr0) {
 
 ; ...likewise volatile accesses.
 define void @f7(i32 *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %ptr1 = getelementptr i32 *%ptr0, i64 2
@@ -320,7 +320,7 @@ define void @f7(i32 *%ptr0) {
 
 ; Check that LRL and STRL are not converted.
 define void @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %val0 = load i32 *@g0
@@ -352,7 +352,7 @@ define void @f8() {
 
 ; Likewise LGRL and STGRL.
 define void @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %val0 = load i64 *@h0
@@ -388,7 +388,7 @@ define void @f9() {
 ; [FI0, FI1] -> [FI1, FI2], but applied it in the form FI0 -> FI1 -> FI2,
 ; so that both operands ended up being the same.
 define void @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lgrl [[REG:%r[0-9]+]], h9
 ; CHECK: stg [[REG]], [[VAL9:[0-9]+]](%r15)
 ; CHECK: brasl %r14, foo@PLT
@@ -459,7 +459,7 @@ skip:
 
 ; This used to generate a no-op MVC.  It is very sensitive to spill heuristics.
 define void @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: mvc [[OFFSET:[0-9]+]](8,%r15), [[OFFSET]](%r15)
 ; CHECK: br %r14
 entry:
diff --git a/test/CodeGen/SystemZ/tls-01.ll b/test/CodeGen/SystemZ/tls-01.ll
index 49037ad..16bc8f6 100644
--- a/test/CodeGen/SystemZ/tls-01.ll
+++ b/test/CodeGen/SystemZ/tls-01.ll
@@ -11,7 +11,7 @@ define i32 *@foo() {
 ; CHECK-CP: .LCP{{.*}}:
 ; CHECK-CP: .quad x@NTPOFF
 ;
-; CHECK-MAIN: foo:
+; CHECK-MAIN-LABEL: foo:
 ; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0
 ; CHECK-MAIN: sllg %r2, [[HIGH]], 32
 ; CHECK-MAIN: ear %r2, %a1
diff --git a/test/CodeGen/SystemZ/unaligned-01.ll b/test/CodeGen/SystemZ/unaligned-01.ll
index be237ac..621069d 100644
--- a/test/CodeGen/SystemZ/unaligned-01.ll
+++ b/test/CodeGen/SystemZ/unaligned-01.ll
@@ -21,7 +21,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check that unaligned 2-byte accesses are allowed.
 define i16 @f2(i16 *%src, i16 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: sth %r2, 0(%r3)
 ; CHECK: br %r14
@@ -32,7 +32,7 @@ define i16 @f2(i16 *%src, i16 *%dst) {
 
 ; Check that unaligned 4-byte accesses are allowed.
 define i32 @f3(i32 *%src1, i32 *%src2, i32 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: st %r2, 0(%r4)
@@ -46,7 +46,7 @@ define i32 @f3(i32 *%src1, i32 *%src2, i32 *%dst) {
 
 ; Check that unaligned 8-byte accesses are allowed.
 define i64 @f4(i64 *%src1, i64 *%src2, i64 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: stg %r2, 0(%r4)
diff --git a/test/CodeGen/SystemZ/xor-01.ll b/test/CodeGen/SystemZ/xor-01.ll
index d0c69a0..f9ba2eb 100644
--- a/test/CodeGen/SystemZ/xor-01.ll
+++ b/test/CodeGen/SystemZ/xor-01.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Check XR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xr %r2, %r3
 ; CHECK: br %r14
   %xor = xor i32 %a, %b
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the X range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: x %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +25,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned X range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: x %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -36,7 +36,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use XY instead of X.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -47,7 +47,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned XY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xy %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -59,7 +59,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: x %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned XY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xy %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -82,7 +82,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the XY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: xy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -94,7 +94,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: x %r2, 0(%r3)
 ; CHECK: br %r14
@@ -106,7 +106,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that X allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: x %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -119,7 +119,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that XY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: xy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -132,7 +132,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
 
 ; Check that XORs of spilled values can use X rather than XR.
 define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: x %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/xor-02.ll b/test/CodeGen/SystemZ/xor-02.ll
index c2b52b9..7e28e23 100644
--- a/test/CodeGen/SystemZ/xor-02.ll
+++ b/test/CodeGen/SystemZ/xor-02.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful XILF value.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xilf %r2, 1
 ; CHECK: br %r14
   %xor = xor i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the signed range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xilf %r2, 2147483647
 ; CHECK: br %r14
   %xor = xor i32 %a, 2147483647
@@ -23,7 +23,7 @@ define i32 @f2(i32 %a) {
 ; Check the low end of the signed range, which should be treated
 ; as a positive value.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf %r2, 2147483648
 ; CHECK: br %r14
   %xor = xor i32 %a, -2147483648
@@ -32,7 +32,7 @@ define i32 @f3(i32 %a) {
 
 ; Check the high end of the XILF range.
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xilf %r2, 4294967295
 ; CHECK: br %r14
   %xor = xor i32 %a, 4294967295
diff --git a/test/CodeGen/SystemZ/xor-03.ll b/test/CodeGen/SystemZ/xor-03.ll
index f4f1b88..2cd428a 100644
--- a/test/CodeGen/SystemZ/xor-03.ll
+++ b/test/CodeGen/SystemZ/xor-03.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check XGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xgr %r2, %r3
 ; CHECK: br %r14
   %xor = xor i64 %a, %b
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check XG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xg %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -25,7 +25,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned XG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xg %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: xg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned XG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xg %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -60,7 +60,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the XG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xg %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: xg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that XG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: xg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that XORs of spilled values can use OG rather than OGR.
 define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: xg %r2, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/xor-04.ll b/test/CodeGen/SystemZ/xor-04.ll
index cc141d3..44f0a4c 100644
--- a/test/CodeGen/SystemZ/xor-04.ll
+++ b/test/CodeGen/SystemZ/xor-04.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful XILF value.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xilf %r2, 1
 ; CHECK: br %r14
   %xor = xor i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the XILF range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xilf %r2, 4294967295
 ; CHECK: br %r14
   %xor = xor i64 %a, 4294967295
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; Check the lowest useful XIHF value, which is one up from the above.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xihf %r2, 1
 ; CHECK: br %r14
   %xor = xor i64 %a, 4294967296
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check the next value up again, which needs a combination of XIHF and XILF.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xihf %r2, 1
 ; CHECK: xilf %r2, 4294967295
 ; CHECK: br %r14
@@ -41,7 +41,7 @@ define i64 @f4(i64 %a) {
 
 ; Check the high end of the XIHF range.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xihf %r2, 4294967295
 ; CHECK: br %r14
   %xor = xor i64 %a, -4294967296
@@ -50,7 +50,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the next value up, which again must use XIHF and XILF.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xihf %r2, 4294967295
 ; CHECK: xilf %r2, 1
 ; CHECK: br %r14
@@ -60,7 +60,7 @@ define i64 @f6(i64 %a) {
 
 ; Check full bitwise negation
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xihf %r2, 4294967295
 ; CHECK: xilf %r2, 4294967295
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/xor-05.ll b/test/CodeGen/SystemZ/xor-05.ll
index 9ef0d20..fbd5660 100644
--- a/test/CodeGen/SystemZ/xor-05.ll
+++ b/test/CodeGen/SystemZ/xor-05.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful constant, expressed as a signed integer.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a signed integer.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -26,7 +26,7 @@ define void @f2(i8 *%ptr) {
 
 ; Check the lowest useful constant, expressed as an unsigned integer.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -37,7 +37,7 @@ define void @f3(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a unsigned integer.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -48,7 +48,7 @@ define void @f4(i8 *%ptr) {
 
 ; Check the high end of the XI range.
 define void @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xi 4095(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -60,7 +60,7 @@ define void @f5(i8 *%src) {
 
 ; Check the next byte up, which should use XIY instead of XI.
 define void @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xiy 4096(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -72,7 +72,7 @@ define void @f6(i8 *%src) {
 
 ; Check the high end of the XIY range.
 define void @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xiy 524287(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -85,7 +85,7 @@ define void @f7(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, 524288
 ; CHECK: xi 0(%r2), 127
 ; CHECK: br %r14
@@ -98,7 +98,7 @@ define void @f8(i8 *%src) {
 
 ; Check the high end of the negative XIY range.
 define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: xiy -1(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -110,7 +110,7 @@ define void @f9(i8 *%src) {
 
 ; Check the low end of the XIY range.
 define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: xiy -524288(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -123,7 +123,7 @@ define void @f10(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, -524289
 ; CHECK: xi 0(%r2), 127
 ; CHECK: br %r14
@@ -136,7 +136,7 @@ define void @f11(i8 *%src) {
 
 ; Check that XI does not allow an index
 define void @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agr %r2, %r3
 ; CHECK: xi 4095(%r2), 127
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define void @f12(i64 %src, i64 %index) {
 
 ; Check that XIY does not allow an index
 define void @f13(i64 %src, i64 %index) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agr %r2, %r3
 ; CHECK: xiy 4096(%r2), 127
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/xor-06.ll b/test/CodeGen/SystemZ/xor-06.ll
index 0ffff47..f39c0fe 100644
--- a/test/CodeGen/SystemZ/xor-06.ll
+++ b/test/CodeGen/SystemZ/xor-06.ll
@@ -5,7 +5,7 @@
 
 ; Zero extension to 32 bits, negative constant.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -18,7 +18,7 @@ define void @f1(i8 *%ptr) {
 
 ; Zero extension to 64 bits, negative constant.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -31,7 +31,7 @@ define void @f2(i8 *%ptr) {
 
 ; Zero extension to 32 bits, positive constant.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define void @f3(i8 *%ptr) {
 
 ; Zero extension to 64 bits, positive constant.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -57,7 +57,7 @@ define void @f4(i8 *%ptr) {
 
 ; Sign extension to 32 bits, negative constant.
 define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -70,7 +70,7 @@ define void @f5(i8 *%ptr) {
 
 ; Sign extension to 64 bits, negative constant.
 define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -83,7 +83,7 @@ define void @f6(i8 *%ptr) {
 
 ; Sign extension to 32 bits, positive constant.
 define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -96,7 +96,7 @@ define void @f7(i8 *%ptr) {
 
 ; Sign extension to 64 bits, positive constant.
 define void @f8(i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
index 7876557..414b76d 100644
--- a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
+++ b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
@@ -10,7 +10,7 @@
 @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (%struct.asl_file_t*, i64, i64*)* @t to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
 
 define i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: adds {{r[0-7]}}, #8
 entry:
   %val = alloca i64, align 4                      ; <i64*> [#uses=3]
diff --git a/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll b/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll
index a4c05d2..b39978b 100644
--- a/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll
+++ b/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll
@@ -3,7 +3,7 @@
 ; rdar://11331541
 
 define i32 @t(i32 %a) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: asrs [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], #31
 ; CHECK: eors [[REG1]], [[REG2]]
   %tmp0 = ashr i32 %a, 31
diff --git a/test/CodeGen/Thumb/barrier.ll b/test/CodeGen/Thumb/barrier.ll
index 50d138f..8fca273 100644
--- a/test/CodeGen/Thumb/barrier.ll
+++ b/test/CodeGen/Thumb/barrier.ll
@@ -3,10 +3,10 @@
 ; RUN: llc < %s -march=thumb -mcpu=cortex-m0   | FileCheck %s -check-prefix=V6M
 
 define void @t1() {
-; V6: t1:
+; V6-LABEL: t1:
 ; V6: blx {{_*}}sync_synchronize
 
-; V6M: t1:
+; V6M-LABEL: t1:
 ; V6M: dmb ish
   fence seq_cst
   ret void
diff --git a/test/CodeGen/Thumb/dyn-stackalloc.ll b/test/CodeGen/Thumb/dyn-stackalloc.ll
index f3f0834..6c6de55 100644
--- a/test/CodeGen/Thumb/dyn-stackalloc.ll
+++ b/test/CodeGen/Thumb/dyn-stackalloc.ll
@@ -5,7 +5,7 @@
 	%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
 
 define void @t1(%struct.state* %v) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: push
 ; CHECK: add r7, sp, #12
 ; CHECK: lsls r[[R0:[0-9]+]]
@@ -39,7 +39,7 @@ declare fastcc void @f2(float*, float*, float*, i32)
 @str215 = external global [2 x i8]
 
 define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: push
 ; CHECK: add r7, sp, #12
 ; CHECK: sub sp, #
diff --git a/test/CodeGen/Thumb/ldr_frame.ll b/test/CodeGen/Thumb/ldr_frame.ll
index 81782cd..6c58638 100644
--- a/test/CodeGen/Thumb/ldr_frame.ll
+++ b/test/CodeGen/Thumb/ldr_frame.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb | FileCheck %s
 
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldr r0
 	%buf = alloca [32 x i32], align 4
 	%tmp = getelementptr [32 x i32]* %buf, i32 0, i32 0
@@ -10,7 +10,7 @@ define i32 @f1() {
 }
 
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mov r0
 ; CHECK: ldrb
 	%buf = alloca [32 x i8], align 4
@@ -21,7 +21,7 @@ define i32 @f2() {
 }
 
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ldr r0
 	%buf = alloca [32 x i32], align 4
 	%tmp = getelementptr [32 x i32]* %buf, i32 0, i32 32
@@ -30,7 +30,7 @@ define i32 @f3() {
 }
 
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mov r0
 ; CHECK: ldrb
 	%buf = alloca [32 x i8], align 4
diff --git a/test/CodeGen/Thumb/pop.ll b/test/CodeGen/Thumb/pop.ll
index 63f2feb..1e45c7f 100644
--- a/test/CodeGen/Thumb/pop.ll
+++ b/test/CodeGen/Thumb/pop.ll
@@ -2,7 +2,7 @@
 ; rdar://7268481
 
 define void @t(i8* %a, ...) nounwind {
-; CHECK:      t:
+; CHECK-LABEL:      t:
 ; CHECK:      pop {r3}
 ; CHECK-NEXT: add sp, #12
 ; CHECK-NEXT: bx r3
diff --git a/test/CodeGen/Thumb/push.ll b/test/CodeGen/Thumb/push.ll
index 94ef8e9..62229c6 100644
--- a/test/CodeGen/Thumb/push.ll
+++ b/test/CodeGen/Thumb/push.ll
@@ -2,7 +2,7 @@
 ; rdar://7268481
 
 define void @t() nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: push {r7}
 entry:
   call void asm sideeffect alignstack ".long 0xe7ffdefe", ""() nounwind
diff --git a/test/CodeGen/Thumb/select.ll b/test/CodeGen/Thumb/select.ll
index 3f10b05..fe69a39 100644
--- a/test/CodeGen/Thumb/select.ll
+++ b/test/CodeGen/Thumb/select.ll
@@ -7,9 +7,9 @@ entry:
     %tmp1.s = select i1 %tmp, i32 2, i32 3
     ret i32 %tmp1.s
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: beq
-; CHECK-EABI: f1:
+; CHECK-EABI-LABEL: f1:
 ; CHECK-EABI: beq
 
 define i32 @f2(i32 %a.s) {
@@ -18,9 +18,9 @@ entry:
     %tmp1.s = select i1 %tmp, i32 2, i32 3
     ret i32 %tmp1.s
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: bgt
-; CHECK-EABI: f2:
+; CHECK-EABI-LABEL: f2:
 ; CHECK-EABI: bgt
 
 define i32 @f3(i32 %a.s, i32 %b.s) {
@@ -29,9 +29,9 @@ entry:
     %tmp1.s = select i1 %tmp, i32 2, i32 3
     ret i32 %tmp1.s
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blt
-; CHECK-EABI: f3:
+; CHECK-EABI-LABEL: f3:
 ; CHECK-EABI: blt
 
 define i32 @f4(i32 %a.s, i32 %b.s) {
@@ -40,9 +40,9 @@ entry:
     %tmp1.s = select i1 %tmp, i32 2, i32 3
     ret i32 %tmp1.s
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ble
-; CHECK-EABI: f4:
+; CHECK-EABI-LABEL: f4:
 ; CHECK-EABI: ble
 
 define i32 @f5(i32 %a.u, i32 %b.u) {
@@ -51,9 +51,9 @@ entry:
     %tmp1.s = select i1 %tmp, i32 2, i32 3
     ret i32 %tmp1.s
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: bls
-; CHECK-EABI: f5:
+; CHECK-EABI-LABEL: f5:
 ; CHECK-EABI: bls
 
 define i32 @f6(i32 %a.u, i32 %b.u) {
@@ -62,9 +62,9 @@ entry:
     %tmp1.s = select i1 %tmp, i32 2, i32 3
     ret i32 %tmp1.s
 }
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: bhi
-; CHECK-EABI: f6:
+; CHECK-EABI-LABEL: f6:
 ; CHECK-EABI: bhi
 
 define double @f7(double %a, double %b) {
@@ -72,11 +72,11 @@ define double @f7(double %a, double %b) {
     %tmp1 = select i1 %tmp, double -1.000e+00, double %b
     ret double %tmp1
 }
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: blt
 ; CHECK: blt
 ; CHECK: __ltdf2
-; CHECK-EABI: f7:
+; CHECK-EABI-LABEL: f7:
 ; CHECK-EABI: __aeabi_dcmplt
 ; CHECK-EABI: bne
 ; CHECK-EABI: bne
diff --git a/test/CodeGen/Thumb/trap.ll b/test/CodeGen/Thumb/trap.ll
index 04cd3ee..e04059c 100644
--- a/test/CodeGen/Thumb/trap.ll
+++ b/test/CodeGen/Thumb/trap.ll
@@ -3,7 +3,7 @@
 
 define void @t() nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: trap
   call void @llvm.trap()
   unreachable
diff --git a/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll b/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
index 4616dcf..4abeca9 100644
--- a/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
+++ b/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
@@ -5,7 +5,7 @@
 
 define i32 @t(i32, ...) nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: add r7, sp, #12
 	%1 = load i8** undef, align 4		; <i8*> [#uses=3]
 	%2 = getelementptr i8* %1, i32 4		; <i8*> [#uses=1]
diff --git a/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll b/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
index 095aecc..e014453 100644
--- a/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
+++ b/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
@@ -7,7 +7,7 @@
 @sep = external global [20 x i32]		; <[20 x i32]*> [#uses=1]
 
 define void @main(i32 %argc, i8** %argv) noreturn nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK: ldrb
 entry:
 	%nb.i.i.i = alloca [25 x i8], align 1		; <[25 x i8]*> [#uses=0]
diff --git a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
index ff68e66..940cfd1 100644
--- a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
+++ b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
@@ -4,7 +4,7 @@
 
 define hidden i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind {
 entry:
-; CHECK: __gcov_execlp:
+; CHECK-LABEL: __gcov_execlp:
 ; CHECK: sub sp, #8
 ; CHECK: push
 ; CHECK: add r7, sp, #4
diff --git a/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll b/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
index ac3e80a..52066d3 100644
--- a/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
+++ b/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
@@ -5,7 +5,7 @@
 @getNeighbour = external global void (i32, i32, i32, i32, %struct.pix_pos*)*, align 4 ; <void (i32, i32, i32, i32, %struct.pix_pos*)**> [#uses=2]
 
 define void @t() nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK:      it eq
 ; CHECK-NEXT: cmpeq
 entry:
diff --git a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
index 18c2e0b..04d46e6 100644
--- a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
+++ b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
@@ -10,7 +10,7 @@
 
 
 define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) {
-; CHECK: _ZNKSs7compareERKSs:
+; CHECK-LABEL: _ZNKSs7compareERKSs:
 ; CHECK:      it  eq
 ; CHECK-NEXT: subeq{{(.w)?}} r0, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK-NEXT: pop.w
diff --git a/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll b/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
index 2246de3..486c064 100644
--- a/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
+++ b/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
@@ -6,7 +6,7 @@
 
 define void @t() nounwind ssp {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
   %size = mul i32 8, 2
 ; CHECK:  subs  r0, #16
 ; CHECK:  mov sp, r0
diff --git a/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll b/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll
index 47d7a9c..547950f 100644
--- a/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll
+++ b/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll
@@ -4,7 +4,7 @@
 
 define internal fastcc i32 @Callee(i32 %i) nounwind {
 entry:
-; CHECK: Callee:
+; CHECK-LABEL: Callee:
 ; CHECK: push
 ; CHECK: mov r4, sp
 ; CHECK: sub.w [[R12:r[0-9]+]], r4, #1000
@@ -33,7 +33,7 @@ bb2:                                              ; preds = %entry
 declare i32 @__sprintf_chk(i8*, i32, i32, i8*, ...) nounwind
 
 define i32 @main() nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
 bb.nph:
   br label %bb
 
diff --git a/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll b/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
index 5cb266b..75f5439 100644
--- a/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
+++ b/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
@@ -6,7 +6,7 @@
 declare void @bar() nounwind optsize
 
 define void @foo() nounwind optsize {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: push
 ; CHECK: mov r7, sp
 ; CHECK: sub sp, #4
diff --git a/test/CodeGen/Thumb2/2011-04-21-FILoweringBug.ll b/test/CodeGen/Thumb2/2011-04-21-FILoweringBug.ll
index 604a352..9878ae8 100644
--- a/test/CodeGen/Thumb2/2011-04-21-FILoweringBug.ll
+++ b/test/CodeGen/Thumb2/2011-04-21-FILoweringBug.ll
@@ -7,7 +7,7 @@
 
 define i32 @t() nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: sub sp, #12
 ; CHECK-NOT: sub
 ; CHECK: add r0, sp, #4
diff --git a/test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll b/test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll
index 4acdd9e..5008715 100644
--- a/test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll
+++ b/test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll
@@ -12,7 +12,7 @@
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
 
 define hidden fastcc void @rdictionary_lookup(%struct.Dict_node_struct* %dn, i8* nocapture %s) nounwind ssp {
-; CHECK: rdictionary_lookup:
+; CHECK-LABEL: rdictionary_lookup:
 entry:
   br label %tailrecurse
 
diff --git a/test/CodeGen/Thumb2/buildvector-crash.ll b/test/CodeGen/Thumb2/buildvector-crash.ll
index ce42f4b..8a3c895 100644
--- a/test/CodeGen/Thumb2/buildvector-crash.ll
+++ b/test/CodeGen/Thumb2/buildvector-crash.ll
@@ -12,6 +12,6 @@ bb8:                                              ; preds = %bb8, %bb.nph372
   %3 = fadd <4 x float> undef, %2
   store <4 x float> %3, <4 x float>* undef, align 4
   br label %bb8
-; CHECK: RotateStarsFP_Vec:
+; CHECK-LABEL: RotateStarsFP_Vec:
 ; CHECK: vld1.64
 }
diff --git a/test/CodeGen/Thumb2/carry.ll b/test/CodeGen/Thumb2/carry.ll
index 85b4370..da1902b 100644
--- a/test/CodeGen/Thumb2/carry.ll
+++ b/test/CodeGen/Thumb2/carry.ll
@@ -2,7 +2,7 @@
 
 define i64 @f1(i64 %a, i64 %b) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: subs r0, r0, r2
 ; CHECK: sbcs r1, r3
 	%tmp = sub i64 %a, %b
@@ -11,7 +11,7 @@ entry:
 
 define i64 @f2(i64 %a, i64 %b) {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: adds r0, r0, r0
 ; CHECK: adcs r1, r1
 ; CHECK: subs r0, r0, r2
@@ -24,7 +24,7 @@ entry:
 ; rdar://12559385
 define i64 @f3(i32 %vi) {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: movw [[REG:r[0-9]+]], #36102
 ; CHECK: sbcs r{{[0-9]+}}, [[REG]]
     %v0 = zext i32 %vi to i64
diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
index edbf834..a9f948c 100644
--- a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
+++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | FileCheck %s
 
 define void @fht(float* nocapture %fz, i16 signext %n) nounwind {
-; CHECK: fht:
+; CHECK-LABEL: fht:
 entry:
   br label %bb5
 
diff --git a/test/CodeGen/Thumb2/longMACt.ll b/test/CodeGen/Thumb2/longMACt.ll
index beefd60..a457333 100644
--- a/test/CodeGen/Thumb2/longMACt.ll
+++ b/test/CodeGen/Thumb2/longMACt.ll
@@ -2,7 +2,7 @@
 ; Check generated signed and unsigned multiply accumulate long.
 
 define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
-;CHECK: MACLongTest1:
+;CHECK-LABEL: MACLongTest1:
 ;CHECK: umlal
   %conv = zext i32 %a to i64
   %conv1 = zext i32 %b to i64
@@ -12,7 +12,7 @@ define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
 }
 
 define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c)  {
-;CHECK: MACLongTest2:
+;CHECK-LABEL: MACLongTest2:
 ;CHECK: smlal
   %conv = sext i32 %a to i64
   %conv1 = sext i32 %b to i64
@@ -22,7 +22,7 @@ define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c)  {
 }
 
 define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {
-;CHECK: MACLongTest3:
+;CHECK-LABEL: MACLongTest3:
 ;CHECK: umlal
   %conv = zext i32 %b to i64
   %conv1 = zext i32 %a to i64
@@ -33,7 +33,7 @@ define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {
 }
 
 define i64 @MACLongTest4(i32 %a, i32 %b, i32 %c) {
-;CHECK: MACLongTest4:
+;CHECK-LABEL: MACLongTest4:
 ;CHECK: smlal
   %conv = sext i32 %b to i64
   %conv1 = sext i32 %a to i64
diff --git a/test/CodeGen/Thumb2/lsr-deficiency.ll b/test/CodeGen/Thumb2/lsr-deficiency.ll
index 9aaa821..7ce6768 100644
--- a/test/CodeGen/Thumb2/lsr-deficiency.ll
+++ b/test/CodeGen/Thumb2/lsr-deficiency.ll
@@ -7,7 +7,7 @@
 @array = external global i32*                     ; <i32**> [#uses=1]
 
 define void @t() nounwind optsize {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: mov{{.*}}, #1000
 entry:
   %.pre = load i32* @G, align 4                   ; <i32> [#uses=1]
diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll
index 01df373..d9da846 100644
--- a/test/CodeGen/Thumb2/machine-licm.ll
+++ b/test/CodeGen/Thumb2/machine-licm.ll
@@ -7,7 +7,7 @@
 
 define void @t1(i32* nocapture %vals, i32 %c) nounwind {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: bxeq lr
 
   %0 = icmp eq i32 %c, 0                          ; <i1> [#uses=1]
@@ -50,7 +50,7 @@ return:                                           ; preds = %bb, %entry
 ; rdar://8001136
 define void @t2(i8* %ptr1, i8* %ptr2) nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: vmov.f32 q{{.*}}, #1.000000e+00
   br i1 undef, label %bb1, label %bb2
 
@@ -82,7 +82,7 @@ declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwin
 ; rdar://8241368
 ; isel should not fold immediate into eor's which would have prevented LICM.
 define zeroext i16 @t3(i8 zeroext %data, i16 zeroext %crc) nounwind readnone {
-; CHECK: t3:
+; CHECK-LABEL: t3:
 bb.nph:
 ; CHECK: bb.nph
 ; CHECK: movw {{(r[0-9])|(lr)}}, #32768
diff --git a/test/CodeGen/Thumb2/mul_const.ll b/test/CodeGen/Thumb2/mul_const.ll
index 9a2ec93..488f4d1 100644
--- a/test/CodeGen/Thumb2/mul_const.ll
+++ b/test/CodeGen/Thumb2/mul_const.ll
@@ -3,7 +3,7 @@
 
 define i32 @t1(i32 %v) nounwind readnone {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: add.w r0, r0, r0, lsl #3
 	%0 = mul i32 %v, 9
 	ret i32 %0
@@ -11,7 +11,7 @@ entry:
 
 define i32 @t2(i32 %v) nounwind readnone {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: rsb r0, r0, r0, lsl #3
 	%0 = mul i32 %v, 7
 	ret i32 %0
diff --git a/test/CodeGen/Thumb2/pic-load.ll b/test/CodeGen/Thumb2/pic-load.ll
index 35a03e7..b22fd1d 100644
--- a/test/CodeGen/Thumb2/pic-load.ll
+++ b/test/CodeGen/Thumb2/pic-load.ll
@@ -7,7 +7,7 @@
 
 define hidden i32 @atexit(void ()* %func) nounwind {
 entry:
-; CHECK: atexit:
+; CHECK-LABEL: atexit:
 ; CHECK: add r0, pc
 	%r = alloca %struct.one_atexit_routine, align 4		; <%struct.one_atexit_routine*> [#uses=3]
 	%0 = getelementptr %struct.one_atexit_routine* %r, i32 0, i32 0, i32 0		; <void ()**> [#uses=1]
diff --git a/test/CodeGen/Thumb2/thumb2-adc.ll b/test/CodeGen/Thumb2/thumb2-adc.ll
index 702df91..7c34cfd 100644
--- a/test/CodeGen/Thumb2/thumb2-adc.ll
+++ b/test/CodeGen/Thumb2/thumb2-adc.ll
@@ -2,7 +2,7 @@
 
 ; 734439407618 = 0x000000ab00000002
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: adds r0, #2
     %tmp = add i64 %a, 734439407618
     ret i64 %tmp
@@ -10,7 +10,7 @@ define i64 @f1(i64 %a) {
 
 ; 5066626890203138 = 0x0012001200000002
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: adds r0, #2
     %tmp = add i64 %a, 5066626890203138
     ret i64 %tmp
@@ -18,7 +18,7 @@ define i64 @f2(i64 %a) {
 
 ; 3747052064576897026 = 0x3400340000000002
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: adds r0, #2
     %tmp = add i64 %a, 3747052064576897026
     ret i64 %tmp
@@ -26,7 +26,7 @@ define i64 @f3(i64 %a) {
 
 ; 6221254862626095106 = 0x5656565600000002
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: adds r0, #2
     %tmp = add i64 %a, 6221254862626095106 
     ret i64 %tmp
@@ -34,14 +34,14 @@ define i64 @f4(i64 %a) {
 
 ; 287104476244869122 = 0x03fc000000000002
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: adds r0, #2
     %tmp = add i64 %a, 287104476244869122
     ret i64 %tmp
 }
 
 define i64 @f6(i64 %a, i64 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: adds r0, r0, r2
     %tmp = add i64 %a, %b
     ret i64 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-add.ll b/test/CodeGen/Thumb2/thumb2-add.ll
index 66fca13..c23c74a 100644
--- a/test/CodeGen/Thumb2/thumb2-add.ll
+++ b/test/CodeGen/Thumb2/thumb2-add.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s 
 
 define i32 @t2ADDrc_255(i32 %lhs) {
-; CHECK: t2ADDrc_255:
+; CHECK-LABEL: t2ADDrc_255:
 ; CHECK-NOT: bx lr
 ; CHECK: add{{.*}} #255
 ; CHECK: bx lr
@@ -11,7 +11,7 @@ define i32 @t2ADDrc_255(i32 %lhs) {
 }
 
 define i32 @t2ADDrc_256(i32 %lhs) {
-; CHECK: t2ADDrc_256:
+; CHECK-LABEL: t2ADDrc_256:
 ; CHECK-NOT: bx lr
 ; CHECK: add{{.*}} #256
 ; CHECK: bx lr
@@ -21,7 +21,7 @@ define i32 @t2ADDrc_256(i32 %lhs) {
 }
 
 define i32 @t2ADDrc_257(i32 %lhs) {
-; CHECK: t2ADDrc_257:
+; CHECK-LABEL: t2ADDrc_257:
 ; CHECK-NOT: bx lr
 ; CHECK: add{{.*}} #257
 ; CHECK: bx lr
@@ -31,7 +31,7 @@ define i32 @t2ADDrc_257(i32 %lhs) {
 }
 
 define i32 @t2ADDrc_4094(i32 %lhs) {
-; CHECK: t2ADDrc_4094:
+; CHECK-LABEL: t2ADDrc_4094:
 ; CHECK-NOT: bx lr
 ; CHECK: add{{.*}} #4094
 ; CHECK: bx lr
@@ -41,7 +41,7 @@ define i32 @t2ADDrc_4094(i32 %lhs) {
 }
 
 define i32 @t2ADDrc_4095(i32 %lhs) {
-; CHECK: t2ADDrc_4095:
+; CHECK-LABEL: t2ADDrc_4095:
 ; CHECK-NOT: bx lr
 ; CHECK: add{{.*}} #4095
 ; CHECK: bx lr
@@ -51,7 +51,7 @@ define i32 @t2ADDrc_4095(i32 %lhs) {
 }
 
 define i32 @t2ADDrc_4096(i32 %lhs) {
-; CHECK: t2ADDrc_4096:
+; CHECK-LABEL: t2ADDrc_4096:
 ; CHECK-NOT: bx lr
 ; CHECK: add{{.*}} #4096
 ; CHECK: bx lr
@@ -61,7 +61,7 @@ define i32 @t2ADDrc_4096(i32 %lhs) {
 }
 
 define i32 @t2ADDrr(i32 %lhs, i32 %rhs) {
-; CHECK: t2ADDrr:
+; CHECK-LABEL: t2ADDrr:
 ; CHECK-NOT: bx lr
 ; CHECK: add
 ; CHECK: bx lr
@@ -71,7 +71,7 @@ define i32 @t2ADDrr(i32 %lhs, i32 %rhs) {
 }
 
 define i32 @t2ADDrs(i32 %lhs, i32 %rhs) {
-; CHECK: t2ADDrs:
+; CHECK-LABEL: t2ADDrs:
 ; CHECK-NOT: bx lr
 ; CHECK: add{{.*}} lsl #8
 ; CHECK: bx lr
diff --git a/test/CodeGen/Thumb2/thumb2-add2.ll b/test/CodeGen/Thumb2/thumb2-add2.ll
index e496654..3bbc3bf 100644
--- a/test/CodeGen/Thumb2/thumb2-add2.ll
+++ b/test/CodeGen/Thumb2/thumb2-add2.ll
@@ -2,7 +2,7 @@
 
 ; 171 = 0x000000ab
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: adds r0, #171
     %tmp = add i32 %a, 171
     ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
 
 ; 1179666 = 0x00120012
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: add.w r0, r0, #1179666
     %tmp = add i32 %a, 1179666
     ret i32 %tmp
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a) {
 
 ; 872428544 = 0x34003400
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: add.w r0, r0, #872428544
     %tmp = add i32 %a, 872428544
     ret i32 %tmp
@@ -26,7 +26,7 @@ define i32 @f3(i32 %a) {
 
 ; 1448498774 = 0x56565656
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: add.w r0, r0, #1448498774
     %tmp = add i32 %a, 1448498774
     ret i32 %tmp
@@ -34,7 +34,7 @@ define i32 @f4(i32 %a) {
 
 ; 510 = 0x000001fe
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: add.w r0, r0, #510
     %tmp = add i32 %a, 510
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-add3.ll b/test/CodeGen/Thumb2/thumb2-add3.ll
index 58fc333..6cd818c 100644
--- a/test/CodeGen/Thumb2/thumb2-add3.ll
+++ b/test/CodeGen/Thumb2/thumb2-add3.ll
@@ -5,5 +5,5 @@ define i32 @f1(i32 %a) {
     ret i32 %tmp
 }
 
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	addw	r0, r0, #4095
diff --git a/test/CodeGen/Thumb2/thumb2-add4.ll b/test/CodeGen/Thumb2/thumb2-add4.ll
index b94e84d..8b95711 100644
--- a/test/CodeGen/Thumb2/thumb2-add4.ll
+++ b/test/CodeGen/Thumb2/thumb2-add4.ll
@@ -2,7 +2,7 @@
 
 ; 171 = 0x000000ab
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: adds r0, #171
 ; CHECK: adc r1, r1, #0
     %tmp = add i64 %a, 171
@@ -11,7 +11,7 @@ define i64 @f1(i64 %a) {
 
 ; 1179666 = 0x00120012
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: adds.w r0, r0, #1179666
 ; CHECK: adc r1, r1, #0
     %tmp = add i64 %a, 1179666
@@ -20,7 +20,7 @@ define i64 @f2(i64 %a) {
 
 ; 872428544 = 0x34003400
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: adds.w r0, r0, #872428544
 ; CHECK: adc r1, r1, #0
     %tmp = add i64 %a, 872428544
@@ -29,7 +29,7 @@ define i64 @f3(i64 %a) {
 
 ; 1448498774 = 0x56565656
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: adds.w r0, r0, #1448498774
 ; CHECK: adc r1, r1, #0
     %tmp = add i64 %a, 1448498774
@@ -38,7 +38,7 @@ define i64 @f4(i64 %a) {
 
 ; 66846720 = 0x03fc0000
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: adds.w r0, r0, #66846720
 ; CHECK: adc r1, r1, #0
     %tmp = add i64 %a, 66846720
diff --git a/test/CodeGen/Thumb2/thumb2-add5.ll b/test/CodeGen/Thumb2/thumb2-add5.ll
index 8b3a4f6..beaa09e 100644
--- a/test/CodeGen/Thumb2/thumb2-add5.ll
+++ b/test/CodeGen/Thumb2/thumb2-add5.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: add r0, r1
     %tmp = add i32 %a, %b
     ret i32 %tmp
 }
 
 define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: add.w r0, r0, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = add i32 %a, %tmp
@@ -16,7 +16,7 @@ define i32 @f2(i32 %a, i32 %b) {
 }
 
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: add.w r0, r0, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = add i32 %a, %tmp
@@ -24,7 +24,7 @@ define i32 @f3(i32 %a, i32 %b) {
 }
 
 define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: add.w r0, r0, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = add i32 %a, %tmp
@@ -32,7 +32,7 @@ define i32 @f4(i32 %a, i32 %b) {
 }
 
 define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: add.w r0, r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/thumb2-add6.ll b/test/CodeGen/Thumb2/thumb2-add6.ll
index 0ecaa79..0d2f122 100644
--- a/test/CodeGen/Thumb2/thumb2-add6.ll
+++ b/test/CodeGen/Thumb2/thumb2-add6.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: adds r0, r0, r2
 ; CHECK: adcs r1, r3
     %tmp = add i64 %a, %b
diff --git a/test/CodeGen/Thumb2/thumb2-and.ll b/test/CodeGen/Thumb2/thumb2-and.ll
index 8e2245a..c9578d9 100644
--- a/test/CodeGen/Thumb2/thumb2-and.ll
+++ b/test/CodeGen/Thumb2/thumb2-and.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ands r0, r1
     %tmp = and i32 %a, %b
     ret i32 %tmp
 }
 
 define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: and.w r0, r0, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = and i32 %a, %tmp
@@ -16,7 +16,7 @@ define i32 @f2(i32 %a, i32 %b) {
 }
 
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: and.w r0, r0, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = and i32 %a, %tmp
@@ -24,7 +24,7 @@ define i32 @f3(i32 %a, i32 %b) {
 }
 
 define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: and.w r0, r0, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = and i32 %a, %tmp
@@ -32,7 +32,7 @@ define i32 @f4(i32 %a, i32 %b) {
 }
 
 define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: and.w r0, r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/thumb2-and2.ll b/test/CodeGen/Thumb2/thumb2-and2.ll
index 7b0432d..c0501ab 100644
--- a/test/CodeGen/Thumb2/thumb2-and2.ll
+++ b/test/CodeGen/Thumb2/thumb2-and2.ll
@@ -5,7 +5,7 @@ define i32 @f1(i32 %a) {
     %tmp = and i32 %a, 171
     ret i32 %tmp
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	and	r0, r0, #171
 
 ; 1179666 = 0x00120012
@@ -13,7 +13,7 @@ define i32 @f2(i32 %a) {
     %tmp = and i32 %a, 1179666
     ret i32 %tmp
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	and	r0, r0, #1179666
 
 ; 872428544 = 0x34003400
@@ -21,7 +21,7 @@ define i32 @f3(i32 %a) {
     %tmp = and i32 %a, 872428544
     ret i32 %tmp
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	and	r0, r0, #872428544
 
 ; 1448498774 = 0x56565656
@@ -29,7 +29,7 @@ define i32 @f4(i32 %a) {
     %tmp = and i32 %a, 1448498774
     ret i32 %tmp
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: bic r0, r0, #-1448498775
 
 ; 66846720 = 0x03fc0000
@@ -37,5 +37,5 @@ define i32 @f5(i32 %a) {
     %tmp = and i32 %a, 66846720
     ret i32 %tmp
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: 	and	r0, r0, #66846720
diff --git a/test/CodeGen/Thumb2/thumb2-asr.ll b/test/CodeGen/Thumb2/thumb2-asr.ll
index a0a60e6..ba782dd 100644
--- a/test/CodeGen/Thumb2/thumb2-asr.ll
+++ b/test/CodeGen/Thumb2/thumb2-asr.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: asrs r0, r1
     %tmp = ashr i32 %a, %b
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-asr2.ll b/test/CodeGen/Thumb2/thumb2-asr2.ll
index 9c8634f..3685bad 100644
--- a/test/CodeGen/Thumb2/thumb2-asr2.ll
+++ b/test/CodeGen/Thumb2/thumb2-asr2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: asrs r0, r0, #17
     %tmp = ashr i32 %a, 17
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-bcc.ll b/test/CodeGen/Thumb2/thumb2-bcc.ll
index 4a2d600..81f7de9 100644
--- a/test/CodeGen/Thumb2/thumb2-bcc.ll
+++ b/test/CodeGen/Thumb2/thumb2-bcc.ll
@@ -4,7 +4,7 @@
 ; happen and we get actual branches.
 
 define i32 @t1(i32 %a, i32 %b, i32 %c) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: cbz
   %tmp2 = icmp eq i32 %a, 0
   br i1 %tmp2, label %cond_false, label %cond_true
diff --git a/test/CodeGen/Thumb2/thumb2-bfc.ll b/test/CodeGen/Thumb2/thumb2-bfc.ll
index b486045..327b6d1 100644
--- a/test/CodeGen/Thumb2/thumb2-bfc.ll
+++ b/test/CodeGen/Thumb2/thumb2-bfc.ll
@@ -2,7 +2,7 @@
 
 ; 4278190095 = 0xff00000f
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: bfc r
     %tmp = and i32 %a, 4278190095
     ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
 
 ; 4286578688 = 0xff800000
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: bfc r
     %tmp = and i32 %a, 4286578688
     ret i32 %tmp
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a) {
 
 ; 4095 = 0x00000fff
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: bfc r
     %tmp = and i32 %a, 4095
     ret i32 %tmp
@@ -26,7 +26,7 @@ define i32 @f3(i32 %a) {
 
 ; 2147483646 = 0x7ffffffe   not implementable w/ BFC
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
     %tmp = and i32 %a, 2147483646
     ret i32 %tmp
 }
diff --git a/test/CodeGen/Thumb2/thumb2-bic.ll b/test/CodeGen/Thumb2/thumb2-bic.ll
index 4e35383..5938fa1 100644
--- a/test/CodeGen/Thumb2/thumb2-bic.ll
+++ b/test/CodeGen/Thumb2/thumb2-bic.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: bics r0, r1
     %tmp = xor i32 %b, 4294967295
     %tmp1 = and i32 %a, %tmp
@@ -9,7 +9,7 @@ define i32 @f1(i32 %a, i32 %b) {
 }
 
 define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: bics r0, r1
     %tmp = xor i32 %b, 4294967295
     %tmp1 = and i32 %tmp, %a
@@ -17,7 +17,7 @@ define i32 @f2(i32 %a, i32 %b) {
 }
 
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: bics r0, r1
     %tmp = xor i32 4294967295, %b
     %tmp1 = and i32 %a, %tmp
@@ -25,7 +25,7 @@ define i32 @f3(i32 %a, i32 %b) {
 }
 
 define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: bics r0, r1
     %tmp = xor i32 4294967295, %b
     %tmp1 = and i32 %tmp, %a
@@ -33,7 +33,7 @@ define i32 @f4(i32 %a, i32 %b) {
 }
 
 define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: bic.w r0, r0, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = xor i32 4294967295, %tmp
@@ -42,7 +42,7 @@ define i32 @f5(i32 %a, i32 %b) {
 }
 
 define i32 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: bic.w r0, r0, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = xor i32 %tmp, 4294967295
@@ -51,7 +51,7 @@ define i32 @f6(i32 %a, i32 %b) {
 }
 
 define i32 @f7(i32 %a, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: bic.w r0, r0, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = xor i32 %tmp, 4294967295
@@ -60,7 +60,7 @@ define i32 @f7(i32 %a, i32 %b) {
 }
 
 define i32 @f8(i32 %a, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: bic.w r0, r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
@@ -75,7 +75,7 @@ define i32 @f9(i32 %a) {
     %tmp = and i32 %a, 4294967108
     ret i32 %tmp
     
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: bic r0, r0, #187
 }
 
@@ -84,7 +84,7 @@ define i32 @f10(i32 %a) {
     %tmp = and i32 %a, 4283826005
     ret i32 %tmp
     
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: bic r0, r0, #11141290
 }
 
@@ -92,7 +92,7 @@ define i32 @f10(i32 %a) {
 define i32 @f11(i32 %a) {
     %tmp = and i32 %a, 872363007
     ret i32 %tmp
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: bic r0, r0, #-872363008
 }
 
@@ -100,6 +100,6 @@ define i32 @f11(i32 %a) {
 define i32 @f12(i32 %a) {
     %tmp = and i32 %a, 4293853183
     ret i32 %tmp
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: bic r0, r0, #1114112
 }
diff --git a/test/CodeGen/Thumb2/thumb2-branch.ll b/test/CodeGen/Thumb2/thumb2-branch.ll
index 5e3a7d1..a00b22d 100644
--- a/test/CodeGen/Thumb2/thumb2-branch.ll
+++ b/test/CodeGen/Thumb2/thumb2-branch.ll
@@ -7,7 +7,7 @@ declare void @foo()
 
 define i32 @f1(i32 %a, i32 %b, i32* %v) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: bne LBB
         %tmp = icmp eq i32 %a, %b               ; <i1> [#uses=1]
         br i1 %tmp, label %cond_true, label %return
@@ -24,7 +24,7 @@ return:         ; preds = %entry
 
 define i32 @f2(i32 %a, i32 %b, i32* %v) {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: bge LBB
         %tmp = icmp slt i32 %a, %b              ; <i1> [#uses=1]
         br i1 %tmp, label %cond_true, label %return
@@ -41,7 +41,7 @@ return:         ; preds = %entry
 
 define i32 @f3(i32 %a, i32 %b, i32* %v) {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: bhs LBB
         %tmp = icmp ult i32 %a, %b              ; <i1> [#uses=1]
         br i1 %tmp, label %cond_true, label %return
@@ -58,7 +58,7 @@ return:         ; preds = %entry
 
 define i32 @f4(i32 %a, i32 %b, i32* %v) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: blo LBB
         %tmp = icmp uge i32 %a, %b              ; <i1> [#uses=1]
         br i1 %tmp, label %cond_true, label %return
diff --git a/test/CodeGen/Thumb2/thumb2-call-tc.ll b/test/CodeGen/Thumb2/thumb2-call-tc.ll
index 2e4da1b..2902949 100644
--- a/test/CodeGen/Thumb2/thumb2-call-tc.ll
+++ b/test/CodeGen/Thumb2/thumb2-call-tc.ll
@@ -7,20 +7,20 @@
 declare void @g(i32, i32, i32, i32)
 
 define void @f() {
-; DARWIN: f:
+; DARWIN-LABEL: f:
 ; DARWIN: blx _g
 
-; LINUX: f:
+; LINUX-LABEL: f:
 ; LINUX: bl g
         tail call void @g( i32 1, i32 2, i32 3, i32 4 )
         ret void
 }
 
 define void @h() {
-; DARWIN: h:
+; DARWIN-LABEL: h:
 ; DARWIN: bx r0 @ TAILCALL
 
-; LINUX: h:
+; LINUX-LABEL: h:
 ; LINUX: bx r0 @ TAILCALL
         %tmp = load i32 ()** @t         ; <i32 ()*> [#uses=1]
         %tmp.upgrd.2 = tail call i32 %tmp( )            ; <i32> [#uses=0]
@@ -28,10 +28,10 @@ define void @h() {
 }
 
 define void @j() {
-; DARWIN: j:
+; DARWIN-LABEL: j:
 ; DARWIN: b.w _f  @ TAILCALL
 
-; LINUX: j:
+; LINUX-LABEL: j:
 ; LINUX: b.w f  @ TAILCALL
         tail call void @f()
         ret void
diff --git a/test/CodeGen/Thumb2/thumb2-call.ll b/test/CodeGen/Thumb2/thumb2-call.ll
index 8513cfb..1d2eaa7 100644
--- a/test/CodeGen/Thumb2/thumb2-call.ll
+++ b/test/CodeGen/Thumb2/thumb2-call.ll
@@ -6,20 +6,20 @@
 declare void @g(i32, i32, i32, i32)
 
 define void @f() {
-; DARWIN: f:
+; DARWIN-LABEL: f:
 ; DARWIN: blx _g
 
-; LINUX: f:
+; LINUX-LABEL: f:
 ; LINUX: bl g
         call void @g( i32 1, i32 2, i32 3, i32 4 )
         ret void
 }
 
 define void @h() {
-; DARWIN: h:
+; DARWIN-LABEL: h:
 ; DARWIN: blx r0
 
-; LINUX: h:
+; LINUX-LABEL: h:
 ; LINUX: blx r0
         %tmp = load i32 ()** @t         ; <i32 ()*> [#uses=1]
         %tmp.upgrd.2 = call i32 %tmp( )            ; <i32> [#uses=0]
diff --git a/test/CodeGen/Thumb2/thumb2-clz.ll b/test/CodeGen/Thumb2/thumb2-clz.ll
index f7e9665..dbdaae2 100644
--- a/test/CodeGen/Thumb2/thumb2-clz.ll
+++ b/test/CodeGen/Thumb2/thumb2-clz.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7 | FileCheck %s
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clz r
     %tmp = tail call i32 @llvm.ctlz.i32(i32 %a, i1 true)
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-cmn.ll b/test/CodeGen/Thumb2/thumb2-cmn.ll
index 67b07e6..8bcaa7e 100644
--- a/test/CodeGen/Thumb2/thumb2-cmn.ll
+++ b/test/CodeGen/Thumb2/thumb2-cmn.ll
@@ -8,7 +8,7 @@ define i1 @f1(i32 %a, i32 %b) {
     %tmp = icmp ne i32 %a, %nb
     ret i1 %tmp
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	cmn	{{.*}}, r1
 
 define i1 @f2(i32 %a, i32 %b) {
@@ -16,7 +16,7 @@ define i1 @f2(i32 %a, i32 %b) {
     %tmp = icmp ne i32 %nb, %a
     ret i1 %tmp
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	cmn	{{.*}}, r1
 
 define i1 @f3(i32 %a, i32 %b) {
@@ -24,7 +24,7 @@ define i1 @f3(i32 %a, i32 %b) {
     %tmp = icmp eq i32 %a, %nb
     ret i1 %tmp
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	cmn	{{.*}}, r1
 
 define i1 @f4(i32 %a, i32 %b) {
@@ -32,7 +32,7 @@ define i1 @f4(i32 %a, i32 %b) {
     %tmp = icmp eq i32 %nb, %a
     ret i1 %tmp
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: 	cmn	{{.*}}, r1
 
 define i1 @f5(i32 %a, i32 %b) {
@@ -41,7 +41,7 @@ define i1 @f5(i32 %a, i32 %b) {
     %tmp1 = icmp eq i32 %nb, %a
     ret i1 %tmp1
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: 	cmn.w	{{.*}}, r1, lsl #5
 
 define i1 @f6(i32 %a, i32 %b) {
@@ -50,7 +50,7 @@ define i1 @f6(i32 %a, i32 %b) {
     %tmp1 = icmp ne i32 %nb, %a
     ret i1 %tmp1
 }
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: 	cmn.w	{{.*}}, r1, lsr #6
 
 define i1 @f7(i32 %a, i32 %b) {
@@ -59,7 +59,7 @@ define i1 @f7(i32 %a, i32 %b) {
     %tmp1 = icmp eq i32 %a, %nb
     ret i1 %tmp1
 }
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: 	cmn.w	{{.*}}, r1, asr #7
 
 define i1 @f8(i32 %a, i32 %b) {
@@ -70,7 +70,7 @@ define i1 @f8(i32 %a, i32 %b) {
     %tmp1 = icmp ne i32 %a, %nb
     ret i1 %tmp1
 }
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: 	cmn.w	{{.*}}, {{.*}}, ror #8
 
 
@@ -81,5 +81,5 @@ define void @f9(i32 %a, i32 %b) nounwind optsize {
 
 !0 = metadata !{i32 81}
 
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: 	cmn.w	r0, r1
diff --git a/test/CodeGen/Thumb2/thumb2-cmn2.ll b/test/CodeGen/Thumb2/thumb2-cmn2.ll
index c0e19f6..f5db728 100644
--- a/test/CodeGen/Thumb2/thumb2-cmn2.ll
+++ b/test/CodeGen/Thumb2/thumb2-cmn2.ll
@@ -2,7 +2,7 @@
 
 ; -0x000000bb = 4294967109
 define i1 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cmn.w {{r.*}}, #187
     %tmp = icmp ne i32 %a, 4294967109
     ret i1 %tmp
@@ -10,7 +10,7 @@ define i1 @f1(i32 %a) {
 
 ; -0x00aa00aa = 4283826006
 define i1 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cmn.w {{r.*}}, #11141290
     %tmp = icmp eq i32 %a, 4283826006
     ret i1 %tmp
@@ -18,7 +18,7 @@ define i1 @f2(i32 %a) {
 
 ; -0xcc00cc00 = 872363008
 define i1 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cmn.w {{r.*}}, #-872363008
     %tmp = icmp ne i32 %a, 872363008
     ret i1 %tmp
@@ -26,7 +26,7 @@ define i1 @f3(i32 %a) {
 
 ; -0x00110000 = 4293853184
 define i1 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cmn.w {{r.*}}, #1114112
     %tmp = icmp eq i32 %a, 4293853184
     ret i1 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-cmp.ll b/test/CodeGen/Thumb2/thumb2-cmp.ll
index 4ce7acc..8741344 100644
--- a/test/CodeGen/Thumb2/thumb2-cmp.ll
+++ b/test/CodeGen/Thumb2/thumb2-cmp.ll
@@ -5,7 +5,7 @@
 
 ; 0x000000bb = 187
 define i1 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cmp {{.*}}, #187
     %tmp = icmp ne i32 %a, 187
     ret i1 %tmp
@@ -13,7 +13,7 @@ define i1 @f1(i32 %a) {
 
 ; 0x00aa00aa = 11141290
 define i1 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cmp.w {{.*}}, #11141290
     %tmp = icmp eq i32 %a, 11141290 
     ret i1 %tmp
@@ -21,7 +21,7 @@ define i1 @f2(i32 %a) {
 
 ; 0xcc00cc00 = 3422604288
 define i1 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cmp.w {{.*}}, #-872363008
     %tmp = icmp ne i32 %a, 3422604288
     ret i1 %tmp
@@ -29,7 +29,7 @@ define i1 @f3(i32 %a) {
 
 ; 0xdddddddd = 3722304989
 define i1 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cmp.w {{.*}}, #-572662307
     %tmp = icmp ne i32 %a, 3722304989
     ret i1 %tmp
@@ -37,7 +37,7 @@ define i1 @f4(i32 %a) {
 
 ; 0x00110000 = 1114112
 define i1 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cmp.w {{.*}}, #1114112
     %tmp = icmp eq i32 %a, 1114112
     ret i1 %tmp
@@ -45,7 +45,7 @@ define i1 @f5(i32 %a) {
 
 ; Check that we don't do an invalid (a > b) --> !(a < b + 1) transform.
 ;
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: cmp.w {{.*}}, #-2147483648
 ; CHECK: bx lr
 define i32 @f6(i32 %a) {
diff --git a/test/CodeGen/Thumb2/thumb2-cmp2.ll b/test/CodeGen/Thumb2/thumb2-cmp2.ll
index f6790de..5b880f1 100644
--- a/test/CodeGen/Thumb2/thumb2-cmp2.ll
+++ b/test/CodeGen/Thumb2/thumb2-cmp2.ll
@@ -4,21 +4,21 @@
 ; test as 'mov.w r0, #0'.
 
 define i1 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cmp {{.*}}, r1
     %tmp = icmp ne i32 %a, %b
     ret i1 %tmp
 }
 
 define i1 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cmp {{.*}}, r1
     %tmp = icmp eq i32 %a, %b
     ret i1 %tmp
 }
 
 define i1 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cmp.w {{.*}}, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = icmp eq i32 %tmp, %a
@@ -26,7 +26,7 @@ define i1 @f6(i32 %a, i32 %b) {
 }
 
 define i1 @f7(i32 %a, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cmp.w {{.*}}, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = icmp ne i32 %tmp, %a
@@ -34,7 +34,7 @@ define i1 @f7(i32 %a, i32 %b) {
 }
 
 define i1 @f8(i32 %a, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cmp.w {{.*}}, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = icmp eq i32 %a, %tmp
@@ -42,7 +42,7 @@ define i1 @f8(i32 %a, i32 %b) {
 }
 
 define i1 @f9(i32 %a, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cmp.w {{.*}}, {{.*}}, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/thumb2-eor.ll b/test/CodeGen/Thumb2/thumb2-eor.ll
index 116a1a3..b3e323c 100644
--- a/test/CodeGen/Thumb2/thumb2-eor.ll
+++ b/test/CodeGen/Thumb2/thumb2-eor.ll
@@ -1,28 +1,28 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: eors r0, r1
     %tmp = xor i32 %a, %b
     ret i32 %tmp
 }
 
 define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: eors r0, r1
     %tmp = xor i32 %b, %a
     ret i32 %tmp
 }
 
 define i32 @f2b(i32 %a, i32 %b, i32 %c) {
-; CHECK: f2b:
+; CHECK-LABEL: f2b:
 ; CHECK: eor.w r0, r1, r2
     %tmp = xor i32 %b, %c
     ret i32 %tmp
 }
 
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: eor.w r0, r0, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = xor i32 %a, %tmp
@@ -30,7 +30,7 @@ define i32 @f3(i32 %a, i32 %b) {
 }
 
 define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: eor.w r0, r0, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = xor i32 %tmp, %a
@@ -38,7 +38,7 @@ define i32 @f4(i32 %a, i32 %b) {
 }
 
 define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: eor.w r0, r0, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = xor i32 %a, %tmp
@@ -46,7 +46,7 @@ define i32 @f5(i32 %a, i32 %b) {
 }
 
 define i32 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: eor.w r0, r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/thumb2-eor2.ll b/test/CodeGen/Thumb2/thumb2-eor2.ll
index 6b2e9dc..5daa13d 100644
--- a/test/CodeGen/Thumb2/thumb2-eor2.ll
+++ b/test/CodeGen/Thumb2/thumb2-eor2.ll
@@ -2,7 +2,7 @@
 
 ; 0x000000bb = 187
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: eor {{.*}}#187
     %tmp = xor i32 %a, 187
     ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
 
 ; 0x00aa00aa = 11141290
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: eor {{.*}}#11141290
     %tmp = xor i32 %a, 11141290 
     ret i32 %tmp
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a) {
 
 ; 0xcc00cc00 = 3422604288
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: eor {{.*}}#-872363008
     %tmp = xor i32 %a, 3422604288
     ret i32 %tmp
@@ -26,7 +26,7 @@ define i32 @f3(i32 %a) {
 
 ; 0xdddddddd = 3722304989
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: eor {{.*}}#-572662307
     %tmp = xor i32 %a, 3722304989
     ret i32 %tmp
@@ -34,7 +34,7 @@ define i32 @f4(i32 %a) {
 
 ; 0x00110000 = 1114112
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: eor {{.*}}#1114112
     %tmp = xor i32 %a, 1114112
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll b/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll
index 5315535..d86a897 100644
--- a/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll
@@ -2,7 +2,7 @@
 ; XFAIL: *
 
 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: it ne
 ; CHECK: cmpne
 	switch i32 %c, label %cond_next [
@@ -23,7 +23,7 @@ cond_next:
 ; FIXME: Check for # of unconditional branch after adding branch folding post ifcvt.
 define i32 @t2(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: ite gt
 ; CHECK: subgt
 ; CHECK: suble
@@ -71,7 +71,7 @@ entry:
 ; Tail call prevents use of ifcvt in this one.  Seems like a win though.
 define void @t3(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK-NOT: it lt
 ; CHECK-NOT: poplt
 ; CHECK: b.w _foo @ TAILCALL
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
index af8fcc6..85943cf 100644
--- a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
 
 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: ittt ne
 ; CHECK: cmpne
 ; CHECK: addne
@@ -24,7 +24,7 @@ cond_next:
 define i32 @t2(i32 %a, i32 %b) nounwind {
 entry:
 ; Do not if-convert when branches go to the different loops.
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK-NOT: ite gt
 ; CHECK-NOT: subgt
 ; CHECK-NOT: suble
@@ -71,7 +71,7 @@ entry:
 
 define void @t3(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: itt ge
 ; CHECK: movge r0, r1
 ; CHECK: blge  _foo
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
index 5aa9a73..d7bae42 100644
--- a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
@@ -2,7 +2,7 @@
 
 define void @foo(i32 %X, i32 %Y) {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: it ne
 ; CHECK: cmpne
 ; CHECK: it hi
@@ -28,7 +28,7 @@ declare i32 @bar(...)
 
 define fastcc i32 @CountTree(%struct.quad_struct* %tree) {
 entry:
-; CHECK: CountTree:
+; CHECK-LABEL: CountTree:
 ; CHECK: itt eq
 ; CHECK: moveq
 ; CHECK: popeq
@@ -65,7 +65,7 @@ declare void @abort()
 
 define fastcc void @t1(%struct.SString* %word, i8 signext  %c) {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: it ne
 ; CHECK: popne {r7, pc}
 	%tmp1 = icmp eq %struct.SString* %word, null		; <i1> [#uses=1]
@@ -81,7 +81,7 @@ cond_false:		; preds = %entry
 
 define fastcc void @t2() nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: cmp r0, #0
 ; CHECK: %growMapping.exit
 	br i1 undef, label %bb.i.i3, label %growMapping.exit
diff --git a/test/CodeGen/Thumb2/thumb2-ldm.ll b/test/CodeGen/Thumb2/thumb2-ldm.ll
index b2328e7..8716d80 100644
--- a/test/CodeGen/Thumb2/thumb2-ldm.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldm.ll
@@ -3,7 +3,7 @@
 @X = external global [0 x i32]          ; <[0 x i32]*> [#uses=5]
 
 define i32 @t1() {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: push {r7, lr}
 ; CHECK: pop {r7, pc}
         %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0)            ; <i32> [#uses=1]
@@ -13,7 +13,7 @@ define i32 @t1() {
 }
 
 define i32 @t2() {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: push {r7, lr}
 ; CHECK: ldm
 ; CHECK: pop {r7, pc}
@@ -25,7 +25,7 @@ define i32 @t2() {
 }
 
 define i32 @t3() {
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: push {r7, lr}
 ; CHECK: pop {r7, pc}
         %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1)            ; <i32> [#uses=1]
diff --git a/test/CodeGen/Thumb2/thumb2-ldr.ll b/test/CodeGen/Thumb2/thumb2-ldr.ll
index 88434f1..7f68f66 100644
--- a/test/CodeGen/Thumb2/thumb2-ldr.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldr.ll
@@ -2,7 +2,7 @@
 
 define i32 @f1(i32* %v) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldr r0, [r0]
         %tmp = load i32* %v
         ret i32 %tmp
@@ -10,7 +10,7 @@ entry:
 
 define i32 @f2(i32* %v) {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldr.w r0, [r0, #4092]
         %tmp2 = getelementptr i32* %v, i32 1023
         %tmp = load i32* %tmp2
@@ -19,7 +19,7 @@ entry:
 
 define i32 @f3(i32* %v) {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov.w r1, #4096
 ; CHECK: ldr r0, [r0, r1]
         %tmp2 = getelementptr i32* %v, i32 1024
@@ -29,7 +29,7 @@ entry:
 
 define i32 @f4(i32 %base) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldr r0, [r0, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i32*
@@ -39,7 +39,7 @@ entry:
 
 define i32 @f5(i32 %base, i32 %offset) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldr r0, [r0, r1]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i32*
@@ -49,7 +49,7 @@ entry:
 
 define i32 @f6(i32 %base, i32 %offset) {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ldr.w r0, [r0, r1, lsl #2]
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
@@ -60,7 +60,7 @@ entry:
 
 define i32 @f7(i32 %base, i32 %offset) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lsrs r1, r1, #2
 ; CHECK: ldr r0, [r0, r1]
 
diff --git a/test/CodeGen/Thumb2/thumb2-ldrb.ll b/test/CodeGen/Thumb2/thumb2-ldrb.ll
index bf10097..c135eff 100644
--- a/test/CodeGen/Thumb2/thumb2-ldrb.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldrb.ll
@@ -2,7 +2,7 @@
 
 define i8 @f1(i8* %v) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldrb r0, [r0]
         %tmp = load i8* %v
         ret i8 %tmp
@@ -10,7 +10,7 @@ entry:
 
 define i8 @f2(i8* %v) {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldrb r0, [r0, #-1]
         %tmp2 = getelementptr i8* %v, i8 1023
         %tmp = load i8* %tmp2
@@ -19,7 +19,7 @@ entry:
 
 define i8 @f3(i32 %base) {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov.w r1, #4096
 ; CHECK: ldrb r0, [r0, r1]
         %tmp1 = add i32 %base, 4096
@@ -30,7 +30,7 @@ entry:
 
 define i8 @f4(i32 %base) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldrb r0, [r0, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i8*
@@ -40,7 +40,7 @@ entry:
 
 define i8 @f5(i32 %base, i32 %offset) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldrb r0, [r0, r1]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i8*
@@ -50,7 +50,7 @@ entry:
 
 define i8 @f6(i32 %base, i32 %offset) {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ldrb.w r0, [r0, r1, lsl #2]
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
@@ -61,7 +61,7 @@ entry:
 
 define i8 @f7(i32 %base, i32 %offset) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lsrs r1, r1, #2
 ; CHECK: ldrb r0, [r0, r1]
         %tmp1 = lshr i32 %offset, 2
diff --git a/test/CodeGen/Thumb2/thumb2-ldrh.ll b/test/CodeGen/Thumb2/thumb2-ldrh.ll
index fee97bf..99f6aba 100644
--- a/test/CodeGen/Thumb2/thumb2-ldrh.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldrh.ll
@@ -2,7 +2,7 @@
 
 define i16 @f1(i16* %v) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldrh r0, [r0]
         %tmp = load i16* %v
         ret i16 %tmp
@@ -10,7 +10,7 @@ entry:
 
 define i16 @f2(i16* %v) {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldrh.w r0, [r0, #2046]
         %tmp2 = getelementptr i16* %v, i16 1023
         %tmp = load i16* %tmp2
@@ -19,7 +19,7 @@ entry:
 
 define i16 @f3(i16* %v) {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov.w r1, #4096
 ; CHECK: ldrh r0, [r0, r1]
         %tmp2 = getelementptr i16* %v, i16 2048
@@ -29,7 +29,7 @@ entry:
 
 define i16 @f4(i32 %base) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldrh r0, [r0, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i16*
@@ -39,7 +39,7 @@ entry:
 
 define i16 @f5(i32 %base, i32 %offset) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldrh r0, [r0, r1]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i16*
@@ -49,7 +49,7 @@ entry:
 
 define i16 @f6(i32 %base, i32 %offset) {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ldrh.w r0, [r0, r1, lsl #2]
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
@@ -60,7 +60,7 @@ entry:
 
 define i16 @f7(i32 %base, i32 %offset) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lsrs r1, r1, #2
 ; CHECK: ldrh r0, [r0, r1]
         %tmp1 = lshr i32 %offset, 2
diff --git a/test/CodeGen/Thumb2/thumb2-lsl.ll b/test/CodeGen/Thumb2/thumb2-lsl.ll
index 6b0818a..1b48538 100644
--- a/test/CodeGen/Thumb2/thumb2-lsl.ll
+++ b/test/CodeGen/Thumb2/thumb2-lsl.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lsls r0, r0, #5
     %tmp = shl i32 %a, 5
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-lsl2.ll b/test/CodeGen/Thumb2/thumb2-lsl2.ll
index f283eef..bc0978e 100644
--- a/test/CodeGen/Thumb2/thumb2-lsl2.ll
+++ b/test/CodeGen/Thumb2/thumb2-lsl2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lsls r0, r1
     %tmp = shl i32 %a, %b
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-lsr.ll b/test/CodeGen/Thumb2/thumb2-lsr.ll
index 7cbee54..a3b207c 100644
--- a/test/CodeGen/Thumb2/thumb2-lsr.ll
+++ b/test/CodeGen/Thumb2/thumb2-lsr.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lsrs r0, r0, #13
     %tmp = lshr i32 %a, 13
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-lsr2.ll b/test/CodeGen/Thumb2/thumb2-lsr2.ll
index 87800f9..ae55735 100644
--- a/test/CodeGen/Thumb2/thumb2-lsr2.ll
+++ b/test/CodeGen/Thumb2/thumb2-lsr2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lsrs r0, r1
     %tmp = lshr i32 %a, %b
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-mla.ll b/test/CodeGen/Thumb2/thumb2-mla.ll
index 594d974..709fa13 100644
--- a/test/CodeGen/Thumb2/thumb2-mla.ll
+++ b/test/CodeGen/Thumb2/thumb2-mla.ll
@@ -6,9 +6,9 @@ define i32 @f1(i32 %a, i32 %b, i32 %c) {
     %tmp2 = add i32 %c, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	mla	r0, r0, r1, r2
-; NO_MULOPS: f1:
+; NO_MULOPS-LABEL: f1:
 ; NO_MULOPS: muls r0, r1, r0
 ; NO_MULOPS-NEXT: add r0, r2
 
@@ -17,8 +17,8 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) {
     %tmp2 = add i32 %tmp1, %c
     ret i32 %tmp2
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	mla	r0, r0, r1, r2
-; NO_MULOPS: f2:
+; NO_MULOPS-LABEL: f2:
 ; NO_MULOPS: muls r0, r1, r0
 ; NO_MULOPS-NEXT: add r0, r2
diff --git a/test/CodeGen/Thumb2/thumb2-mls.ll b/test/CodeGen/Thumb2/thumb2-mls.ll
index 58f9add..86e147b 100644
--- a/test/CodeGen/Thumb2/thumb2-mls.ll
+++ b/test/CodeGen/Thumb2/thumb2-mls.ll
@@ -5,7 +5,7 @@ define i32 @f1(i32 %a, i32 %b, i32 %c) {
     %tmp2 = sub i32 %c, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	mls	r0, r0, r1, r2
 
 ; sub doesn't commute, so no mls for this one
@@ -14,6 +14,6 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) {
     %tmp2 = sub i32 %tmp1, %c
     ret i32 %tmp2
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	muls	r0, r1, r0
 
diff --git a/test/CodeGen/Thumb2/thumb2-mov.ll b/test/CodeGen/Thumb2/thumb2-mov.ll
index adb6dde..077be12 100644
--- a/test/CodeGen/Thumb2/thumb2-mov.ll
+++ b/test/CodeGen/Thumb2/thumb2-mov.ll
@@ -4,14 +4,14 @@
 
 ; var 2.1 - 0x00ab00ab
 define i32 @t2_const_var2_1_ok_1(i32 %lhs) {
-;CHECK: t2_const_var2_1_ok_1:
+;CHECK-LABEL: t2_const_var2_1_ok_1:
 ;CHECK: add.w   r0, r0, #11206827
     %ret = add i32 %lhs, 11206827 ; 0x00ab00ab
     ret i32 %ret
 }
 
 define i32 @t2_const_var2_1_ok_2(i32 %lhs) {
-;CHECK: t2_const_var2_1_ok_2:
+;CHECK-LABEL: t2_const_var2_1_ok_2:
 ;CHECK: add.w   r0, r0, #11206656
 ;CHECK: adds    r0, #187
     %ret = add i32 %lhs, 11206843 ; 0x00ab00bb
@@ -19,7 +19,7 @@ define i32 @t2_const_var2_1_ok_2(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_1_ok_3(i32 %lhs) {
-;CHECK: t2_const_var2_1_ok_3:
+;CHECK-LABEL: t2_const_var2_1_ok_3:
 ;CHECK: add.w   r0, r0, #11206827
 ;CHECK: add.w   r0, r0, #16777216
     %ret = add i32 %lhs, 27984043 ; 0x01ab00ab
@@ -27,7 +27,7 @@ define i32 @t2_const_var2_1_ok_3(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_1_ok_4(i32 %lhs) {
-;CHECK: t2_const_var2_1_ok_4:
+;CHECK-LABEL: t2_const_var2_1_ok_4:
 ;CHECK: add.w   r0, r0, #16777472
 ;CHECK: add.w   r0, r0, #11206827
     %ret = add i32 %lhs, 27984299 ; 0x01ab01ab
@@ -35,7 +35,7 @@ define i32 @t2_const_var2_1_ok_4(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
-;CHECK: t2_const_var2_1_fail_1:
+;CHECK-LABEL: t2_const_var2_1_fail_1:
 ;CHECK: movw    r1, #43777
 ;CHECK: movt    r1, #427
 ;CHECK: add     r0, r1
@@ -45,14 +45,14 @@ define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
 
 ; var 2.2 - 0xab00ab00
 define i32 @t2_const_var2_2_ok_1(i32 %lhs) {
-;CHECK: t2_const_var2_2_ok_1:
+;CHECK-LABEL: t2_const_var2_2_ok_1:
 ;CHECK: add.w   r0, r0, #-1426019584
     %ret = add i32 %lhs, 2868947712 ; 0xab00ab00
     ret i32 %ret
 }
 
 define i32 @t2_const_var2_2_ok_2(i32 %lhs) {
-;CHECK: t2_const_var2_2_ok_2:
+;CHECK-LABEL: t2_const_var2_2_ok_2:
 ;CHECK: add.w   r0, r0, #2868903936
 ;CHECK: add.w   r0, r0, #47616
     %ret = add i32 %lhs, 2868951552 ; 0xab00ba00
@@ -60,7 +60,7 @@ define i32 @t2_const_var2_2_ok_2(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_2_ok_3(i32 %lhs) {
-;CHECK: t2_const_var2_2_ok_3:
+;CHECK-LABEL: t2_const_var2_2_ok_3:
 ;CHECK: add.w   r0, r0, #2868947712
 ;CHECK: adds    r0, #16
     %ret = add i32 %lhs, 2868947728 ; 0xab00ab10
@@ -68,7 +68,7 @@ define i32 @t2_const_var2_2_ok_3(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_2_ok_4(i32 %lhs) {
-;CHECK: t2_const_var2_2_ok_4:
+;CHECK-LABEL: t2_const_var2_2_ok_4:
 ;CHECK: add.w   r0, r0, #2868947712
 ;CHECK: add.w   r0, r0, #1048592
     %ret = add i32 %lhs, 2869996304 ; 0xab10ab10
@@ -76,7 +76,7 @@ define i32 @t2_const_var2_2_ok_4(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
-;CHECK: t2_const_var2_2_fail_1:
+;CHECK-LABEL: t2_const_var2_2_fail_1:
 ;CHECK: movw    r1, #43792
 ;CHECK: movt    r1, #4267
 ;CHECK: add     r0, r1
@@ -86,14 +86,14 @@ define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
 
 ; var 2.3 - 0xabababab
 define i32 @t2_const_var2_3_ok_1(i32 %lhs) {
-;CHECK: t2_const_var2_3_ok_1:
+;CHECK-LABEL: t2_const_var2_3_ok_1:
 ;CHECK: add.w   r0, r0, #-1414812757
     %ret = add i32 %lhs, 2880154539 ; 0xabababab
     ret i32 %ret
 }
 
 define i32 @t2_const_var2_3_fail_1(i32 %lhs) {
-;CHECK: t2_const_var2_3_fail_1:
+;CHECK-LABEL: t2_const_var2_3_fail_1:
 ;CHECK: movw    r1, #43962
 ;CHECK: movt    r1, #43947
 ;CHECK: add     r0, r1
@@ -102,7 +102,7 @@ define i32 @t2_const_var2_3_fail_1(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_3_fail_2(i32 %lhs) {
-;CHECK: t2_const_var2_3_fail_2:
+;CHECK-LABEL: t2_const_var2_3_fail_2:
 ;CHECK: movw    r1, #47787
 ;CHECK: movt    r1, #43947
 ;CHECK: add     r0, r1
@@ -111,7 +111,7 @@ define i32 @t2_const_var2_3_fail_2(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_3_fail_3(i32 %lhs) {
-;CHECK: t2_const_var2_3_fail_3:
+;CHECK-LABEL: t2_const_var2_3_fail_3:
 ;CHECK: movw    r1, #43947
 ;CHECK: movt    r1, #43962
 ;CHECK: add     r0, r1
@@ -120,7 +120,7 @@ define i32 @t2_const_var2_3_fail_3(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_3_fail_4(i32 %lhs) {
-;CHECK: t2_const_var2_3_fail_4:
+;CHECK-LABEL: t2_const_var2_3_fail_4:
 ;CHECK: movw    r1, #43947
 ;CHECK: movt    r1, #47787
 ;CHECK: add     r0, r1
@@ -130,21 +130,21 @@ define i32 @t2_const_var2_3_fail_4(i32 %lhs) {
 
 ; var 3 - 0x0F000000
 define i32 @t2_const_var3_1_ok_1(i32 %lhs) {
-;CHECK: t2_const_var3_1_ok_1:
+;CHECK-LABEL: t2_const_var3_1_ok_1:
 ;CHECK: add.w   r0, r0, #251658240
     %ret = add i32 %lhs, 251658240 ; 0x0F000000
     ret i32 %ret
 }
 
 define i32 @t2_const_var3_2_ok_1(i32 %lhs) {
-;CHECK: t2_const_var3_2_ok_1:
+;CHECK-LABEL: t2_const_var3_2_ok_1:
 ;CHECK: add.w   r0, r0, #3948544
     %ret = add i32 %lhs, 3948544 ; 0b00000000001111000100000000000000
     ret i32 %ret
 }
 
 define i32 @t2_const_var3_2_ok_2(i32 %lhs) {
-;CHECK: t2_const_var3_2_ok_2:
+;CHECK-LABEL: t2_const_var3_2_ok_2:
 ;CHECK: add.w   r0, r0, #2097152
 ;CHECK: add.w   r0, r0, #1843200
     %ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000
@@ -152,21 +152,21 @@ define i32 @t2_const_var3_2_ok_2(i32 %lhs) {
 }
 
 define i32 @t2_const_var3_3_ok_1(i32 %lhs) {
-;CHECK: t2_const_var3_3_ok_1:
+;CHECK-LABEL: t2_const_var3_3_ok_1:
 ;CHECK: add.w   r0, r0, #258
     %ret = add i32 %lhs, 258 ; 0b00000000000000000000000100000010
     ret i32 %ret
 }
 
 define i32 @t2_const_var3_4_ok_1(i32 %lhs) {
-;CHECK: t2_const_var3_4_ok_1:
+;CHECK-LABEL: t2_const_var3_4_ok_1:
 ;CHECK: add.w   r0, r0, #-268435456
     %ret = add i32 %lhs, 4026531840 ; 0xF0000000
     ret i32 %ret
 }
 
 define i32 @t2MOVTi16_ok_1(i32 %a) {
-; CHECK: t2MOVTi16_ok_1:
+; CHECK-LABEL: t2MOVTi16_ok_1:
 ; CHECK: movt r0, #1234
     %1 = and i32 %a, 65535
     %2 = shl i32 1234, 16
@@ -176,7 +176,7 @@ define i32 @t2MOVTi16_ok_1(i32 %a) {
 }
 
 define i32 @t2MOVTi16_test_1(i32 %a) {
-; CHECK: t2MOVTi16_test_1:
+; CHECK-LABEL: t2MOVTi16_test_1:
 ; CHECK: movt r0, #1234
     %1 = shl i32  255,   8
     %2 = shl i32 1234,   8
@@ -189,7 +189,7 @@ define i32 @t2MOVTi16_test_1(i32 %a) {
 }
 
 define i32 @t2MOVTi16_test_2(i32 %a) {
-; CHECK: t2MOVTi16_test_2:
+; CHECK-LABEL: t2MOVTi16_test_2:
 ; CHECK: movt r0, #1234
     %1 = shl i32  255,   8
     %2 = shl i32 1234,   8
@@ -203,7 +203,7 @@ define i32 @t2MOVTi16_test_2(i32 %a) {
 }
 
 define i32 @t2MOVTi16_test_3(i32 %a) {
-; CHECK: t2MOVTi16_test_3:
+; CHECK-LABEL: t2MOVTi16_test_3:
 ; CHECK: movt r0, #1234
     %1 = shl i32  255,   8
     %2 = shl i32 1234,   8
@@ -220,7 +220,7 @@ define i32 @t2MOVTi16_test_3(i32 %a) {
 
 ; 171 = 0x000000ab
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: movs r0, #171
     %tmp = add i32 0, 171
     ret i32 %tmp
@@ -228,7 +228,7 @@ define i32 @f1(i32 %a) {
 
 ; 1179666 = 0x00120012
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mov.w r0, #1179666
     %tmp = add i32 0, 1179666
     ret i32 %tmp
@@ -236,7 +236,7 @@ define i32 @f2(i32 %a) {
 
 ; 872428544 = 0x34003400
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov.w r0, #872428544
     %tmp = add i32 0, 872428544
     ret i32 %tmp
@@ -244,7 +244,7 @@ define i32 @f3(i32 %a) {
 
 ; 1448498774 = 0x56565656
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mov.w r0, #1448498774
     %tmp = add i32 0, 1448498774
     ret i32 %tmp
@@ -252,7 +252,7 @@ define i32 @f4(i32 %a) {
 
 ; 66846720 = 0x03fc0000
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mov.w r0, #66846720
     %tmp = add i32 0, 66846720
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-mul.ll b/test/CodeGen/Thumb2/thumb2-mul.ll
index a8134e6..a989989 100644
--- a/test/CodeGen/Thumb2/thumb2-mul.ll
+++ b/test/CodeGen/Thumb2/thumb2-mul.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b, i32 %c) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: muls r0, r1, r0
     %tmp = mul i32 %a, %b
     ret i32 %tmp
@@ -12,7 +12,7 @@ define i32 @f1(i32 %a, i32 %b, i32 %c) {
 
 define %struct.CMPoint* @t1(i32 %i, i32 %j, i32 %n, %struct.CMPoint* %thePoints) nounwind readnone ssp {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: mla     r0, r2, r0, r1
 ; CHECK: add.w   r0, r0, r0, lsl #3
 ; CHECK: add.w   r0, r3, r0, lsl #2
diff --git a/test/CodeGen/Thumb2/thumb2-mvn.ll b/test/CodeGen/Thumb2/thumb2-mvn.ll
index a8c8f83..a5592f6 100644
--- a/test/CodeGen/Thumb2/thumb2-mvn.ll
+++ b/test/CodeGen/Thumb2/thumb2-mvn.ll
@@ -2,7 +2,7 @@
 
 ; 0x000000bb = 187
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvn r0, #187
     %tmp = xor i32 4294967295, 187
     ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
 
 ; 0x00aa00aa = 11141290
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvn r0, #11141290
     %tmp = xor i32 4294967295, 11141290 
     ret i32 %tmp
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a) {
 
 ; 0xcc00cc00 = 3422604288
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvn r0, #-872363008
     %tmp = xor i32 4294967295, 3422604288
     ret i32 %tmp
@@ -26,7 +26,7 @@ define i32 @f3(i32 %a) {
 
 ; 0x00110000 = 1114112
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvn r0, #1114112
     %tmp = xor i32 4294967295, 1114112
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-mvn2.ll b/test/CodeGen/Thumb2/thumb2-mvn2.ll
index 375d0aa..bce54a3 100644
--- a/test/CodeGen/Thumb2/thumb2-mvn2.ll
+++ b/test/CodeGen/Thumb2/thumb2-mvn2.ll
@@ -1,21 +1,21 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvns r0, r0
     %tmp = xor i32 4294967295, %a
     ret i32 %tmp
 }
 
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvns r0, r0
     %tmp = xor i32 %a, 4294967295
     ret i32 %tmp
 }
 
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvn.w r0, r0, lsl #5
     %tmp = shl i32 %a, 5
     %tmp1 = xor i32 %tmp, 4294967295
@@ -23,7 +23,7 @@ define i32 @f5(i32 %a) {
 }
 
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvn.w r0, r0, lsr #6
     %tmp = lshr i32 %a, 6
     %tmp1 = xor i32 %tmp, 4294967295
@@ -31,7 +31,7 @@ define i32 @f6(i32 %a) {
 }
 
 define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvn.w r0, r0, asr #7
     %tmp = ashr i32 %a, 7
     %tmp1 = xor i32 %tmp, 4294967295
@@ -39,7 +39,7 @@ define i32 @f7(i32 %a) {
 }
 
 define i32 @f8(i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: mvn.w r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/thumb2-neg.ll b/test/CodeGen/Thumb2/thumb2-neg.ll
index 6bf11ec..40e8098 100644
--- a/test/CodeGen/Thumb2/thumb2-neg.ll
+++ b/test/CodeGen/Thumb2/thumb2-neg.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: rsbs r0, r0, #0
     %tmp = sub i32 0, %a
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-orn.ll b/test/CodeGen/Thumb2/thumb2-orn.ll
index 97a3fd7..5bbe653 100644
--- a/test/CodeGen/Thumb2/thumb2-orn.ll
+++ b/test/CodeGen/Thumb2/thumb2-orn.ll
@@ -6,7 +6,7 @@ define i32 @f1(i32 %a, i32 %b) {
     %tmp1 = or i32 %a, %tmp
     ret i32 %tmp1
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	orn	r0, r0, r1
 
 define i32 @f2(i32 %a, i32 %b) {
@@ -14,7 +14,7 @@ define i32 @f2(i32 %a, i32 %b) {
     %tmp1 = or i32 %tmp, %a
     ret i32 %tmp1
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	orn	r0, r0, r1
 
 define i32 @f3(i32 %a, i32 %b) {
@@ -22,7 +22,7 @@ define i32 @f3(i32 %a, i32 %b) {
     %tmp1 = or i32 %a, %tmp
     ret i32 %tmp1
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	orn	r0, r0, r1
 
 define i32 @f4(i32 %a, i32 %b) {
@@ -30,7 +30,7 @@ define i32 @f4(i32 %a, i32 %b) {
     %tmp1 = or i32 %tmp, %a
     ret i32 %tmp1
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: 	orn	r0, r0, r1
 
 define i32 @f5(i32 %a, i32 %b) {
@@ -39,7 +39,7 @@ define i32 @f5(i32 %a, i32 %b) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: 	orn	r0, r0, r1, lsl #5
 
 define i32 @f6(i32 %a, i32 %b) {
@@ -48,7 +48,7 @@ define i32 @f6(i32 %a, i32 %b) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: 	orn	r0, r0, r1, lsr #6
 
 define i32 @f7(i32 %a, i32 %b) {
@@ -57,7 +57,7 @@ define i32 @f7(i32 %a, i32 %b) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: 	orn	r0, r0, r1, asr #7
 
 define i32 @f8(i32 %a, i32 %b) {
@@ -68,5 +68,5 @@ define i32 @f8(i32 %a, i32 %b) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: 	orn	r0, r0, r0, ror #8
diff --git a/test/CodeGen/Thumb2/thumb2-orn2.ll b/test/CodeGen/Thumb2/thumb2-orn2.ll
index 34ab3a5..eff3ae3 100644
--- a/test/CodeGen/Thumb2/thumb2-orn2.ll
+++ b/test/CodeGen/Thumb2/thumb2-orn2.ll
@@ -7,7 +7,7 @@ define i32 @f1(i32 %a) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	orn	r0, r0, #187
 
 ; 0x00aa00aa = 11141290
@@ -16,7 +16,7 @@ define i32 @f2(i32 %a) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	orn	r0, r0, #11141290
 
 ; 0xcc00cc00 = 3422604288
@@ -25,7 +25,7 @@ define i32 @f3(i32 %a) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	orn	r0, r0, #-872363008
 
 ; 0x00110000 = 1114112
@@ -34,5 +34,5 @@ define i32 @f5(i32 %a) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: 	orn	r0, r0, #1114112
diff --git a/test/CodeGen/Thumb2/thumb2-orr.ll b/test/CodeGen/Thumb2/thumb2-orr.ll
index 89ab7b1..13ed862 100644
--- a/test/CodeGen/Thumb2/thumb2-orr.ll
+++ b/test/CodeGen/Thumb2/thumb2-orr.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: orrs r0, r1
     %tmp2 = or i32 %a, %b
     ret i32 %tmp2
 }
 
 define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: orr.w r0, r0, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp2 = or i32 %a, %tmp
@@ -16,7 +16,7 @@ define i32 @f5(i32 %a, i32 %b) {
 }
 
 define i32 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: orr.w r0, r0, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp2 = or i32 %a, %tmp
@@ -24,7 +24,7 @@ define i32 @f6(i32 %a, i32 %b) {
 }
 
 define i32 @f7(i32 %a, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: orr.w r0, r0, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp2 = or i32 %a, %tmp
@@ -32,7 +32,7 @@ define i32 @f7(i32 %a, i32 %b) {
 }
 
 define i32 @f8(i32 %a, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: orr.w r0, r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/thumb2-orr2.ll b/test/CodeGen/Thumb2/thumb2-orr2.ll
index 8f7a3c2..837bb1c 100644
--- a/test/CodeGen/Thumb2/thumb2-orr2.ll
+++ b/test/CodeGen/Thumb2/thumb2-orr2.ll
@@ -6,7 +6,7 @@ define i32 @f1(i32 %a) {
     %tmp2 = or i32 %a, 187
     ret i32 %tmp2
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	orr	r0, r0, #187
 
 ; 0x00aa00aa = 11141290
@@ -14,7 +14,7 @@ define i32 @f2(i32 %a) {
     %tmp2 = or i32 %a, 11141290 
     ret i32 %tmp2
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	orr	r0, r0, #11141290
 
 ; 0xcc00cc00 = 3422604288
@@ -22,7 +22,7 @@ define i32 @f3(i32 %a) {
     %tmp2 = or i32 %a, 3422604288
     ret i32 %tmp2
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	orr	r0, r0, #-872363008
 
 ; 0x44444444 = 1145324612
@@ -30,7 +30,7 @@ define i32 @f4(i32 %a) {
     %tmp2 = or i32 %a, 1145324612
     ret i32 %tmp2
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: 	orr	r0, r0, #1145324612
 
 ; 0x00110000 = 1114112
@@ -38,5 +38,5 @@ define i32 @f5(i32 %a) {
     %tmp2 = or i32 %a, 1114112
     ret i32 %tmp2
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: 	orr	r0, r0, #1114112
diff --git a/test/CodeGen/Thumb2/thumb2-rev.ll b/test/CodeGen/Thumb2/thumb2-rev.ll
index b469bbd..67cd623 100644
--- a/test/CodeGen/Thumb2/thumb2-rev.ll
+++ b/test/CodeGen/Thumb2/thumb2-rev.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7,+t2xtpk | FileCheck %s
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: rev r0, r0
     %tmp = tail call i32 @llvm.bswap.i32(i32 %a)
     ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
 declare i32 @llvm.bswap.i32(i32) nounwind readnone
 
 define i32 @f2(i32 %X) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: revsh r0, r0
         %tmp1 = lshr i32 %X, 8
         %tmp1.upgrd.1 = trunc i32 %tmp1 to i16
diff --git a/test/CodeGen/Thumb2/thumb2-ror.ll b/test/CodeGen/Thumb2/thumb2-ror.ll
index 5ad92cd..2a218ea 100644
--- a/test/CodeGen/Thumb2/thumb2-ror.ll
+++ b/test/CodeGen/Thumb2/thumb2-ror.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 ; RUN: llc < %s -march=thumb | FileCheck %s -check-prefix=THUMB1
 
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	ror.w	r0, r0, #22
 define i32 @f1(i32 %a) {
     %l8 = shl i32 %a, 10
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
     ret i32 %tmp
 }
 
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: and
 ; CHECK: ror
 ; THUMB1: f2
diff --git a/test/CodeGen/Thumb2/thumb2-rsb.ll b/test/CodeGen/Thumb2/thumb2-rsb.ll
index 15185be..150a25f 100644
--- a/test/CodeGen/Thumb2/thumb2-rsb.ll
+++ b/test/CodeGen/Thumb2/thumb2-rsb.ll
@@ -5,7 +5,7 @@ define i32 @f1(i32 %a, i32 %b) {
     %tmp1 = sub i32 %tmp, %a
     ret i32 %tmp1
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	rsb	r0, r0, r1, lsl #5
 
 define i32 @f2(i32 %a, i32 %b) {
@@ -13,7 +13,7 @@ define i32 @f2(i32 %a, i32 %b) {
     %tmp1 = sub i32 %tmp, %a
     ret i32 %tmp1
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	rsb	r0, r0, r1, lsr #6
 
 define i32 @f3(i32 %a, i32 %b) {
@@ -21,7 +21,7 @@ define i32 @f3(i32 %a, i32 %b) {
     %tmp1 = sub i32 %tmp, %a
     ret i32 %tmp1
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	rsb	r0, r0, r1, asr #7
 
 define i32 @f4(i32 %a, i32 %b) {
@@ -31,5 +31,5 @@ define i32 @f4(i32 %a, i32 %b) {
     %tmp1 = sub i32 %tmp, %a
     ret i32 %tmp1
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: 	rsb	r0, r0, r0, ror #8
diff --git a/test/CodeGen/Thumb2/thumb2-rsb2.ll b/test/CodeGen/Thumb2/thumb2-rsb2.ll
index 61fb619..15aa8af 100644
--- a/test/CodeGen/Thumb2/thumb2-rsb2.ll
+++ b/test/CodeGen/Thumb2/thumb2-rsb2.ll
@@ -5,7 +5,7 @@ define i32 @f1(i32 %a) {
     %tmp = sub i32 171, %a
     ret i32 %tmp
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	rsb.w	r0, r0, #171
 
 ; 1179666 = 0x00120012
@@ -13,7 +13,7 @@ define i32 @f2(i32 %a) {
     %tmp = sub i32 1179666, %a
     ret i32 %tmp
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	rsb.w	r0, r0, #1179666
 
 ; 872428544 = 0x34003400
@@ -21,7 +21,7 @@ define i32 @f3(i32 %a) {
     %tmp = sub i32 872428544, %a
     ret i32 %tmp
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	rsb.w	r0, r0, #872428544
 
 ; 1448498774 = 0x56565656
@@ -29,7 +29,7 @@ define i32 @f4(i32 %a) {
     %tmp = sub i32 1448498774, %a
     ret i32 %tmp
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: 	rsb.w	r0, r0, #1448498774
 
 ; 66846720 = 0x03fc0000
@@ -37,5 +37,5 @@ define i32 @f5(i32 %a) {
     %tmp = sub i32 66846720, %a
     ret i32 %tmp
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: 	rsb.w	r0, r0, #66846720
diff --git a/test/CodeGen/Thumb2/thumb2-sbc.ll b/test/CodeGen/Thumb2/thumb2-sbc.ll
index 492e5f0..0c37984 100644
--- a/test/CodeGen/Thumb2/thumb2-sbc.ll
+++ b/test/CodeGen/Thumb2/thumb2-sbc.ll
@@ -54,7 +54,7 @@ define i64 @f6(i64 %a) {
 
 ; Example from numerics code that manually computes wider-than-64 values.
 ;
-; CHECK: livecarry:
+; CHECK-LABEL: livecarry:
 ; CHECK: adds
 ; CHECK: adc
 define i64 @livecarry(i64 %carry, i32 %digit) nounwind {
diff --git a/test/CodeGen/Thumb2/thumb2-select.ll b/test/CodeGen/Thumb2/thumb2-select.ll
index 2dcf8aa..0feaf95 100644
--- a/test/CodeGen/Thumb2/thumb2-select.ll
+++ b/test/CodeGen/Thumb2/thumb2-select.ll
@@ -2,7 +2,7 @@
 
 define i32 @f1(i32 %a.s) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: it eq
 ; CHECK: moveq
 
@@ -13,7 +13,7 @@ entry:
 
 define i32 @f2(i32 %a.s) {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: it gt
 ; CHECK: movgt
     %tmp = icmp sgt i32 %a.s, 4
@@ -23,7 +23,7 @@ entry:
 
 define i32 @f3(i32 %a.s, i32 %b.s) {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: it lt
 ; CHECK: movlt
     %tmp = icmp slt i32 %a.s, %b.s
@@ -33,7 +33,7 @@ entry:
 
 define i32 @f4(i32 %a.s, i32 %b.s) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: it le
 ; CHECK: movle
 
@@ -44,7 +44,7 @@ entry:
 
 define i32 @f5(i32 %a.u, i32 %b.u) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: it ls
 ; CHECK: movls
     %tmp = icmp ule i32 %a.u, %b.u
@@ -54,7 +54,7 @@ entry:
 
 define i32 @f6(i32 %a.u, i32 %b.u) {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: it hi
 ; CHECK: movhi
     %tmp = icmp ugt i32 %a.u, %b.u
@@ -64,7 +64,7 @@ entry:
 
 define i32 @f7(i32 %a, i32 %b, i32 %c) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: it hi
 ; CHECK: lsrhi.w
     %tmp1 = icmp ugt i32 %a, %b
@@ -75,7 +75,7 @@ entry:
 
 define i32 @f8(i32 %a, i32 %b, i32 %c) {
 entry:
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: it lo
 ; CHECK: lsllo.w
     %tmp1 = icmp ult i32 %a, %b
@@ -86,7 +86,7 @@ entry:
 
 define i32 @f9(i32 %a, i32 %b, i32 %c) {
 entry:
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: it ge
 ; CHECK: rorge.w
     %tmp1 = icmp sge i32 %a, %b
diff --git a/test/CodeGen/Thumb2/thumb2-spill-q.ll b/test/CodeGen/Thumb2/thumb2-spill-q.ll
index 5bff268..52c1063 100644
--- a/test/CodeGen/Thumb2/thumb2-spill-q.ll
+++ b/test/CodeGen/Thumb2/thumb2-spill-q.ll
@@ -10,7 +10,7 @@
 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
 
 define void @aaa(%quuz* %this, i8* %block) {
-; CHECK: aaa:
+; CHECK-LABEL: aaa:
 ; CHECK: bic r4, r4, #15
 ; CHECK: vst1.64 {{.*}}[{{.*}}:128]
 ; CHECK: vld1.64 {{.*}}[{{.*}}:128]
diff --git a/test/CodeGen/Thumb2/thumb2-str.ll b/test/CodeGen/Thumb2/thumb2-str.ll
index 11bb936..fb5fa16 100644
--- a/test/CodeGen/Thumb2/thumb2-str.ll
+++ b/test/CodeGen/Thumb2/thumb2-str.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32* %v) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: str r0, [r1]
         store i32 %a, i32* %v
         ret i32 %a
 }
 
 define i32 @f2(i32 %a, i32* %v) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: str.w r0, [r1, #4092]
         %tmp2 = getelementptr i32* %v, i32 1023
         store i32 %a, i32* %tmp2
@@ -16,7 +16,7 @@ define i32 @f2(i32 %a, i32* %v) {
 }
 
 define i32 @f2a(i32 %a, i32* %v) {
-; CHECK: f2a:
+; CHECK-LABEL: f2a:
 ; CHECK: str r0, [r1, #-128]
         %tmp2 = getelementptr i32* %v, i32 -32
         store i32 %a, i32* %tmp2
@@ -24,7 +24,7 @@ define i32 @f2a(i32 %a, i32* %v) {
 }
 
 define i32 @f3(i32 %a, i32* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov.w r2, #4096
 ; CHECK: str r0, [r1, r2]
         %tmp2 = getelementptr i32* %v, i32 1024
@@ -34,7 +34,7 @@ define i32 @f3(i32 %a, i32* %v) {
 
 define i32 @f4(i32 %a, i32 %base) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: str r0, [r1, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i32*
@@ -44,7 +44,7 @@ entry:
 
 define i32 @f5(i32 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: str r0, [r1, r2]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i32*
@@ -54,7 +54,7 @@ entry:
 
 define i32 @f6(i32 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: str.w r0, [r1, r2, lsl #2]
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
@@ -65,7 +65,7 @@ entry:
 
 define i32 @f7(i32 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lsrs r2, r2, #2
 ; CHECK: str r0, [r1, r2]
         %tmp1 = lshr i32 %offset, 2
diff --git a/test/CodeGen/Thumb2/thumb2-strb.ll b/test/CodeGen/Thumb2/thumb2-strb.ll
index 7978e7f..cc39b7d 100644
--- a/test/CodeGen/Thumb2/thumb2-strb.ll
+++ b/test/CodeGen/Thumb2/thumb2-strb.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i8 @f1(i8 %a, i8* %v) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: strb r0, [r1]
         store i8 %a, i8* %v
         ret i8 %a
 }
 
 define i8 @f2(i8 %a, i8* %v) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: strb.w r0, [r1, #4092]
         %tmp2 = getelementptr i8* %v, i32 4092
         store i8 %a, i8* %tmp2
@@ -16,7 +16,7 @@ define i8 @f2(i8 %a, i8* %v) {
 }
 
 define i8 @f2a(i8 %a, i8* %v) {
-; CHECK: f2a:
+; CHECK-LABEL: f2a:
 ; CHECK: strb r0, [r1, #-128]
         %tmp2 = getelementptr i8* %v, i32 -128
         store i8 %a, i8* %tmp2
@@ -24,7 +24,7 @@ define i8 @f2a(i8 %a, i8* %v) {
 }
 
 define i8 @f3(i8 %a, i8* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov.w r2, #4096
 ; CHECK: strb r0, [r1, r2]
         %tmp2 = getelementptr i8* %v, i32 4096
@@ -34,7 +34,7 @@ define i8 @f3(i8 %a, i8* %v) {
 
 define i8 @f4(i8 %a, i32 %base) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: strb r0, [r1, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i8*
@@ -44,7 +44,7 @@ entry:
 
 define i8 @f5(i8 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: strb r0, [r1, r2]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i8*
@@ -54,7 +54,7 @@ entry:
 
 define i8 @f6(i8 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: strb.w r0, [r1, r2, lsl #2]
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
@@ -65,7 +65,7 @@ entry:
 
 define i8 @f7(i8 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lsrs r2, r2, #2
 ; CHECK: strb r0, [r1, r2]
         %tmp1 = lshr i32 %offset, 2
diff --git a/test/CodeGen/Thumb2/thumb2-strh.ll b/test/CodeGen/Thumb2/thumb2-strh.ll
index 97110a72..d686938 100644
--- a/test/CodeGen/Thumb2/thumb2-strh.ll
+++ b/test/CodeGen/Thumb2/thumb2-strh.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i16 @f1(i16 %a, i16* %v) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: strh r0, [r1]
         store i16 %a, i16* %v
         ret i16 %a
 }
 
 define i16 @f2(i16 %a, i16* %v) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: strh.w r0, [r1, #4092]
         %tmp2 = getelementptr i16* %v, i32 2046
         store i16 %a, i16* %tmp2
@@ -16,7 +16,7 @@ define i16 @f2(i16 %a, i16* %v) {
 }
 
 define i16 @f2a(i16 %a, i16* %v) {
-; CHECK: f2a:
+; CHECK-LABEL: f2a:
 ; CHECK: strh r0, [r1, #-128]
         %tmp2 = getelementptr i16* %v, i32 -64
         store i16 %a, i16* %tmp2
@@ -24,7 +24,7 @@ define i16 @f2a(i16 %a, i16* %v) {
 }
 
 define i16 @f3(i16 %a, i16* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov.w r2, #4096
 ; CHECK: strh r0, [r1, r2]
         %tmp2 = getelementptr i16* %v, i32 2048
@@ -34,7 +34,7 @@ define i16 @f3(i16 %a, i16* %v) {
 
 define i16 @f4(i16 %a, i32 %base) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: strh r0, [r1, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i16*
@@ -44,7 +44,7 @@ entry:
 
 define i16 @f5(i16 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: strh r0, [r1, r2]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i16*
@@ -54,7 +54,7 @@ entry:
 
 define i16 @f6(i16 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: strh.w r0, [r1, r2, lsl #2]
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
@@ -65,7 +65,7 @@ entry:
 
 define i16 @f7(i16 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lsrs r2, r2, #2
 ; CHECK: strh r0, [r1, r2]
         %tmp1 = lshr i32 %offset, 2
diff --git a/test/CodeGen/Thumb2/thumb2-sub.ll b/test/CodeGen/Thumb2/thumb2-sub.ll
index 95335a2..f83dfe2 100644
--- a/test/CodeGen/Thumb2/thumb2-sub.ll
+++ b/test/CodeGen/Thumb2/thumb2-sub.ll
@@ -2,7 +2,7 @@
 
 ; 171 = 0x000000ab
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: subs r0, #171
     %tmp = sub i32 %a, 171
     ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
 
 ; 1179666 = 0x00120012
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sub.w r0, r0, #1179666
     %tmp = sub i32 %a, 1179666
     ret i32 %tmp
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a) {
 
 ; 872428544 = 0x34003400
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sub.w r0, r0, #872428544
     %tmp = sub i32 %a, 872428544
     ret i32 %tmp
@@ -26,7 +26,7 @@ define i32 @f3(i32 %a) {
 
 ; 1448498774 = 0x56565656
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sub.w r0, r0, #1448498774
     %tmp = sub i32 %a, 1448498774
     ret i32 %tmp
@@ -34,7 +34,7 @@ define i32 @f4(i32 %a) {
 
 ; 510 = 0x000001fe
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sub.w r0, r0, #510
     %tmp = sub i32 %a, 510
     ret i32 %tmp
@@ -42,7 +42,7 @@ define i32 @f5(i32 %a) {
 
 ; Don't change this to an add.
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: subs r0, #1
     %tmp = sub i32 %a, 1
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-sub2.ll b/test/CodeGen/Thumb2/thumb2-sub2.ll
index bb99cbd..47eb1e1 100644
--- a/test/CodeGen/Thumb2/thumb2-sub2.ll
+++ b/test/CodeGen/Thumb2/thumb2-sub2.ll
@@ -4,5 +4,5 @@ define i32 @f1(i32 %a) {
     %tmp = sub i32 %a, 4095
     ret i32 %tmp
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	subw	r0, r0, #4095
diff --git a/test/CodeGen/Thumb2/thumb2-sub4.ll b/test/CodeGen/Thumb2/thumb2-sub4.ll
index a040d17..ff1441a 100644
--- a/test/CodeGen/Thumb2/thumb2-sub4.ll
+++ b/test/CodeGen/Thumb2/thumb2-sub4.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: subs r0, r0, r1
     %tmp = sub i32 %a, %b
     ret i32 %tmp
 }
 
 define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sub.w r0, r0, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = sub i32 %a, %tmp
@@ -16,7 +16,7 @@ define i32 @f2(i32 %a, i32 %b) {
 }
 
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sub.w r0, r0, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = sub i32 %a, %tmp
@@ -24,7 +24,7 @@ define i32 @f3(i32 %a, i32 %b) {
 }
 
 define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sub.w r0, r0, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = sub i32 %a, %tmp
@@ -32,7 +32,7 @@ define i32 @f4(i32 %a, i32 %b) {
 }
 
 define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sub.w r0, r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/thumb2-sub5.ll b/test/CodeGen/Thumb2/thumb2-sub5.ll
index 6edd789..5941dd6 100644
--- a/test/CodeGen/Thumb2/thumb2-sub5.ll
+++ b/test/CodeGen/Thumb2/thumb2-sub5.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 -mattr=+32bit | FileCheck %s
 
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: subs.w r0, r0, r2
 ; To test dead_carry, +32bit prevents sbc conveting to 16-bit sbcs
 ; CHECK: sbc.w  r1, r1, r3
diff --git a/test/CodeGen/Thumb2/thumb2-tbb.ll b/test/CodeGen/Thumb2/thumb2-tbb.ll
index a9d71d6..d57638b 100644
--- a/test/CodeGen/Thumb2/thumb2-tbb.ll
+++ b/test/CodeGen/Thumb2/thumb2-tbb.ll
@@ -3,7 +3,7 @@
 
 define void @bar(i32 %n.u) {
 entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: tbb
 ; CHECK: .data_region jt8
 ; CHECK: .end_data_region
diff --git a/test/CodeGen/Thumb2/thumb2-tbh.ll b/test/CodeGen/Thumb2/thumb2-tbh.ll
index cd9c8e1..bf1c7c6 100644
--- a/test/CodeGen/Thumb2/thumb2-tbh.ll
+++ b/test/CodeGen/Thumb2/thumb2-tbh.ll
@@ -15,7 +15,7 @@ declare void @Z_fatal(i8*) noreturn nounwind
 declare noalias i8* @calloc(i32, i32) nounwind
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK: tbb
 entry:
 	br label %bb42.i
diff --git a/test/CodeGen/Thumb2/thumb2-teq.ll b/test/CodeGen/Thumb2/thumb2-teq.ll
index d453f46..5acda35 100644
--- a/test/CodeGen/Thumb2/thumb2-teq.ll
+++ b/test/CodeGen/Thumb2/thumb2-teq.ll
@@ -9,7 +9,7 @@ define i1 @f2(i32 %a) {
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	teq.w	{{.*}}, #187
 
 ; 0x00aa00aa = 11141290
@@ -18,7 +18,7 @@ define i1 @f3(i32 %a) {
     %tmp1 = icmp eq i32 %tmp, 0
     ret i1 %tmp1
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	teq.w	{{.*}}, #11141290
 
 ; 0xcc00cc00 = 3422604288
@@ -27,7 +27,7 @@ define i1 @f6(i32 %a) {
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: 	teq.w	{{.*}}, #-872363008
 
 ; 0xdddddddd = 3722304989
@@ -36,7 +36,7 @@ define i1 @f7(i32 %a) {
     %tmp1 = icmp eq i32 %tmp, 0
     ret i1 %tmp1
 }
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: 	teq.w	{{.*}}, #-572662307
 
 ; 0xdddddddd = 3722304989
@@ -52,6 +52,6 @@ define i1 @f10(i32 %a) {
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: 	teq.w	{{.*}}, #1114112
 
diff --git a/test/CodeGen/Thumb2/thumb2-tst.ll b/test/CodeGen/Thumb2/thumb2-tst.ll
index 67fe82e..31eafea 100644
--- a/test/CodeGen/Thumb2/thumb2-tst.ll
+++ b/test/CodeGen/Thumb2/thumb2-tst.ll
@@ -9,7 +9,7 @@ define i1 @f2(i32 %a) {
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	tst.w	{{.*}}, #187
 
 ; 0x00aa00aa = 11141290
@@ -18,7 +18,7 @@ define i1 @f3(i32 %a) {
     %tmp1 = icmp eq i32 %tmp, 0
     ret i1 %tmp1
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	tst.w	{{.*}}, #11141290
 
 ; 0xcc00cc00 = 3422604288
@@ -27,7 +27,7 @@ define i1 @f6(i32 %a) {
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: 	tst.w	{{.*}}, #-872363008
 
 ; 0xdddddddd = 3722304989
@@ -36,7 +36,7 @@ define i1 @f7(i32 %a) {
     %tmp1 = icmp eq i32 %tmp, 0
     ret i1 %tmp1
 }
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: 	tst.w	{{.*}}, #-572662307
 
 ; 0x00110000 = 1114112
@@ -45,5 +45,5 @@ define i1 @f10(i32 %a) {
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: 	tst.w	{{.*}}, #1114112
diff --git a/test/CodeGen/Thumb2/thumb2-tst2.ll b/test/CodeGen/Thumb2/thumb2-tst2.ll
index e3fe792..f71e91d 100644
--- a/test/CodeGen/Thumb2/thumb2-tst2.ll
+++ b/test/CodeGen/Thumb2/thumb2-tst2.ll
@@ -4,7 +4,7 @@
 ; tst as 'mov.w r0, #0'.
 
 define i1 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: tst {{.*}}, r1
     %tmp = and i32 %a, %b
     %tmp1 = icmp eq i32 %tmp, 0
@@ -12,7 +12,7 @@ define i1 @f2(i32 %a, i32 %b) {
 }
 
 define i1 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: tst {{.*}}, r1
     %tmp = and i32 %a, %b
     %tmp1 = icmp eq i32 0, %tmp
@@ -20,7 +20,7 @@ define i1 @f4(i32 %a, i32 %b) {
 }
 
 define i1 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: tst.w {{.*}}, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = and i32 %a, %tmp
@@ -29,7 +29,7 @@ define i1 @f6(i32 %a, i32 %b) {
 }
 
 define i1 @f7(i32 %a, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: tst.w {{.*}}, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = and i32 %a, %tmp
@@ -38,7 +38,7 @@ define i1 @f7(i32 %a, i32 %b) {
 }
 
 define i1 @f8(i32 %a, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: tst.w {{.*}}, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = and i32 %a, %tmp
@@ -47,7 +47,7 @@ define i1 @f8(i32 %a, i32 %b) {
 }
 
 define i1 @f9(i32 %a, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: tst.w {{.*}}, {{.*}}, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/tls2.ll b/test/CodeGen/Thumb2/tls2.ll
index b8a0657..6cb019f 100644
--- a/test/CodeGen/Thumb2/tls2.ll
+++ b/test/CodeGen/Thumb2/tls2.ll
@@ -5,12 +5,12 @@
 
 define i32 @f() {
 entry:
-; CHECK-NOT-PIC: f:
+; CHECK-NOT-PIC-LABEL: f:
 ; CHECK-NOT-PIC: add r0, pc
 ; CHECK-NOT-PIC: ldr r1, [r0]
 ; CHECK-NOT-PIC: i(gottpoff)
 
-; CHECK-PIC: f:
+; CHECK-PIC-LABEL: f:
 ; CHECK-PIC: bl __tls_get_addr(PLT)
 	%tmp1 = load i32* @i		; <i32> [#uses=1]
 	ret i32 %tmp1
@@ -18,12 +18,12 @@ entry:
 
 define i32* @g() {
 entry:
-; CHECK-NOT-PIC: g:
+; CHECK-NOT-PIC-LABEL: g:
 ; CHECK-NOT-PIC: add r0, pc
 ; CHECK-NOT-PIC: ldr r1, [r0]
 ; CHECK-NOT-PIC: i(gottpoff)
 
-; CHECK-PIC: g:
+; CHECK-PIC-LABEL: g:
 ; CHECK-PIC: bl __tls_get_addr(PLT)
 	ret i32* @i
 }
diff --git a/test/CodeGen/X86/2006-11-12-CSRetCC.ll b/test/CodeGen/X86/2006-11-12-CSRetCC.ll
index a58c9b1..d7af1c3 100644
--- a/test/CodeGen/X86/2006-11-12-CSRetCC.ll
+++ b/test/CodeGen/X86/2006-11-12-CSRetCC.ll
@@ -4,7 +4,7 @@ target triple = "i686-pc-linux-gnu"
 @str = internal constant [9 x i8] c"%f+%f*i\0A\00"              ; <[9 x i8]*> [#uses=1]
 
 define i32 @main() {
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK-NOT: ret
 ; CHECK: subl $4, %{{.*}}
 ; CHECK: ret
diff --git a/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll b/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
index f7ffb93..88057c8 100644
--- a/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
+++ b/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
@@ -7,7 +7,7 @@ entry:
 	%tmp2 = call x86_fp80 @llvm.sqrt.f80( x86_fp80 %x )
 	ret x86_fp80 %tmp2
         
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: fldt 4(%esp)
 ; CHECK-NEXT: fsqrt
 ; CHECK-NEXT: ret
@@ -19,7 +19,7 @@ define x86_fp80 @bar(x86_fp80 %x) nounwind {
 entry:
 	%tmp2 = call x86_fp80 @llvm.powi.f80( x86_fp80 %x, i32 3 )
 	ret x86_fp80 %tmp2
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: fldt 4(%esp)
 ; CHECK-NEXT: fld	%st(0)
 ; CHECK-NEXT: fmul	%st(1)
diff --git a/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll b/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll
index fc38135..da56ce7 100644
--- a/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll
+++ b/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll
@@ -8,7 +8,7 @@ entry:
         ret void
 }
 
-; CHECK: a:
+; CHECK-LABEL: a:
 ; CHECK: movups
 ; CHECK: movups
 ; CHECK-NOT: movups
diff --git a/test/CodeGen/X86/2008-08-19-SubAndFetch.ll b/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
index 360ec73..9324d5d 100644
--- a/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
+++ b/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
@@ -4,7 +4,7 @@
 
 define i32 @main() nounwind {
 entry:
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK: lock
 ; CHECK: decq
 	atomicrmw sub i64* @var, i64 1 monotonic
diff --git a/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll b/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
index d64c966..7549651 100644
--- a/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
+++ b/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
@@ -5,7 +5,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 target triple = "i386-apple-darwin9.6"
 
 define void @f() nounwind {
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK-NOT: ret
 ; CHECK: foo $-81920
 ; CHECK-NOT: ret
diff --git a/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll b/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll
index 3cd5416..7c87598 100644
--- a/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll
+++ b/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll
@@ -9,7 +9,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define i64 @foo(i64 %b) nounwind readnone {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: shlq $56, %rdi
 ; CHECK: sarq $48, %rdi
 ; CHECK: leaq 1(%rdi), %rax
diff --git a/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll b/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll
index 80b8835..0268d81 100644
--- a/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll
+++ b/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=i386-apple-darwin10.0 -relocation-model=pic | FileCheck %s
 
 define void @dot(i16* nocapture %A, i32 %As, i16* nocapture %B, i32 %Bs, i16* nocapture %C, i32 %N) nounwind ssp {
-; CHECK: dot:
+; CHECK-LABEL: dot:
 ; CHECK: decl %
 ; CHECK-NEXT: jne
 entry:
diff --git a/test/CodeGen/X86/2009-11-16-MachineLICM.ll b/test/CodeGen/X86/2009-11-16-MachineLICM.ll
index 2ac688f..fedb2a5 100644
--- a/test/CodeGen/X86/2009-11-16-MachineLICM.ll
+++ b/test/CodeGen/X86/2009-11-16-MachineLICM.ll
@@ -5,7 +5,7 @@
 
 define void @foo(i32 %n, float* nocapture %x) nounwind ssp {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
   %0 = icmp sgt i32 %n, 0                         ; <i1> [#uses=1]
   br i1 %0, label %bb.nph, label %return
 
diff --git a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll
index c2d9d84..08a99e3 100644
--- a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll
+++ b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll
@@ -5,7 +5,7 @@
 
 define void @t(i32 %count) ssp nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movups L_str+12(%rip), %xmm0
 ; CHECK: movups L_str(%rip), %xmm1
   %tmp0 = alloca [60 x i8], align 1
diff --git a/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll b/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
index 0700323..b166447 100644
--- a/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
+++ b/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
@@ -3,7 +3,7 @@
 
 define void @t() nounwind ssp {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movl %ecx, %eax
 ; CHECK: %eax = foo (%eax, %ecx)
   %b = alloca i32                                 ; <i32*> [#uses=2]
@@ -21,7 +21,7 @@ return:                                           ; preds = %entry
 
 define void @t2() nounwind ssp {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: movl
 ; CHECK: [[D2:%e.x]] = foo
 ; CHECK: ([[D2]],
diff --git a/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll b/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll
index 823e0ca..65b70a7 100644
--- a/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll
+++ b/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll
@@ -18,7 +18,7 @@ target triple = "x86_64-unknown-linux-gnu"
 @_dm_offset_addr_mask = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0]
 
 define void @leaf() nounwind {
-; CHECK: leaf:
+; CHECK-LABEL: leaf:
 ; CHECK-NOT: -8(%rsp)
 ; CHECK: leaq link_ptr@TLSGD
 ; CHECK: callq __tls_get_addr@PLT
diff --git a/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll b/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
index 3d058bc..f9bf310 100644
--- a/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
+++ b/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
@@ -6,7 +6,7 @@
 
 define void @t(i64* nocapture %p) nounwind ssp {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movl ([[REG:%[a-z]+]]), %eax
 ; CHECK: movl 4([[REG]]), %edx
 ; CHECK: LBB0_1:
diff --git a/test/CodeGen/X86/2010-02-23-DAGCombineBug.ll b/test/CodeGen/X86/2010-02-23-DAGCombineBug.ll
index 6a58e9e..a8c87fa 100644
--- a/test/CodeGen/X86/2010-02-23-DAGCombineBug.ll
+++ b/test/CodeGen/X86/2010-02-23-DAGCombineBug.ll
@@ -2,7 +2,7 @@
 
 define i32* @t() nounwind optsize ssp {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: testl %eax, %eax
 ; CHECK: js
   %cmp = icmp slt i32 undef, 0                    ; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
index 9a5958e..5e86ecf 100644
--- a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
+++ b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
@@ -11,7 +11,7 @@
 
 define void @t(%struct.F* %this) nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: addq $12, %rsi
   %BitValueArray = alloca [32 x i32], align 4
   %tmp2 = getelementptr inbounds %struct.F* %this, i64 0, i32 0
diff --git a/test/CodeGen/X86/2010-07-29-SetccSimplify.ll b/test/CodeGen/X86/2010-07-29-SetccSimplify.ll
index 96016cf..47e511f 100644
--- a/test/CodeGen/X86/2010-07-29-SetccSimplify.ll
+++ b/test/CodeGen/X86/2010-07-29-SetccSimplify.ll
@@ -9,6 +9,6 @@ entry:
   ret i32 %3
 }
 
-; CHECK: extend2bit_v2:
+; CHECK-LABEL: extend2bit_v2:
 ; CHECK: xorl	%eax, %eax
 ; CHECK-NEXT: ret
diff --git a/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll b/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll
index 7632034..aea53b3 100644
--- a/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll
+++ b/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll
@@ -16,5 +16,5 @@ entry:
   %tmp10 = sext i8 %tmp9 to i32
   ret i32 %tmp10
 }
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: movsbl	-2147483647
diff --git a/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll b/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll
index fcaabdd..df9823a 100644
--- a/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll
+++ b/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll
@@ -2,7 +2,7 @@
 ; PR11494
 
 define void @test(<4 x i32>* nocapture %p) nounwind {
-  ; CHECK: test:
+  ; CHECK-LABEL: test:
   ; CHECK: vpxor %xmm0, %xmm0, %xmm0
   ; CHECK-NEXT: vpmaxsd {{.*}}, %xmm0, %xmm0
   ; CHECK-NEXT: vmovdqu	%xmm0, (%rdi)
diff --git a/test/CodeGen/X86/2012-04-26-sdglue.ll b/test/CodeGen/X86/2012-04-26-sdglue.ll
index 0465952..186fafb 100644
--- a/test/CodeGen/X86/2012-04-26-sdglue.ll
+++ b/test/CodeGen/X86/2012-04-26-sdglue.ll
@@ -4,7 +4,7 @@
 
 ; It's hard to test for the ISEL condition because CodeGen optimizes
 ; away the bugpointed code. Just ensure the basics are still there.
-;CHECK: func:
+;CHECK-LABEL: func:
 ;CHECK: vxorps
 ;CHECK: vinsertf128
 ;CHECK: vpshufd
diff --git a/test/CodeGen/X86/2012-05-17-TwoAddressBug.ll b/test/CodeGen/X86/2012-05-17-TwoAddressBug.ll
index 171c3f1..881fa37 100644
--- a/test/CodeGen/X86/2012-05-17-TwoAddressBug.ll
+++ b/test/CodeGen/X86/2012-05-17-TwoAddressBug.ll
@@ -6,7 +6,7 @@
 ; rdar://11472010
 define i32 @t(i32 %mask) nounwind readnone ssp {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK-NOT: mov
   %sub = add i32 %mask, -65535
   %shr = lshr i32 %sub, 23
diff --git a/test/CodeGen/X86/2012-08-07-CmpISelBug.ll b/test/CodeGen/X86/2012-08-07-CmpISelBug.ll
index 000b853..eba970e 100644
--- a/test/CodeGen/X86/2012-08-07-CmpISelBug.ll
+++ b/test/CodeGen/X86/2012-08-07-CmpISelBug.ll
@@ -6,7 +6,7 @@
 
 define void @foo(i8 %arg4, i32 %arg5, i32* %arg14) nounwind {
 bb:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NOT: testl
 ; CHECK: testb
   %tmp48 = zext i8 %arg4 to i32
diff --git a/test/CodeGen/X86/2012-08-16-setcc.ll b/test/CodeGen/X86/2012-08-16-setcc.ll
index ed51156..c03b923 100644
--- a/test/CodeGen/X86/2012-08-16-setcc.ll
+++ b/test/CodeGen/X86/2012-08-16-setcc.ll
@@ -2,7 +2,7 @@
 
 ; rdar://12081007
 
-; CHECK: and_1:
+; CHECK-LABEL: and_1:
 ; CHECK: andb
 ; CHECK-NEXT: cmovnel
 ; CHECK: ret
@@ -13,7 +13,7 @@ define i32 @and_1(i8 zeroext %a, i8 zeroext %b, i32 %x) {
   ret i32 %3
 }
 
-; CHECK: and_2:
+; CHECK-LABEL: and_2:
 ; CHECK: andb
 ; CHECK-NEXT: setne
 ; CHECK: ret
@@ -23,7 +23,7 @@ define zeroext i1 @and_2(i8 zeroext %a, i8 zeroext %b) {
   ret i1 %2
 }
 
-; CHECK: xor_1:
+; CHECK-LABEL: xor_1:
 ; CHECK: xorb
 ; CHECK-NEXT: cmovnel
 ; CHECK: ret
@@ -34,7 +34,7 @@ define i32 @xor_1(i8 zeroext %a, i8 zeroext %b, i32 %x) {
   ret i32 %3
 }
 
-; CHECK: xor_2:
+; CHECK-LABEL: xor_2:
 ; CHECK: xorb
 ; CHECK-NEXT: setne
 ; CHECK: ret
diff --git a/test/CodeGen/X86/2012-08-17-legalizer-crash.ll b/test/CodeGen/X86/2012-08-17-legalizer-crash.ll
index cb9fa2e..971e56d 100644
--- a/test/CodeGen/X86/2012-08-17-legalizer-crash.ll
+++ b/test/CodeGen/X86/2012-08-17-legalizer-crash.ll
@@ -25,7 +25,7 @@ if.then:                                          ; preds = %entry
 if.end:                                           ; preds = %if.then, %entry
   ret void
 
-; CHECK: fn1:
+; CHECK-LABEL: fn1:
 ; CHECK: shrq $32, [[REG:%.*]]
 ; CHECK: je
 }
diff --git a/test/CodeGen/X86/3addr-16bit.ll b/test/CodeGen/X86/3addr-16bit.ll
index c51247a..77c3c16 100644
--- a/test/CodeGen/X86/3addr-16bit.ll
+++ b/test/CodeGen/X86/3addr-16bit.ll
@@ -5,12 +5,12 @@
 
 define zeroext i16 @t1(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
-; 32BIT:     t1:
+; 32BIT-LABEL:     t1:
 ; 32BIT:     movw 20(%esp), %ax
 ; 32BIT-NOT: movw %ax, %cx
 ; 32BIT:     leal 1(%eax), %ecx
 
-; 64BIT:     t1:
+; 64BIT-LABEL:     t1:
 ; 64BIT-NOT: movw %si, %ax
 ; 64BIT:     leal 1(%rsi), %eax
   %0 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
@@ -27,12 +27,12 @@ bb1:                                              ; preds = %entry
 
 define zeroext i16 @t2(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
-; 32BIT:     t2:
+; 32BIT-LABEL:     t2:
 ; 32BIT:     movw 20(%esp), %ax
 ; 32BIT-NOT: movw %ax, %cx
 ; 32BIT:     leal -1(%eax), %ecx
 
-; 64BIT:     t2:
+; 64BIT-LABEL:     t2:
 ; 64BIT-NOT: movw %si, %ax
 ; 64BIT:     leal -1(%rsi), %eax
   %0 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
@@ -51,12 +51,12 @@ declare void @foo(i16 zeroext)
 
 define zeroext i16 @t3(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
-; 32BIT:     t3:
+; 32BIT-LABEL:     t3:
 ; 32BIT:     movw 20(%esp), %ax
 ; 32BIT-NOT: movw %ax, %cx
 ; 32BIT:     leal 2(%eax), %ecx
 
-; 64BIT:     t3:
+; 64BIT-LABEL:     t3:
 ; 64BIT-NOT: movw %si, %ax
 ; 64BIT:     leal 2(%rsi), %eax
   %0 = add i16 %k, 2                              ; <i16> [#uses=3]
@@ -73,13 +73,13 @@ bb1:                                              ; preds = %entry
 
 define zeroext i16 @t4(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
-; 32BIT:     t4:
+; 32BIT-LABEL:     t4:
 ; 32BIT:     movw 16(%esp), %ax
 ; 32BIT:     movw 20(%esp), %cx
 ; 32BIT-NOT: movw %cx, %dx
 ; 32BIT:     leal (%ecx,%eax), %edx
 
-; 64BIT:     t4:
+; 64BIT-LABEL:     t4:
 ; 64BIT-NOT: movw %si, %ax
 ; 64BIT:     leal (%rsi,%rdi), %eax
   %0 = add i16 %k, %c                             ; <i16> [#uses=3]
diff --git a/test/CodeGen/X86/abi-isel.ll b/test/CodeGen/X86/abi-isel.ll
index 955fc62..3b84231 100644
--- a/test/CodeGen/X86/abi-isel.ll
+++ b/test/CodeGen/X86/abi-isel.ll
@@ -37,22 +37,22 @@ entry:
 	store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 0), align 4
 	ret void
 
-; LINUX-64-STATIC: foo00:
+; LINUX-64-STATIC-LABEL: foo00:
 ; LINUX-64-STATIC: movl	src(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl	[[EAX]], dst
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo00:
+; LINUX-32-STATIC-LABEL: foo00:
 ; LINUX-32-STATIC: 	movl	src, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dst
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo00:
+; LINUX-32-PIC-LABEL: foo00:
 ; LINUX-32-PIC: 	movl	src, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dst
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo00:
+; LINUX-64-PIC-LABEL: foo00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r..]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e..]]
 ; LINUX-64-PIC-NEXT: 	movq	dst@GOTPCREL(%rip), [[RCX:%r..]]
@@ -109,22 +109,22 @@ entry:
 	store i32 %0, i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 0), align 4
 	ret void
 
-; LINUX-64-STATIC: fxo00:
+; LINUX-64-STATIC-LABEL: fxo00:
 ; LINUX-64-STATIC: movl	xsrc(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl	[[EAX]], xdst
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: fxo00:
+; LINUX-32-STATIC-LABEL: fxo00:
 ; LINUX-32-STATIC: 	movl	xsrc, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], xdst
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: fxo00:
+; LINUX-32-PIC-LABEL: fxo00:
 ; LINUX-32-PIC: 	movl	xsrc, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], xdst
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: fxo00:
+; LINUX-64-PIC-LABEL: fxo00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	xdst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -179,19 +179,19 @@ define void @foo01() nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @dst, i32 0, i32 0), i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: foo01:
+; LINUX-64-STATIC-LABEL: foo01:
 ; LINUX-64-STATIC: movq	$dst, ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo01:
+; LINUX-32-STATIC-LABEL: foo01:
 ; LINUX-32-STATIC: 	movl	$dst, ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo01:
+; LINUX-32-PIC-LABEL: foo01:
 ; LINUX-32-PIC: 	movl	$dst, ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo01:
+; LINUX-64-PIC-LABEL: foo01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
@@ -239,19 +239,19 @@ define void @fxo01() nounwind {
 entry:
 	store i32* getelementptr ([32 x i32]* @xdst, i32 0, i32 0), i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: fxo01:
+; LINUX-64-STATIC-LABEL: fxo01:
 ; LINUX-64-STATIC: movq	$xdst, ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: fxo01:
+; LINUX-32-STATIC-LABEL: fxo01:
 ; LINUX-32-STATIC: 	movl	$xdst, ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: fxo01:
+; LINUX-32-PIC-LABEL: fxo01:
 ; LINUX-32-PIC: 	movl	$xdst, ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: fxo01:
+; LINUX-64-PIC-LABEL: fxo01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
@@ -301,25 +301,25 @@ entry:
 	%1 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 0), align 4
 	store i32 %1, i32* %0, align 4
 	ret void
-; LINUX-64-STATIC: foo02:
+; LINUX-64-STATIC-LABEL: foo02:
 ; LINUX-64-STATIC: movl    src(%rip), %
 ; LINUX-64-STATIC: movq    ptr(%rip), %
 ; LINUX-64-STATIC: movl
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo02:
+; LINUX-32-STATIC-LABEL: foo02:
 ; LINUX-32-STATIC: 	movl	src, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo02:
+; LINUX-32-PIC-LABEL: foo02:
 ; LINUX-32-PIC: 	movl	src, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo02:
+; LINUX-64-PIC-LABEL: foo02:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -382,26 +382,26 @@ entry:
 	%0 = load i32** @ptr, align 8
 	%1 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 0), align 4
 	store i32 %1, i32* %0, align 4
-; LINUX-64-STATIC: fxo02:
+; LINUX-64-STATIC-LABEL: fxo02:
 ; LINUX-64-STATIC: movl    xsrc(%rip), %
 ; LINUX-64-STATIC: movq    ptr(%rip), %
 ; LINUX-64-STATIC: movl
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: fxo02:
+; LINUX-32-STATIC-LABEL: fxo02:
 ; LINUX-32-STATIC: 	movl	xsrc, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
-; LINUX-32-PIC: fxo02:
+; LINUX-32-PIC-LABEL: fxo02:
 ; LINUX-32-PIC: 	movl	xsrc, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: fxo02:
+; LINUX-64-PIC-LABEL: fxo02:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -464,22 +464,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 0), align 32
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 0), align 32
 	ret void
-; LINUX-64-STATIC: foo03:
+; LINUX-64-STATIC-LABEL: foo03:
 ; LINUX-64-STATIC: movl    dsrc(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ddst
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo03:
+; LINUX-32-STATIC-LABEL: foo03:
 ; LINUX-32-STATIC: 	movl	dsrc, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ddst
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo03:
+; LINUX-32-PIC-LABEL: foo03:
 ; LINUX-32-PIC: 	movl	dsrc, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ddst
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo03:
+; LINUX-64-PIC-LABEL: foo03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ddst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -524,19 +524,19 @@ define void @foo04() nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i32 0), i32** @dptr, align 8
 	ret void
-; LINUX-64-STATIC: foo04:
+; LINUX-64-STATIC-LABEL: foo04:
 ; LINUX-64-STATIC: movq    $ddst, dptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo04:
+; LINUX-32-STATIC-LABEL: foo04:
 ; LINUX-32-STATIC: 	movl	$ddst, dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo04:
+; LINUX-32-PIC-LABEL: foo04:
 ; LINUX-32-PIC: 	movl	$ddst, dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo04:
+; LINUX-64-PIC-LABEL: foo04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
@@ -580,25 +580,25 @@ entry:
 	%1 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 0), align 32
 	store i32 %1, i32* %0, align 4
 	ret void
-; LINUX-64-STATIC: foo05:
+; LINUX-64-STATIC-LABEL: foo05:
 ; LINUX-64-STATIC: movl    dsrc(%rip), %
 ; LINUX-64-STATIC: movq    dptr(%rip), %
 ; LINUX-64-STATIC: movl
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo05:
+; LINUX-32-STATIC-LABEL: foo05:
 ; LINUX-32-STATIC: 	movl	dsrc, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo05:
+; LINUX-32-PIC-LABEL: foo05:
 ; LINUX-32-PIC: 	movl	dsrc, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo05:
+; LINUX-64-PIC-LABEL: foo05:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -651,22 +651,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 0), align 4
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 0), align 4
 	ret void
-; LINUX-64-STATIC: foo06:
+; LINUX-64-STATIC-LABEL: foo06:
 ; LINUX-64-STATIC: movl    lsrc(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ldst(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo06:
+; LINUX-32-STATIC-LABEL: foo06:
 ; LINUX-32-STATIC: 	movl	lsrc, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ldst
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo06:
+; LINUX-32-PIC-LABEL: foo06:
 ; LINUX-32-PIC: 	movl	lsrc, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ldst
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo06:
+; LINUX-64-PIC-LABEL: foo06:
 ; LINUX-64-PIC: 	movl	lsrc(%rip), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ldst(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
@@ -709,19 +709,19 @@ define void @foo07() nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i32 0), i32** @lptr, align 8
 	ret void
-; LINUX-64-STATIC: foo07:
+; LINUX-64-STATIC-LABEL: foo07:
 ; LINUX-64-STATIC: movq    $ldst, lptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo07:
+; LINUX-32-STATIC-LABEL: foo07:
 ; LINUX-32-STATIC: 	movl	$ldst, lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo07:
+; LINUX-32-PIC-LABEL: foo07:
 ; LINUX-32-PIC: 	movl	$ldst, lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo07:
+; LINUX-64-PIC-LABEL: foo07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
@@ -764,25 +764,25 @@ entry:
 	%1 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 0), align 4
 	store i32 %1, i32* %0, align 4
 	ret void
-; LINUX-64-STATIC: foo08:
+; LINUX-64-STATIC-LABEL: foo08:
 ; LINUX-64-STATIC: movl    lsrc(%rip), %
 ; LINUX-64-STATIC: movq    lptr(%rip), %
 ; LINUX-64-STATIC: movl
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo08:
+; LINUX-32-STATIC-LABEL: foo08:
 ; LINUX-32-STATIC: 	movl	lsrc, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo08:
+; LINUX-32-PIC-LABEL: foo08:
 ; LINUX-32-PIC: 	movl	lsrc, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo08:
+; LINUX-64-PIC-LABEL: foo08:
 ; LINUX-64-PIC: 	movl	lsrc(%rip), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
@@ -833,22 +833,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16), align 4
 	store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16), align 4
 	ret void
-; LINUX-64-STATIC: qux00:
+; LINUX-64-STATIC-LABEL: qux00:
 ; LINUX-64-STATIC: movl    src+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], dst+64(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux00:
+; LINUX-32-STATIC-LABEL: qux00:
 ; LINUX-32-STATIC: 	movl	src+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dst+64
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qux00:
+; LINUX-32-PIC-LABEL: qux00:
 ; LINUX-32-PIC: 	movl	src+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dst+64
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux00:
+; LINUX-64-PIC-LABEL: qux00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -904,22 +904,22 @@ entry:
 	%0 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16), align 4
 	store i32 %0, i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16), align 4
 	ret void
-; LINUX-64-STATIC: qxx00:
+; LINUX-64-STATIC-LABEL: qxx00:
 ; LINUX-64-STATIC: movl    xsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], xdst+64(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qxx00:
+; LINUX-32-STATIC-LABEL: qxx00:
 ; LINUX-32-STATIC: 	movl	xsrc+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], xdst+64
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qxx00:
+; LINUX-32-PIC-LABEL: qxx00:
 ; LINUX-32-PIC: 	movl	xsrc+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], xdst+64
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qxx00:
+; LINUX-64-PIC-LABEL: qxx00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	xdst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -974,19 +974,19 @@ define void @qux01() nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16), i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: qux01:
+; LINUX-64-STATIC-LABEL: qux01:
 ; LINUX-64-STATIC: movq    $dst+64, ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux01:
+; LINUX-32-STATIC-LABEL: qux01:
 ; LINUX-32-STATIC: 	movl	$dst+64, ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qux01:
+; LINUX-32-PIC-LABEL: qux01:
 ; LINUX-32-PIC: 	movl	$dst+64, ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux01:
+; LINUX-64-PIC-LABEL: qux01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	addq	$64, [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1040,19 +1040,19 @@ define void @qxx01() nounwind {
 entry:
 	store i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16), i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: qxx01:
+; LINUX-64-STATIC-LABEL: qxx01:
 ; LINUX-64-STATIC: movq    $xdst+64, ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qxx01:
+; LINUX-32-STATIC-LABEL: qxx01:
 ; LINUX-32-STATIC: 	movl	$xdst+64, ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qxx01:
+; LINUX-32-PIC-LABEL: qxx01:
 ; LINUX-32-PIC: 	movl	$xdst+64, ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qxx01:
+; LINUX-64-PIC-LABEL: qxx01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	addq	$64, [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1108,26 +1108,26 @@ entry:
 	%1 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16), align 4
 	%2 = getelementptr i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
-; LINUX-64-STATIC: qux02:
+; LINUX-64-STATIC-LABEL: qux02:
 ; LINUX-64-STATIC: movl    src+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]])
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux02:
+; LINUX-32-STATIC-LABEL: qux02:
 ; LINUX-32-STATIC: 	movl	src+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
-; LINUX-32-PIC: qux02:
+; LINUX-32-PIC-LABEL: qux02:
 ; LINUX-32-PIC: 	movl	src+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux02:
+; LINUX-64-PIC-LABEL: qux02:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1191,26 +1191,26 @@ entry:
 	%1 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16), align 4
 	%2 = getelementptr i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
-; LINUX-64-STATIC: qxx02:
+; LINUX-64-STATIC-LABEL: qxx02:
 ; LINUX-64-STATIC: movl    xsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]])
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qxx02:
+; LINUX-32-STATIC-LABEL: qxx02:
 ; LINUX-32-STATIC: 	movl	xsrc+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
-; LINUX-32-PIC: qxx02:
+; LINUX-32-PIC-LABEL: qxx02:
 ; LINUX-32-PIC: 	movl	xsrc+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qxx02:
+; LINUX-64-PIC-LABEL: qxx02:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1273,22 +1273,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16), align 32
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16), align 32
 	ret void
-; LINUX-64-STATIC: qux03:
+; LINUX-64-STATIC-LABEL: qux03:
 ; LINUX-64-STATIC: movl    dsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ddst+64(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux03:
+; LINUX-32-STATIC-LABEL: qux03:
 ; LINUX-32-STATIC: 	movl	dsrc+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ddst+64
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qux03:
+; LINUX-32-PIC-LABEL: qux03:
 ; LINUX-32-PIC: 	movl	dsrc+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ddst+64
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux03:
+; LINUX-64-PIC-LABEL: qux03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ddst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1333,19 +1333,19 @@ define void @qux04() nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16), i32** @dptr, align 8
 	ret void
-; LINUX-64-STATIC: qux04:
+; LINUX-64-STATIC-LABEL: qux04:
 ; LINUX-64-STATIC: movq    $ddst+64, dptr(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux04:
+; LINUX-32-STATIC-LABEL: qux04:
 ; LINUX-32-STATIC: 	movl	$ddst+64, dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qux04:
+; LINUX-32-PIC-LABEL: qux04:
 ; LINUX-32-PIC: 	movl	$ddst+64, dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux04:
+; LINUX-64-PIC-LABEL: qux04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	addq	$64, [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1390,26 +1390,26 @@ entry:
 	%1 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16), align 32
 	%2 = getelementptr i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
-; LINUX-64-STATIC: qux05:
+; LINUX-64-STATIC-LABEL: qux05:
 ; LINUX-64-STATIC: movl    dsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]])
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux05:
+; LINUX-32-STATIC-LABEL: qux05:
 ; LINUX-32-STATIC: 	movl	dsrc+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
-; LINUX-32-PIC: qux05:
+; LINUX-32-PIC-LABEL: qux05:
 ; LINUX-32-PIC: 	movl	dsrc+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux05:
+; LINUX-64-PIC-LABEL: qux05:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1462,22 +1462,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16), align 4
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16), align 4
 	ret void
-; LINUX-64-STATIC: qux06:
+; LINUX-64-STATIC-LABEL: qux06:
 ; LINUX-64-STATIC: movl    lsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ldst+64
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux06:
+; LINUX-32-STATIC-LABEL: qux06:
 ; LINUX-32-STATIC: 	movl	lsrc+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ldst+64
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qux06:
+; LINUX-32-PIC-LABEL: qux06:
 ; LINUX-32-PIC: 	movl	lsrc+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ldst+64
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux06:
+; LINUX-64-PIC-LABEL: qux06:
 ; LINUX-64-PIC: 	movl	lsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ldst+64(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
@@ -1520,19 +1520,19 @@ define void @qux07() nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16), i32** @lptr, align 8
 	ret void
-; LINUX-64-STATIC: qux07:
+; LINUX-64-STATIC-LABEL: qux07:
 ; LINUX-64-STATIC: movq    $ldst+64, lptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux07:
+; LINUX-32-STATIC-LABEL: qux07:
 ; LINUX-32-STATIC: 	movl	$ldst+64, lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qux07:
+; LINUX-32-PIC-LABEL: qux07:
 ; LINUX-32-PIC: 	movl	$ldst+64, lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux07:
+; LINUX-64-PIC-LABEL: qux07:
 ; LINUX-64-PIC: 	leaq	ldst+64(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
@@ -1575,26 +1575,26 @@ entry:
 	%1 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16), align 4
 	%2 = getelementptr i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
-; LINUX-64-STATIC: qux08:
+; LINUX-64-STATIC-LABEL: qux08:
 ; LINUX-64-STATIC: movl    lsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]])
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux08:
+; LINUX-32-STATIC-LABEL: qux08:
 ; LINUX-32-STATIC: 	movl	lsrc+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
-; LINUX-32-PIC: qux08:
+; LINUX-32-PIC-LABEL: qux08:
 ; LINUX-32-PIC: 	movl	lsrc+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux08:
+; LINUX-64-PIC-LABEL: qux08:
 ; LINUX-64-PIC: 	movl	lsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
@@ -1647,24 +1647,24 @@ entry:
 	%2 = getelementptr [131072 x i32]* @dst, i64 0, i64 %i
 	store i32 %1, i32* %2, align 4
 	ret void
-; LINUX-64-STATIC: ind00:
+; LINUX-64-STATIC-LABEL: ind00:
 ; LINUX-64-STATIC: movl    src(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], dst(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind00:
+; LINUX-32-STATIC-LABEL: ind00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	src(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], dst(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind00:
+; LINUX-32-PIC-LABEL: ind00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	src(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], dst(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind00:
+; LINUX-64-PIC-LABEL: ind00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1725,24 +1725,24 @@ entry:
 	%2 = getelementptr [32 x i32]* @xdst, i64 0, i64 %i
 	store i32 %1, i32* %2, align 4
 	ret void
-; LINUX-64-STATIC: ixd00:
+; LINUX-64-STATIC-LABEL: ixd00:
 ; LINUX-64-STATIC: movl    xsrc(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], xdst(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ixd00:
+; LINUX-32-STATIC-LABEL: ixd00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	xsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], xdst(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ixd00:
+; LINUX-32-PIC-LABEL: ixd00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	xsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], xdst(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ixd00:
+; LINUX-64-PIC-LABEL: ixd00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	xdst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1801,24 +1801,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %i
 	store i32* %0, i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: ind01:
+; LINUX-64-STATIC-LABEL: ind01:
 ; LINUX-64-STATIC: leaq    dst(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind01:
+; LINUX-32-STATIC-LABEL: ind01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	dst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind01:
+; LINUX-32-PIC-LABEL: ind01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	dst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind01:
+; LINUX-64-PIC-LABEL: ind01:
 ; LINUX-64-PIC: 	shlq	$2, %rdi
 ; LINUX-64-PIC-NEXT: 	addq	dst@GOTPCREL(%rip), %rdi
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RAX:%r.x]]
@@ -1877,24 +1877,24 @@ entry:
 	%0 = getelementptr [32 x i32]* @xdst, i64 0, i64 %i
 	store i32* %0, i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: ixd01:
+; LINUX-64-STATIC-LABEL: ixd01:
 ; LINUX-64-STATIC: leaq    xdst(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ixd01:
+; LINUX-32-STATIC-LABEL: ixd01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	xdst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ixd01:
+; LINUX-32-PIC-LABEL: ixd01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	xdst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ixd01:
+; LINUX-64-PIC-LABEL: ixd01:
 ; LINUX-64-PIC: 	shlq	$2, %rdi
 ; LINUX-64-PIC-NEXT: 	addq	xdst@GOTPCREL(%rip), %rdi
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RAX:%r.x]]
@@ -1956,27 +1956,27 @@ entry:
 	%3 = getelementptr i32* %0, i64 %i
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: ind02:
+; LINUX-64-STATIC-LABEL: ind02:
 ; LINUX-64-STATIC: movl    src(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind02:
+; LINUX-32-STATIC-LABEL: ind02:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	src(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind02:
+; LINUX-32-PIC-LABEL: ind02:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	src(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind02:
+; LINUX-64-PIC-LABEL: ind02:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2045,27 +2045,27 @@ entry:
 	%3 = getelementptr i32* %0, i64 %i
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: ixd02:
+; LINUX-64-STATIC-LABEL: ixd02:
 ; LINUX-64-STATIC: movl    xsrc(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ixd02:
+; LINUX-32-STATIC-LABEL: ixd02:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	xsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ixd02:
+; LINUX-32-PIC-LABEL: ixd02:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	xsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ixd02:
+; LINUX-64-PIC-LABEL: ixd02:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2133,24 +2133,24 @@ entry:
 	%2 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %i
 	store i32 %1, i32* %2, align 4
 	ret void
-; LINUX-64-STATIC: ind03:
+; LINUX-64-STATIC-LABEL: ind03:
 ; LINUX-64-STATIC: movl    dsrc(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ddst(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind03:
+; LINUX-32-STATIC-LABEL: ind03:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ddst(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind03:
+; LINUX-32-PIC-LABEL: ind03:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ddst(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind03:
+; LINUX-64-PIC-LABEL: ind03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ddst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2205,24 +2205,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %i
 	store i32* %0, i32** @dptr, align 8
 	ret void
-; LINUX-64-STATIC: ind04:
+; LINUX-64-STATIC-LABEL: ind04:
 ; LINUX-64-STATIC: leaq    ddst(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], dptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind04:
+; LINUX-32-STATIC-LABEL: ind04:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ddst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind04:
+; LINUX-32-PIC-LABEL: ind04:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ddst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind04:
+; LINUX-64-PIC-LABEL: ind04:
 ; LINUX-64-PIC: 	shlq	$2, %rdi
 ; LINUX-64-PIC-NEXT: 	addq	ddst@GOTPCREL(%rip), %rdi
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RAX:%r.x]]
@@ -2277,27 +2277,27 @@ entry:
 	%3 = getelementptr i32* %0, i64 %i
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: ind05:
+; LINUX-64-STATIC-LABEL: ind05:
 ; LINUX-64-STATIC: movl    dsrc(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind05:
+; LINUX-32-STATIC-LABEL: ind05:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind05:
+; LINUX-32-PIC-LABEL: ind05:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind05:
+; LINUX-64-PIC-LABEL: ind05:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2358,24 +2358,24 @@ entry:
 	%2 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %i
 	store i32 %1, i32* %2, align 4
 	ret void
-; LINUX-64-STATIC: ind06:
+; LINUX-64-STATIC-LABEL: ind06:
 ; LINUX-64-STATIC: movl    lsrc(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ldst(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind06:
+; LINUX-32-STATIC-LABEL: ind06:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ldst(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind06:
+; LINUX-32-PIC-LABEL: ind06:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ldst(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind06:
+; LINUX-64-PIC-LABEL: ind06:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	ldst(%rip), [[RCX:%r.x]]
@@ -2430,24 +2430,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %i
 	store i32* %0, i32** @lptr, align 8
 	ret void
-; LINUX-64-STATIC: ind07:
+; LINUX-64-STATIC-LABEL: ind07:
 ; LINUX-64-STATIC: leaq    ldst(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], lptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind07:
+; LINUX-32-STATIC-LABEL: ind07:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ldst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind07:
+; LINUX-32-PIC-LABEL: ind07:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ldst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind07:
+; LINUX-64-PIC-LABEL: ind07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
@@ -2501,27 +2501,27 @@ entry:
 	%3 = getelementptr i32* %0, i64 %i
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: ind08:
+; LINUX-64-STATIC-LABEL: ind08:
 ; LINUX-64-STATIC: movl    lsrc(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind08:
+; LINUX-32-STATIC-LABEL: ind08:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind08:
+; LINUX-32-PIC-LABEL: ind08:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind08:
+; LINUX-64-PIC-LABEL: ind08:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
@@ -2582,24 +2582,24 @@ entry:
 	%3 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: off00:
+; LINUX-64-STATIC-LABEL: off00:
 ; LINUX-64-STATIC: movl    src+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], dst+64(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off00:
+; LINUX-32-STATIC-LABEL: off00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	src+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], dst+64(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off00:
+; LINUX-32-PIC-LABEL: off00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	src+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], dst+64(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off00:
+; LINUX-64-PIC-LABEL: off00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2661,24 +2661,24 @@ entry:
 	%3 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: oxf00:
+; LINUX-64-STATIC-LABEL: oxf00:
 ; LINUX-64-STATIC: movl    xsrc+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], xdst+64(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: oxf00:
+; LINUX-32-STATIC-LABEL: oxf00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], xdst+64(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: oxf00:
+; LINUX-32-PIC-LABEL: oxf00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], xdst+64(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: oxf00:
+; LINUX-64-PIC-LABEL: oxf00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	xdst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2738,24 +2738,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %.sum
 	store i32* %0, i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: off01:
+; LINUX-64-STATIC-LABEL: off01:
 ; LINUX-64-STATIC: leaq    dst+64(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off01:
+; LINUX-32-STATIC-LABEL: off01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	dst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off01:
+; LINUX-32-PIC-LABEL: off01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	dst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off01:
+; LINUX-64-PIC-LABEL: off01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2815,24 +2815,24 @@ entry:
 	%0 = getelementptr [32 x i32]* @xdst, i64 0, i64 %.sum
 	store i32* %0, i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: oxf01:
+; LINUX-64-STATIC-LABEL: oxf01:
 ; LINUX-64-STATIC: leaq    xdst+64(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: oxf01:
+; LINUX-32-STATIC-LABEL: oxf01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	xdst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: oxf01:
+; LINUX-32-PIC-LABEL: oxf01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	xdst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: oxf01:
+; LINUX-64-PIC-LABEL: oxf01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2895,27 +2895,27 @@ entry:
 	%4 = getelementptr i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
-; LINUX-64-STATIC: off02:
+; LINUX-64-STATIC-LABEL: off02:
 ; LINUX-64-STATIC: movl    src+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off02:
+; LINUX-32-STATIC-LABEL: off02:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	src+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off02:
+; LINUX-32-PIC-LABEL: off02:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	src+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off02:
+; LINUX-64-PIC-LABEL: off02:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2985,27 +2985,27 @@ entry:
 	%4 = getelementptr i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
-; LINUX-64-STATIC: oxf02:
+; LINUX-64-STATIC-LABEL: oxf02:
 ; LINUX-64-STATIC: movl    xsrc+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: oxf02:
+; LINUX-32-STATIC-LABEL: oxf02:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: oxf02:
+; LINUX-32-PIC-LABEL: oxf02:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: oxf02:
+; LINUX-64-PIC-LABEL: oxf02:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3074,24 +3074,24 @@ entry:
 	%3 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: off03:
+; LINUX-64-STATIC-LABEL: off03:
 ; LINUX-64-STATIC: movl    dsrc+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ddst+64(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off03:
+; LINUX-32-STATIC-LABEL: off03:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ddst+64(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off03:
+; LINUX-32-PIC-LABEL: off03:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ddst+64(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off03:
+; LINUX-64-PIC-LABEL: off03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ddst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3147,24 +3147,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %.sum
 	store i32* %0, i32** @dptr, align 8
 	ret void
-; LINUX-64-STATIC: off04:
+; LINUX-64-STATIC-LABEL: off04:
 ; LINUX-64-STATIC: leaq    ddst+64(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], dptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off04:
+; LINUX-32-STATIC-LABEL: off04:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ddst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off04:
+; LINUX-32-PIC-LABEL: off04:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ddst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off04:
+; LINUX-64-PIC-LABEL: off04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3220,27 +3220,27 @@ entry:
 	%4 = getelementptr i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
-; LINUX-64-STATIC: off05:
+; LINUX-64-STATIC-LABEL: off05:
 ; LINUX-64-STATIC: movl    dsrc+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off05:
+; LINUX-32-STATIC-LABEL: off05:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off05:
+; LINUX-32-PIC-LABEL: off05:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off05:
+; LINUX-64-PIC-LABEL: off05:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3302,24 +3302,24 @@ entry:
 	%3 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: off06:
+; LINUX-64-STATIC-LABEL: off06:
 ; LINUX-64-STATIC: movl    lsrc+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ldst+64(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off06:
+; LINUX-32-STATIC-LABEL: off06:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ldst+64(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off06:
+; LINUX-32-PIC-LABEL: off06:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ldst+64(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off06:
+; LINUX-64-PIC-LABEL: off06:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	ldst(%rip), [[RCX:%r.x]]
@@ -3375,24 +3375,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %.sum
 	store i32* %0, i32** @lptr, align 8
 	ret void
-; LINUX-64-STATIC: off07:
+; LINUX-64-STATIC-LABEL: off07:
 ; LINUX-64-STATIC: leaq    ldst+64(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], lptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off07:
+; LINUX-32-STATIC-LABEL: off07:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ldst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off07:
+; LINUX-32-PIC-LABEL: off07:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ldst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off07:
+; LINUX-64-PIC-LABEL: off07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
@@ -3447,27 +3447,27 @@ entry:
 	%4 = getelementptr i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
-; LINUX-64-STATIC: off08:
+; LINUX-64-STATIC-LABEL: off08:
 ; LINUX-64-STATIC: movl    lsrc+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off08:
+; LINUX-32-STATIC-LABEL: off08:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off08:
+; LINUX-32-PIC-LABEL: off08:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off08:
+; LINUX-64-PIC-LABEL: off08:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
@@ -3525,22 +3525,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 65536), align 4
 	store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536), align 4
 	ret void
-; LINUX-64-STATIC: moo00:
+; LINUX-64-STATIC-LABEL: moo00:
 ; LINUX-64-STATIC: movl    src+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], dst+262144(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo00:
+; LINUX-32-STATIC-LABEL: moo00:
 ; LINUX-32-STATIC: 	movl	src+262144, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dst+262144
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo00:
+; LINUX-32-PIC-LABEL: moo00:
 ; LINUX-32-PIC: 	movl	src+262144, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dst+262144
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo00:
+; LINUX-64-PIC-LABEL: moo00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3595,19 +3595,19 @@ define void @moo01(i64 %i) nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536), i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: moo01:
+; LINUX-64-STATIC-LABEL: moo01:
 ; LINUX-64-STATIC: movq    $dst+262144, ptr(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo01:
+; LINUX-32-STATIC-LABEL: moo01:
 ; LINUX-32-STATIC: 	movl	$dst+262144, ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo01:
+; LINUX-32-PIC-LABEL: moo01:
 ; LINUX-32-PIC: 	movl	$dst+262144, ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo01:
+; LINUX-64-PIC-LABEL: moo01:
 ; LINUX-64-PIC: 	movl	$262144, [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	addq	dst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3664,25 +3664,25 @@ entry:
 	%2 = getelementptr i32* %0, i64 65536
 	store i32 %1, i32* %2, align 4
 	ret void
-; LINUX-64-STATIC: moo02:
+; LINUX-64-STATIC-LABEL: moo02:
 ; LINUX-64-STATIC: movl    src+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]])
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo02:
+; LINUX-32-STATIC-LABEL: moo02:
 ; LINUX-32-STATIC: 	movl	src+262144, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo02:
+; LINUX-32-PIC-LABEL: moo02:
 ; LINUX-32-PIC: 	movl	src+262144, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo02:
+; LINUX-64-PIC-LABEL: moo02:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3745,22 +3745,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 65536), align 32
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536), align 32
 	ret void
-; LINUX-64-STATIC: moo03:
+; LINUX-64-STATIC-LABEL: moo03:
 ; LINUX-64-STATIC: movl    dsrc+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ddst+262144(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo03:
+; LINUX-32-STATIC-LABEL: moo03:
 ; LINUX-32-STATIC: 	movl	dsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ddst+262144
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo03:
+; LINUX-32-PIC-LABEL: moo03:
 ; LINUX-32-PIC: 	movl	dsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ddst+262144
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo03:
+; LINUX-64-PIC-LABEL: moo03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ddst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3805,19 +3805,19 @@ define void @moo04(i64 %i) nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536), i32** @dptr, align 8
 	ret void
-; LINUX-64-STATIC: moo04:
+; LINUX-64-STATIC-LABEL: moo04:
 ; LINUX-64-STATIC: movq    $ddst+262144, dptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo04:
+; LINUX-32-STATIC-LABEL: moo04:
 ; LINUX-32-STATIC: 	movl	$ddst+262144, dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo04:
+; LINUX-32-PIC-LABEL: moo04:
 ; LINUX-32-PIC: 	movl	$ddst+262144, dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo04:
+; LINUX-64-PIC-LABEL: moo04:
 ; LINUX-64-PIC: 	movl	$262144, [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	addq	ddst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3863,25 +3863,25 @@ entry:
 	%2 = getelementptr i32* %0, i64 65536
 	store i32 %1, i32* %2, align 4
 	ret void
-; LINUX-64-STATIC: moo05:
+; LINUX-64-STATIC-LABEL: moo05:
 ; LINUX-64-STATIC: movl    dsrc+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]])
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo05:
+; LINUX-32-STATIC-LABEL: moo05:
 ; LINUX-32-STATIC: 	movl	dsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo05:
+; LINUX-32-PIC-LABEL: moo05:
 ; LINUX-32-PIC: 	movl	dsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo05:
+; LINUX-64-PIC-LABEL: moo05:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3934,22 +3934,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 65536), align 4
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536), align 4
 	ret void
-; LINUX-64-STATIC: moo06:
+; LINUX-64-STATIC-LABEL: moo06:
 ; LINUX-64-STATIC: movl    lsrc+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ldst+262144(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo06:
+; LINUX-32-STATIC-LABEL: moo06:
 ; LINUX-32-STATIC: 	movl	lsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ldst+262144
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo06:
+; LINUX-32-PIC-LABEL: moo06:
 ; LINUX-32-PIC: 	movl	lsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ldst+262144
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo06:
+; LINUX-64-PIC-LABEL: moo06:
 ; LINUX-64-PIC: 	movl	lsrc+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ldst+262144(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
@@ -3992,19 +3992,19 @@ define void @moo07(i64 %i) nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536), i32** @lptr, align 8
 	ret void
-; LINUX-64-STATIC: moo07:
+; LINUX-64-STATIC-LABEL: moo07:
 ; LINUX-64-STATIC: movq    $ldst+262144, lptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo07:
+; LINUX-32-STATIC-LABEL: moo07:
 ; LINUX-32-STATIC: 	movl	$ldst+262144, lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo07:
+; LINUX-32-PIC-LABEL: moo07:
 ; LINUX-32-PIC: 	movl	$ldst+262144, lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo07:
+; LINUX-64-PIC-LABEL: moo07:
 ; LINUX-64-PIC: 	leaq	ldst+262144(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
@@ -4048,25 +4048,25 @@ entry:
 	%2 = getelementptr i32* %0, i64 65536
 	store i32 %1, i32* %2, align 4
 	ret void
-; LINUX-64-STATIC: moo08:
+; LINUX-64-STATIC-LABEL: moo08:
 ; LINUX-64-STATIC: movl    lsrc+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]])
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo08:
+; LINUX-32-STATIC-LABEL: moo08:
 ; LINUX-32-STATIC: 	movl	lsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo08:
+; LINUX-32-PIC-LABEL: moo08:
 ; LINUX-32-PIC: 	movl	lsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo08:
+; LINUX-64-PIC-LABEL: moo08:
 ; LINUX-64-PIC: 	movl	lsrc+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
@@ -4120,24 +4120,24 @@ entry:
 	%3 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: big00:
+; LINUX-64-STATIC-LABEL: big00:
 ; LINUX-64-STATIC: movl    src+262144(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], dst+262144(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big00:
+; LINUX-32-STATIC-LABEL: big00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	src+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], dst+262144(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big00:
+; LINUX-32-PIC-LABEL: big00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	src+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], dst+262144(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big00:
+; LINUX-64-PIC-LABEL: big00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -4197,24 +4197,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %.sum
 	store i32* %0, i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: big01:
+; LINUX-64-STATIC-LABEL: big01:
 ; LINUX-64-STATIC: leaq    dst+262144(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], ptr(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big01:
+; LINUX-32-STATIC-LABEL: big01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	dst+262144(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big01:
+; LINUX-32-PIC-LABEL: big01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	dst+262144(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big01:
+; LINUX-64-PIC-LABEL: big01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -4277,27 +4277,27 @@ entry:
 	%4 = getelementptr i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
-; LINUX-64-STATIC: big02:
+; LINUX-64-STATIC-LABEL: big02:
 ; LINUX-64-STATIC: movl    src+262144(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big02:
+; LINUX-32-STATIC-LABEL: big02:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	src+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big02:
+; LINUX-32-PIC-LABEL: big02:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	src+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big02:
+; LINUX-64-PIC-LABEL: big02:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -4366,24 +4366,24 @@ entry:
 	%3 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: big03:
+; LINUX-64-STATIC-LABEL: big03:
 ; LINUX-64-STATIC: movl    dsrc+262144(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ddst+262144(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big03:
+; LINUX-32-STATIC-LABEL: big03:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ddst+262144(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big03:
+; LINUX-32-PIC-LABEL: big03:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ddst+262144(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big03:
+; LINUX-64-PIC-LABEL: big03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ddst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -4439,24 +4439,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %.sum
 	store i32* %0, i32** @dptr, align 8
 	ret void
-; LINUX-64-STATIC: big04:
+; LINUX-64-STATIC-LABEL: big04:
 ; LINUX-64-STATIC: leaq    ddst+262144(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], dptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big04:
+; LINUX-32-STATIC-LABEL: big04:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ddst+262144(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big04:
+; LINUX-32-PIC-LABEL: big04:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ddst+262144(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big04:
+; LINUX-64-PIC-LABEL: big04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -4512,27 +4512,27 @@ entry:
 	%4 = getelementptr i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
-; LINUX-64-STATIC: big05:
+; LINUX-64-STATIC-LABEL: big05:
 ; LINUX-64-STATIC: movl    dsrc+262144(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big05:
+; LINUX-32-STATIC-LABEL: big05:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big05:
+; LINUX-32-PIC-LABEL: big05:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big05:
+; LINUX-64-PIC-LABEL: big05:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -4594,24 +4594,24 @@ entry:
 	%3 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: big06:
+; LINUX-64-STATIC-LABEL: big06:
 ; LINUX-64-STATIC: movl    lsrc+262144(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ldst+262144(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big06:
+; LINUX-32-STATIC-LABEL: big06:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ldst+262144(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big06:
+; LINUX-32-PIC-LABEL: big06:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ldst+262144(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big06:
+; LINUX-64-PIC-LABEL: big06:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	ldst(%rip), [[RCX:%r.x]]
@@ -4667,24 +4667,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %.sum
 	store i32* %0, i32** @lptr, align 8
 	ret void
-; LINUX-64-STATIC: big07:
+; LINUX-64-STATIC-LABEL: big07:
 ; LINUX-64-STATIC: leaq    ldst+262144(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], lptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big07:
+; LINUX-32-STATIC-LABEL: big07:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ldst+262144(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big07:
+; LINUX-32-PIC-LABEL: big07:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ldst+262144(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big07:
+; LINUX-64-PIC-LABEL: big07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
@@ -4739,27 +4739,27 @@ entry:
 	%4 = getelementptr i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
-; LINUX-64-STATIC: big08:
+; LINUX-64-STATIC-LABEL: big08:
 ; LINUX-64-STATIC: movl    lsrc+262144(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big08:
+; LINUX-32-STATIC-LABEL: big08:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big08:
+; LINUX-32-PIC-LABEL: big08:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big08:
+; LINUX-64-PIC-LABEL: big08:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
@@ -4815,19 +4815,19 @@ entry:
 define i8* @bar00() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @src to i8*)
-; LINUX-64-STATIC: bar00:
+; LINUX-64-STATIC-LABEL: bar00:
 ; LINUX-64-STATIC: movl    $src, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar00:
+; LINUX-32-STATIC-LABEL: bar00:
 ; LINUX-32-STATIC: 	movl	$src, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar00:
+; LINUX-32-PIC-LABEL: bar00:
 ; LINUX-32-PIC: 	movl	$src, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar00:
+; LINUX-64-PIC-LABEL: bar00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -4862,19 +4862,19 @@ entry:
 define i8* @bxr00() nounwind {
 entry:
 	ret i8* bitcast ([32 x i32]* @xsrc to i8*)
-; LINUX-64-STATIC: bxr00:
+; LINUX-64-STATIC-LABEL: bxr00:
 ; LINUX-64-STATIC: movl    $xsrc, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bxr00:
+; LINUX-32-STATIC-LABEL: bxr00:
 ; LINUX-32-STATIC: 	movl	$xsrc, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bxr00:
+; LINUX-32-PIC-LABEL: bxr00:
 ; LINUX-32-PIC: 	movl	$xsrc, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bxr00:
+; LINUX-64-PIC-LABEL: bxr00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -4909,19 +4909,19 @@ entry:
 define i8* @bar01() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @dst to i8*)
-; LINUX-64-STATIC: bar01:
+; LINUX-64-STATIC-LABEL: bar01:
 ; LINUX-64-STATIC: movl    $dst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar01:
+; LINUX-32-STATIC-LABEL: bar01:
 ; LINUX-32-STATIC: 	movl	$dst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar01:
+; LINUX-32-PIC-LABEL: bar01:
 ; LINUX-32-PIC: 	movl	$dst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar01:
+; LINUX-64-PIC-LABEL: bar01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -4956,19 +4956,19 @@ entry:
 define i8* @bxr01() nounwind {
 entry:
 	ret i8* bitcast ([32 x i32]* @xdst to i8*)
-; LINUX-64-STATIC: bxr01:
+; LINUX-64-STATIC-LABEL: bxr01:
 ; LINUX-64-STATIC: movl    $xdst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bxr01:
+; LINUX-32-STATIC-LABEL: bxr01:
 ; LINUX-32-STATIC: 	movl	$xdst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bxr01:
+; LINUX-32-PIC-LABEL: bxr01:
 ; LINUX-32-PIC: 	movl	$xdst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bxr01:
+; LINUX-64-PIC-LABEL: bxr01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5003,19 +5003,19 @@ entry:
 define i8* @bar02() nounwind {
 entry:
 	ret i8* bitcast (i32** @ptr to i8*)
-; LINUX-64-STATIC: bar02:
+; LINUX-64-STATIC-LABEL: bar02:
 ; LINUX-64-STATIC: movl    $ptr, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar02:
+; LINUX-32-STATIC-LABEL: bar02:
 ; LINUX-32-STATIC: 	movl	$ptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar02:
+; LINUX-32-PIC-LABEL: bar02:
 ; LINUX-32-PIC: 	movl	$ptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar02:
+; LINUX-64-PIC-LABEL: bar02:
 ; LINUX-64-PIC: 	movq	ptr@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5050,19 +5050,19 @@ entry:
 define i8* @bar03() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @dsrc to i8*)
-; LINUX-64-STATIC: bar03:
+; LINUX-64-STATIC-LABEL: bar03:
 ; LINUX-64-STATIC: movl    $dsrc, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar03:
+; LINUX-32-STATIC-LABEL: bar03:
 ; LINUX-32-STATIC: 	movl	$dsrc, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar03:
+; LINUX-32-PIC-LABEL: bar03:
 ; LINUX-32-PIC: 	movl	$dsrc, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar03:
+; LINUX-64-PIC-LABEL: bar03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5097,19 +5097,19 @@ entry:
 define i8* @bar04() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @ddst to i8*)
-; LINUX-64-STATIC: bar04:
+; LINUX-64-STATIC-LABEL: bar04:
 ; LINUX-64-STATIC: movl    $ddst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar04:
+; LINUX-32-STATIC-LABEL: bar04:
 ; LINUX-32-STATIC: 	movl	$ddst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar04:
+; LINUX-32-PIC-LABEL: bar04:
 ; LINUX-32-PIC: 	movl	$ddst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar04:
+; LINUX-64-PIC-LABEL: bar04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5144,19 +5144,19 @@ entry:
 define i8* @bar05() nounwind {
 entry:
 	ret i8* bitcast (i32** @dptr to i8*)
-; LINUX-64-STATIC: bar05:
+; LINUX-64-STATIC-LABEL: bar05:
 ; LINUX-64-STATIC: movl    $dptr, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar05:
+; LINUX-32-STATIC-LABEL: bar05:
 ; LINUX-32-STATIC: 	movl	$dptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar05:
+; LINUX-32-PIC-LABEL: bar05:
 ; LINUX-32-PIC: 	movl	$dptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar05:
+; LINUX-64-PIC-LABEL: bar05:
 ; LINUX-64-PIC: 	movq	dptr@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5191,19 +5191,19 @@ entry:
 define i8* @bar06() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @lsrc to i8*)
-; LINUX-64-STATIC: bar06:
+; LINUX-64-STATIC-LABEL: bar06:
 ; LINUX-64-STATIC: movl    $lsrc, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar06:
+; LINUX-32-STATIC-LABEL: bar06:
 ; LINUX-32-STATIC: 	movl	$lsrc, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar06:
+; LINUX-32-PIC-LABEL: bar06:
 ; LINUX-32-PIC: 	movl	$lsrc, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar06:
+; LINUX-64-PIC-LABEL: bar06:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5238,19 +5238,19 @@ entry:
 define i8* @bar07() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @ldst to i8*)
-; LINUX-64-STATIC: bar07:
+; LINUX-64-STATIC-LABEL: bar07:
 ; LINUX-64-STATIC: movl    $ldst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar07:
+; LINUX-32-STATIC-LABEL: bar07:
 ; LINUX-32-STATIC: 	movl	$ldst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar07:
+; LINUX-32-PIC-LABEL: bar07:
 ; LINUX-32-PIC: 	movl	$ldst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar07:
+; LINUX-64-PIC-LABEL: bar07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5285,19 +5285,19 @@ entry:
 define i8* @bar08() nounwind {
 entry:
 	ret i8* bitcast (i32** @lptr to i8*)
-; LINUX-64-STATIC: bar08:
+; LINUX-64-STATIC-LABEL: bar08:
 ; LINUX-64-STATIC: movl    $lptr, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar08:
+; LINUX-32-STATIC-LABEL: bar08:
 ; LINUX-32-STATIC: 	movl	$lptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar08:
+; LINUX-32-PIC-LABEL: bar08:
 ; LINUX-32-PIC: 	movl	$lptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar08:
+; LINUX-64-PIC-LABEL: bar08:
 ; LINUX-64-PIC: 	leaq	lptr(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5332,19 +5332,19 @@ entry:
 define i8* @har00() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @src to i8*)
-; LINUX-64-STATIC: har00:
+; LINUX-64-STATIC-LABEL: har00:
 ; LINUX-64-STATIC: movl    $src, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har00:
+; LINUX-32-STATIC-LABEL: har00:
 ; LINUX-32-STATIC: 	movl	$src, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har00:
+; LINUX-32-PIC-LABEL: har00:
 ; LINUX-32-PIC: 	movl	$src, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har00:
+; LINUX-64-PIC-LABEL: har00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5379,19 +5379,19 @@ entry:
 define i8* @hxr00() nounwind {
 entry:
 	ret i8* bitcast ([32 x i32]* @xsrc to i8*)
-; LINUX-64-STATIC: hxr00:
+; LINUX-64-STATIC-LABEL: hxr00:
 ; LINUX-64-STATIC: movl    $xsrc, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: hxr00:
+; LINUX-32-STATIC-LABEL: hxr00:
 ; LINUX-32-STATIC: 	movl	$xsrc, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: hxr00:
+; LINUX-32-PIC-LABEL: hxr00:
 ; LINUX-32-PIC: 	movl	$xsrc, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: hxr00:
+; LINUX-64-PIC-LABEL: hxr00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5426,19 +5426,19 @@ entry:
 define i8* @har01() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @dst to i8*)
-; LINUX-64-STATIC: har01:
+; LINUX-64-STATIC-LABEL: har01:
 ; LINUX-64-STATIC: movl    $dst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har01:
+; LINUX-32-STATIC-LABEL: har01:
 ; LINUX-32-STATIC: 	movl	$dst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har01:
+; LINUX-32-PIC-LABEL: har01:
 ; LINUX-32-PIC: 	movl	$dst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har01:
+; LINUX-64-PIC-LABEL: har01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5473,19 +5473,19 @@ entry:
 define i8* @hxr01() nounwind {
 entry:
 	ret i8* bitcast ([32 x i32]* @xdst to i8*)
-; LINUX-64-STATIC: hxr01:
+; LINUX-64-STATIC-LABEL: hxr01:
 ; LINUX-64-STATIC: movl    $xdst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: hxr01:
+; LINUX-32-STATIC-LABEL: hxr01:
 ; LINUX-32-STATIC: 	movl	$xdst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: hxr01:
+; LINUX-32-PIC-LABEL: hxr01:
 ; LINUX-32-PIC: 	movl	$xdst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: hxr01:
+; LINUX-64-PIC-LABEL: hxr01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5522,19 +5522,19 @@ entry:
 	%0 = load i32** @ptr, align 8
 	%1 = bitcast i32* %0 to i8*
 	ret i8* %1
-; LINUX-64-STATIC: har02:
+; LINUX-64-STATIC-LABEL: har02:
 ; LINUX-64-STATIC: movq    ptr(%rip), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har02:
+; LINUX-32-STATIC-LABEL: har02:
 ; LINUX-32-STATIC: 	movl	ptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har02:
+; LINUX-32-PIC-LABEL: har02:
 ; LINUX-32-PIC: 	movl	ptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har02:
+; LINUX-64-PIC-LABEL: har02:
 ; LINUX-64-PIC: 	movq	ptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -5575,19 +5575,19 @@ entry:
 define i8* @har03() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @dsrc to i8*)
-; LINUX-64-STATIC: har03:
+; LINUX-64-STATIC-LABEL: har03:
 ; LINUX-64-STATIC: movl    $dsrc, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har03:
+; LINUX-32-STATIC-LABEL: har03:
 ; LINUX-32-STATIC: 	movl	$dsrc, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har03:
+; LINUX-32-PIC-LABEL: har03:
 ; LINUX-32-PIC: 	movl	$dsrc, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har03:
+; LINUX-64-PIC-LABEL: har03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5622,19 +5622,19 @@ entry:
 define i8* @har04() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @ddst to i8*)
-; LINUX-64-STATIC: har04:
+; LINUX-64-STATIC-LABEL: har04:
 ; LINUX-64-STATIC: movl    $ddst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har04:
+; LINUX-32-STATIC-LABEL: har04:
 ; LINUX-32-STATIC: 	movl	$ddst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har04:
+; LINUX-32-PIC-LABEL: har04:
 ; LINUX-32-PIC: 	movl	$ddst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har04:
+; LINUX-64-PIC-LABEL: har04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5671,19 +5671,19 @@ entry:
 	%0 = load i32** @dptr, align 8
 	%1 = bitcast i32* %0 to i8*
 	ret i8* %1
-; LINUX-64-STATIC: har05:
+; LINUX-64-STATIC-LABEL: har05:
 ; LINUX-64-STATIC: movq    dptr(%rip), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har05:
+; LINUX-32-STATIC-LABEL: har05:
 ; LINUX-32-STATIC: 	movl	dptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har05:
+; LINUX-32-PIC-LABEL: har05:
 ; LINUX-32-PIC: 	movl	dptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har05:
+; LINUX-64-PIC-LABEL: har05:
 ; LINUX-64-PIC: 	movq	dptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -5719,19 +5719,19 @@ entry:
 define i8* @har06() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @lsrc to i8*)
-; LINUX-64-STATIC: har06:
+; LINUX-64-STATIC-LABEL: har06:
 ; LINUX-64-STATIC: movl    $lsrc, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har06:
+; LINUX-32-STATIC-LABEL: har06:
 ; LINUX-32-STATIC: 	movl	$lsrc, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har06:
+; LINUX-32-PIC-LABEL: har06:
 ; LINUX-32-PIC: 	movl	$lsrc, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har06:
+; LINUX-64-PIC-LABEL: har06:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5766,19 +5766,19 @@ entry:
 define i8* @har07() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @ldst to i8*)
-; LINUX-64-STATIC: har07:
+; LINUX-64-STATIC-LABEL: har07:
 ; LINUX-64-STATIC: movl    $ldst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har07:
+; LINUX-32-STATIC-LABEL: har07:
 ; LINUX-32-STATIC: 	movl	$ldst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har07:
+; LINUX-32-PIC-LABEL: har07:
 ; LINUX-32-PIC: 	movl	$ldst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har07:
+; LINUX-64-PIC-LABEL: har07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5815,19 +5815,19 @@ entry:
 	%0 = load i32** @lptr, align 8
 	%1 = bitcast i32* %0 to i8*
 	ret i8* %1
-; LINUX-64-STATIC: har08:
+; LINUX-64-STATIC-LABEL: har08:
 ; LINUX-64-STATIC: movq    lptr(%rip), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har08:
+; LINUX-32-STATIC-LABEL: har08:
 ; LINUX-32-STATIC: 	movl	lptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har08:
+; LINUX-32-PIC-LABEL: har08:
 ; LINUX-32-PIC: 	movl	lptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har08:
+; LINUX-64-PIC-LABEL: har08:
 ; LINUX-64-PIC: 	movq	lptr(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5862,19 +5862,19 @@ entry:
 define i8* @bat00() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat00:
+; LINUX-64-STATIC-LABEL: bat00:
 ; LINUX-64-STATIC: movl    $src+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat00:
+; LINUX-32-STATIC-LABEL: bat00:
 ; LINUX-32-STATIC: 	movl	$src+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat00:
+; LINUX-32-PIC-LABEL: bat00:
 ; LINUX-32-PIC: 	movl	$src+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat00:
+; LINUX-64-PIC-LABEL: bat00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -5915,19 +5915,19 @@ entry:
 define i8* @bxt00() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bxt00:
+; LINUX-64-STATIC-LABEL: bxt00:
 ; LINUX-64-STATIC: movl    $xsrc+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bxt00:
+; LINUX-32-STATIC-LABEL: bxt00:
 ; LINUX-32-STATIC: 	movl	$xsrc+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bxt00:
+; LINUX-32-PIC-LABEL: bxt00:
 ; LINUX-32-PIC: 	movl	$xsrc+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bxt00:
+; LINUX-64-PIC-LABEL: bxt00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -5968,19 +5968,19 @@ entry:
 define i8* @bat01() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat01:
+; LINUX-64-STATIC-LABEL: bat01:
 ; LINUX-64-STATIC: movl    $dst+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat01:
+; LINUX-32-STATIC-LABEL: bat01:
 ; LINUX-32-STATIC: 	movl	$dst+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat01:
+; LINUX-32-PIC-LABEL: bat01:
 ; LINUX-32-PIC: 	movl	$dst+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat01:
+; LINUX-64-PIC-LABEL: bat01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6021,19 +6021,19 @@ entry:
 define i8* @bxt01() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bxt01:
+; LINUX-64-STATIC-LABEL: bxt01:
 ; LINUX-64-STATIC: movl    $xdst+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bxt01:
+; LINUX-32-STATIC-LABEL: bxt01:
 ; LINUX-32-STATIC: 	movl	$xdst+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bxt01:
+; LINUX-32-PIC-LABEL: bxt01:
 ; LINUX-32-PIC: 	movl	$xdst+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bxt01:
+; LINUX-64-PIC-LABEL: bxt01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6077,22 +6077,22 @@ entry:
 	%1 = getelementptr i32* %0, i64 16
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: bat02:
+; LINUX-64-STATIC-LABEL: bat02:
 ; LINUX-64-STATIC: movq    ptr(%rip), %rax
 ; LINUX-64-STATIC: addq    $64, %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat02:
+; LINUX-32-STATIC-LABEL: bat02:
 ; LINUX-32-STATIC: 	movl	ptr, %eax
 ; LINUX-32-STATIC-NEXT: 	addl	$64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat02:
+; LINUX-32-PIC-LABEL: bat02:
 ; LINUX-32-PIC: 	movl	ptr, %eax
 ; LINUX-32-PIC-NEXT: 	addl	$64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat02:
+; LINUX-64-PIC-LABEL: bat02:
 ; LINUX-64-PIC: 	movq	ptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
@@ -6140,19 +6140,19 @@ entry:
 define i8* @bat03() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat03:
+; LINUX-64-STATIC-LABEL: bat03:
 ; LINUX-64-STATIC: movl    $dsrc+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat03:
+; LINUX-32-STATIC-LABEL: bat03:
 ; LINUX-32-STATIC: 	movl	$dsrc+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat03:
+; LINUX-32-PIC-LABEL: bat03:
 ; LINUX-32-PIC: 	movl	$dsrc+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat03:
+; LINUX-64-PIC-LABEL: bat03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6188,19 +6188,19 @@ entry:
 define i8* @bat04() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat04:
+; LINUX-64-STATIC-LABEL: bat04:
 ; LINUX-64-STATIC: movl    $ddst+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat04:
+; LINUX-32-STATIC-LABEL: bat04:
 ; LINUX-32-STATIC: 	movl	$ddst+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat04:
+; LINUX-32-PIC-LABEL: bat04:
 ; LINUX-32-PIC: 	movl	$ddst+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat04:
+; LINUX-64-PIC-LABEL: bat04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6239,22 +6239,22 @@ entry:
 	%1 = getelementptr i32* %0, i64 16
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: bat05:
+; LINUX-64-STATIC-LABEL: bat05:
 ; LINUX-64-STATIC: movq    dptr(%rip), %rax
 ; LINUX-64-STATIC: addq    $64, %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat05:
+; LINUX-32-STATIC-LABEL: bat05:
 ; LINUX-32-STATIC: 	movl	dptr, %eax
 ; LINUX-32-STATIC-NEXT: 	addl	$64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat05:
+; LINUX-32-PIC-LABEL: bat05:
 ; LINUX-32-PIC: 	movl	dptr, %eax
 ; LINUX-32-PIC-NEXT: 	addl	$64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat05:
+; LINUX-64-PIC-LABEL: bat05:
 ; LINUX-64-PIC: 	movq	dptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
@@ -6297,19 +6297,19 @@ entry:
 define i8* @bat06() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat06:
+; LINUX-64-STATIC-LABEL: bat06:
 ; LINUX-64-STATIC: movl    $lsrc+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat06:
+; LINUX-32-STATIC-LABEL: bat06:
 ; LINUX-32-STATIC: 	movl	$lsrc+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat06:
+; LINUX-32-PIC-LABEL: bat06:
 ; LINUX-32-PIC: 	movl	$lsrc+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat06:
+; LINUX-64-PIC-LABEL: bat06:
 ; LINUX-64-PIC: 	leaq	lsrc+64(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -6344,19 +6344,19 @@ entry:
 define i8* @bat07() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat07:
+; LINUX-64-STATIC-LABEL: bat07:
 ; LINUX-64-STATIC: movl    $ldst+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat07:
+; LINUX-32-STATIC-LABEL: bat07:
 ; LINUX-32-STATIC: 	movl	$ldst+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat07:
+; LINUX-32-PIC-LABEL: bat07:
 ; LINUX-32-PIC: 	movl	$ldst+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat07:
+; LINUX-64-PIC-LABEL: bat07:
 ; LINUX-64-PIC: 	leaq	ldst+64(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -6394,22 +6394,22 @@ entry:
 	%1 = getelementptr i32* %0, i64 16
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: bat08:
+; LINUX-64-STATIC-LABEL: bat08:
 ; LINUX-64-STATIC: movq    lptr(%rip), %rax
 ; LINUX-64-STATIC: addq    $64, %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat08:
+; LINUX-32-STATIC-LABEL: bat08:
 ; LINUX-32-STATIC: 	movl	lptr, %eax
 ; LINUX-32-STATIC-NEXT: 	addl	$64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat08:
+; LINUX-32-PIC-LABEL: bat08:
 ; LINUX-32-PIC: 	movl	lptr, %eax
 ; LINUX-32-PIC-NEXT: 	addl	$64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat08:
+; LINUX-64-PIC-LABEL: bat08:
 ; LINUX-64-PIC: 	movq	lptr(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6451,19 +6451,19 @@ entry:
 define i8* @bam00() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @src, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam00:
+; LINUX-64-STATIC-LABEL: bam00:
 ; LINUX-64-STATIC: movl    $src+262144, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam00:
+; LINUX-32-STATIC-LABEL: bam00:
 ; LINUX-32-STATIC: 	movl	$src+262144, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam00:
+; LINUX-32-PIC-LABEL: bam00:
 ; LINUX-32-PIC: 	movl	$src+262144, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam00:
+; LINUX-64-PIC-LABEL: bam00:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	addq	src@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6504,19 +6504,19 @@ entry:
 define i8* @bam01() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam01:
+; LINUX-64-STATIC-LABEL: bam01:
 ; LINUX-64-STATIC: movl    $dst+262144, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam01:
+; LINUX-32-STATIC-LABEL: bam01:
 ; LINUX-32-STATIC: 	movl	$dst+262144, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam01:
+; LINUX-32-PIC-LABEL: bam01:
 ; LINUX-32-PIC: 	movl	$dst+262144, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam01:
+; LINUX-64-PIC-LABEL: bam01:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	addq	dst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6557,19 +6557,19 @@ entry:
 define i8* @bxm01() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bxm01:
+; LINUX-64-STATIC-LABEL: bxm01:
 ; LINUX-64-STATIC: movl    $xdst+262144, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bxm01:
+; LINUX-32-STATIC-LABEL: bxm01:
 ; LINUX-32-STATIC: 	movl	$xdst+262144, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bxm01:
+; LINUX-32-PIC-LABEL: bxm01:
 ; LINUX-32-PIC: 	movl	$xdst+262144, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bxm01:
+; LINUX-64-PIC-LABEL: bxm01:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	addq	xdst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6613,22 +6613,22 @@ entry:
 	%1 = getelementptr i32* %0, i64 65536
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: bam02:
+; LINUX-64-STATIC-LABEL: bam02:
 ; LINUX-64-STATIC: movl    $262144, %eax
 ; LINUX-64-STATIC: addq    ptr(%rip), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam02:
+; LINUX-32-STATIC-LABEL: bam02:
 ; LINUX-32-STATIC: 	movl	$262144, %eax
 ; LINUX-32-STATIC-NEXT: 	addl	ptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam02:
+; LINUX-32-PIC-LABEL: bam02:
 ; LINUX-32-PIC: 	movl	$262144, %eax
 ; LINUX-32-PIC-NEXT: 	addl	ptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam02:
+; LINUX-64-PIC-LABEL: bam02:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	addq	([[RCX]]), %rax
@@ -6676,19 +6676,19 @@ entry:
 define i8* @bam03() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam03:
+; LINUX-64-STATIC-LABEL: bam03:
 ; LINUX-64-STATIC: movl    $dsrc+262144, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam03:
+; LINUX-32-STATIC-LABEL: bam03:
 ; LINUX-32-STATIC: 	movl	$dsrc+262144, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam03:
+; LINUX-32-PIC-LABEL: bam03:
 ; LINUX-32-PIC: 	movl	$dsrc+262144, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam03:
+; LINUX-64-PIC-LABEL: bam03:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	addq	dsrc@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6724,19 +6724,19 @@ entry:
 define i8* @bam04() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam04:
+; LINUX-64-STATIC-LABEL: bam04:
 ; LINUX-64-STATIC: movl    $ddst+262144, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam04:
+; LINUX-32-STATIC-LABEL: bam04:
 ; LINUX-32-STATIC: 	movl	$ddst+262144, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam04:
+; LINUX-32-PIC-LABEL: bam04:
 ; LINUX-32-PIC: 	movl	$ddst+262144, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam04:
+; LINUX-64-PIC-LABEL: bam04:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	addq	ddst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6775,22 +6775,22 @@ entry:
 	%1 = getelementptr i32* %0, i64 65536
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: bam05:
+; LINUX-64-STATIC-LABEL: bam05:
 ; LINUX-64-STATIC: movl    $262144, %eax
 ; LINUX-64-STATIC: addq    dptr(%rip), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam05:
+; LINUX-32-STATIC-LABEL: bam05:
 ; LINUX-32-STATIC: 	movl	$262144, %eax
 ; LINUX-32-STATIC-NEXT: 	addl	dptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam05:
+; LINUX-32-PIC-LABEL: bam05:
 ; LINUX-32-PIC: 	movl	$262144, %eax
 ; LINUX-32-PIC-NEXT: 	addl	dptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam05:
+; LINUX-64-PIC-LABEL: bam05:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	addq	([[RCX]]), %rax
@@ -6833,19 +6833,19 @@ entry:
 define i8* @bam06() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam06:
+; LINUX-64-STATIC-LABEL: bam06:
 ; LINUX-64-STATIC: movl    $lsrc+262144, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam06:
+; LINUX-32-STATIC-LABEL: bam06:
 ; LINUX-32-STATIC: 	movl	$lsrc+262144, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam06:
+; LINUX-32-PIC-LABEL: bam06:
 ; LINUX-32-PIC: 	movl	$lsrc+262144, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam06:
+; LINUX-64-PIC-LABEL: bam06:
 ; LINUX-64-PIC: 	leaq	lsrc+262144(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -6880,19 +6880,19 @@ entry:
 define i8* @bam07() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam07:
+; LINUX-64-STATIC-LABEL: bam07:
 ; LINUX-64-STATIC: movl    $ldst+262144, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam07:
+; LINUX-32-STATIC-LABEL: bam07:
 ; LINUX-32-STATIC: 	movl	$ldst+262144, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam07:
+; LINUX-32-PIC-LABEL: bam07:
 ; LINUX-32-PIC: 	movl	$ldst+262144, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam07:
+; LINUX-64-PIC-LABEL: bam07:
 ; LINUX-64-PIC: 	leaq	ldst+262144(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -6930,22 +6930,22 @@ entry:
 	%1 = getelementptr i32* %0, i64 65536
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: bam08:
+; LINUX-64-STATIC-LABEL: bam08:
 ; LINUX-64-STATIC: movl    $262144, %eax
 ; LINUX-64-STATIC: addq    lptr(%rip), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam08:
+; LINUX-32-STATIC-LABEL: bam08:
 ; LINUX-32-STATIC: 	movl	$262144, %eax
 ; LINUX-32-STATIC-NEXT: 	addl	lptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam08:
+; LINUX-32-PIC-LABEL: bam08:
 ; LINUX-32-PIC: 	movl	$262144, %eax
 ; LINUX-32-PIC-NEXT: 	addl	lptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam08:
+; LINUX-64-PIC-LABEL: bam08:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	addq	lptr(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6990,21 +6990,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @src, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cat00:
+; LINUX-64-STATIC-LABEL: cat00:
 ; LINUX-64-STATIC: leaq    src+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat00:
+; LINUX-32-STATIC-LABEL: cat00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	src+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat00:
+; LINUX-32-PIC-LABEL: cat00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	src+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat00:
+; LINUX-64-PIC-LABEL: cat00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7051,21 +7051,21 @@ entry:
 	%1 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cxt00:
+; LINUX-64-STATIC-LABEL: cxt00:
 ; LINUX-64-STATIC: leaq    xsrc+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cxt00:
+; LINUX-32-STATIC-LABEL: cxt00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	xsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cxt00:
+; LINUX-32-PIC-LABEL: cxt00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	xsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cxt00:
+; LINUX-64-PIC-LABEL: cxt00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7112,21 +7112,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cat01:
+; LINUX-64-STATIC-LABEL: cat01:
 ; LINUX-64-STATIC: leaq    dst+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat01:
+; LINUX-32-STATIC-LABEL: cat01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	dst+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat01:
+; LINUX-32-PIC-LABEL: cat01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	dst+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat01:
+; LINUX-64-PIC-LABEL: cat01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7173,21 +7173,21 @@ entry:
 	%1 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cxt01:
+; LINUX-64-STATIC-LABEL: cxt01:
 ; LINUX-64-STATIC: leaq    xdst+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cxt01:
+; LINUX-32-STATIC-LABEL: cxt01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	xdst+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cxt01:
+; LINUX-32-PIC-LABEL: cxt01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	xdst+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cxt01:
+; LINUX-64-PIC-LABEL: cxt01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7235,24 +7235,24 @@ entry:
 	%2 = getelementptr i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
-; LINUX-64-STATIC: cat02:
+; LINUX-64-STATIC-LABEL: cat02:
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-STATIC: leaq    64([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat02:
+; LINUX-32-STATIC-LABEL: cat02:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat02:
+; LINUX-32-PIC-LABEL: cat02:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat02:
+; LINUX-64-PIC-LABEL: cat02:
 ; LINUX-64-PIC: 	movq	ptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
@@ -7306,21 +7306,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cat03:
+; LINUX-64-STATIC-LABEL: cat03:
 ; LINUX-64-STATIC: leaq    dsrc+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat03:
+; LINUX-32-STATIC-LABEL: cat03:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	dsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat03:
+; LINUX-32-PIC-LABEL: cat03:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	dsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat03:
+; LINUX-64-PIC-LABEL: cat03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7365,21 +7365,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cat04:
+; LINUX-64-STATIC-LABEL: cat04:
 ; LINUX-64-STATIC: leaq    ddst+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat04:
+; LINUX-32-STATIC-LABEL: cat04:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ddst+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat04:
+; LINUX-32-PIC-LABEL: cat04:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ddst+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat04:
+; LINUX-64-PIC-LABEL: cat04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7425,24 +7425,24 @@ entry:
 	%2 = getelementptr i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
-; LINUX-64-STATIC: cat05:
+; LINUX-64-STATIC-LABEL: cat05:
 ; LINUX-64-STATIC: movq    dptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-STATIC: leaq    64([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat05:
+; LINUX-32-STATIC-LABEL: cat05:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat05:
+; LINUX-32-PIC-LABEL: cat05:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat05:
+; LINUX-64-PIC-LABEL: cat05:
 ; LINUX-64-PIC: 	movq	dptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
@@ -7491,21 +7491,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cat06:
+; LINUX-64-STATIC-LABEL: cat06:
 ; LINUX-64-STATIC: leaq    lsrc+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat06:
+; LINUX-32-STATIC-LABEL: cat06:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	lsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat06:
+; LINUX-32-PIC-LABEL: cat06:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	lsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat06:
+; LINUX-64-PIC-LABEL: cat06:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7550,21 +7550,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cat07:
+; LINUX-64-STATIC-LABEL: cat07:
 ; LINUX-64-STATIC: leaq    ldst+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat07:
+; LINUX-32-STATIC-LABEL: cat07:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ldst+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat07:
+; LINUX-32-PIC-LABEL: cat07:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ldst+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat07:
+; LINUX-64-PIC-LABEL: cat07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7610,24 +7610,24 @@ entry:
 	%2 = getelementptr i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
-; LINUX-64-STATIC: cat08:
+; LINUX-64-STATIC-LABEL: cat08:
 ; LINUX-64-STATIC: movq    lptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-STATIC: leaq    64([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat08:
+; LINUX-32-STATIC-LABEL: cat08:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat08:
+; LINUX-32-PIC-LABEL: cat08:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat08:
+; LINUX-64-PIC-LABEL: cat08:
 ; LINUX-64-PIC: 	movq	lptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7675,21 +7675,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @src, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cam00:
+; LINUX-64-STATIC-LABEL: cam00:
 ; LINUX-64-STATIC: leaq    src+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam00:
+; LINUX-32-STATIC-LABEL: cam00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	src+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam00:
+; LINUX-32-PIC-LABEL: cam00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	src+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam00:
+; LINUX-64-PIC-LABEL: cam00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7736,21 +7736,21 @@ entry:
 	%1 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cxm00:
+; LINUX-64-STATIC-LABEL: cxm00:
 ; LINUX-64-STATIC: leaq    xsrc+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cxm00:
+; LINUX-32-STATIC-LABEL: cxm00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	xsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cxm00:
+; LINUX-32-PIC-LABEL: cxm00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	xsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cxm00:
+; LINUX-64-PIC-LABEL: cxm00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7797,21 +7797,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cam01:
+; LINUX-64-STATIC-LABEL: cam01:
 ; LINUX-64-STATIC: leaq    dst+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam01:
+; LINUX-32-STATIC-LABEL: cam01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	dst+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam01:
+; LINUX-32-PIC-LABEL: cam01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	dst+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam01:
+; LINUX-64-PIC-LABEL: cam01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7858,21 +7858,21 @@ entry:
 	%1 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cxm01:
+; LINUX-64-STATIC-LABEL: cxm01:
 ; LINUX-64-STATIC: leaq    xdst+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cxm01:
+; LINUX-32-STATIC-LABEL: cxm01:
 ; LINUX-32-STATIC: 	movl	4(%esp), %eax
 ; LINUX-32-STATIC-NEXT: 	leal	xdst+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cxm01:
+; LINUX-32-PIC-LABEL: cxm01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	xdst+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cxm01:
+; LINUX-64-PIC-LABEL: cxm01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7920,24 +7920,24 @@ entry:
 	%2 = getelementptr i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
-; LINUX-64-STATIC: cam02:
+; LINUX-64-STATIC-LABEL: cam02:
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-STATIC: leaq    262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam02:
+; LINUX-32-STATIC-LABEL: cam02:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam02:
+; LINUX-32-PIC-LABEL: cam02:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam02:
+; LINUX-64-PIC-LABEL: cam02:
 ; LINUX-64-PIC: 	movq	ptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
@@ -7991,21 +7991,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cam03:
+; LINUX-64-STATIC-LABEL: cam03:
 ; LINUX-64-STATIC: leaq    dsrc+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam03:
+; LINUX-32-STATIC-LABEL: cam03:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	dsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam03:
+; LINUX-32-PIC-LABEL: cam03:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	dsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam03:
+; LINUX-64-PIC-LABEL: cam03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -8050,21 +8050,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cam04:
+; LINUX-64-STATIC-LABEL: cam04:
 ; LINUX-64-STATIC: leaq    ddst+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam04:
+; LINUX-32-STATIC-LABEL: cam04:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ddst+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam04:
+; LINUX-32-PIC-LABEL: cam04:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ddst+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam04:
+; LINUX-64-PIC-LABEL: cam04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -8110,24 +8110,24 @@ entry:
 	%2 = getelementptr i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
-; LINUX-64-STATIC: cam05:
+; LINUX-64-STATIC-LABEL: cam05:
 ; LINUX-64-STATIC: movq    dptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-STATIC: leaq    262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam05:
+; LINUX-32-STATIC-LABEL: cam05:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam05:
+; LINUX-32-PIC-LABEL: cam05:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam05:
+; LINUX-64-PIC-LABEL: cam05:
 ; LINUX-64-PIC: 	movq	dptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
@@ -8176,21 +8176,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cam06:
+; LINUX-64-STATIC-LABEL: cam06:
 ; LINUX-64-STATIC: leaq    lsrc+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam06:
+; LINUX-32-STATIC-LABEL: cam06:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	lsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam06:
+; LINUX-32-PIC-LABEL: cam06:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	lsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam06:
+; LINUX-64-PIC-LABEL: cam06:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -8235,21 +8235,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cam07:
+; LINUX-64-STATIC-LABEL: cam07:
 ; LINUX-64-STATIC: leaq    ldst+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam07:
+; LINUX-32-STATIC-LABEL: cam07:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ldst+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam07:
+; LINUX-32-PIC-LABEL: cam07:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ldst+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam07:
+; LINUX-64-PIC-LABEL: cam07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -8295,24 +8295,24 @@ entry:
 	%2 = getelementptr i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
-; LINUX-64-STATIC: cam08:
+; LINUX-64-STATIC-LABEL: cam08:
 ; LINUX-64-STATIC: movq    lptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-STATIC: leaq    262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam08:
+; LINUX-32-STATIC-LABEL: cam08:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam08:
+; LINUX-32-PIC-LABEL: cam08:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam08:
+; LINUX-64-PIC-LABEL: cam08:
 ; LINUX-64-PIC: 	movq	lptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -8364,7 +8364,7 @@ entry:
 	call void @x() nounwind
 	call void @x() nounwind
 	ret void
-; LINUX-64-STATIC: lcallee:
+; LINUX-64-STATIC-LABEL: lcallee:
 ; LINUX-64-STATIC: callq   x
 ; LINUX-64-STATIC: callq   x
 ; LINUX-64-STATIC: callq   x
@@ -8374,7 +8374,7 @@ entry:
 ; LINUX-64-STATIC: callq   x
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: lcallee:
+; LINUX-32-STATIC-LABEL: lcallee:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	x
 ; LINUX-32-STATIC-NEXT: 	calll	x
@@ -8386,7 +8386,7 @@ entry:
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: lcallee:
+; LINUX-32-PIC-LABEL: lcallee:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	x
 ; LINUX-32-PIC-NEXT: 	calll	x
@@ -8399,7 +8399,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: lcallee:
+; LINUX-64-PIC-LABEL: lcallee:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	x@PLT
 ; LINUX-64-PIC-NEXT: 	callq	x@PLT
@@ -8496,7 +8496,7 @@ entry:
 	call void @y() nounwind
 	call void @y() nounwind
 	ret void
-; LINUX-64-STATIC: dcallee:
+; LINUX-64-STATIC-LABEL: dcallee:
 ; LINUX-64-STATIC: callq   y
 ; LINUX-64-STATIC: callq   y
 ; LINUX-64-STATIC: callq   y
@@ -8506,7 +8506,7 @@ entry:
 ; LINUX-64-STATIC: callq   y
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: dcallee:
+; LINUX-32-STATIC-LABEL: dcallee:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	y
 ; LINUX-32-STATIC-NEXT: 	calll	y
@@ -8518,7 +8518,7 @@ entry:
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: dcallee:
+; LINUX-32-PIC-LABEL: dcallee:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	y
 ; LINUX-32-PIC-NEXT: 	calll	y
@@ -8531,7 +8531,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: dcallee:
+; LINUX-64-PIC-LABEL: dcallee:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	y@PLT
 ; LINUX-64-PIC-NEXT: 	callq	y@PLT
@@ -8621,19 +8621,19 @@ declare void @y()
 define void ()* @address() nounwind {
 entry:
 	ret void ()* @callee
-; LINUX-64-STATIC: address:
+; LINUX-64-STATIC-LABEL: address:
 ; LINUX-64-STATIC: movl    $callee, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: address:
+; LINUX-32-STATIC-LABEL: address:
 ; LINUX-32-STATIC: 	movl	$callee, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: address:
+; LINUX-32-PIC-LABEL: address:
 ; LINUX-32-PIC: 	movl	$callee, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: address:
+; LINUX-64-PIC-LABEL: address:
 ; LINUX-64-PIC: 	movq	callee@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -8670,19 +8670,19 @@ declare void @callee()
 define void ()* @laddress() nounwind {
 entry:
 	ret void ()* @lcallee
-; LINUX-64-STATIC: laddress:
+; LINUX-64-STATIC-LABEL: laddress:
 ; LINUX-64-STATIC: movl    $lcallee, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: laddress:
+; LINUX-32-STATIC-LABEL: laddress:
 ; LINUX-32-STATIC: 	movl	$lcallee, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: laddress:
+; LINUX-32-PIC-LABEL: laddress:
 ; LINUX-32-PIC: 	movl	$lcallee, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: laddress:
+; LINUX-64-PIC-LABEL: laddress:
 ; LINUX-64-PIC: 	movq	lcallee@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -8717,19 +8717,19 @@ entry:
 define void ()* @daddress() nounwind {
 entry:
 	ret void ()* @dcallee
-; LINUX-64-STATIC: daddress:
+; LINUX-64-STATIC-LABEL: daddress:
 ; LINUX-64-STATIC: movl    $dcallee, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: daddress:
+; LINUX-32-STATIC-LABEL: daddress:
 ; LINUX-32-STATIC: 	movl	$dcallee, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: daddress:
+; LINUX-32-PIC-LABEL: daddress:
 ; LINUX-32-PIC: 	movl	$dcallee, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: daddress:
+; LINUX-64-PIC-LABEL: daddress:
 ; LINUX-64-PIC: 	leaq	dcallee(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -8766,19 +8766,19 @@ entry:
 	call void @callee() nounwind
 	call void @callee() nounwind
 	ret void
-; LINUX-64-STATIC: caller:
+; LINUX-64-STATIC-LABEL: caller:
 ; LINUX-64-STATIC: callq   callee
 ; LINUX-64-STATIC: callq   callee
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: caller:
+; LINUX-32-STATIC-LABEL: caller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	callee
 ; LINUX-32-STATIC-NEXT: 	calll	callee
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: caller:
+; LINUX-32-PIC-LABEL: caller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	callee
 ; LINUX-32-PIC-NEXT: 	calll	callee
@@ -8786,7 +8786,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: caller:
+; LINUX-64-PIC-LABEL: caller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	callee@PLT
 ; LINUX-64-PIC-NEXT: 	callq	callee@PLT
@@ -8841,19 +8841,19 @@ entry:
 	call void @dcallee() nounwind
 	call void @dcallee() nounwind
 	ret void
-; LINUX-64-STATIC: dcaller:
+; LINUX-64-STATIC-LABEL: dcaller:
 ; LINUX-64-STATIC: callq   dcallee
 ; LINUX-64-STATIC: callq   dcallee
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: dcaller:
+; LINUX-32-STATIC-LABEL: dcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	dcallee
 ; LINUX-32-STATIC-NEXT: 	calll	dcallee
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: dcaller:
+; LINUX-32-PIC-LABEL: dcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	dcallee
 ; LINUX-32-PIC-NEXT: 	calll	dcallee
@@ -8861,7 +8861,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: dcaller:
+; LINUX-64-PIC-LABEL: dcaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	dcallee
 ; LINUX-64-PIC-NEXT: 	callq	dcallee
@@ -8916,19 +8916,19 @@ entry:
 	call void @lcallee() nounwind
 	call void @lcallee() nounwind
 	ret void
-; LINUX-64-STATIC: lcaller:
+; LINUX-64-STATIC-LABEL: lcaller:
 ; LINUX-64-STATIC: callq   lcallee
 ; LINUX-64-STATIC: callq   lcallee
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: lcaller:
+; LINUX-32-STATIC-LABEL: lcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	lcallee
 ; LINUX-32-STATIC-NEXT: 	calll	lcallee
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: lcaller:
+; LINUX-32-PIC-LABEL: lcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	lcallee
 ; LINUX-32-PIC-NEXT: 	calll	lcallee
@@ -8936,7 +8936,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: lcaller:
+; LINUX-64-PIC-LABEL: lcaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	lcallee@PLT
 ; LINUX-64-PIC-NEXT: 	callq	lcallee@PLT
@@ -8990,24 +8990,24 @@ define void @tailcaller() nounwind {
 entry:
 	call void @callee() nounwind
 	ret void
-; LINUX-64-STATIC: tailcaller:
+; LINUX-64-STATIC-LABEL: tailcaller:
 ; LINUX-64-STATIC: callq   callee
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: tailcaller:
+; LINUX-32-STATIC-LABEL: tailcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	callee
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: tailcaller:
+; LINUX-32-PIC-LABEL: tailcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	callee
 ; LINUX-32-PIC-NEXT: 	addl
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: tailcaller:
+; LINUX-64-PIC-LABEL: tailcaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	callee@PLT
 ; LINUX-64-PIC-NEXT: 	popq
@@ -9054,24 +9054,24 @@ define void @dtailcaller() nounwind {
 entry:
 	call void @dcallee() nounwind
 	ret void
-; LINUX-64-STATIC: dtailcaller:
+; LINUX-64-STATIC-LABEL: dtailcaller:
 ; LINUX-64-STATIC: callq   dcallee
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: dtailcaller:
+; LINUX-32-STATIC-LABEL: dtailcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	dcallee
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: dtailcaller:
+; LINUX-32-PIC-LABEL: dtailcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	dcallee
 ; LINUX-32-PIC-NEXT: 	addl
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: dtailcaller:
+; LINUX-64-PIC-LABEL: dtailcaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	dcallee
 ; LINUX-64-PIC-NEXT: 	popq
@@ -9118,24 +9118,24 @@ define void @ltailcaller() nounwind {
 entry:
 	call void @lcallee() nounwind
 	ret void
-; LINUX-64-STATIC: ltailcaller:
+; LINUX-64-STATIC-LABEL: ltailcaller:
 ; LINUX-64-STATIC: callq   lcallee
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ltailcaller:
+; LINUX-32-STATIC-LABEL: ltailcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	lcallee
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ltailcaller:
+; LINUX-32-PIC-LABEL: ltailcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	lcallee
 ; LINUX-32-PIC-NEXT: 	addl
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ltailcaller:
+; LINUX-64-PIC-LABEL: ltailcaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	lcallee@PLT
 ; LINUX-64-PIC-NEXT: 	popq
@@ -9185,19 +9185,19 @@ entry:
 	%1 = load void ()** @ifunc, align 8
 	call void %1() nounwind
 	ret void
-; LINUX-64-STATIC: icaller:
+; LINUX-64-STATIC-LABEL: icaller:
 ; LINUX-64-STATIC: callq   *ifunc
 ; LINUX-64-STATIC: callq   *ifunc
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: icaller:
+; LINUX-32-STATIC-LABEL: icaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	*ifunc
 ; LINUX-32-STATIC-NEXT: 	calll	*ifunc
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: icaller:
+; LINUX-32-PIC-LABEL: icaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	*ifunc
 ; LINUX-32-PIC-NEXT: 	calll	*ifunc
@@ -9205,7 +9205,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: icaller:
+; LINUX-64-PIC-LABEL: icaller:
 ; LINUX-64-PIC: 	pushq	[[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ifunc@GOTPCREL(%rip), [[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	callq	*([[RBX]])
@@ -9275,19 +9275,19 @@ entry:
 	%1 = load void ()** @difunc, align 8
 	call void %1() nounwind
 	ret void
-; LINUX-64-STATIC: dicaller:
+; LINUX-64-STATIC-LABEL: dicaller:
 ; LINUX-64-STATIC: callq   *difunc
 ; LINUX-64-STATIC: callq   *difunc
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: dicaller:
+; LINUX-32-STATIC-LABEL: dicaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	*difunc
 ; LINUX-32-STATIC-NEXT: 	calll	*difunc
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: dicaller:
+; LINUX-32-PIC-LABEL: dicaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	*difunc
 ; LINUX-32-PIC-NEXT: 	calll	*difunc
@@ -9295,7 +9295,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: dicaller:
+; LINUX-64-PIC-LABEL: dicaller:
 ; LINUX-64-PIC: 	pushq	[[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	difunc@GOTPCREL(%rip), [[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	callq	*([[RBX]])
@@ -9358,19 +9358,19 @@ entry:
 	%1 = load void ()** @lifunc, align 8
 	call void %1() nounwind
 	ret void
-; LINUX-64-STATIC: licaller:
+; LINUX-64-STATIC-LABEL: licaller:
 ; LINUX-64-STATIC: callq   *lifunc
 ; LINUX-64-STATIC: callq   *lifunc
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: licaller:
+; LINUX-32-STATIC-LABEL: licaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	*lifunc
 ; LINUX-32-STATIC-NEXT: 	calll	*lifunc
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: licaller:
+; LINUX-32-PIC-LABEL: licaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	*lifunc
 ; LINUX-32-PIC-NEXT: 	calll	*lifunc
@@ -9378,7 +9378,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: licaller:
+; LINUX-64-PIC-LABEL: licaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	*lifunc(%rip)
 ; LINUX-64-PIC-NEXT: 	callq	*lifunc(%rip)
@@ -9440,19 +9440,19 @@ entry:
 	%1 = load void ()** @ifunc, align 8
 	call void %1() nounwind
 	ret void
-; LINUX-64-STATIC: itailcaller:
+; LINUX-64-STATIC-LABEL: itailcaller:
 ; LINUX-64-STATIC: callq   *ifunc
 ; LINUX-64-STATIC: callq   *ifunc
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: itailcaller:
+; LINUX-32-STATIC-LABEL: itailcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	*ifunc
 ; LINUX-32-STATIC-NEXT: 	calll	*ifunc
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: itailcaller:
+; LINUX-32-PIC-LABEL: itailcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	*ifunc
 ; LINUX-32-PIC-NEXT: 	calll	*ifunc
@@ -9460,7 +9460,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: itailcaller:
+; LINUX-64-PIC-LABEL: itailcaller:
 ; LINUX-64-PIC: 	pushq	[[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ifunc@GOTPCREL(%rip), [[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	callq	*([[RBX]])
@@ -9528,24 +9528,24 @@ entry:
 	%0 = load void ()** @difunc, align 8
 	call void %0() nounwind
 	ret void
-; LINUX-64-STATIC: ditailcaller:
+; LINUX-64-STATIC-LABEL: ditailcaller:
 ; LINUX-64-STATIC: callq   *difunc
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ditailcaller:
+; LINUX-32-STATIC-LABEL: ditailcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	*difunc
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ditailcaller:
+; LINUX-32-PIC-LABEL: ditailcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	*difunc
 ; LINUX-32-PIC-NEXT: 	addl
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ditailcaller:
+; LINUX-64-PIC-LABEL: ditailcaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	movq	difunc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	callq	*([[RAX]])
@@ -9596,24 +9596,24 @@ entry:
 	%0 = load void ()** @lifunc, align 8
 	call void %0() nounwind
 	ret void
-; LINUX-64-STATIC: litailcaller:
+; LINUX-64-STATIC-LABEL: litailcaller:
 ; LINUX-64-STATIC: callq   *lifunc
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: litailcaller:
+; LINUX-32-STATIC-LABEL: litailcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	*lifunc
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: litailcaller:
+; LINUX-32-PIC-LABEL: litailcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	*lifunc
 ; LINUX-32-PIC-NEXT: 	addl
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: litailcaller:
+; LINUX-64-PIC-LABEL: litailcaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	*lifunc(%rip)
 ; LINUX-64-PIC-NEXT: 	popq
diff --git a/test/CodeGen/X86/and-su.ll b/test/CodeGen/X86/and-su.ll
index 38db88a..70c2461 100644
--- a/test/CodeGen/X86/and-su.ll
+++ b/test/CodeGen/X86/and-su.ll
@@ -3,7 +3,7 @@
 ; Don't duplicate the load.
 
 define fastcc i32 @foo(i32* %p) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: andl $10, %eax
 ; CHECK: je
 	%t0 = load i32* %p
@@ -18,7 +18,7 @@ bb76:
 
 define fastcc double @bar(i32 %hash, double %x, double %y) nounwind {
 entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
   %0 = and i32 %hash, 15
   %1 = icmp ult i32 %0, 8
   br i1 %1, label %bb11, label %bb10
diff --git a/test/CodeGen/X86/apm.ll b/test/CodeGen/X86/apm.ll
index aaedf18..4ba1e21 100644
--- a/test/CodeGen/X86/apm.ll
+++ b/test/CodeGen/X86/apm.ll
@@ -2,11 +2,11 @@
 ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse3 | FileCheck %s -check-prefix=WIN64
 ; PR8573
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: leaq    (%rdi), %rax
 ; CHECK-NEXT: movl    %esi, %ecx
 ; CHECK-NEXT: monitor
-; WIN64: foo:
+; WIN64-LABEL: foo:
 ; WIN64:      leaq    (%rcx), %rax
 ; WIN64-NEXT: movl    %edx, %ecx
 ; WIN64-NEXT: movl    %r8d, %edx
@@ -19,11 +19,11 @@ entry:
 
 declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind
 
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: movl    %edi, %ecx
 ; CHECK-NEXT: movl    %esi, %eax
 ; CHECK-NEXT: mwait
-; WIN64: bar:
+; WIN64-LABEL: bar:
 ; WIN64:      movl    %edx, %eax
 ; WIN64-NEXT: mwait
 define void @bar(i32 %E, i32 %H) nounwind {
diff --git a/test/CodeGen/X86/asm-global-imm.ll b/test/CodeGen/X86/asm-global-imm.ll
index 6c569d6..ebf585a 100644
--- a/test/CodeGen/X86/asm-global-imm.ll
+++ b/test/CodeGen/X86/asm-global-imm.ll
@@ -7,7 +7,7 @@ target triple = "i686-apple-darwin9.0.0d2"
 @str = external global [12 x i8]		; <[12 x i8]*> [#uses=1]
 
 define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NOT: ret
 ; CHECK: test1 $_GV
 ; CHECK-NOT: ret
diff --git a/test/CodeGen/X86/asm-modifier-P.ll b/test/CodeGen/X86/asm-modifier-P.ll
index 6139da8..0aa5555 100644
--- a/test/CodeGen/X86/asm-modifier-P.ll
+++ b/test/CodeGen/X86/asm-modifier-P.ll
@@ -21,20 +21,20 @@ define void @test1() nounwind {
 entry:
 ; P suffix removes (rip) in -static 64-bit mode.
 
-; CHECK-PIC-64: test1:
+; CHECK-PIC-64-LABEL: test1:
 ; CHECK-PIC-64: movq	G@GOTPCREL(%rip), %rax
 ; CHECK-PIC-64: frob (%rax) x
 ; CHECK-PIC-64: frob (%rax) x
 
-; CHECK-STATIC-64: test1:
+; CHECK-STATIC-64-LABEL: test1:
 ; CHECK-STATIC-64: frob G(%rip) x
 ; CHECK-STATIC-64: frob G x
 
-; CHECK-PIC-32: test1:
+; CHECK-PIC-32-LABEL: test1:
 ; CHECK-PIC-32: frob G x
 ; CHECK-PIC-32: frob G x
 
-; CHECK-STATIC-32: test1:
+; CHECK-STATIC-32-LABEL: test1:
 ; CHECK-STATIC-32: frob G x
 ; CHECK-STATIC-32: frob G x
 
@@ -45,25 +45,25 @@ entry:
 
 define void @test3() nounwind {
 entry:
-; CHECK-STATIC-64: test3:
+; CHECK-STATIC-64-LABEL: test3:
 ; CHECK-STATIC-64: call bar
 ; CHECK-STATIC-64: call test3
 ; CHECK-STATIC-64: call $bar
 ; CHECK-STATIC-64: call $test3
 
-; CHECK-STATIC-32: test3:
+; CHECK-STATIC-32-LABEL: test3:
 ; CHECK-STATIC-32: call bar
 ; CHECK-STATIC-32: call test3
 ; CHECK-STATIC-32: call $bar
 ; CHECK-STATIC-32: call $test3
 
-; CHECK-PIC-64: test3:
+; CHECK-PIC-64-LABEL: test3:
 ; CHECK-PIC-64: call bar@PLT
 ; CHECK-PIC-64: call test3@PLT
 ; CHECK-PIC-64: call $bar
 ; CHECK-PIC-64: call $test3
 
-; CHECK-PIC-32: test3:
+; CHECK-PIC-32-LABEL: test3:
 ; CHECK-PIC-32: call bar@PLT
 ; CHECK-PIC-32: call test3@PLT
 ; CHECK-PIC-32: call $bar
diff --git a/test/CodeGen/X86/atom-bypass-slow-division-64.ll b/test/CodeGen/X86/atom-bypass-slow-division-64.ll
index 26b9a1e..d1b52a4 100644
--- a/test/CodeGen/X86/atom-bypass-slow-division-64.ll
+++ b/test/CodeGen/X86/atom-bypass-slow-division-64.ll
@@ -3,7 +3,7 @@
 ; Additional tests for 64-bit divide bypass
 
 define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
-; CHECK: Test_get_quotient:
+; CHECK-LABEL: Test_get_quotient:
 ; CHECK: movq %rdi, %rax
 ; CHECK: orq %rsi, %rax
 ; CHECK-NEXT: testq $-65536, %rax
@@ -17,7 +17,7 @@ define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
 }
 
 define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
-; CHECK: Test_get_remainder:
+; CHECK-LABEL: Test_get_remainder:
 ; CHECK: movq %rdi, %rax
 ; CHECK: orq %rsi, %rax
 ; CHECK-NEXT: testq $-65536, %rax
@@ -31,7 +31,7 @@ define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
 }
 
 define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind {
-; CHECK: Test_get_quotient_and_remainder:
+; CHECK-LABEL: Test_get_quotient_and_remainder:
 ; CHECK: movq %rdi, %rax
 ; CHECK: orq %rsi, %rax
 ; CHECK-NEXT: testq $-65536, %rax
diff --git a/test/CodeGen/X86/atom-bypass-slow-division.ll b/test/CodeGen/X86/atom-bypass-slow-division.ll
index 4612940..79001e5 100644
--- a/test/CodeGen/X86/atom-bypass-slow-division.ll
+++ b/test/CodeGen/X86/atom-bypass-slow-division.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s
 
 define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind {
-; CHECK: Test_get_quotient:
+; CHECK-LABEL: Test_get_quotient:
 ; CHECK: orl %ecx, %edx
 ; CHECK-NEXT: testl $-256, %edx
 ; CHECK-NEXT: je
@@ -14,7 +14,7 @@ define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind {
 }
 
 define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind {
-; CHECK: Test_get_remainder:
+; CHECK-LABEL: Test_get_remainder:
 ; CHECK: orl %ecx, %edx
 ; CHECK-NEXT: testl $-256, %edx
 ; CHECK-NEXT: je
@@ -27,7 +27,7 @@ define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind {
 }
 
 define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind {
-; CHECK: Test_get_quotient_and_remainder:
+; CHECK-LABEL: Test_get_quotient_and_remainder:
 ; CHECK: orl %ecx, %edx
 ; CHECK-NEXT: testl $-256, %edx
 ; CHECK-NEXT: je
@@ -44,7 +44,7 @@ define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind {
 }
 
 define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind {
-; CHECK: Test_use_div_and_idiv:
+; CHECK-LABEL: Test_use_div_and_idiv:
 ; CHECK: idivl
 ; CHECK: divb
 ; CHECK: divl
@@ -58,14 +58,14 @@ define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind {
 }
 
 define i32 @Test_use_div_imm_imm() nounwind {
-; CHECK: Test_use_div_imm_imm:
+; CHECK-LABEL: Test_use_div_imm_imm:
 ; CHECK: movl $64
   %resultdiv = sdiv i32 256, 4
   ret i32 %resultdiv
 }
 
 define i32 @Test_use_div_reg_imm(i32 %a) nounwind {
-; CHECK: Test_use_div_reg_imm:
+; CHECK-LABEL: Test_use_div_reg_imm:
 ; CHECK-NOT: test
 ; CHECK-NOT: idiv
 ; CHECK-NOT: divb
@@ -74,7 +74,7 @@ define i32 @Test_use_div_reg_imm(i32 %a) nounwind {
 }
 
 define i32 @Test_use_rem_reg_imm(i32 %a) nounwind {
-; CHECK: Test_use_rem_reg_imm:
+; CHECK-LABEL: Test_use_rem_reg_imm:
 ; CHECK-NOT: test
 ; CHECK-NOT: idiv
 ; CHECK-NOT: divb
@@ -83,7 +83,7 @@ define i32 @Test_use_rem_reg_imm(i32 %a) nounwind {
 }
 
 define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind {
-; CHECK: Test_use_divrem_reg_imm:
+; CHECK-LABEL: Test_use_divrem_reg_imm:
 ; CHECK-NOT: test
 ; CHECK-NOT: idiv
 ; CHECK-NOT: divb
@@ -94,7 +94,7 @@ define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind {
 }
 
 define i32 @Test_use_div_imm_reg(i32 %a) nounwind {
-; CHECK: Test_use_div_imm_reg:
+; CHECK-LABEL: Test_use_div_imm_reg:
 ; CHECK: test
 ; CHECK: idiv
 ; CHECK: divb
@@ -103,7 +103,7 @@ define i32 @Test_use_div_imm_reg(i32 %a) nounwind {
 }
 
 define i32 @Test_use_rem_imm_reg(i32 %a) nounwind {
-; CHECK: Test_use_rem_imm_reg:
+; CHECK-LABEL: Test_use_rem_imm_reg:
 ; CHECK: test
 ; CHECK: idiv
 ; CHECK: divb
diff --git a/test/CodeGen/X86/atomic-minmax-i6432.ll b/test/CodeGen/X86/atomic-minmax-i6432.ll
index 62f784f..1cfbc49 100644
--- a/test/CodeGen/X86/atomic-minmax-i6432.ll
+++ b/test/CodeGen/X86/atomic-minmax-i6432.ll
@@ -97,7 +97,7 @@ define void @atomic_maxmin_i6432() {
 @id = internal global i64 0, align 8
 
 define void @tf_bug(i8* %ptr) nounwind {
-; PIC: tf_bug:
+; PIC-LABEL: tf_bug:
 ; PIC: movl _id-L1$pb(
 ; PIC: movl (_id-L1$pb)+4(
   %tmp1 = atomicrmw add i64* @id, i64 1 seq_cst
diff --git a/test/CodeGen/X86/atomic-or.ll b/test/CodeGen/X86/atomic-or.ll
index d759beb..1687e07 100644
--- a/test/CodeGen/X86/atomic-or.ll
+++ b/test/CodeGen/X86/atomic-or.ll
@@ -7,7 +7,7 @@ entry:
   %p.addr = alloca i64*, align 8
   store i64* %p, i64** %p.addr, align 8
   %tmp = load i64** %p.addr, align 8
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: movl    $2147483648, %eax
 ; CHECK: lock
 ; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}})
@@ -20,7 +20,7 @@ entry:
   %p.addr = alloca i64*, align 8
   store i64* %p, i64** %p.addr, align 8
   %tmp = load i64** %p.addr, align 8
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: lock
 ; CHECK-NEXT: orq $2147483644, (%r{{.*}})
   %0 = atomicrmw or i64* %tmp, i64 2147483644 seq_cst
diff --git a/test/CodeGen/X86/atomic_add.ll b/test/CodeGen/X86/atomic_add.ll
index 6b3a6b2..bdd25e6 100644
--- a/test/CodeGen/X86/atomic_add.ll
+++ b/test/CodeGen/X86/atomic_add.ll
@@ -4,7 +4,7 @@
 
 define void @sub1(i32* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: sub1:
+; CHECK-LABEL: sub1:
 ; CHECK: subl
   %0 = atomicrmw sub i32* %p, i32 %v monotonic
   ret void
@@ -12,7 +12,7 @@ entry:
 
 define void @inc4(i64* nocapture %p) nounwind ssp {
 entry:
-; CHECK: inc4:
+; CHECK-LABEL: inc4:
 ; CHECK: incq
   %0 = atomicrmw add i64* %p, i64 1 monotonic
   ret void
@@ -20,7 +20,7 @@ entry:
 
 define void @add8(i64* nocapture %p) nounwind ssp {
 entry:
-; CHECK: add8:
+; CHECK-LABEL: add8:
 ; CHECK: addq $2
   %0 = atomicrmw add i64* %p, i64 2 monotonic
   ret void
@@ -28,7 +28,7 @@ entry:
 
 define void @add4(i64* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: add4:
+; CHECK-LABEL: add4:
 ; CHECK: addq
   %0 = sext i32 %v to i64		; <i64> [#uses=1]
   %1 = atomicrmw add i64* %p, i64 %0 monotonic
@@ -37,7 +37,7 @@ entry:
 
 define void @inc3(i8* nocapture %p) nounwind ssp {
 entry:
-; CHECK: inc3:
+; CHECK-LABEL: inc3:
 ; CHECK: incb
   %0 = atomicrmw add i8* %p, i8 1 monotonic
   ret void
@@ -45,7 +45,7 @@ entry:
 
 define void @add7(i8* nocapture %p) nounwind ssp {
 entry:
-; CHECK: add7:
+; CHECK-LABEL: add7:
 ; CHECK: addb $2
   %0 = atomicrmw add i8* %p, i8 2 monotonic
   ret void
@@ -53,7 +53,7 @@ entry:
 
 define void @add3(i8* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: add3:
+; CHECK-LABEL: add3:
 ; CHECK: addb
   %0 = trunc i32 %v to i8		; <i8> [#uses=1]
   %1 = atomicrmw add i8* %p, i8 %0 monotonic
@@ -62,7 +62,7 @@ entry:
 
 define void @inc2(i16* nocapture %p) nounwind ssp {
 entry:
-; CHECK: inc2:
+; CHECK-LABEL: inc2:
 ; CHECK: incw
   %0 = atomicrmw add i16* %p, i16 1 monotonic
   ret void
@@ -70,7 +70,7 @@ entry:
 
 define void @add6(i16* nocapture %p) nounwind ssp {
 entry:
-; CHECK: add6:
+; CHECK-LABEL: add6:
 ; CHECK: addw $2
   %0 = atomicrmw add i16* %p, i16 2 monotonic
   ret void
@@ -78,7 +78,7 @@ entry:
 
 define void @add2(i16* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: add2:
+; CHECK-LABEL: add2:
 ; CHECK: addw
 	%0 = trunc i32 %v to i16		; <i16> [#uses=1]
   %1 = atomicrmw add i16* %p, i16 %0 monotonic
@@ -87,7 +87,7 @@ entry:
 
 define void @inc1(i32* nocapture %p) nounwind ssp {
 entry:
-; CHECK: inc1:
+; CHECK-LABEL: inc1:
 ; CHECK: incl
   %0 = atomicrmw add i32* %p, i32 1 monotonic
   ret void
@@ -95,7 +95,7 @@ entry:
 
 define void @add5(i32* nocapture %p) nounwind ssp {
 entry:
-; CHECK: add5:
+; CHECK-LABEL: add5:
 ; CHECK: addl $2
   %0 = atomicrmw add i32* %p, i32 2 monotonic
   ret void
@@ -103,7 +103,7 @@ entry:
 
 define void @add1(i32* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: add1:
+; CHECK-LABEL: add1:
 ; CHECK: addl
   %0 = atomicrmw add i32* %p, i32 %v monotonic
   ret void
@@ -111,7 +111,7 @@ entry:
 
 define void @dec4(i64* nocapture %p) nounwind ssp {
 entry:
-; CHECK: dec4:
+; CHECK-LABEL: dec4:
 ; CHECK: decq
   %0 = atomicrmw sub i64* %p, i64 1 monotonic
   ret void
@@ -119,7 +119,7 @@ entry:
 
 define void @sub8(i64* nocapture %p) nounwind ssp {
 entry:
-; CHECK: sub8:
+; CHECK-LABEL: sub8:
 ; CHECK: subq $2
   %0 = atomicrmw sub i64* %p, i64 2 monotonic
   ret void
@@ -127,7 +127,7 @@ entry:
 
 define void @sub4(i64* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: sub4:
+; CHECK-LABEL: sub4:
 ; CHECK: subq
 	%0 = sext i32 %v to i64		; <i64> [#uses=1]
   %1 = atomicrmw sub i64* %p, i64 %0 monotonic
@@ -136,7 +136,7 @@ entry:
 
 define void @dec3(i8* nocapture %p) nounwind ssp {
 entry:
-; CHECK: dec3:
+; CHECK-LABEL: dec3:
 ; CHECK: decb
   %0 = atomicrmw sub i8* %p, i8 1 monotonic
   ret void
@@ -144,7 +144,7 @@ entry:
 
 define void @sub7(i8* nocapture %p) nounwind ssp {
 entry:
-; CHECK: sub7:
+; CHECK-LABEL: sub7:
 ; CHECK: subb $2
   %0 = atomicrmw sub i8* %p, i8 2 monotonic
   ret void
@@ -152,7 +152,7 @@ entry:
 
 define void @sub3(i8* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: sub3:
+; CHECK-LABEL: sub3:
 ; CHECK: subb
 	%0 = trunc i32 %v to i8		; <i8> [#uses=1]
   %1 = atomicrmw sub i8* %p, i8 %0 monotonic
@@ -161,7 +161,7 @@ entry:
 
 define void @dec2(i16* nocapture %p) nounwind ssp {
 entry:
-; CHECK: dec2:
+; CHECK-LABEL: dec2:
 ; CHECK: decw
   %0 = atomicrmw sub i16* %p, i16 1 monotonic
   ret void
@@ -169,7 +169,7 @@ entry:
 
 define void @sub6(i16* nocapture %p) nounwind ssp {
 entry:
-; CHECK: sub6:
+; CHECK-LABEL: sub6:
 ; CHECK: subw $2
   %0 = atomicrmw sub i16* %p, i16 2 monotonic
   ret void
@@ -177,7 +177,7 @@ entry:
 
 define void @sub2(i16* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: sub2:
+; CHECK-LABEL: sub2:
 ; CHECK-NOT: negl
 ; CHECK: subw
 	%0 = trunc i32 %v to i16		; <i16> [#uses=1]
@@ -187,7 +187,7 @@ entry:
 
 define void @dec1(i32* nocapture %p) nounwind ssp {
 entry:
-; CHECK: dec1:
+; CHECK-LABEL: dec1:
 ; CHECK: decl
   %0 = atomicrmw sub i32* %p, i32 1 monotonic
   ret void
@@ -195,7 +195,7 @@ entry:
 
 define void @sub5(i32* nocapture %p) nounwind ssp {
 entry:
-; CHECK: sub5:
+; CHECK-LABEL: sub5:
 ; CHECK: subl $2
   %0 = atomicrmw sub i32* %p, i32 2 monotonic
   ret void
diff --git a/test/CodeGen/X86/avx-minmax.ll b/test/CodeGen/X86/avx-minmax.ll
index eff9251..c94962b 100644
--- a/test/CodeGen/X86/avx-minmax.ll
+++ b/test/CodeGen/X86/avx-minmax.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+avx -asm-verbose=false -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=UNSAFE %s
 
-; UNSAFE: maxpd:
+; UNSAFE-LABEL: maxpd:
 ; UNSAFE: vmaxpd {{.+}}, %xmm
 define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) {
   %max_is_x = fcmp oge <2 x double> %x, %y
@@ -8,7 +8,7 @@ define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %max
 }
 
-; UNSAFE: minpd:
+; UNSAFE-LABEL: minpd:
 ; UNSAFE: vminpd {{.+}}, %xmm
 define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) {
   %min_is_x = fcmp ole <2 x double> %x, %y
@@ -16,7 +16,7 @@ define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %min
 }
 
-; UNSAFE: maxps:
+; UNSAFE-LABEL: maxps:
 ; UNSAFE: vmaxps {{.+}}, %xmm
 define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) {
   %max_is_x = fcmp oge <4 x float> %x, %y
@@ -24,7 +24,7 @@ define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) {
   ret <4 x float> %max
 }
 
-; UNSAFE: minps:
+; UNSAFE-LABEL: minps:
 ; UNSAFE: vminps {{.+}}, %xmm
 define <4 x float> @minps(<4 x float> %x, <4 x float> %y) {
   %min_is_x = fcmp ole <4 x float> %x, %y
@@ -32,7 +32,7 @@ define <4 x float> @minps(<4 x float> %x, <4 x float> %y) {
   ret <4 x float> %min
 }
 
-; UNSAFE: vmaxpd:
+; UNSAFE-LABEL: vmaxpd:
 ; UNSAFE: vmaxpd {{.+}}, %ymm
 define <4 x double> @vmaxpd(<4 x double> %x, <4 x double> %y) {
   %max_is_x = fcmp oge <4 x double> %x, %y
@@ -40,7 +40,7 @@ define <4 x double> @vmaxpd(<4 x double> %x, <4 x double> %y) {
   ret <4 x double> %max
 }
 
-; UNSAFE: vminpd:
+; UNSAFE-LABEL: vminpd:
 ; UNSAFE: vminpd {{.+}}, %ymm
 define <4 x double> @vminpd(<4 x double> %x, <4 x double> %y) {
   %min_is_x = fcmp ole <4 x double> %x, %y
@@ -48,7 +48,7 @@ define <4 x double> @vminpd(<4 x double> %x, <4 x double> %y) {
   ret <4 x double> %min
 }
 
-; UNSAFE: vmaxps:
+; UNSAFE-LABEL: vmaxps:
 ; UNSAFE: vmaxps {{.+}}, %ymm
 define <8 x float> @vmaxps(<8 x float> %x, <8 x float> %y) {
   %max_is_x = fcmp oge <8 x float> %x, %y
@@ -56,7 +56,7 @@ define <8 x float> @vmaxps(<8 x float> %x, <8 x float> %y) {
   ret <8 x float> %max
 }
 
-; UNSAFE: vminps:
+; UNSAFE-LABEL: vminps:
 ; UNSAFE: vminps {{.+}}, %ymm
 define <8 x float> @vminps(<8 x float> %x, <8 x float> %y) {
   %min_is_x = fcmp ole <8 x float> %x, %y
diff --git a/test/CodeGen/X86/avx-shuffle-x86_32.ll b/test/CodeGen/X86/avx-shuffle-x86_32.ll
index e203c4e..78b4888 100644
--- a/test/CodeGen/X86/avx-shuffle-x86_32.ll
+++ b/test/CodeGen/X86/avx-shuffle-x86_32.ll
@@ -3,6 +3,6 @@
 define <4 x i64> @test1(<4 x i64> %a) nounwind {
  %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  ret <4 x i64>%b
- ; CHECK: test1:
+ ; CHECK-LABEL: test1:
  ; CHECK-NOT: vinsertf128
  }
diff --git a/test/CodeGen/X86/avx-vextractf128.ll b/test/CodeGen/X86/avx-vextractf128.ll
index ad8365b..fa49f94 100644
--- a/test/CodeGen/X86/avx-vextractf128.ll
+++ b/test/CodeGen/X86/avx-vextractf128.ll
@@ -114,7 +114,7 @@ define void @t9(i64* %p) {
  store i64 0, i64* %s
  ret void
 
-; CHECK: t9:
+; CHECK-LABEL: t9:
 ; CHECK: vxorps	%xmm
 ; CHECK-NOT: vextractf
 ; CHECK: vmovups
diff --git a/test/CodeGen/X86/avx2-logic.ll b/test/CodeGen/X86/avx2-logic.ll
index a5bb1a8..3d4fcec 100644
--- a/test/CodeGen/X86/avx2-logic.ll
+++ b/test/CodeGen/X86/avx2-logic.ll
@@ -55,7 +55,7 @@ define <32 x i8> @vpblendvb(<32 x i1> %cond, <32 x i8> %x, <32 x i8> %y) {
 
 define <8 x i32> @signd(<8 x i32> %a, <8 x i32> %b) nounwind {
 entry:
-; CHECK: signd:
+; CHECK-LABEL: signd:
 ; CHECK: psignd
 ; CHECK-NOT: sub
 ; CHECK: ret
@@ -70,7 +70,7 @@ entry:
 
 define <8 x i32> @blendvb(<8 x i32> %b, <8 x i32> %a, <8 x i32> %c) nounwind {
 entry:
-; CHECK: blendvb:
+; CHECK-LABEL: blendvb:
 ; CHECK: pblendvb
 ; CHECK: ret
   %b.lobit = ashr <8 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
diff --git a/test/CodeGen/X86/avx2-phaddsub.ll b/test/CodeGen/X86/avx2-phaddsub.ll
index 4eac71d..3f9c95c 100644
--- a/test/CodeGen/X86/avx2-phaddsub.ll
+++ b/test/CodeGen/X86/avx2-phaddsub.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+avx2 | FileCheck %s
 
-; CHECK: phaddw1:
+; CHECK-LABEL: phaddw1:
 ; CHECK: vphaddw
 define <16 x i16> @phaddw1(<16 x i16> %x, <16 x i16> %y) {
   %a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
@@ -9,7 +9,7 @@ define <16 x i16> @phaddw1(<16 x i16> %x, <16 x i16> %y) {
   ret <16 x i16> %r
 }
 
-; CHECK: phaddw2:
+; CHECK-LABEL: phaddw2:
 ; CHECK: vphaddw
 define <16 x i16> @phaddw2(<16 x i16> %x, <16 x i16> %y) {
   %a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
@@ -18,7 +18,7 @@ define <16 x i16> @phaddw2(<16 x i16> %x, <16 x i16> %y) {
   ret <16 x i16> %r
 }
 
-; CHECK: phaddd1:
+; CHECK-LABEL: phaddd1:
 ; CHECK: vphaddd
 define <8 x i32> @phaddd1(<8 x i32> %x, <8 x i32> %y) {
   %a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
@@ -27,7 +27,7 @@ define <8 x i32> @phaddd1(<8 x i32> %x, <8 x i32> %y) {
   ret <8 x i32> %r
 }
 
-; CHECK: phaddd2:
+; CHECK-LABEL: phaddd2:
 ; CHECK: vphaddd
 define <8 x i32> @phaddd2(<8 x i32> %x, <8 x i32> %y) {
   %a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 1, i32 2, i32 9, i32 10, i32 5, i32 6, i32 13, i32 14>
@@ -36,7 +36,7 @@ define <8 x i32> @phaddd2(<8 x i32> %x, <8 x i32> %y) {
   ret <8 x i32> %r
 }
 
-; CHECK: phaddd3:
+; CHECK-LABEL: phaddd3:
 ; CHECK: vphaddd
 define <8 x i32> @phaddd3(<8 x i32> %x) {
   %a = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
@@ -45,7 +45,7 @@ define <8 x i32> @phaddd3(<8 x i32> %x) {
   ret <8 x i32> %r
 }
 
-; CHECK: phsubw1:
+; CHECK-LABEL: phsubw1:
 ; CHECK: vphsubw
 define <16 x i16> @phsubw1(<16 x i16> %x, <16 x i16> %y) {
   %a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
@@ -54,7 +54,7 @@ define <16 x i16> @phsubw1(<16 x i16> %x, <16 x i16> %y) {
   ret <16 x i16> %r
 }
 
-; CHECK: phsubd1:
+; CHECK-LABEL: phsubd1:
 ; CHECK: vphsubd
 define <8 x i32> @phsubd1(<8 x i32> %x, <8 x i32> %y) {
   %a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
@@ -63,7 +63,7 @@ define <8 x i32> @phsubd1(<8 x i32> %x, <8 x i32> %y) {
   ret <8 x i32> %r
 }
 
-; CHECK: phsubd2:
+; CHECK-LABEL: phsubd2:
 ; CHECK: vphsubd
 define <8 x i32> @phsubd2(<8 x i32> %x, <8 x i32> %y) {
   %a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 undef, i32 8, i32 undef, i32 4, i32 6, i32 12, i32 14>
diff --git a/test/CodeGen/X86/avx2-shift.ll b/test/CodeGen/X86/avx2-shift.ll
index 1f192a0..7fdbaaa 100644
--- a/test/CodeGen/X86/avx2-shift.ll
+++ b/test/CodeGen/X86/avx2-shift.ll
@@ -212,7 +212,7 @@ define <4 x i64> @variable_srl3_load(<4 x i64> %x, <4 x i64>* %y) {
 define <32 x i8> @shl9(<32 x i8> %A) nounwind {
   %B = shl <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <32 x i8> %B
-; CHECK: shl9:
+; CHECK-LABEL: shl9:
 ; CHECK: vpsllw $3
 ; CHECK: vpand
 ; CHECK: ret
@@ -221,7 +221,7 @@ define <32 x i8> @shl9(<32 x i8> %A) nounwind {
 define <32 x i8> @shr9(<32 x i8> %A) nounwind {
   %B = lshr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <32 x i8> %B
-; CHECK: shr9:
+; CHECK-LABEL: shr9:
 ; CHECK: vpsrlw $3
 ; CHECK: vpand
 ; CHECK: ret
@@ -230,7 +230,7 @@ define <32 x i8> @shr9(<32 x i8> %A) nounwind {
 define <32 x i8> @sra_v32i8_7(<32 x i8> %A) nounwind {
   %B = ashr <32 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
   ret <32 x i8> %B
-; CHECK: sra_v32i8_7:
+; CHECK-LABEL: sra_v32i8_7:
 ; CHECK: vpxor
 ; CHECK: vpcmpgtb
 ; CHECK: ret
@@ -239,7 +239,7 @@ define <32 x i8> @sra_v32i8_7(<32 x i8> %A) nounwind {
 define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind {
   %B = ashr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <32 x i8> %B
-; CHECK: sra_v32i8:
+; CHECK-LABEL: sra_v32i8:
 ; CHECK: vpsrlw $3
 ; CHECK: vpand
 ; CHECK: vpxor
diff --git a/test/CodeGen/X86/bmi.ll b/test/CodeGen/X86/bmi.ll
index b89e648..4eda888 100644
--- a/test/CodeGen/X86/bmi.ll
+++ b/test/CodeGen/X86/bmi.ll
@@ -8,21 +8,21 @@ declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone
 define i8 @t1(i8 %x) nounwind  {
   %tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 false )
   ret i8 %tmp
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: tzcntl
 }
 
 define i16 @t2(i16 %x) nounwind  {
   %tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 false )
   ret i16 %tmp
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: tzcntw
 }
 
 define i32 @t3(i32 %x) nounwind  {
   %tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 false )
   ret i32 %tmp
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: tzcntl
 }
 
@@ -30,42 +30,42 @@ define i32 @tzcnt32_load(i32* %x) nounwind  {
   %x1 = load i32* %x
   %tmp = tail call i32 @llvm.cttz.i32(i32 %x1, i1 false )
   ret i32 %tmp
-; CHECK: tzcnt32_load:
+; CHECK-LABEL: tzcnt32_load:
 ; CHECK: tzcntl ({{.*}})
 }
 
 define i64 @t4(i64 %x) nounwind  {
   %tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 false )
   ret i64 %tmp
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: tzcntq
 }
 
 define i8 @t5(i8 %x) nounwind  {
   %tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 true )
   ret i8 %tmp
-; CHECK: t5:
+; CHECK-LABEL: t5:
 ; CHECK: tzcntl
 }
 
 define i16 @t6(i16 %x) nounwind  {
   %tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 true )
   ret i16 %tmp
-; CHECK: t6:
+; CHECK-LABEL: t6:
 ; CHECK: tzcntw
 }
 
 define i32 @t7(i32 %x) nounwind  {
   %tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true )
   ret i32 %tmp
-; CHECK: t7:
+; CHECK-LABEL: t7:
 ; CHECK: tzcntl
 }
 
 define i64 @t8(i64 %x) nounwind  {
   %tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 true )
   ret i64 %tmp
-; CHECK: t8:
+; CHECK-LABEL: t8:
 ; CHECK: tzcntq
 }
 
@@ -73,7 +73,7 @@ define i32 @andn32(i32 %x, i32 %y) nounwind readnone {
   %tmp1 = xor i32 %x, -1
   %tmp2 = and i32 %y, %tmp1
   ret i32 %tmp2
-; CHECK: andn32:
+; CHECK-LABEL: andn32:
 ; CHECK: andnl
 }
 
@@ -82,7 +82,7 @@ define i32 @andn32_load(i32 %x, i32* %y) nounwind readnone {
   %tmp1 = xor i32 %x, -1
   %tmp2 = and i32 %y1, %tmp1
   ret i32 %tmp2
-; CHECK: andn32_load:
+; CHECK-LABEL: andn32_load:
 ; CHECK: andnl ({{.*}})
 }
 
@@ -90,14 +90,14 @@ define i64 @andn64(i64 %x, i64 %y) nounwind readnone {
   %tmp1 = xor i64 %x, -1
   %tmp2 = and i64 %tmp1, %y
   ret i64 %tmp2
-; CHECK: andn64:
+; CHECK-LABEL: andn64:
 ; CHECK: andnq
 }
 
 define i32 @bextr32(i32 %x, i32 %y) nounwind readnone {
   %tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 %y)
   ret i32 %tmp
-; CHECK: bextr32:
+; CHECK-LABEL: bextr32:
 ; CHECK: bextrl
 }
 
@@ -105,7 +105,7 @@ define i32 @bextr32_load(i32* %x, i32 %y) nounwind readnone {
   %x1 = load i32* %x
   %tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x1, i32 %y)
   ret i32 %tmp
-; CHECK: bextr32_load:
+; CHECK-LABEL: bextr32_load:
 ; CHECK: bextrl {{.*}}, ({{.*}}), {{.*}}
 }
 
@@ -114,7 +114,7 @@ declare i32 @llvm.x86.bmi.bextr.32(i32, i32) nounwind readnone
 define i64 @bextr64(i64 %x, i64 %y) nounwind readnone {
   %tmp = tail call i64 @llvm.x86.bmi.bextr.64(i64 %x, i64 %y)
   ret i64 %tmp
-; CHECK: bextr64:
+; CHECK-LABEL: bextr64:
 ; CHECK: bextrq
 }
 
@@ -123,7 +123,7 @@ declare i64 @llvm.x86.bmi.bextr.64(i64, i64) nounwind readnone
 define i32 @bzhi32(i32 %x, i32 %y) nounwind readnone {
   %tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x, i32 %y)
   ret i32 %tmp
-; CHECK: bzhi32:
+; CHECK-LABEL: bzhi32:
 ; CHECK: bzhil
 }
 
@@ -131,7 +131,7 @@ define i32 @bzhi32_load(i32* %x, i32 %y) nounwind readnone {
   %x1 = load i32* %x
   %tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x1, i32 %y)
   ret i32 %tmp
-; CHECK: bzhi32_load:
+; CHECK-LABEL: bzhi32_load:
 ; CHECK: bzhil {{.*}}, ({{.*}}), {{.*}}
 }
 
@@ -140,7 +140,7 @@ declare i32 @llvm.x86.bmi.bzhi.32(i32, i32) nounwind readnone
 define i64 @bzhi64(i64 %x, i64 %y) nounwind readnone {
   %tmp = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %x, i64 %y)
   ret i64 %tmp
-; CHECK: bzhi64:
+; CHECK-LABEL: bzhi64:
 ; CHECK: bzhiq
 }
 
@@ -150,7 +150,7 @@ define i32 @blsi32(i32 %x) nounwind readnone {
   %tmp = sub i32 0, %x
   %tmp2 = and i32 %x, %tmp
   ret i32 %tmp2
-; CHECK: blsi32:
+; CHECK-LABEL: blsi32:
 ; CHECK: blsil
 }
 
@@ -159,7 +159,7 @@ define i32 @blsi32_load(i32* %x) nounwind readnone {
   %tmp = sub i32 0, %x1
   %tmp2 = and i32 %x1, %tmp
   ret i32 %tmp2
-; CHECK: blsi32_load:
+; CHECK-LABEL: blsi32_load:
 ; CHECK: blsil ({{.*}})
 }
 
@@ -167,7 +167,7 @@ define i64 @blsi64(i64 %x) nounwind readnone {
   %tmp = sub i64 0, %x
   %tmp2 = and i64 %tmp, %x
   ret i64 %tmp2
-; CHECK: blsi64:
+; CHECK-LABEL: blsi64:
 ; CHECK: blsiq
 }
 
@@ -175,7 +175,7 @@ define i32 @blsmsk32(i32 %x) nounwind readnone {
   %tmp = sub i32 %x, 1
   %tmp2 = xor i32 %x, %tmp
   ret i32 %tmp2
-; CHECK: blsmsk32:
+; CHECK-LABEL: blsmsk32:
 ; CHECK: blsmskl
 }
 
@@ -184,7 +184,7 @@ define i32 @blsmsk32_load(i32* %x) nounwind readnone {
   %tmp = sub i32 %x1, 1
   %tmp2 = xor i32 %x1, %tmp
   ret i32 %tmp2
-; CHECK: blsmsk32_load:
+; CHECK-LABEL: blsmsk32_load:
 ; CHECK: blsmskl ({{.*}})
 }
 
@@ -192,7 +192,7 @@ define i64 @blsmsk64(i64 %x) nounwind readnone {
   %tmp = sub i64 %x, 1
   %tmp2 = xor i64 %tmp, %x
   ret i64 %tmp2
-; CHECK: blsmsk64:
+; CHECK-LABEL: blsmsk64:
 ; CHECK: blsmskq
 }
 
@@ -200,7 +200,7 @@ define i32 @blsr32(i32 %x) nounwind readnone {
   %tmp = sub i32 %x, 1
   %tmp2 = and i32 %x, %tmp
   ret i32 %tmp2
-; CHECK: blsr32:
+; CHECK-LABEL: blsr32:
 ; CHECK: blsrl
 }
 
@@ -209,7 +209,7 @@ define i32 @blsr32_load(i32* %x) nounwind readnone {
   %tmp = sub i32 %x1, 1
   %tmp2 = and i32 %x1, %tmp
   ret i32 %tmp2
-; CHECK: blsr32_load:
+; CHECK-LABEL: blsr32_load:
 ; CHECK: blsrl ({{.*}})
 }
 
@@ -217,14 +217,14 @@ define i64 @blsr64(i64 %x) nounwind readnone {
   %tmp = sub i64 %x, 1
   %tmp2 = and i64 %tmp, %x
   ret i64 %tmp2
-; CHECK: blsr64:
+; CHECK-LABEL: blsr64:
 ; CHECK: blsrq
 }
 
 define i32 @pdep32(i32 %x, i32 %y) nounwind readnone {
   %tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y)
   ret i32 %tmp
-; CHECK: pdep32:
+; CHECK-LABEL: pdep32:
 ; CHECK: pdepl
 }
 
@@ -232,7 +232,7 @@ define i32 @pdep32_load(i32 %x, i32* %y) nounwind readnone {
   %y1 = load i32* %y
   %tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y1)
   ret i32 %tmp
-; CHECK: pdep32_load:
+; CHECK-LABEL: pdep32_load:
 ; CHECK: pdepl ({{.*}})
 }
 
@@ -241,7 +241,7 @@ declare i32 @llvm.x86.bmi.pdep.32(i32, i32) nounwind readnone
 define i64 @pdep64(i64 %x, i64 %y) nounwind readnone {
   %tmp = tail call i64 @llvm.x86.bmi.pdep.64(i64 %x, i64 %y)
   ret i64 %tmp
-; CHECK: pdep64:
+; CHECK-LABEL: pdep64:
 ; CHECK: pdepq
 }
 
@@ -250,7 +250,7 @@ declare i64 @llvm.x86.bmi.pdep.64(i64, i64) nounwind readnone
 define i32 @pext32(i32 %x, i32 %y) nounwind readnone {
   %tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y)
   ret i32 %tmp
-; CHECK: pext32:
+; CHECK-LABEL: pext32:
 ; CHECK: pextl
 }
 
@@ -258,7 +258,7 @@ define i32 @pext32_load(i32 %x, i32* %y) nounwind readnone {
   %y1 = load i32* %y
   %tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y1)
   ret i32 %tmp
-; CHECK: pext32_load:
+; CHECK-LABEL: pext32_load:
 ; CHECK: pextl ({{.*}})
 }
 
@@ -267,7 +267,7 @@ declare i32 @llvm.x86.bmi.pext.32(i32, i32) nounwind readnone
 define i64 @pext64(i64 %x, i64 %y) nounwind readnone {
   %tmp = tail call i64 @llvm.x86.bmi.pext.64(i64 %x, i64 %y)
   ret i64 %tmp
-; CHECK: pext64:
+; CHECK-LABEL: pext64:
 ; CHECK: pextq
 }
 
diff --git a/test/CodeGen/X86/break-sse-dep.ll b/test/CodeGen/X86/break-sse-dep.ll
index 4d80189..8124d6f 100644
--- a/test/CodeGen/X86/break-sse-dep.ll
+++ b/test/CodeGen/X86/break-sse-dep.ll
@@ -3,7 +3,7 @@
 
 define double @t1(float* nocapture %x) nounwind readonly ssp {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: movss ([[A0:%rdi|%rcx]]), %xmm0
 ; CHECK: cvtss2sd %xmm0, %xmm0
 
@@ -14,7 +14,7 @@ entry:
 
 define float @t2(double* nocapture %x) nounwind readonly ssp optsize {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: cvtsd2ss ([[A0]]), %xmm0
   %0 = load double* %x, align 8
   %1 = fptrunc double %0 to float
@@ -23,7 +23,7 @@ entry:
 
 define float @squirtf(float* %x) nounwind {
 entry:
-; CHECK: squirtf:
+; CHECK-LABEL: squirtf:
 ; CHECK: movss ([[A0]]), %xmm0
 ; CHECK: sqrtss %xmm0, %xmm0
   %z = load float* %x
@@ -33,7 +33,7 @@ entry:
 
 define double @squirt(double* %x) nounwind {
 entry:
-; CHECK: squirt:
+; CHECK-LABEL: squirt:
 ; CHECK: sqrtsd ([[A0]]), %xmm0
   %z = load double* %x
   %t = call double @llvm.sqrt.f64(double %z)
@@ -42,7 +42,7 @@ entry:
 
 define float @squirtf_size(float* %x) nounwind optsize {
 entry:
-; CHECK: squirtf_size:
+; CHECK-LABEL: squirtf_size:
 ; CHECK: sqrtss ([[A0]]), %xmm0
   %z = load float* %x
   %t = call float @llvm.sqrt.f32(float %z)
@@ -51,7 +51,7 @@ entry:
 
 define double @squirt_size(double* %x) nounwind optsize {
 entry:
-; CHECK: squirt_size:
+; CHECK-LABEL: squirt_size:
 ; CHECK: sqrtsd ([[A0]]), %xmm0
   %z = load double* %x
   %t = call double @llvm.sqrt.f64(double %z)
diff --git a/test/CodeGen/X86/bswap-inline-asm.ll b/test/CodeGen/X86/bswap-inline-asm.ll
index d69bfa6..f8f154c 100644
--- a/test/CodeGen/X86/bswap-inline-asm.ll
+++ b/test/CodeGen/X86/bswap-inline-asm.ll
@@ -3,84 +3,84 @@
 
 ; CHK-NOT: InlineAsm
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: bswapq
 define i64 @foo(i64 %x) nounwind {
 	%asmtmp = tail call i64 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
 	ret i64 %asmtmp
 }
 
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: bswapq
 define i64 @bar(i64 %x) nounwind {
 	%asmtmp = tail call i64 asm "bswapq ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
 	ret i64 %asmtmp
 }
 
-; CHECK: pen:
+; CHECK-LABEL: pen:
 ; CHECK: bswapl
 define i32 @pen(i32 %x) nounwind {
 	%asmtmp = tail call i32 asm "bswapl ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind
 	ret i32 %asmtmp
 }
 
-; CHECK: s16:
+; CHECK-LABEL: s16:
 ; CHECK: rolw    $8,
 define zeroext i16 @s16(i16 zeroext %x) nounwind {
   %asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind
   ret i16 %asmtmp
 }
 
-; CHECK: t16:
+; CHECK-LABEL: t16:
 ; CHECK: rolw    $8,
 define zeroext i16 @t16(i16 zeroext %x) nounwind {
   %asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind
   ret i16 %asmtmp
 }
 
-; CHECK: u16:
+; CHECK-LABEL: u16:
 ; CHECK: rolw    $8,
 define zeroext i16 @u16(i16 zeroext %x) nounwind {
   %asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind
   ret i16 %asmtmp
 }
 
-; CHECK: v16:
+; CHECK-LABEL: v16:
 ; CHECK: rolw    $8,
 define zeroext i16 @v16(i16 zeroext %x) nounwind {
   %asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind
   ret i16 %asmtmp
 }
 
-; CHECK: s32:
+; CHECK-LABEL: s32:
 ; CHECK: bswapl
 define i32 @s32(i32 %x) nounwind {
   %asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind
   ret i32 %asmtmp
 }
 
-; CHECK: t32:
+; CHECK-LABEL: t32:
 ; CHECK: bswapl
 define i32 @t32(i32 %x) nounwind {
   %asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind
   ret i32 %asmtmp
 }
 
-; CHECK: u32:
+; CHECK-LABEL: u32:
 ; CHECK: bswapl
 define i32 @u32(i32 %x) nounwind {
   %asmtmp = tail call i32 asm "rorw $$8, ${0:w};rorl $$16, $0;rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind
   ret i32 %asmtmp
 }
 
-; CHECK: s64:
+; CHECK-LABEL: s64:
 ; CHECK: bswapq
 define i64 @s64(i64 %x) nounwind {
   %asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
   ret i64 %asmtmp
 }
 
-; CHECK: t64:
+; CHECK-LABEL: t64:
 ; CHECK: bswapq
 define i64 @t64(i64 %x) nounwind {
   %asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{fpsr},~{dirflag},~{flags}"(i64 %x) nounwind
diff --git a/test/CodeGen/X86/bswap.ll b/test/CodeGen/X86/bswap.ll
index d2d6f90..9e46592 100644
--- a/test/CodeGen/X86/bswap.ll
+++ b/test/CodeGen/X86/bswap.ll
@@ -9,21 +9,21 @@ declare i32 @llvm.bswap.i32(i32)
 declare i64 @llvm.bswap.i64(i64)
 
 define i16 @W(i16 %A) {
-; CHECK: W:
+; CHECK-LABEL: W:
 ; CHECK: rolw $8, %ax
         %Z = call i16 @llvm.bswap.i16( i16 %A )         ; <i16> [#uses=1]
         ret i16 %Z
 }
 
 define i32 @X(i32 %A) {
-; CHECK: X:
+; CHECK-LABEL: X:
 ; CHECK: bswapl %eax
         %Z = call i32 @llvm.bswap.i32( i32 %A )         ; <i32> [#uses=1]
         ret i32 %Z
 }
 
 define i64 @Y(i64 %A) {
-; CHECK: Y:
+; CHECK-LABEL: Y:
 ; CHECK: bswapl %eax
 ; CHECK: bswapl %edx
         %Z = call i64 @llvm.bswap.i64( i64 %A )         ; <i64> [#uses=1]
diff --git a/test/CodeGen/X86/byval7.ll b/test/CodeGen/X86/byval7.ll
index 98a26e4..8a96e41 100644
--- a/test/CodeGen/X86/byval7.ll
+++ b/test/CodeGen/X86/byval7.ll
@@ -6,7 +6,7 @@
 
 define i32 @main() nounwind  {
 entry:
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK: movl $1, (%esp)
 ; CHECK: leal 16(%esp), %edi
 ; CHECK: leal 160(%esp), %esi
diff --git a/test/CodeGen/X86/call-push.ll b/test/CodeGen/X86/call-push.ll
index e69f8c1..ccb98fe 100644
--- a/test/CodeGen/X86/call-push.ll
+++ b/test/CodeGen/X86/call-push.ll
@@ -4,7 +4,7 @@
         %struct.range_t = type { float, float, i32, i32, i32, [0 x i8] }
 
 define i32 @decode_byte(%struct.decode_t* %decode) nounwind {
-; CHECK: decode_byte:
+; CHECK-LABEL: decode_byte:
 ; CHECK: pushl
 ; CHECK: popl
 ; CHECK: jmp
diff --git a/test/CodeGen/X86/change-compare-stride-1.ll b/test/CodeGen/X86/change-compare-stride-1.ll
index 1c5c113..b45b404 100644
--- a/test/CodeGen/X86/change-compare-stride-1.ll
+++ b/test/CodeGen/X86/change-compare-stride-1.ll
@@ -8,7 +8,7 @@
 ; XFAIL: *
 
 define void @borf(i8* nocapture %in, i8* nocapture %out) nounwind {
-; CHECK: borf:
+; CHECK-LABEL: borf:
 ; CHECK-NOT: inc
 ; CHECK-NOT: leal 1(
 ; CHECK-NOT: leal -1(
diff --git a/test/CodeGen/X86/change-compare-stride-trickiness-0.ll b/test/CodeGen/X86/change-compare-stride-trickiness-0.ll
index 1f7f6ec..be9e709 100644
--- a/test/CodeGen/X86/change-compare-stride-trickiness-0.ll
+++ b/test/CodeGen/X86/change-compare-stride-trickiness-0.ll
@@ -5,7 +5,7 @@ target triple = "x86_64-apple-darwin9"
 ; The comparison happens before the relevant use, but it can still be rewritten
 ; to compare with zero.
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: align
 ; CHECK: incl  %eax
 ; CHECK-NEXT: decl  %ecx
diff --git a/test/CodeGen/X86/change-compare-stride-trickiness-1.ll b/test/CodeGen/X86/change-compare-stride-trickiness-1.ll
index a3933e2..63733ab 100644
--- a/test/CodeGen/X86/change-compare-stride-trickiness-1.ll
+++ b/test/CodeGen/X86/change-compare-stride-trickiness-1.ll
@@ -7,7 +7,7 @@
 ; could be made simpler.
 
 define void @foo() nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NOT: ret
 ; CHECK: cmpl $10
 ; CHECK: ret
diff --git a/test/CodeGen/X86/clz.ll b/test/CodeGen/X86/clz.ll
index 763079f..6a6f525 100644
--- a/test/CodeGen/X86/clz.ll
+++ b/test/CodeGen/X86/clz.ll
@@ -12,7 +12,7 @@ declare i64 @llvm.ctlz.i64(i64, i1)
 define i8 @cttz_i8(i8 %x)  {
   %tmp = call i8 @llvm.cttz.i8( i8 %x, i1 true )
   ret i8 %tmp
-; CHECK: cttz_i8:
+; CHECK-LABEL: cttz_i8:
 ; CHECK: bsfl
 ; CHECK-NOT: cmov
 ; CHECK: ret
@@ -21,7 +21,7 @@ define i8 @cttz_i8(i8 %x)  {
 define i16 @cttz_i16(i16 %x)  {
   %tmp = call i16 @llvm.cttz.i16( i16 %x, i1 true )
   ret i16 %tmp
-; CHECK: cttz_i16:
+; CHECK-LABEL: cttz_i16:
 ; CHECK: bsfw
 ; CHECK-NOT: cmov
 ; CHECK: ret
@@ -30,7 +30,7 @@ define i16 @cttz_i16(i16 %x)  {
 define i32 @cttz_i32(i32 %x)  {
   %tmp = call i32 @llvm.cttz.i32( i32 %x, i1 true )
   ret i32 %tmp
-; CHECK: cttz_i32:
+; CHECK-LABEL: cttz_i32:
 ; CHECK: bsfl
 ; CHECK-NOT: cmov
 ; CHECK: ret
@@ -39,7 +39,7 @@ define i32 @cttz_i32(i32 %x)  {
 define i64 @cttz_i64(i64 %x)  {
   %tmp = call i64 @llvm.cttz.i64( i64 %x, i1 true )
   ret i64 %tmp
-; CHECK: cttz_i64:
+; CHECK-LABEL: cttz_i64:
 ; CHECK: bsfq
 ; CHECK-NOT: cmov
 ; CHECK: ret
@@ -49,7 +49,7 @@ define i8 @ctlz_i8(i8 %x) {
 entry:
   %tmp2 = call i8 @llvm.ctlz.i8( i8 %x, i1 true )
   ret i8 %tmp2
-; CHECK: ctlz_i8:
+; CHECK-LABEL: ctlz_i8:
 ; CHECK: bsrl
 ; CHECK-NOT: cmov
 ; CHECK: xorl $7,
@@ -60,7 +60,7 @@ define i16 @ctlz_i16(i16 %x) {
 entry:
   %tmp2 = call i16 @llvm.ctlz.i16( i16 %x, i1 true )
   ret i16 %tmp2
-; CHECK: ctlz_i16:
+; CHECK-LABEL: ctlz_i16:
 ; CHECK: bsrw
 ; CHECK-NOT: cmov
 ; CHECK: xorl $15,
@@ -70,7 +70,7 @@ entry:
 define i32 @ctlz_i32(i32 %x) {
   %tmp = call i32 @llvm.ctlz.i32( i32 %x, i1 true )
   ret i32 %tmp
-; CHECK: ctlz_i32:
+; CHECK-LABEL: ctlz_i32:
 ; CHECK: bsrl
 ; CHECK-NOT: cmov
 ; CHECK: xorl $31,
@@ -80,7 +80,7 @@ define i32 @ctlz_i32(i32 %x) {
 define i64 @ctlz_i64(i64 %x) {
   %tmp = call i64 @llvm.ctlz.i64( i64 %x, i1 true )
   ret i64 %tmp
-; CHECK: ctlz_i64:
+; CHECK-LABEL: ctlz_i64:
 ; CHECK: bsrq
 ; CHECK-NOT: cmov
 ; CHECK: xorq $63,
@@ -90,7 +90,7 @@ define i64 @ctlz_i64(i64 %x) {
 define i32 @ctlz_i32_cmov(i32 %n) {
 entry:
 ; Generate a cmov to handle zero inputs when necessary.
-; CHECK: ctlz_i32_cmov:
+; CHECK-LABEL: ctlz_i32_cmov:
 ; CHECK: bsrl
 ; CHECK: cmov
 ; CHECK: xorl $31,
@@ -104,7 +104,7 @@ entry:
 ; Don't generate the cmovne when the source is known non-zero (and bsr would
 ; not set ZF).
 ; rdar://9490949
-; CHECK: ctlz_i32_fold_cmov:
+; CHECK-LABEL: ctlz_i32_fold_cmov:
 ; CHECK: bsrl
 ; CHECK-NOT: cmov
 ; CHECK: xorl $31,
@@ -118,7 +118,7 @@ define i32 @ctlz_bsr(i32 %n) {
 entry:
 ; Don't generate any xors when a 'ctlz' intrinsic is actually used to compute
 ; the most significant bit, which is what 'bsr' does natively.
-; CHECK: ctlz_bsr:
+; CHECK-LABEL: ctlz_bsr:
 ; CHECK: bsrl
 ; CHECK-NOT: xorl
 ; CHECK: ret
@@ -131,7 +131,7 @@ define i32 @ctlz_bsr_cmov(i32 %n) {
 entry:
 ; Same as ctlz_bsr, but ensure this happens even when there is a potential
 ; zero.
-; CHECK: ctlz_bsr_cmov:
+; CHECK-LABEL: ctlz_bsr_cmov:
 ; CHECK: bsrl
 ; CHECK-NOT: xorl
 ; CHECK: ret
diff --git a/test/CodeGen/X86/codegen-prepare.ll b/test/CodeGen/X86/codegen-prepare.ll
index e8ee070..316accf 100644
--- a/test/CodeGen/X86/codegen-prepare.ll
+++ b/test/CodeGen/X86/codegen-prepare.ll
@@ -38,7 +38,7 @@ if.end:                                           ; preds = %if.then, %if.else,
   ret void
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: movss 12([[THIS:%[a-zA-Z0-9]+]]), [[REGISTER:%[a-zA-Z0-9]+]]
 ; CHECK-NEXT: movss [[REGISTER]], 60([[THIS]])
 
diff --git a/test/CodeGen/X86/codemodel.ll b/test/CodeGen/X86/codemodel.ll
index b6ca1ce..3aebc13 100644
--- a/test/CodeGen/X86/codemodel.ll
+++ b/test/CodeGen/X86/codemodel.ll
@@ -7,9 +7,9 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @foo() nounwind readonly {
 entry:
-; CHECK-SMALL:  foo:
+; CHECK-SMALL-LABEL:  foo:
 ; CHECK-SMALL:   movl data(%rip), %eax
-; CHECK-KERNEL: foo:
+; CHECK-KERNEL-LABEL: foo:
 ; CHECK-KERNEL:  movl data, %eax
 	%0 = load i32* getelementptr ([0 x i32]* @data, i64 0, i64 0), align 4		; <i32> [#uses=1]
 	ret i32 %0
@@ -17,9 +17,9 @@ entry:
 
 define i32 @foo2() nounwind readonly {
 entry:
-; CHECK-SMALL:  foo2:
+; CHECK-SMALL-LABEL:  foo2:
 ; CHECK-SMALL:   movl data+40(%rip), %eax
-; CHECK-KERNEL: foo2:
+; CHECK-KERNEL-LABEL: foo2:
 ; CHECK-KERNEL:  movl data+40, %eax
 	%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 10), align 4		; <i32> [#uses=1]
 	ret i32 %0
@@ -27,9 +27,9 @@ entry:
 
 define i32 @foo3() nounwind readonly {
 entry:
-; CHECK-SMALL:  foo3:
+; CHECK-SMALL-LABEL:  foo3:
 ; CHECK-SMALL:   movl data-40(%rip), %eax
-; CHECK-KERNEL: foo3:
+; CHECK-KERNEL-LABEL: foo3:
 ; CHECK-KERNEL:  movq $-40, %rax
 	%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 -10), align 4		; <i32> [#uses=1]
 	ret i32 %0
@@ -38,10 +38,10 @@ entry:
 define i32 @foo4() nounwind readonly {
 entry:
 ; FIXME: We really can use movabsl here!
-; CHECK-SMALL:  foo4:
+; CHECK-SMALL-LABEL:  foo4:
 ; CHECK-SMALL:   movl $16777216, %eax
 ; CHECK-SMALL:   movl data(%rax), %eax
-; CHECK-KERNEL: foo4:
+; CHECK-KERNEL-LABEL: foo4:
 ; CHECK-KERNEL:  movl data+16777216, %eax
 	%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 4194304), align 4		; <i32> [#uses=1]
 	ret i32 %0
@@ -49,18 +49,18 @@ entry:
 
 define i32 @foo1() nounwind readonly {
 entry:
-; CHECK-SMALL:  foo1:
+; CHECK-SMALL-LABEL:  foo1:
 ; CHECK-SMALL:   movl data+16777212(%rip), %eax
-; CHECK-KERNEL: foo1:
+; CHECK-KERNEL-LABEL: foo1:
 ; CHECK-KERNEL:  movl data+16777212, %eax
         %0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 4194303), align 4            ; <i32> [#uses=1]
         ret i32 %0
 }
 define i32 @foo5() nounwind readonly {
 entry:
-; CHECK-SMALL:  foo5:
+; CHECK-SMALL-LABEL:  foo5:
 ; CHECK-SMALL:   movl data-16777216(%rip), %eax
-; CHECK-KERNEL: foo5:
+; CHECK-KERNEL-LABEL: foo5:
 ; CHECK-KERNEL:  movq $-16777216, %rax
 	%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 -4194304), align 4		; <i32> [#uses=1]
 	ret i32 %0
diff --git a/test/CodeGen/X86/commute-two-addr.ll b/test/CodeGen/X86/commute-two-addr.ll
index 0ceea29..eb44e08 100644
--- a/test/CodeGen/X86/commute-two-addr.ll
+++ b/test/CodeGen/X86/commute-two-addr.ll
@@ -11,7 +11,7 @@
 declare void @ext(i32)
 
 define i32 @t1(i32 %X, i32 %Y) nounwind {
-; LINUX: t1:
+; LINUX-LABEL: t1:
 ; LINUX: movl 4(%esp), %eax
 ; LINUX: movl 8(%esp), %ecx
 ; LINUX: addl %eax, %ecx
@@ -22,7 +22,7 @@ define i32 @t1(i32 %X, i32 %Y) nounwind {
 }
 
 define i32 @t2(i32 %X, i32 %Y) nounwind {
-; LINUX: t2:
+; LINUX-LABEL: t2:
 ; LINUX: movl 4(%esp), %eax
 ; LINUX: movl 8(%esp), %ecx
 ; LINUX: xorl %eax, %ecx
@@ -37,7 +37,7 @@ define i32 @t2(i32 %X, i32 %Y) nounwind {
 
 define %0 @t3(i32 %lb, i8 zeroext %has_lb, i8 zeroext %lb_inclusive, i32 %ub, i8 zeroext %has_ub, i8 zeroext %ub_inclusive) nounwind {
 entry:
-; DARWIN: t3:
+; DARWIN-LABEL: t3:
 ; DARWIN: shll $16
 ; DARWIN: shlq $32, %rcx
 ; DARWIN-NOT: leaq
diff --git a/test/CodeGen/X86/compare-inf.ll b/test/CodeGen/X86/compare-inf.ll
index 9aa44a3..d592fc1 100644
--- a/test/CodeGen/X86/compare-inf.ll
+++ b/test/CodeGen/X86/compare-inf.ll
@@ -3,7 +3,7 @@
 ; Convert oeq and une to ole/oge/ule/uge when comparing with infinity
 ; and negative infinity, because those are more efficient on x86.
 
-; CHECK: oeq_inff:
+; CHECK-LABEL: oeq_inff:
 ; CHECK: ucomiss
 ; CHECK: jb
 define float @oeq_inff(float %x, float %y) nounwind readonly {
@@ -12,7 +12,7 @@ define float @oeq_inff(float %x, float %y) nounwind readonly {
   ret float %t1
 }
 
-; CHECK: oeq_inf:
+; CHECK-LABEL: oeq_inf:
 ; CHECK: ucomisd
 ; CHECK: jb
 define double @oeq_inf(double %x, double %y) nounwind readonly {
@@ -21,7 +21,7 @@ define double @oeq_inf(double %x, double %y) nounwind readonly {
   ret double %t1
 }
 
-; CHECK: une_inff:
+; CHECK-LABEL: une_inff:
 ; CHECK: ucomiss
 ; CHECK: jae
 define float @une_inff(float %x, float %y) nounwind readonly {
@@ -30,7 +30,7 @@ define float @une_inff(float %x, float %y) nounwind readonly {
   ret float %t1
 }
 
-; CHECK: une_inf:
+; CHECK-LABEL: une_inf:
 ; CHECK: ucomisd
 ; CHECK: jae
 define double @une_inf(double %x, double %y) nounwind readonly {
@@ -39,7 +39,7 @@ define double @une_inf(double %x, double %y) nounwind readonly {
   ret double %t1
 }
 
-; CHECK: oeq_neg_inff:
+; CHECK-LABEL: oeq_neg_inff:
 ; CHECK: ucomiss
 ; CHECK: jb
 define float @oeq_neg_inff(float %x, float %y) nounwind readonly {
@@ -48,7 +48,7 @@ define float @oeq_neg_inff(float %x, float %y) nounwind readonly {
   ret float %t1
 }
 
-; CHECK: oeq_neg_inf:
+; CHECK-LABEL: oeq_neg_inf:
 ; CHECK: ucomisd
 ; CHECK: jb
 define double @oeq_neg_inf(double %x, double %y) nounwind readonly {
@@ -57,7 +57,7 @@ define double @oeq_neg_inf(double %x, double %y) nounwind readonly {
   ret double %t1
 }
 
-; CHECK: une_neg_inff:
+; CHECK-LABEL: une_neg_inff:
 ; CHECK: ucomiss
 ; CHECK: jae
 define float @une_neg_inff(float %x, float %y) nounwind readonly {
@@ -66,7 +66,7 @@ define float @une_neg_inff(float %x, float %y) nounwind readonly {
   ret float %t1
 }
 
-; CHECK: une_neg_inf:
+; CHECK-LABEL: une_neg_inf:
 ; CHECK: ucomisd
 ; CHECK: jae
 define double @une_neg_inf(double %x, double %y) nounwind readonly {
diff --git a/test/CodeGen/X86/extractelement-load.ll b/test/CodeGen/X86/extractelement-load.ll
index 06d739c..cadc0fb 100644
--- a/test/CodeGen/X86/extractelement-load.ll
+++ b/test/CodeGen/X86/extractelement-load.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | FileCheck %s
 
 define i32 @t(<2 x i64>* %val) nounwind  {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK-NOT: movd
 ; CHECK: movl 8(
 ; CHECK-NEXT: ret
@@ -15,7 +15,7 @@ define i32 @t(<2 x i64>* %val) nounwind  {
 ; Case where extractelement of load ends up as undef.
 ; (Making sure this doesn't crash.)
 define i32 @t2(<8 x i32>* %xp) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: ret
   %x = load <8 x i32>* %xp
   %Shuff68 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32
diff --git a/test/CodeGen/X86/fast-isel-fneg.ll b/test/CodeGen/X86/fast-isel-fneg.ll
index 67fdad2..8b38587 100644
--- a/test/CodeGen/X86/fast-isel-fneg.ll
+++ b/test/CodeGen/X86/fast-isel-fneg.ll
@@ -5,14 +5,14 @@
 ; SSE2: xor
 ; SSE2-NOT: xor
 
-; CHECK: doo:
+; CHECK-LABEL: doo:
 ; CHECK: xor
 define double @doo(double %x) nounwind {
   %y = fsub double -0.0, %x
   ret double %y
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: xor
 define float @foo(float %x) nounwind {
   %y = fsub float -0.0, %x
diff --git a/test/CodeGen/X86/fast-isel-mem.ll b/test/CodeGen/X86/fast-isel-mem.ll
index 52b1e85..7fcef03 100644
--- a/test/CodeGen/X86/fast-isel-mem.ll
+++ b/test/CodeGen/X86/fast-isel-mem.ll
@@ -12,7 +12,7 @@ entry:
         store i32 %2, i32* @src
 	ret i32 %2
 ; This should fold one of the loads into the add.
-; CHECK: loadgv:
+; CHECK-LABEL: loadgv:
 ; CHECK: 	movl	L_src$non_lazy_ptr, %ecx
 ; CHECK: 	movl	(%ecx), %eax
 ; CHECK: 	addl	(%ecx), %eax
diff --git a/test/CodeGen/X86/fast-isel-ret-ext.ll b/test/CodeGen/X86/fast-isel-ret-ext.ll
index 395ad1e..0370d99 100644
--- a/test/CodeGen/X86/fast-isel-ret-ext.ll
+++ b/test/CodeGen/X86/fast-isel-ret-ext.ll
@@ -4,35 +4,35 @@
 define zeroext i8 @test1(i32 %y) nounwind {
   %conv = trunc i32 %y to i8
   ret i8 %conv
-  ; CHECK: test1:
+  ; CHECK-LABEL: test1:
   ; CHECK: movzbl {{.*}}, %eax
 }
 
 define signext i8 @test2(i32 %y) nounwind {
   %conv = trunc i32 %y to i8
   ret i8 %conv
-  ; CHECK: test2:
+  ; CHECK-LABEL: test2:
   ; CHECK: movsbl {{.*}}, %eax
 }
 
 define zeroext i16 @test3(i32 %y) nounwind {
   %conv = trunc i32 %y to i16
   ret i16 %conv
-  ; CHECK: test3:
+  ; CHECK-LABEL: test3:
   ; CHECK: movzwl {{.*}}, %eax
 }
 
 define signext i16 @test4(i32 %y) nounwind {
   %conv = trunc i32 %y to i16
   ret i16 %conv
-  ; CHECK: test4:
+  ; CHECK-LABEL: test4:
   ; CHECK: {{(movswl.%.x, %eax|cwtl)}}
 }
 
 define zeroext i1 @test5(i32 %y) nounwind {
   %conv = trunc i32 %y to i1
   ret i1 %conv
-  ; CHECK: test5:
+  ; CHECK-LABEL: test5:
   ; CHECK: andb $1
   ; CHECK: movzbl {{.*}}, %eax
 }
diff --git a/test/CodeGen/X86/fast-isel-tls.ll b/test/CodeGen/X86/fast-isel-tls.ll
index 0963c52..f71abd2 100644
--- a/test/CodeGen/X86/fast-isel-tls.ll
+++ b/test/CodeGen/X86/fast-isel-tls.ll
@@ -9,7 +9,7 @@ entry:
           ret i32 %s
 }
 
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: leal	v@TLSGD
 ; CHECK: __tls_get_addr
 
@@ -21,6 +21,6 @@ entry:
           ret i32 %s
 }
 
-; CHECK: f_alias:
+; CHECK-LABEL: f_alias:
 ; CHECK: leal	v@TLSGD
 ; CHECK: __tls_get_addr
diff --git a/test/CodeGen/X86/fold-add.ll b/test/CodeGen/X86/fold-add.ll
index 63e7d36..0b27387 100644
--- a/test/CodeGen/X86/fold-add.ll
+++ b/test/CodeGen/X86/fold-add.ll
@@ -7,7 +7,7 @@ target triple = "x86_64-apple-darwin9.6"
 @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32)* @longest_match to i8*)]		; <[1 x i8*]*> [#uses=0]
 
 define fastcc i32 @longest_match(i32 %cur_match) nounwind {
-; CHECK: longest_match:
+; CHECK-LABEL: longest_match:
 ; CHECK-NOT: ret
 ; CHECK: cmpb $0, (%r{{.*}},%r{{.*}})
 ; CHECK: ret
diff --git a/test/CodeGen/X86/fold-and-shift.ll b/test/CodeGen/X86/fold-and-shift.ll
index 93baa0e..a5eb8b5 100644
--- a/test/CodeGen/X86/fold-and-shift.ll
+++ b/test/CodeGen/X86/fold-and-shift.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86 | FileCheck %s
 
 define i32 @t1(i8* %X, i32 %i) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK-NOT: and
 ; CHECK: movzbl
 ; CHECK: movl (%{{...}},%{{...}},4),
@@ -17,7 +17,7 @@ entry:
 }
 
 define i32 @t2(i16* %X, i32 %i) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK-NOT: and
 ; CHECK: movzwl
 ; CHECK: movl (%{{...}},%{{...}},4),
@@ -39,7 +39,7 @@ define i32 @t3(i16* %i.ptr, i32* %arr) {
 ; To make matters worse, because of the two-phase zext of %i and their reuse in
 ; the function, the DAG can get confusing trying to re-use both of them and
 ; prevent easy analysis of the mask in order to match this.
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK-NOT: and
 ; CHECK: shrl
 ; CHECK: addl (%{{...}},%{{...}},4),
@@ -58,7 +58,7 @@ entry:
 define i32 @t4(i16* %i.ptr, i32* %arr) {
 ; A version of @t3 that has more zero extends and more re-use of intermediate
 ; values. This exercise slightly different bits of canonicalization.
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK-NOT: and
 ; CHECK: shrl
 ; CHECK: addl (%{{...}},%{{...}},4),
diff --git a/test/CodeGen/X86/fold-pcmpeqd-1.ll b/test/CodeGen/X86/fold-pcmpeqd-1.ll
index d850630..663e2af 100644
--- a/test/CodeGen/X86/fold-pcmpeqd-1.ll
+++ b/test/CodeGen/X86/fold-pcmpeqd-1.ll
@@ -2,14 +2,14 @@
 
 define <2 x double> @foo() nounwind {
   ret <2 x double> bitcast (<2 x i64><i64 -1, i64 -1> to <2 x double>)
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: pcmpeqd %xmm0, %xmm0
 ; CHECK-NOT: %xmm
 ; CHECK: ret
 }
 define <2 x double> @bar() nounwind {
   ret <2 x double> bitcast (<2 x i64><i64 0, i64 0> to <2 x double>)
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: xorps %xmm0, %xmm0
 ; CHECK-NOT: %xmm
 ; CHECK: ret
diff --git a/test/CodeGen/X86/fold-pcmpeqd-2.ll b/test/CodeGen/X86/fold-pcmpeqd-2.ll
index 2bde76e..0a3afb7 100644
--- a/test/CodeGen/X86/fold-pcmpeqd-2.ll
+++ b/test/CodeGen/X86/fold-pcmpeqd-2.ll
@@ -11,7 +11,7 @@
 ; CHECK: .space 16,255
 
 ; No pcmpeqd instructions, everybody uses the constant pool.
-; CHECK: program_1:
+; CHECK-LABEL: program_1:
 ; CHECK-NOT: pcmpeqd
 
 	%struct.__ImageExecInfo = type <{ <4 x i32>, <4 x float>, <2 x i64>, i8*, i8*, i8*, i32, i32, i32, i32, i32 }>
diff --git a/test/CodeGen/X86/force-align-stack-alloca.ll b/test/CodeGen/X86/force-align-stack-alloca.ll
index 2ada194..95defc8 100644
--- a/test/CodeGen/X86/force-align-stack-alloca.ll
+++ b/test/CodeGen/X86/force-align-stack-alloca.ll
@@ -16,7 +16,7 @@ entry:
 }
 
 define i64 @g(i32 %i) nounwind {
-; CHECK: g:
+; CHECK-LABEL: g:
 ; CHECK:      pushl  %ebp
 ; CHECK-NEXT: movl   %esp, %ebp
 ; CHECK-NEXT: pushl
diff --git a/test/CodeGen/X86/fp-elim-and-no-fp-elim.ll b/test/CodeGen/X86/fp-elim-and-no-fp-elim.ll
index 3468a45..c3b2dfb 100644
--- a/test/CodeGen/X86/fp-elim-and-no-fp-elim.ll
+++ b/test/CodeGen/X86/fp-elim-and-no-fp-elim.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple x86_64-apple-darwin | FileCheck %s
 
 define void @bar(i32 %argc) #0 {
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: pushq %rbp
 entry:
   %conv = sitofp i32 %argc to double
@@ -14,7 +14,7 @@ entry:
 }
 
 define void @qux(i32 %argc) #1 {
-; CHECK: qux:
+; CHECK-LABEL: qux:
 ; CHECK-NOT: pushq %rbp
 entry:
   %conv = sitofp i32 %argc to double
diff --git a/test/CodeGen/X86/fp-elim.ll b/test/CodeGen/X86/fp-elim.ll
index 60892a2..d43ee36 100644
--- a/test/CodeGen/X86/fp-elim.ll
+++ b/test/CodeGen/X86/fp-elim.ll
@@ -7,16 +7,16 @@
 
 define i32 @t1() nounwind readnone {
 entry:
-; FP-ELIM:      t1:
+; FP-ELIM-LABEL:      t1:
 ; FP-ELIM-NEXT: movl
 ; FP-ELIM-NEXT: ret
 
-; NO-ELIM:      t1:
+; NO-ELIM-LABEL:      t1:
 ; NO-ELIM-NEXT: pushl %ebp
 ; NO-ELIM:      popl %ebp
 ; NO-ELIM-NEXT: ret
 
-; NON-LEAF:      t1:
+; NON-LEAF-LABEL:      t1:
 ; NON-LEAF-NEXT: movl
 ; NON-LEAF-NEXT: ret
   ret i32 10
@@ -24,16 +24,16 @@ entry:
 
 define void @t2() nounwind {
 entry:
-; FP-ELIM:     t2:
+; FP-ELIM-LABEL:     t2:
 ; FP-ELIM-NOT: pushl %ebp
 ; FP-ELIM:     ret
 
-; NO-ELIM:      t2:
+; NO-ELIM-LABEL:      t2:
 ; NO-ELIM-NEXT: pushl %ebp
 ; NO-ELIM:      popl %ebp
 ; NO-ELIM-NEXT: ret
 
-; NON-LEAF:      t2:
+; NON-LEAF-LABEL:      t2:
 ; NON-LEAF-NEXT: pushl %ebp
 ; NON-LEAF:      popl %ebp
 ; NON-LEAF-NEXT: ret
diff --git a/test/CodeGen/X86/fp_constant_op.ll b/test/CodeGen/X86/fp_constant_op.ll
index b3ec538..3cd32e6 100644
--- a/test/CodeGen/X86/fp_constant_op.ll
+++ b/test/CodeGen/X86/fp_constant_op.ll
@@ -6,41 +6,41 @@ define double @foo_add(double %P) {
 	%tmp.1 = fadd double %P, 1.230000e+02		; <double> [#uses=1]
 	ret double %tmp.1
 }
-; CHECK: foo_add:
+; CHECK-LABEL: foo_add:
 ; CHECK: fadd DWORD PTR
 
 define double @foo_mul(double %P) {
 	%tmp.1 = fmul double %P, 1.230000e+02		; <double> [#uses=1]
 	ret double %tmp.1
 }
-; CHECK: foo_mul:
+; CHECK-LABEL: foo_mul:
 ; CHECK: fmul DWORD PTR
 
 define double @foo_sub(double %P) {
 	%tmp.1 = fsub double %P, 1.230000e+02		; <double> [#uses=1]
 	ret double %tmp.1
 }
-; CHECK: foo_sub:
+; CHECK-LABEL: foo_sub:
 ; CHECK: fadd DWORD PTR
 
 define double @foo_subr(double %P) {
 	%tmp.1 = fsub double 1.230000e+02, %P		; <double> [#uses=1]
 	ret double %tmp.1
 }
-; CHECK: foo_subr:
+; CHECK-LABEL: foo_subr:
 ; CHECK: fsub QWORD PTR
 
 define double @foo_div(double %P) {
 	%tmp.1 = fdiv double %P, 1.230000e+02		; <double> [#uses=1]
 	ret double %tmp.1
 }
-; CHECK: foo_div:
+; CHECK-LABEL: foo_div:
 ; CHECK: fdiv DWORD PTR
 
 define double @foo_divr(double %P) {
 	%tmp.1 = fdiv double 1.230000e+02, %P		; <double> [#uses=1]
 	ret double %tmp.1
 }
-; CHECK: foo_divr:
+; CHECK-LABEL: foo_divr:
 ; CHECK: fdiv QWORD PTR
 
diff --git a/test/CodeGen/X86/h-registers-0.ll b/test/CodeGen/X86/h-registers-0.ll
index cdc75af..71b3b43 100644
--- a/test/CodeGen/X86/h-registers-0.ll
+++ b/test/CodeGen/X86/h-registers-0.ll
@@ -6,17 +6,17 @@
 ; of h registers yet, due to x86 encoding complications.
 
 define void @bar64(i64 inreg %x, i8* inreg %p) nounwind {
-; X86-64: bar64:
+; X86-64-LABEL: bar64:
 ; X86-64: shrq $8, %rdi
 ; X86-64: incb %dil
 
 ; See FIXME: on regclass GR8.
 ; It could be optimally transformed like; incb %ch; movb %ch, (%rdx)
-; WIN64:  bar64:
+; WIN64-LABEL:  bar64:
 ; WIN64:  shrq $8, %rcx
 ; WIN64:  incb %cl
 
-; X86-32: bar64:
+; X86-32-LABEL: bar64:
 ; X86-32: incb %ah
   %t0 = lshr i64 %x, 8
   %t1 = trunc i64 %t0 to i8
@@ -26,15 +26,15 @@ define void @bar64(i64 inreg %x, i8* inreg %p) nounwind {
 }
 
 define void @bar32(i32 inreg %x, i8* inreg %p) nounwind {
-; X86-64: bar32:
+; X86-64-LABEL: bar32:
 ; X86-64: shrl $8, %edi
 ; X86-64: incb %dil
 
-; WIN64:  bar32:
+; WIN64-LABEL:  bar32:
 ; WIN64:  shrl $8, %ecx
 ; WIN64:  incb %cl
 
-; X86-32: bar32:
+; X86-32-LABEL: bar32:
 ; X86-32: incb %ah
   %t0 = lshr i32 %x, 8
   %t1 = trunc i32 %t0 to i8
@@ -44,15 +44,15 @@ define void @bar32(i32 inreg %x, i8* inreg %p) nounwind {
 }
 
 define void @bar16(i16 inreg %x, i8* inreg %p) nounwind {
-; X86-64: bar16:
+; X86-64-LABEL: bar16:
 ; X86-64: shrl $8, %edi
 ; X86-64: incb %dil
 
-; WIN64:  bar16:
+; WIN64-LABEL:  bar16:
 ; WIN64:  shrl $8, %ecx
 ; WIN64:  incb %cl
 
-; X86-32: bar16:
+; X86-32-LABEL: bar16:
 ; X86-32: incb %ah
   %t0 = lshr i16 %x, 8
   %t1 = trunc i16 %t0 to i8
@@ -62,14 +62,14 @@ define void @bar16(i16 inreg %x, i8* inreg %p) nounwind {
 }
 
 define i64 @qux64(i64 inreg %x) nounwind {
-; X86-64: qux64:
+; X86-64-LABEL: qux64:
 ; X86-64: movq %rdi, %rax
 ; X86-64: movzbl %ah, %eax
 
-; WIN64:  qux64:
+; WIN64-LABEL:  qux64:
 ; WIN64:  movzbl %ch, %eax
 
-; X86-32: qux64:
+; X86-32-LABEL: qux64:
 ; X86-32: movzbl %ah, %eax
   %t0 = lshr i64 %x, 8
   %t1 = and i64 %t0, 255
@@ -77,14 +77,14 @@ define i64 @qux64(i64 inreg %x) nounwind {
 }
 
 define i32 @qux32(i32 inreg %x) nounwind {
-; X86-64: qux32:
+; X86-64-LABEL: qux32:
 ; X86-64: movl %edi, %eax
 ; X86-64: movzbl %ah, %eax
 
-; WIN64:  qux32:
+; WIN64-LABEL:  qux32:
 ; WIN64:  movzbl %ch, %eax
 
-; X86-32: qux32:
+; X86-32-LABEL: qux32:
 ; X86-32: movzbl %ah, %eax
   %t0 = lshr i32 %x, 8
   %t1 = and i32 %t0, 255
@@ -92,14 +92,14 @@ define i32 @qux32(i32 inreg %x) nounwind {
 }
 
 define i16 @qux16(i16 inreg %x) nounwind {
-; X86-64: qux16:
+; X86-64-LABEL: qux16:
 ; X86-64: movl %edi, %eax
 ; X86-64: movzbl %ah, %eax
 
-; WIN64:  qux16:
+; WIN64-LABEL:  qux16:
 ; WIN64:  movzbl %ch, %eax
 
-; X86-32: qux16:
+; X86-32-LABEL: qux16:
 ; X86-32: movzbl %ah, %eax
   %t0 = lshr i16 %x, 8
   ret i16 %t0
diff --git a/test/CodeGen/X86/h-registers-2.ll b/test/CodeGen/X86/h-registers-2.ll
index 488444c..91acb7d 100644
--- a/test/CodeGen/X86/h-registers-2.ll
+++ b/test/CodeGen/X86/h-registers-2.ll
@@ -4,7 +4,7 @@
 ; non-address use(s).
 
 define i32 @foo(i8* %x, i32 %y) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NOT: ret
 ; CHECK: movzbl %{{[abcd]h}},
 ; CHECK-NOT: ret
diff --git a/test/CodeGen/X86/haddsub.ll b/test/CodeGen/X86/haddsub.ll
index 5f1f4fd..9feb5f6 100644
--- a/test/CodeGen/X86/haddsub.ll
+++ b/test/CodeGen/X86/haddsub.ll
@@ -1,10 +1,10 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+sse3,-avx | FileCheck %s -check-prefix=SSE3
 ; RUN: llc < %s -march=x86-64 -mattr=-sse3,+avx | FileCheck %s -check-prefix=AVX
 
-; SSE3: haddpd1:
+; SSE3-LABEL: haddpd1:
 ; SSE3-NOT: vhaddpd
 ; SSE3: haddpd
-; AVX: haddpd1:
+; AVX-LABEL: haddpd1:
 ; AVX: vhaddpd
 define <2 x double> @haddpd1(<2 x double> %x, <2 x double> %y) {
   %a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
@@ -13,10 +13,10 @@ define <2 x double> @haddpd1(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %r
 }
 
-; SSE3: haddpd2:
+; SSE3-LABEL: haddpd2:
 ; SSE3-NOT: vhaddpd
 ; SSE3: haddpd
-; AVX: haddpd2:
+; AVX-LABEL: haddpd2:
 ; AVX: vhaddpd
 define <2 x double> @haddpd2(<2 x double> %x, <2 x double> %y) {
   %a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 2>
@@ -25,10 +25,10 @@ define <2 x double> @haddpd2(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %r
 }
 
-; SSE3: haddpd3:
+; SSE3-LABEL: haddpd3:
 ; SSE3-NOT: vhaddpd
 ; SSE3: haddpd
-; AVX: haddpd3:
+; AVX-LABEL: haddpd3:
 ; AVX: vhaddpd
 define <2 x double> @haddpd3(<2 x double> %x) {
   %a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
@@ -37,10 +37,10 @@ define <2 x double> @haddpd3(<2 x double> %x) {
   ret <2 x double> %r
 }
 
-; SSE3: haddps1:
+; SSE3-LABEL: haddps1:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
-; AVX: haddps1:
+; AVX-LABEL: haddps1:
 ; AVX: vhaddps
 define <4 x float> @haddps1(<4 x float> %x, <4 x float> %y) {
   %a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -49,10 +49,10 @@ define <4 x float> @haddps1(<4 x float> %x, <4 x float> %y) {
   ret <4 x float> %r
 }
 
-; SSE3: haddps2:
+; SSE3-LABEL: haddps2:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
-; AVX: haddps2:
+; AVX-LABEL: haddps2:
 ; AVX: vhaddps
 define <4 x float> @haddps2(<4 x float> %x, <4 x float> %y) {
   %a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
@@ -61,10 +61,10 @@ define <4 x float> @haddps2(<4 x float> %x, <4 x float> %y) {
   ret <4 x float> %r
 }
 
-; SSE3: haddps3:
+; SSE3-LABEL: haddps3:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
-; AVX: haddps3:
+; AVX-LABEL: haddps3:
 ; AVX: vhaddps
 define <4 x float> @haddps3(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
@@ -73,10 +73,10 @@ define <4 x float> @haddps3(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: haddps4:
+; SSE3-LABEL: haddps4:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
-; AVX: haddps4:
+; AVX-LABEL: haddps4:
 ; AVX: vhaddps
 define <4 x float> @haddps4(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
@@ -85,10 +85,10 @@ define <4 x float> @haddps4(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: haddps5:
+; SSE3-LABEL: haddps5:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
-; AVX: haddps5:
+; AVX-LABEL: haddps5:
 ; AVX: vhaddps
 define <4 x float> @haddps5(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
@@ -97,10 +97,10 @@ define <4 x float> @haddps5(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: haddps6:
+; SSE3-LABEL: haddps6:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
-; AVX: haddps6:
+; AVX-LABEL: haddps6:
 ; AVX: vhaddps
 define <4 x float> @haddps6(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
@@ -109,10 +109,10 @@ define <4 x float> @haddps6(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: haddps7:
+; SSE3-LABEL: haddps7:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
-; AVX: haddps7:
+; AVX-LABEL: haddps7:
 ; AVX: vhaddps
 define <4 x float> @haddps7(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
@@ -121,10 +121,10 @@ define <4 x float> @haddps7(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: hsubpd1:
+; SSE3-LABEL: hsubpd1:
 ; SSE3-NOT: vhsubpd
 ; SSE3: hsubpd
-; AVX: hsubpd1:
+; AVX-LABEL: hsubpd1:
 ; AVX: vhsubpd
 define <2 x double> @hsubpd1(<2 x double> %x, <2 x double> %y) {
   %a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
@@ -133,10 +133,10 @@ define <2 x double> @hsubpd1(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %r
 }
 
-; SSE3: hsubpd2:
+; SSE3-LABEL: hsubpd2:
 ; SSE3-NOT: vhsubpd
 ; SSE3: hsubpd
-; AVX: hsubpd2:
+; AVX-LABEL: hsubpd2:
 ; AVX: vhsubpd
 define <2 x double> @hsubpd2(<2 x double> %x) {
   %a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
@@ -145,10 +145,10 @@ define <2 x double> @hsubpd2(<2 x double> %x) {
   ret <2 x double> %r
 }
 
-; SSE3: hsubps1:
+; SSE3-LABEL: hsubps1:
 ; SSE3-NOT: vhsubps
 ; SSE3: hsubps
-; AVX: hsubps1:
+; AVX-LABEL: hsubps1:
 ; AVX: vhsubps
 define <4 x float> @hsubps1(<4 x float> %x, <4 x float> %y) {
   %a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -157,10 +157,10 @@ define <4 x float> @hsubps1(<4 x float> %x, <4 x float> %y) {
   ret <4 x float> %r
 }
 
-; SSE3: hsubps2:
+; SSE3-LABEL: hsubps2:
 ; SSE3-NOT: vhsubps
 ; SSE3: hsubps
-; AVX: hsubps2:
+; AVX-LABEL: hsubps2:
 ; AVX: vhsubps
 define <4 x float> @hsubps2(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
@@ -169,10 +169,10 @@ define <4 x float> @hsubps2(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: hsubps3:
+; SSE3-LABEL: hsubps3:
 ; SSE3-NOT: vhsubps
 ; SSE3: hsubps
-; AVX: hsubps3:
+; AVX-LABEL: hsubps3:
 ; AVX: vhsubps
 define <4 x float> @hsubps3(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
@@ -181,10 +181,10 @@ define <4 x float> @hsubps3(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: hsubps4:
+; SSE3-LABEL: hsubps4:
 ; SSE3-NOT: vhsubps
 ; SSE3: hsubps
-; AVX: hsubps4:
+; AVX-LABEL: hsubps4:
 ; AVX: vhsubps
 define <4 x float> @hsubps4(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
@@ -193,11 +193,11 @@ define <4 x float> @hsubps4(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: vhaddps1:
+; SSE3-LABEL: vhaddps1:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
 ; SSE3: haddps
-; AVX: vhaddps1:
+; AVX-LABEL: vhaddps1:
 ; AVX: vhaddps
 define <8 x float> @vhaddps1(<8 x float> %x, <8 x float> %y) {
   %a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
@@ -206,11 +206,11 @@ define <8 x float> @vhaddps1(<8 x float> %x, <8 x float> %y) {
   ret <8 x float> %r
 }
 
-; SSE3: vhaddps2:
+; SSE3-LABEL: vhaddps2:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
 ; SSE3: haddps
-; AVX: vhaddps2:
+; AVX-LABEL: vhaddps2:
 ; AVX: vhaddps
 define <8 x float> @vhaddps2(<8 x float> %x, <8 x float> %y) {
   %a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 2, i32 9, i32 10, i32 5, i32 6, i32 13, i32 14>
@@ -219,11 +219,11 @@ define <8 x float> @vhaddps2(<8 x float> %x, <8 x float> %y) {
   ret <8 x float> %r
 }
 
-; SSE3: vhaddps3:
+; SSE3-LABEL: vhaddps3:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
 ; SSE3: haddps
-; AVX: vhaddps3:
+; AVX-LABEL: vhaddps3:
 ; AVX: vhaddps
 define <8 x float> @vhaddps3(<8 x float> %x) {
   %a = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
@@ -232,11 +232,11 @@ define <8 x float> @vhaddps3(<8 x float> %x) {
   ret <8 x float> %r
 }
 
-; SSE3: vhsubps1:
+; SSE3-LABEL: vhsubps1:
 ; SSE3-NOT: vhsubps
 ; SSE3: hsubps
 ; SSE3: hsubps
-; AVX: vhsubps1:
+; AVX-LABEL: vhsubps1:
 ; AVX: vhsubps
 define <8 x float> @vhsubps1(<8 x float> %x, <8 x float> %y) {
   %a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
@@ -245,11 +245,11 @@ define <8 x float> @vhsubps1(<8 x float> %x, <8 x float> %y) {
   ret <8 x float> %r
 }
 
-; SSE3: vhsubps3:
+; SSE3-LABEL: vhsubps3:
 ; SSE3-NOT: vhsubps
 ; SSE3: hsubps
 ; SSE3: hsubps
-; AVX: vhsubps3:
+; AVX-LABEL: vhsubps3:
 ; AVX: vhsubps
 define <8 x float> @vhsubps3(<8 x float> %x) {
   %a = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
@@ -258,11 +258,11 @@ define <8 x float> @vhsubps3(<8 x float> %x) {
   ret <8 x float> %r
 }
 
-; SSE3: vhaddpd1:
+; SSE3-LABEL: vhaddpd1:
 ; SSE3-NOT: vhaddpd
 ; SSE3: haddpd
 ; SSE3: haddpd
-; AVX: vhaddpd1:
+; AVX-LABEL: vhaddpd1:
 ; AVX: vhaddpd
 define <4 x double> @vhaddpd1(<4 x double> %x, <4 x double> %y) {
   %a = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
@@ -271,11 +271,11 @@ define <4 x double> @vhaddpd1(<4 x double> %x, <4 x double> %y) {
   ret <4 x double> %r
 }
 
-; SSE3: vhsubpd1:
+; SSE3-LABEL: vhsubpd1:
 ; SSE3-NOT: vhsubpd
 ; SSE3: hsubpd
 ; SSE3: hsubpd
-; AVX: vhsubpd1:
+; AVX-LABEL: vhsubpd1:
 ; AVX: vhsubpd
 define <4 x double> @vhsubpd1(<4 x double> %x, <4 x double> %y) {
   %a = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
diff --git a/test/CodeGen/X86/hidden-vis-4.ll b/test/CodeGen/X86/hidden-vis-4.ll
index a8aede5..25a87b9 100644
--- a/test/CodeGen/X86/hidden-vis-4.ll
+++ b/test/CodeGen/X86/hidden-vis-4.ll
@@ -4,7 +4,7 @@
 
 define i32 @t() nounwind readonly {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movl _x, %eax
 ; CHECK: .comm _x,4
 	%0 = load i32* @x, align 4		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/hidden-vis.ll b/test/CodeGen/X86/hidden-vis.ll
index fcb74fc..a072cb0 100644
--- a/test/CodeGen/X86/hidden-vis.ll
+++ b/test/CodeGen/X86/hidden-vis.ll
@@ -9,12 +9,12 @@
 
 define weak hidden void @t1() nounwind {
 ; LINUX: .hidden t1
-; LINUX: t1:
+; LINUX-LABEL: t1:
 
 ; DARWIN: .private_extern _t1
-; DARWIN: t1:
+; DARWIN-LABEL: t1:
 
-; WINDOWS: t1:
+; WINDOWS-LABEL: t1:
 ; WINDOWS-NOT: hidden
   ret void
 }
diff --git a/test/CodeGen/X86/hipe-prologue.ll b/test/CodeGen/X86/hipe-prologue.ll
index ff3c5c8..2f16423 100644
--- a/test/CodeGen/X86/hipe-prologue.ll
+++ b/test/CodeGen/X86/hipe-prologue.ll
@@ -9,10 +9,10 @@
 declare void @dummy_use(i32*, i32)
 
 define {i32, i32} @test_basic(i32 %hp, i32 %p) {
-  ; X32-Linux:       test_basic:
+  ; X32-Linux-LABEL:       test_basic:
   ; X32-Linux-NOT:   calll inc_stack_0
 
-  ; X64-Linux:       test_basic:
+  ; X64-Linux-LABEL:       test_basic:
   ; X64-Linux-NOT:   callq inc_stack_0
 
   %mem = alloca i32, i32 10
@@ -23,7 +23,7 @@ define {i32, i32} @test_basic(i32 %hp, i32 %p) {
 }
 
 define cc 11 {i32, i32} @test_basic_hipecc(i32 %hp, i32 %p) {
-  ; X32-Linux:       test_basic_hipecc:
+  ; X32-Linux-LABEL:       test_basic_hipecc:
   ; X32-Linux:       leal -156(%esp), %ebx
   ; X32-Linux-NEXT:  cmpl 76(%ebp), %ebx
   ; X32-Linux-NEXT:  jb .LBB1_1
@@ -33,7 +33,7 @@ define cc 11 {i32, i32} @test_basic_hipecc(i32 %hp, i32 %p) {
   ; X32-Linux:       .LBB1_1:
   ; X32-Linux-NEXT:  calll inc_stack_0
 
-  ; X64-Linux:       test_basic_hipecc:
+  ; X64-Linux-LABEL:       test_basic_hipecc:
   ; X64-Linux:       leaq -232(%rsp), %r14
   ; X64-Linux-NEXT:  cmpq 144(%rbp), %r14
   ; X64-Linux-NEXT:  jb .LBB1_1
@@ -51,10 +51,10 @@ define cc 11 {i32, i32} @test_basic_hipecc(i32 %hp, i32 %p) {
 }
 
 define cc 11 {i32,i32,i32} @test_nocall_hipecc(i32 %hp,i32 %p,i32 %x,i32 %y) {
-  ; X32-Linux:       test_nocall_hipecc:
+  ; X32-Linux-LABEL:       test_nocall_hipecc:
   ; X32-Linux-NOT:   calll inc_stack_0
 
-  ; X64-Linux:       test_nocall_hipecc:
+  ; X64-Linux-LABEL:       test_nocall_hipecc:
   ; X64-Linux-NOT:   callq inc_stack_0
 
   %1 = add i32 %x, %y
diff --git a/test/CodeGen/X86/hoist-common.ll b/test/CodeGen/X86/hoist-common.ll
index cdfdea3..6b26876 100644
--- a/test/CodeGen/X86/hoist-common.ll
+++ b/test/CodeGen/X86/hoist-common.ll
@@ -7,7 +7,7 @@
 
 define zeroext i1 @t(i32 %c) nounwind ssp {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: xorl %eax, %eax
 ; CHECK: test
 ; CHECK: je
diff --git a/test/CodeGen/X86/i128-sdiv.ll b/test/CodeGen/X86/i128-sdiv.ll
index ab5cdda..89cd495 100644
--- a/test/CodeGen/X86/i128-sdiv.ll
+++ b/test/CodeGen/X86/i128-sdiv.ll
@@ -3,21 +3,21 @@
 ; trigger correctly.
 
 define i128 @test1(i128 %x) {
-  ; CHECK: test1:
+  ; CHECK-LABEL: test1:
   ; CHECK-NOT: call
   %tmp = sdiv i128 %x, 73786976294838206464
   ret i128 %tmp
 }
 
 define i128 @test2(i128 %x) {
-  ; CHECK: test2:
+  ; CHECK-LABEL: test2:
   ; CHECK-NOT: call
   %tmp = sdiv i128 %x, -73786976294838206464
   ret i128 %tmp
 }
 
 define i128 @test3(i128 %x) {
-  ; CHECK: test3:
+  ; CHECK-LABEL: test3:
   ; CHECK: call
   %tmp = sdiv i128 %x, -73786976294838206467
   ret i128 %tmp
diff --git a/test/CodeGen/X86/inline-asm-R-constraint.ll b/test/CodeGen/X86/inline-asm-R-constraint.ll
index 66c27ac..d17e04d 100644
--- a/test/CodeGen/X86/inline-asm-R-constraint.ll
+++ b/test/CodeGen/X86/inline-asm-R-constraint.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-apple-darwin10.0"
 
 define void @udiv8(i8* %quotient, i16 zeroext %a, i8 zeroext %b, i8 zeroext %c, i8* %remainder) nounwind ssp {
 entry:
-; CHECK: udiv8:
+; CHECK-LABEL: udiv8:
 ; CHECK-NOT: movb %ah, (%r8)
   %a_addr = alloca i16, align 2                   ; <i16*> [#uses=2]
   %b_addr = alloca i8, align 1                    ; <i8*> [#uses=2]
diff --git a/test/CodeGen/X86/inreg.ll b/test/CodeGen/X86/inreg.ll
index 6653cfb..e4610e3 100644
--- a/test/CodeGen/X86/inreg.ll
+++ b/test/CodeGen/X86/inreg.ll
@@ -8,7 +8,7 @@ entry:
   %tmp = alloca %struct.s1, align 4
   call void @f(%struct.s1* inreg sret %tmp, i32 inreg 41, i32 inreg 42, i32 43)
   ret void
-  ; DAG: g1:
+  ; DAG-LABEL: g1:
   ; DAG: subl $[[AMT:.*]], %esp
   ; DAG-NEXT: $43, (%esp)
   ; DAG-NEXT: leal    16(%esp), %eax
@@ -18,7 +18,7 @@ entry:
   ; DAG-NEXT: addl $[[AMT]], %esp
   ; DAG-NEXT: ret
 
-  ; FAST: g1:
+  ; FAST-LABEL: g1:
   ; FAST: subl $[[AMT:.*]], %esp
   ; FAST-NEXT: leal    8(%esp), %eax
   ; FAST-NEXT: movl    $41, %edx
diff --git a/test/CodeGen/X86/ins_subreg_coalesce-1.ll b/test/CodeGen/X86/ins_subreg_coalesce-1.ll
index 8367436..bec98a2 100644
--- a/test/CodeGen/X86/ins_subreg_coalesce-1.ll
+++ b/test/CodeGen/X86/ins_subreg_coalesce-1.ll
@@ -2,7 +2,7 @@
 
 define fastcc i32 @t() nounwind  {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movzwl 0, %eax
 ; CHECK: orl $2, %eax
 ; CHECK: movw %ax, 0
diff --git a/test/CodeGen/X86/jump_sign.ll b/test/CodeGen/X86/jump_sign.ll
index 91ac942..3d3a9a9 100644
--- a/test/CodeGen/X86/jump_sign.ll
+++ b/test/CodeGen/X86/jump_sign.ll
@@ -2,7 +2,7 @@
 
 define i32 @f(i32 %X) {
 entry:
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: jns
 	%tmp1 = add i32 %X, 1		; <i32> [#uses=1]
 	%tmp = icmp slt i32 %tmp1, 0		; <i1> [#uses=1]
@@ -25,7 +25,7 @@ declare i32 @baz(...)
 ; rdar://11355268
 define i32 @g(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: g:
+; CHECK-LABEL: g:
 ; CHECK-NOT: test
 ; CHECK: cmovs
   %sub = sub nsw i32 %a, %b
@@ -37,7 +37,7 @@ entry:
 ; rdar://10734411
 define i32 @h(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: h:
+; CHECK-LABEL: h:
 ; CHECK-NOT: cmp
 ; CHECK: cmov
 ; CHECK-NOT: movl
@@ -49,7 +49,7 @@ entry:
 }
 define i32 @i(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: i:
+; CHECK-LABEL: i:
 ; CHECK-NOT: cmp
 ; CHECK: cmov
 ; CHECK-NOT: movl
@@ -61,7 +61,7 @@ entry:
 }
 define i32 @j(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: j:
+; CHECK-LABEL: j:
 ; CHECK-NOT: cmp
 ; CHECK: cmov
 ; CHECK-NOT: movl
@@ -73,7 +73,7 @@ entry:
 }
 define i32 @k(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: k:
+; CHECK-LABEL: k:
 ; CHECK-NOT: cmp
 ; CHECK: cmov
 ; CHECK-NOT: movl
@@ -86,7 +86,7 @@ entry:
 ; redundant cmp instruction
 define i32 @l(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: l:
+; CHECK-LABEL: l:
 ; CHECK-NOT: cmp
   %cmp = icmp slt i32 %b, %a
   %sub = sub nsw i32 %a, %b
@@ -95,7 +95,7 @@ entry:
 }
 define i32 @m(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: m:
+; CHECK-LABEL: m:
 ; CHECK-NOT: cmp
   %cmp = icmp sgt i32 %a, %b
   %sub = sub nsw i32 %a, %b
@@ -106,7 +106,7 @@ entry:
 ; a swapped sub.
 define i32 @l2(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: l2:
+; CHECK-LABEL: l2:
 ; CHECK: cmp
   %cmp = icmp eq i32 %b, %a
   %sub = sub nsw i32 %a, %b
@@ -122,7 +122,7 @@ if.else:
 }
 define i32 @l3(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: l3:
+; CHECK-LABEL: l3:
 ; CHECK: sub
 ; CHECK-NOT: cmp
 ; CHECK: jge
@@ -141,7 +141,7 @@ if.else:
 ; When Movr0 is between sub and cmp, we need to move "Movr0" before sub.
 define i32 @l4(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: l4:
+; CHECK-LABEL: l4:
 ; CHECK: xor
 ; CHECK: sub
 ; CHECK-NOT: cmp
@@ -153,7 +153,7 @@ entry:
 ; rdar://11540023
 define i32 @n(i32 %x, i32 %y) nounwind {
 entry:
-; CHECK: n:
+; CHECK-LABEL: n:
 ; CHECK-NOT: sub
 ; CHECK: cmp
   %sub = sub nsw i32 %x, %y
@@ -177,7 +177,7 @@ sw.bb:                                            ; preds = %if.end.i
   br i1 undef, label %if.then44, label %if.end29
 
 if.end29:                                         ; preds = %sw.bb
-; CHECK: o:
+; CHECK-LABEL: o:
 ; CHECK: cmp
   %1 = urem i16 %0, 10
   %cmp25 = icmp eq i16 %1, 0
@@ -206,7 +206,7 @@ if.else.i104:                                     ; preds = %if.then44
 ; rdar://11855129
 define i32 @p(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: p:
+; CHECK-LABEL: p:
 ; CHECK-NOT: test
 ; CHECK: cmovs
   %add = add nsw i32 %b, %a
@@ -218,7 +218,7 @@ entry:
 ; If we have sub a, b and cmp b, a and the result of cmp is used
 ; by sbb, we should not optimize cmp away.
 define i32 @q(i32 %j.4, i32 %w, i32 %el) {
-; CHECK: q:
+; CHECK-LABEL: q:
 ; CHECK: cmp
 ; CHECK-NEXT: sbb
   %tmp532 = add i32 %j.4, %w
@@ -232,7 +232,7 @@ define i32 @q(i32 %j.4, i32 %w, i32 %el) {
 ; rdar://11873276
 define i8* @r(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
 entry:
-; CHECK: r:
+; CHECK-LABEL: r:
 ; CHECK: sub
 ; CHECK-NOT: cmp
 ; CHECK: j
@@ -256,7 +256,7 @@ return:
 ; Test optimizations of dec/inc.
 define i32 @dec(i32 %a) nounwind {
 entry:
-; CHECK: dec:
+; CHECK-LABEL: dec:
 ; CHECK: decl
 ; CHECK-NOT: test
 ; CHECK: cmovsl
@@ -268,7 +268,7 @@ entry:
 
 define i32 @inc(i32 %a) nounwind {
 entry:
-; CHECK: inc:
+; CHECK-LABEL: inc:
 ; CHECK: incl
 ; CHECK-NOT: test
 ; CHECK: cmovsl
diff --git a/test/CodeGen/X86/lock-inst-encoding.ll b/test/CodeGen/X86/lock-inst-encoding.ll
index 9765fae..5ce771f 100644
--- a/test/CodeGen/X86/lock-inst-encoding.ll
+++ b/test/CodeGen/X86/lock-inst-encoding.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10.0.0"
 
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: addq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x01,0x37]
 ; CHECK: ret
 define void @f1(i64* %a, i64 %b) nounwind {
@@ -11,7 +11,7 @@ define void @f1(i64* %a, i64 %b) nounwind {
   ret void
 }
 
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: subq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x29,0x37]
 ; CHECK: ret
 define void @f2(i64* %a, i64 %b) nounwind {
@@ -19,7 +19,7 @@ define void @f2(i64* %a, i64 %b) nounwind {
   ret void
 }
 
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: andq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x21,0x37]
 ; CHECK: ret
 define void @f3(i64* %a, i64 %b) nounwind {
@@ -27,7 +27,7 @@ define void @f3(i64* %a, i64 %b) nounwind {
   ret void
 }
 
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: orq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x09,0x37]
 ; CHECK: ret
 define void @f4(i64* %a, i64 %b) nounwind {
@@ -35,7 +35,7 @@ define void @f4(i64* %a, i64 %b) nounwind {
   ret void
 }
 
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xorq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x31,0x37]
 ; CHECK: ret
 define void @f5(i64* %a, i64 %b) nounwind {
diff --git a/test/CodeGen/X86/loop-blocks.ll b/test/CodeGen/X86/loop-blocks.ll
index 4bd162b..a81ceb9 100644
--- a/test/CodeGen/X86/loop-blocks.ll
+++ b/test/CodeGen/X86/loop-blocks.ll
@@ -6,7 +6,7 @@
 ; CodeGen should insert a branch into the middle of the loop in
 ; order to avoid a branch within the loop.
 
-; CHECK: simple:
+; CHECK-LABEL: simple:
 ;      CHECK:   jmp   .LBB0_1
 ; CHECK-NEXT:   align
 ; CHECK-NEXT: .LBB0_2:
@@ -36,7 +36,7 @@ done:
 ; CodeGen should move block_a to the top of the loop so that it
 ; falls through into the loop, avoiding a branch within the loop.
 
-; CHECK: slightly_more_involved:
+; CHECK-LABEL: slightly_more_involved:
 ;      CHECK:   jmp .LBB1_1
 ; CHECK-NEXT:   align
 ; CHECK-NEXT: .LBB1_4:
@@ -72,7 +72,7 @@ exit:
 ; fallthrough edges which should be preserved.
 ; "callq block_a_merge_func" is tail duped.
 
-; CHECK: yet_more_involved:
+; CHECK-LABEL: yet_more_involved:
 ;      CHECK:   jmp .LBB2_1
 ; CHECK-NEXT:   align
 ; CHECK-NEXT: .LBB2_5:
@@ -132,7 +132,7 @@ exit:
 ; conveniently fit anywhere so that they are at least contiguous with the
 ; loop.
 
-; CHECK: cfg_islands:
+; CHECK-LABEL: cfg_islands:
 ;      CHECK:   jmp     .LBB3_1
 ; CHECK-NEXT:   align
 ; CHECK-NEXT: .LBB3_7:
diff --git a/test/CodeGen/X86/lsr-loop-exit-cond.ll b/test/CodeGen/X86/lsr-loop-exit-cond.ll
index 8a81f70..68048ab 100644
--- a/test/CodeGen/X86/lsr-loop-exit-cond.ll
+++ b/test/CodeGen/X86/lsr-loop-exit-cond.ll
@@ -1,12 +1,12 @@
 ; RUN: llc -mtriple=x86_64-darwin -mcpu=generic < %s | FileCheck %s
 ; RUN: llc -mtriple=x86_64-darwin -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s
 
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: decq
 ; CHECK-NEXT: movl (%r9,%rax,4), %eax
 ; CHECK-NEXT: jne
 
-; ATOM: t:
+; ATOM-LABEL: t:
 ; ATOM: movl (%r9,%rax,4), %eax
 ; ATOM-NEXT: decq
 ; ATOM-NEXT: jne
@@ -148,14 +148,14 @@ bb2:		; preds = %bb
 ; is equal to the stride.
 ; It must not fold (cmp (add iv, 1), 1) --> (cmp iv, 0).
 
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: %for.body
 ; CHECK: incl [[IV:%e..]]
 ; CHECK: cmpl $1, [[IV]]
 ; CHECK: jne
 ; CHECK: ret
 
-; ATOM: f:
+; ATOM-LABEL: f:
 ; ATOM: %for.body
 ; ATOM: incl [[IV:%e..]]
 ; ATOM: cmpl $1, [[IV]]
diff --git a/test/CodeGen/X86/lsr-reuse.ll b/test/CodeGen/X86/lsr-reuse.ll
index a267450..40c041a 100644
--- a/test/CodeGen/X86/lsr-reuse.ll
+++ b/test/CodeGen/X86/lsr-reuse.ll
@@ -8,7 +8,7 @@ target triple = "x86_64-unknown-unknown"
 ; Instruction selection should use the FLAGS value from the dec for
 ; the branch. Scheduling should push the adds upwards.
 
-; CHECK: full_me_0:
+; CHECK-LABEL: full_me_0:
 ; CHECK: movsd   (%rsi), %xmm0
 ; CHECK: mulsd   (%rdx), %xmm0
 ; CHECK: movsd   %xmm0, (%rdi)
@@ -50,7 +50,7 @@ return:
 ; would be better on x86-64, since the start value would be 0 instead of
 ; 2048.
 
-; CHECK: mostly_full_me_0:
+; CHECK-LABEL: mostly_full_me_0:
 ; CHECK: movsd   -2048(%rsi), %xmm0
 ; CHECK: mulsd   -2048(%rdx), %xmm0
 ; CHECK: movsd   %xmm0, -2048(%rdi)
@@ -96,7 +96,7 @@ return:
 ; A minor variation on mostly_full_me_0.
 ; Prefer to start the indvar at 0.
 
-; CHECK: mostly_full_me_1:
+; CHECK-LABEL: mostly_full_me_1:
 ; CHECK: movsd   (%rsi), %xmm0
 ; CHECK: mulsd   (%rdx), %xmm0
 ; CHECK: movsd   %xmm0, (%rdi)
@@ -141,7 +141,7 @@ return:
 
 ; A slightly less minor variation on mostly_full_me_0.
 
-; CHECK: mostly_full_me_2:
+; CHECK-LABEL: mostly_full_me_2:
 ; CHECK: movsd   (%rsi), %xmm0
 ; CHECK: mulsd   (%rdx), %xmm0
 ; CHECK: movsd   %xmm0, (%rdi)
@@ -190,7 +190,7 @@ return:
 ; cases away, but it's useful here to verify that LSR's register pressure
 ; heuristics are working as expected.
 
-; CHECK: count_me_0:
+; CHECK-LABEL: count_me_0:
 ; CHECK: movsd   (%rsi,%rax,8), %xmm0
 ; CHECK: mulsd   (%rdx,%rax,8), %xmm0
 ; CHECK: movsd   %xmm0, (%rdi,%rax,8)
@@ -225,7 +225,7 @@ return:
 ; would not reduce register pressure.
 ; (though it would reduce register pressure inside the loop...)
 
-; CHECK: count_me_1:
+; CHECK-LABEL: count_me_1:
 ; CHECK: movsd   (%rsi,%rax,8), %xmm0
 ; CHECK: mulsd   (%rdx,%rax,8), %xmm0
 ; CHECK: movsd   %xmm0, (%rdi,%rax,8)
@@ -259,7 +259,7 @@ return:
 ; Full strength reduction doesn't save any registers here because the
 ; loop tripcount is a constant.
 
-; CHECK: count_me_2:
+; CHECK-LABEL: count_me_2:
 ; CHECK: movl    $10, %eax
 ; CHECK: align
 ; CHECK: BB6_1:
@@ -305,7 +305,7 @@ return:
 
 ; This should be fully strength-reduced to reduce register pressure.
 
-; CHECK: full_me_1:
+; CHECK-LABEL: full_me_1:
 ; CHECK: align
 ; CHECK: BB7_1:
 ; CHECK: movsd   (%rdi), %xmm0
@@ -353,7 +353,7 @@ return:
 ; This is a variation on full_me_0 in which the 0,+,1 induction variable
 ; has a non-address use, pinning that value in a register.
 
-; CHECK: count_me_3:
+; CHECK-LABEL: count_me_3:
 ; CHECK: call
 ; CHECK: movsd   (%r{{[^,]*}},%r{{[^,]*}},8), %xmm0
 ; CHECK: mulsd   (%r{{[^,]*}},%r{{[^,]*}},8), %xmm0
@@ -390,7 +390,7 @@ return:
 ; LSR should use only one indvar for the inner loop.
 ; rdar://7657764
 
-; CHECK: asd:
+; CHECK-LABEL: asd:
 ; CHECK: BB9_4:
 ; CHECK-NEXT: addl  (%r{{[^,]*}},%rdi,4), %e
 ; CHECK-NEXT: incq  %rdi
diff --git a/test/CodeGen/X86/lzcnt.ll b/test/CodeGen/X86/lzcnt.ll
index 2faa24a..ff83f85 100644
--- a/test/CodeGen/X86/lzcnt.ll
+++ b/test/CodeGen/X86/lzcnt.ll
@@ -8,55 +8,55 @@ declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
 define i8 @t1(i8 %x) nounwind  {
 	%tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 false )
 	ret i8 %tmp
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: lzcntl
 }
 
 define i16 @t2(i16 %x) nounwind  {
 	%tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 false )
 	ret i16 %tmp
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: lzcntw
 }
 
 define i32 @t3(i32 %x) nounwind  {
 	%tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 false )
 	ret i32 %tmp
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: lzcntl
 }
 
 define i64 @t4(i64 %x) nounwind  {
 	%tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 false )
 	ret i64 %tmp
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: lzcntq
 }
 
 define i8 @t5(i8 %x) nounwind  {
 	%tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 true )
 	ret i8 %tmp
-; CHECK: t5:
+; CHECK-LABEL: t5:
 ; CHECK: lzcntl
 }
 
 define i16 @t6(i16 %x) nounwind  {
 	%tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 true )
 	ret i16 %tmp
-; CHECK: t6:
+; CHECK-LABEL: t6:
 ; CHECK: lzcntw
 }
 
 define i32 @t7(i32 %x) nounwind  {
 	%tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 true )
 	ret i32 %tmp
-; CHECK: t7:
+; CHECK-LABEL: t7:
 ; CHECK: lzcntl
 }
 
 define i64 @t8(i64 %x) nounwind  {
 	%tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 true )
 	ret i64 %tmp
-; CHECK: t8:
+; CHECK-LABEL: t8:
 ; CHECK: lzcntq
 }
diff --git a/test/CodeGen/X86/machine-cp.ll b/test/CodeGen/X86/machine-cp.ll
index 8e97b99..f04e111 100644
--- a/test/CodeGen/X86/machine-cp.ll
+++ b/test/CodeGen/X86/machine-cp.ll
@@ -4,7 +4,7 @@
 ; rdar://10640363
 define i32 @t1(i32 %a, i32 %b) nounwind  {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: je [[LABEL:.*BB.*]]
   %cmp1 = icmp eq i32 %b, 0
   br i1 %cmp1, label %while.end, label %while.body
@@ -29,7 +29,7 @@ while.end:                                        ; preds = %while.body, %entry
 ; rdar://10428165
 define <8 x i16> @t2(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK-NOT: movdqa
   %tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef >
   ret <8 x i16> %tmp8
diff --git a/test/CodeGen/X86/machine-cse.ll b/test/CodeGen/X86/machine-cse.ll
index b42d82e..409147b 100644
--- a/test/CodeGen/X86/machine-cse.ll
+++ b/test/CodeGen/X86/machine-cse.ll
@@ -8,7 +8,7 @@
 
 define fastcc i8* @t(i32 %base) nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: leaq (%rax,%rax,4)
   %0 = zext i32 %base to i64
   %1 = getelementptr inbounds %struct.s2* null, i64 %0
@@ -43,7 +43,7 @@ declare fastcc i8* @foo(%struct.s2*) nounwind
 declare void @printf(...) nounwind
 
 define void @commute(i32 %test_case, i32 %scale) nounwind ssp {
-; CHECK: commute:
+; CHECK-LABEL: commute:
 entry:
   switch i32 %test_case, label %sw.bb307 [
     i32 1, label %sw.bb
@@ -83,7 +83,7 @@ sw.bb307:                                         ; preds = %sw.bb, %entry
 ; rdar://10660865
 define i32 @cross_mbb_phys_cse(i32 %a, i32 %b) nounwind ssp {
 entry:
-; CHECK: cross_mbb_phys_cse:
+; CHECK-LABEL: cross_mbb_phys_cse:
 ; CHECK: cmpl
 ; CHECK: ja
   %cmp = icmp ugt i32 %a, %b
@@ -153,7 +153,7 @@ a:
 b:
   ret i32 0
 
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: t2_global@GOTPCREL(%rip)
 ; CHECK-NOT: t2_global@GOTPCREL(%rip)
 }
diff --git a/test/CodeGen/X86/mcinst-lowering.ll b/test/CodeGen/X86/mcinst-lowering.ll
index 391f939..a82cfc4 100644
--- a/test/CodeGen/X86/mcinst-lowering.ll
+++ b/test/CodeGen/X86/mcinst-lowering.ll
@@ -30,7 +30,7 @@ define i32 @f1() nounwind {
   %conv = sext i16 %ax to i32
   ret i32 %conv
 
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cwtl ## encoding: [0x98]
 }
 
@@ -39,6 +39,6 @@ define i64 @f2() nounwind {
   %conv = sext i32 %eax to i64
   ret i64 %conv
 
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cltq ## encoding: [0x48,0x98]
 }
diff --git a/test/CodeGen/X86/memcmp.ll b/test/CodeGen/X86/memcmp.ll
index 723d1d8..cb0797d 100644
--- a/test/CodeGen/X86/memcmp.ll
+++ b/test/CodeGen/X86/memcmp.ll
@@ -21,10 +21,10 @@ bb:                                               ; preds = %entry
 
 return:                                           ; preds = %entry
   ret void
-; CHECK: memcmp2:
+; CHECK-LABEL: memcmp2:
 ; CHECK: movw    ([[A0:%rdi|%rcx]]), %ax
 ; CHECK: cmpw    ([[A1:%rsi|%rdx]]), %ax
-; NOBUILTIN: memcmp2:
+; NOBUILTIN-LABEL: memcmp2:
 ; NOBUILTIN: callq
 }
 
@@ -40,7 +40,7 @@ bb:                                               ; preds = %entry
 
 return:                                           ; preds = %entry
   ret void
-; CHECK: memcmp2a:
+; CHECK-LABEL: memcmp2a:
 ; CHECK: cmpw    $28527, ([[A0]])
 }
 
@@ -57,7 +57,7 @@ bb:                                               ; preds = %entry
 
 return:                                           ; preds = %entry
   ret void
-; CHECK: memcmp4:
+; CHECK-LABEL: memcmp4:
 ; CHECK: movl    ([[A0]]), %eax
 ; CHECK: cmpl    ([[A1]]), %eax
 }
@@ -74,7 +74,7 @@ bb:                                               ; preds = %entry
 
 return:                                           ; preds = %entry
   ret void
-; CHECK: memcmp4a:
+; CHECK-LABEL: memcmp4a:
 ; CHECK: cmpl $1869573999, ([[A0]])
 }
 
@@ -90,7 +90,7 @@ bb:                                               ; preds = %entry
 
 return:                                           ; preds = %entry
   ret void
-; CHECK: memcmp8:
+; CHECK-LABEL: memcmp8:
 ; CHECK: movq    ([[A0]]), %rax
 ; CHECK: cmpq    ([[A1]]), %rax
 }
@@ -107,7 +107,7 @@ bb:                                               ; preds = %entry
 
 return:                                           ; preds = %entry
   ret void
-; CHECK: memcmp8a:
+; CHECK-LABEL: memcmp8a:
 ; CHECK: movabsq $8029759185026510694, %rax
 ; CHECK: cmpq	%rax, ([[A0]])
 }
diff --git a/test/CodeGen/X86/memcpy-2.ll b/test/CodeGen/X86/memcpy-2.ll
index 630c0ed..c17cc7f 100644
--- a/test/CodeGen/X86/memcpy-2.ll
+++ b/test/CodeGen/X86/memcpy-2.ll
@@ -9,28 +9,28 @@
 
 define void @t1(i32 %argc, i8** %argv) nounwind  {
 entry:
-; SSE2-Darwin: t1:
+; SSE2-Darwin-LABEL: t1:
 ; SSE2-Darwin: movsd _.str+16, %xmm0
 ; SSE2-Darwin: movsd %xmm0, 16(%esp)
 ; SSE2-Darwin: movaps _.str, %xmm0
 ; SSE2-Darwin: movaps %xmm0
 ; SSE2-Darwin: movb $0, 24(%esp)
 
-; SSE2-Mingw32: t1:
+; SSE2-Mingw32-LABEL: t1:
 ; SSE2-Mingw32: movsd _.str+16, %xmm0
 ; SSE2-Mingw32: movsd %xmm0, 16(%esp)
 ; SSE2-Mingw32: movaps _.str, %xmm0
 ; SSE2-Mingw32: movups %xmm0
 ; SSE2-Mingw32: movb $0, 24(%esp)
 
-; SSE1: t1:
+; SSE1-LABEL: t1:
 ; SSE1: movaps _.str, %xmm0
 ; SSE1: movaps %xmm0
 ; SSE1: movb $0, 24(%esp)
 ; SSE1: movl $0, 20(%esp)
 ; SSE1: movl $0, 16(%esp)
 
-; NOSSE: t1:
+; NOSSE-LABEL: t1:
 ; NOSSE: movb $0
 ; NOSSE: movl $0
 ; NOSSE: movl $0
@@ -39,7 +39,7 @@ entry:
 ; NOSSE: movl $101
 ; NOSSE: movl $1734438249
 
-; X86-64: t1:
+; X86-64-LABEL: t1:
 ; X86-64: movaps _.str(%rip), %xmm0
 ; X86-64: movaps %xmm0
 ; X86-64: movb $0
@@ -55,19 +55,19 @@ entry:
 
 define void @t2(%struct.s0* nocapture %a, %struct.s0* nocapture %b) nounwind ssp {
 entry:
-; SSE2-Darwin: t2:
+; SSE2-Darwin-LABEL: t2:
 ; SSE2-Darwin: movaps (%eax), %xmm0
 ; SSE2-Darwin: movaps %xmm0, (%eax)
 
-; SSE2-Mingw32: t2:
+; SSE2-Mingw32-LABEL: t2:
 ; SSE2-Mingw32: movaps (%eax), %xmm0
 ; SSE2-Mingw32: movaps %xmm0, (%eax)
 
-; SSE1: t2:
+; SSE1-LABEL: t2:
 ; SSE1: movaps (%eax), %xmm0
 ; SSE1: movaps %xmm0, (%eax)
 
-; NOSSE: t2:
+; NOSSE-LABEL: t2:
 ; NOSSE: movl
 ; NOSSE: movl
 ; NOSSE: movl
@@ -79,7 +79,7 @@ entry:
 ; NOSSE: movl
 ; NOSSE: movl
 
-; X86-64: t2:
+; X86-64-LABEL: t2:
 ; X86-64: movaps (%rsi), %xmm0
 ; X86-64: movaps %xmm0, (%rdi)
   %tmp2 = bitcast %struct.s0* %a to i8*           ; <i8*> [#uses=1]
@@ -90,19 +90,19 @@ entry:
 
 define void @t3(%struct.s0* nocapture %a, %struct.s0* nocapture %b) nounwind ssp {
 entry:
-; SSE2-Darwin: t3:
+; SSE2-Darwin-LABEL: t3:
 ; SSE2-Darwin: movsd (%eax), %xmm0
 ; SSE2-Darwin: movsd 8(%eax), %xmm1
 ; SSE2-Darwin: movsd %xmm1, 8(%eax)
 ; SSE2-Darwin: movsd %xmm0, (%eax)
 
-; SSE2-Mingw32: t3:
+; SSE2-Mingw32-LABEL: t3:
 ; SSE2-Mingw32: movsd (%eax), %xmm0
 ; SSE2-Mingw32: movsd 8(%eax), %xmm1
 ; SSE2-Mingw32: movsd %xmm1, 8(%eax)
 ; SSE2-Mingw32: movsd %xmm0, (%eax)
 
-; SSE1: t3:
+; SSE1-LABEL: t3:
 ; SSE1: movl
 ; SSE1: movl
 ; SSE1: movl
@@ -114,7 +114,7 @@ entry:
 ; SSE1: movl
 ; SSE1: movl
 
-; NOSSE: t3:
+; NOSSE-LABEL: t3:
 ; NOSSE: movl
 ; NOSSE: movl
 ; NOSSE: movl
@@ -126,7 +126,7 @@ entry:
 ; NOSSE: movl
 ; NOSSE: movl
 
-; X86-64: t3:
+; X86-64-LABEL: t3:
 ; X86-64: movq (%rsi), %rax
 ; X86-64: movq 8(%rsi), %rcx
 ; X86-64: movq %rcx, 8(%rdi)
@@ -139,7 +139,7 @@ entry:
 
 define void @t4() nounwind {
 entry:
-; SSE2-Darwin: t4:
+; SSE2-Darwin-LABEL: t4:
 ; SSE2-Darwin: movw $120
 ; SSE2-Darwin: movl $2021161080
 ; SSE2-Darwin: movl $2021161080
@@ -149,7 +149,7 @@ entry:
 ; SSE2-Darwin: movl $2021161080
 ; SSE2-Darwin: movl $2021161080
 
-; SSE2-Mingw32: t4:
+; SSE2-Mingw32-LABEL: t4:
 ; SSE2-Mingw32: movw $120
 ; SSE2-Mingw32: movl $2021161080
 ; SSE2-Mingw32: movl $2021161080
@@ -159,7 +159,7 @@ entry:
 ; SSE2-Mingw32: movl $2021161080
 ; SSE2-Mingw32: movl $2021161080
 
-; SSE1: t4:
+; SSE1-LABEL: t4:
 ; SSE1: movw $120
 ; SSE1: movl $2021161080
 ; SSE1: movl $2021161080
@@ -169,7 +169,7 @@ entry:
 ; SSE1: movl $2021161080
 ; SSE1: movl $2021161080
 
-; NOSSE: t4:
+; NOSSE-LABEL: t4:
 ; NOSSE: movw $120
 ; NOSSE: movl $2021161080
 ; NOSSE: movl $2021161080
@@ -179,7 +179,7 @@ entry:
 ; NOSSE: movl $2021161080
 ; NOSSE: movl $2021161080
 
-; X86-64: t4:
+; X86-64-LABEL: t4:
 ; X86-64: movabsq $8680820740569200760, %rax
 ; X86-64: movq %rax
 ; X86-64: movq %rax
diff --git a/test/CodeGen/X86/memset-2.ll b/test/CodeGen/X86/memset-2.ll
index b2bd72b..d0a3c7a 100644
--- a/test/CodeGen/X86/memset-2.ll
+++ b/test/CodeGen/X86/memset-2.ll
@@ -4,7 +4,7 @@ declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind
 
 define fastcc void @t1() nounwind {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: calll _memset
   call void @llvm.memset.p0i8.i32(i8* null, i8 0, i32 188, i32 1, i1 false)
   unreachable
@@ -12,7 +12,7 @@ entry:
 
 define fastcc void @t2(i8 signext %c) nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: calll _memset
   call void @llvm.memset.p0i8.i32(i8* undef, i8 %c, i32 76, i32 1, i1 false)
   unreachable
@@ -24,7 +24,7 @@ define void @t3(i8* nocapture %s, i8 %a) nounwind {
 entry:
   tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 8, i32 1, i1 false)
   ret void
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: imull $16843009
 }
 
@@ -32,7 +32,7 @@ define void @t4(i8* nocapture %s, i8 %a) nounwind {
 entry:
   tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 15, i32 1, i1 false)
   ret void
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: imull $16843009
 ; CHECK-NOT: imul
 ; CHECK: ret
diff --git a/test/CodeGen/X86/mmx-arg-passing.ll b/test/CodeGen/X86/mmx-arg-passing.ll
index d9ea487..3a0fb95 100644
--- a/test/CodeGen/X86/mmx-arg-passing.ll
+++ b/test/CodeGen/X86/mmx-arg-passing.ll
@@ -13,10 +13,10 @@ define void @t1(x86_mmx %v1) nounwind  {
 	store x86_mmx %v1, x86_mmx* @u1, align 8
 	ret void
 
-; X86-32: t1:
+; X86-32-LABEL: t1:
 ; X86-32: movq %mm0
 
-; X86-64: t1:
+; X86-64-LABEL: t1:
 ; X86-64: movdq2q %xmm0
 ; X86-64: movq %mm0
 }
@@ -28,11 +28,11 @@ define void @t2(<1 x i64> %v1) nounwind  {
 	store x86_mmx %tmp, x86_mmx* @u2, align 8
 	ret void
 
-; X86-32: t2:
+; X86-32-LABEL: t2:
 ; X86-32: movl 4(%esp)
 ; X86-32: movl 8(%esp)
 
-; X86-64: t2:
+; X86-64-LABEL: t2:
 ; X86-64: movq %rdi
 }
 
diff --git a/test/CodeGen/X86/mmx-shift.ll b/test/CodeGen/X86/mmx-shift.ll
index 2b6dc6f..c7c6e75 100644
--- a/test/CodeGen/X86/mmx-shift.ll
+++ b/test/CodeGen/X86/mmx-shift.ll
@@ -8,7 +8,7 @@ entry:
         %retval1112 = bitcast x86_mmx %tmp6 to i64
 	ret i64 %retval1112
 
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: psllq $32
 }
 
@@ -20,7 +20,7 @@ entry:
         %retval1112 = bitcast x86_mmx %tmp7 to i64
 	ret i64 %retval1112
 
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: psrad
 }
 
@@ -32,7 +32,7 @@ entry:
         %retval1314 = bitcast x86_mmx %tmp8 to i64
 	ret i64 %retval1314
 
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: psrlw
 }
 
diff --git a/test/CodeGen/X86/movgs.ll b/test/CodeGen/X86/movgs.ll
index e5afb27..d3930fa 100644
--- a/test/CodeGen/X86/movgs.ll
+++ b/test/CodeGen/X86/movgs.ll
@@ -45,12 +45,12 @@ entry:
   %3 = bitcast <4 x i32> %2 to <2 x i64>
   ret <2 x i64> %3
   
-; X32: pmovsxwd_1:
+; X32-LABEL: pmovsxwd_1:
 ; X32: 	movl	4(%esp), %eax
 ; X32: 	pmovsxwd	%gs:(%eax), %xmm0
 ; X32: 	ret
 
-; X64: pmovsxwd_1:
+; X64-LABEL: pmovsxwd_1:
 ; X64:	pmovsxwd	%gs:([[A0]]), %xmm0
 ; X64:	ret
 }
diff --git a/test/CodeGen/X86/movmsk.ll b/test/CodeGen/X86/movmsk.ll
index 928ad03..2520662 100644
--- a/test/CodeGen/X86/movmsk.ll
+++ b/test/CodeGen/X86/movmsk.ll
@@ -83,7 +83,7 @@ define void @float_call_signbit(double %n) {
 entry:
 ; FIXME: This should also use movmskps; we don't form the FGETSIGN node
 ; in this case, though.
-; CHECK: float_call_signbit:
+; CHECK-LABEL: float_call_signbit:
 ; CHECK: movd %xmm0, %rdi
 ; FIXME
   %t0 = bitcast double %n to i64
@@ -99,7 +99,7 @@ declare void @float_call_signbit_callee(i1 zeroext)
 
 define i32 @t1(<4 x float> %x, i32* nocapture %indexTable) nounwind uwtable readonly ssp {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: movmskps
 ; CHECK-NOT: movslq
   %0 = tail call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %x) nounwind
@@ -111,7 +111,7 @@ entry:
 
 define i32 @t2(<4 x float> %x, i32* nocapture %indexTable) nounwind uwtable readonly ssp {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: movmskpd
 ; CHECK-NOT: movslq
   %0 = bitcast <4 x float> %x to <2 x double>
diff --git a/test/CodeGen/X86/ms-inline-asm.ll b/test/CodeGen/X86/ms-inline-asm.ll
index 5048a93..5e7ba37 100644
--- a/test/CodeGen/X86/ms-inline-asm.ll
+++ b/test/CodeGen/X86/ms-inline-asm.ll
@@ -75,7 +75,7 @@ define void @t19() nounwind {
 entry:
   call void asm sideeffect inteldialect "call $0", "r,~{dirflag},~{fpsr},~{flags}"(void ()* @t19_helper) nounwind
   ret void
-; CHECK: t19:
+; CHECK-LABEL: t19:
 ; CHECK: movl %esp, %ebp
 ; CHECK: movl ${{_?}}t19_helper, %eax
 ; CHECK: {{## InlineAsm Start|#APP}}
@@ -94,7 +94,7 @@ entry:
   call void asm sideeffect inteldialect "mov dword ptr $0, edi", "=*m,~{dirflag},~{fpsr},~{flags}"(i32** %res) nounwind
   %0 = load i32** %res, align 4
   ret i32* %0
-; CHECK: t30:
+; CHECK-LABEL: t30:
 ; CHECK: movl %esp, %ebp
 ; CHECK: {{## InlineAsm Start|#APP}}
 ; CHECK: .intel_syntax
diff --git a/test/CodeGen/X86/narrow_op-1.ll b/test/CodeGen/X86/narrow_op-1.ll
index d203d49..89ae3f1 100644
--- a/test/CodeGen/X86/narrow_op-1.ll
+++ b/test/CodeGen/X86/narrow_op-1.ll
@@ -10,7 +10,7 @@ entry:
 	store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
 	ret void
 
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: orb $1
 ; CHECK-NEXT: ret
 }
@@ -22,7 +22,7 @@ entry:
 	store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
 	ret void
 
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: orl $16842752
 ; CHECK-NEXT: ret
 }
diff --git a/test/CodeGen/X86/neg_cmp.ll b/test/CodeGen/X86/neg_cmp.ll
index 866514e..7905072 100644
--- a/test/CodeGen/X86/neg_cmp.ll
+++ b/test/CodeGen/X86/neg_cmp.ll
@@ -4,7 +4,7 @@
 ; PR12545
 define void @f(i32 %x, i32 %y) nounwind uwtable ssp {
 entry:
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK-NOT: neg
 ; CHECK: add
   %sub = sub i32 0, %y
diff --git a/test/CodeGen/X86/non-lazy-bind.ll b/test/CodeGen/X86/non-lazy-bind.ll
index f729658..546a136 100644
--- a/test/CodeGen/X86/non-lazy-bind.ll
+++ b/test/CodeGen/X86/non-lazy-bind.ll
@@ -3,7 +3,7 @@
 declare void @lazy() nonlazybind
 declare void @not()
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK:  callq _not
 ; CHECK:  callq *_lazy@GOTPCREL(%rip)
 define void @foo() nounwind {
@@ -12,14 +12,14 @@ define void @foo() nounwind {
   ret void
 }
 
-; CHECK: tail_call_regular:
+; CHECK-LABEL: tail_call_regular:
 ; CHECK:   jmp _not
 define void @tail_call_regular() nounwind {
   tail call void @not()
   ret void
 }
 
-; CHECK: tail_call_eager:
+; CHECK-LABEL: tail_call_eager:
 ; CHECK:   jmpq *_lazy@GOTPCREL(%rip)
 define void @tail_call_eager() nounwind {
   tail call void @lazy()
diff --git a/test/CodeGen/X86/optimize-max-3.ll b/test/CodeGen/X86/optimize-max-3.ll
index d092916..1b65373 100644
--- a/test/CodeGen/X86/optimize-max-3.ll
+++ b/test/CodeGen/X86/optimize-max-3.ll
@@ -3,7 +3,7 @@
 
 ; LSR's OptimizeMax should eliminate the select (max).
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NOT: cmov
 ; CHECK: jle
 
@@ -37,7 +37,7 @@ for.end:                                          ; preds = %for.body, %entry
 ; OptimizeMax should handle this case.
 ; PR7454
 
-;      CHECK: _Z18GenerateStatusPagei:
+;      CHECK-LABEL: _Z18GenerateStatusPagei:
 
 ;      CHECK:         jle
 ;  CHECK-NOT:         cmov
diff --git a/test/CodeGen/X86/palignr-2.ll b/test/CodeGen/X86/palignr-2.ll
index 116d4c7..4df9a22 100644
--- a/test/CodeGen/X86/palignr-2.ll
+++ b/test/CodeGen/X86/palignr-2.ll
@@ -7,7 +7,7 @@
 
 define void @t1(<2 x i64> %a, <2 x i64> %b) nounwind ssp {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; palignr $3, %xmm1, %xmm0
   %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i8 24) nounwind readnone
   store <2 x i64> %0, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16
@@ -18,7 +18,7 @@ declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwin
 
 define void @t2() nounwind ssp {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; palignr $4, _b, %xmm0
   %0 = load <2 x i64>* bitcast ([4 x i32]* @b to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1]
   %1 = load <2 x i64>* bitcast ([4 x i32]* @a to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1]
diff --git a/test/CodeGen/X86/pass-three.ll b/test/CodeGen/X86/pass-three.ll
index 23005c7..39ff69a 100644
--- a/test/CodeGen/X86/pass-three.ll
+++ b/test/CodeGen/X86/pass-three.ll
@@ -11,6 +11,6 @@ entry:
   ret { i8*, i64, i64* } %2
 }
 
-; CHECK: copy_3:
+; CHECK-LABEL: copy_3:
 ; CHECK-NOT: (%rdi)
 ; CHECK: ret
diff --git a/test/CodeGen/X86/peep-test-3.ll b/test/CodeGen/X86/peep-test-3.ll
index a7c456a..b3d4f58 100644
--- a/test/CodeGen/X86/peep-test-3.ll
+++ b/test/CodeGen/X86/peep-test-3.ll
@@ -3,7 +3,7 @@
 
 ; LLVM should omit the testl and use the flags result from the orl.
 
-; CHECK: or:
+; CHECK-LABEL: or:
 define void @or(float* %A, i32 %IA, i32 %N) nounwind {
 entry:
   %0 = ptrtoint float* %A to i32                  ; <i32> [#uses=1]
@@ -22,7 +22,7 @@ bb:                                               ; preds = %entry
 return:                                           ; preds = %entry
   ret void
 }
-; CHECK: xor:
+; CHECK-LABEL: xor:
 define void @xor(float* %A, i32 %IA, i32 %N) nounwind {
 entry:
   %0 = ptrtoint float* %A to i32                  ; <i32> [#uses=1]
@@ -41,7 +41,7 @@ bb:                                               ; preds = %entry
 return:                                           ; preds = %entry
   ret void
 }
-; CHECK: and:
+; CHECK-LABEL: and:
 define void @and(float* %A, i32 %IA, i32 %N, i8* %p) nounwind {
 entry:
   store i8 0, i8* %p
diff --git a/test/CodeGen/X86/peep-test-4.ll b/test/CodeGen/X86/peep-test-4.ll
index a1eea00..884ee7c 100644
--- a/test/CodeGen/X86/peep-test-4.ll
+++ b/test/CodeGen/X86/peep-test-4.ll
@@ -2,7 +2,7 @@
 declare void @foo(i32)
 declare void @foo64(i64)
 
-; CHECK: neg:
+; CHECK-LABEL: neg:
 ; CHECK: negl %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -20,7 +20,7 @@ return:
   ret void
 }
 
-; CHECK: sar:
+; CHECK-LABEL: sar:
 ; CHECK: sarl %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -38,7 +38,7 @@ return:
   ret void
 }
 
-; CHECK: shr:
+; CHECK-LABEL: shr:
 ; CHECK: shrl %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -56,7 +56,7 @@ return:
   ret void
 }
 
-; CHECK: shri:
+; CHECK-LABEL: shri:
 ; CHECK: shrl $3, %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -74,7 +74,7 @@ return:
   ret void
 }
 
-; CHECK: shl:
+; CHECK-LABEL: shl:
 ; CHECK: addl %edi, %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -92,7 +92,7 @@ return:
   ret void
 }
 
-; CHECK: shli:
+; CHECK-LABEL: shli:
 ; CHECK: shll $4, %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -110,7 +110,7 @@ return:
   ret void
 }
 
-; CHECK: adc:
+; CHECK-LABEL: adc:
 ; CHECK: movabsq $-9223372036854775808, %rax
 ; CHECK-NEXT: addq  %rdi, %rax
 ; CHECK-NEXT: adcq  $0, %rsi
@@ -122,7 +122,7 @@ define zeroext i1 @adc(i128 %x) nounwind {
   ret i1 %cmp
 }
 
-; CHECK: sbb:
+; CHECK-LABEL: sbb:
 ; CHECK: cmpq  %rdx, %rdi
 ; CHECK-NEXT: sbbq  %rcx, %rsi
 ; CHECK-NEXT: setns %al
@@ -133,7 +133,7 @@ define zeroext i1 @sbb(i128 %x, i128 %y) nounwind {
   ret i1 %cmp
 }
 
-; CHECK: andn:
+; CHECK-LABEL: andn:
 ; CHECK: andnl   %esi, %edi, %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -152,7 +152,7 @@ return:
   ret void
 }
 
-; CHECK: bextr:
+; CHECK-LABEL: bextr:
 ; CHECK: bextrl   %esi, %edi, %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -171,7 +171,7 @@ return:
   ret void
 }
 
-; CHECK: popcnt:
+; CHECK-LABEL: popcnt:
 ; CHECK: popcntl
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
diff --git a/test/CodeGen/X86/phaddsub.ll b/test/CodeGen/X86/phaddsub.ll
index 62d85f7..17e7e1d 100644
--- a/test/CodeGen/X86/phaddsub.ll
+++ b/test/CodeGen/X86/phaddsub.ll
@@ -1,10 +1,10 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+ssse3,-avx | FileCheck %s -check-prefix=SSSE3
 ; RUN: llc < %s -march=x86-64 -mattr=-ssse3,+avx | FileCheck %s -check-prefix=AVX
 
-; SSSE3: phaddw1:
+; SSSE3-LABEL: phaddw1:
 ; SSSE3-NOT: vphaddw
 ; SSSE3: phaddw
-; AVX: phaddw1:
+; AVX-LABEL: phaddw1:
 ; AVX: vphaddw
 define <8 x i16> @phaddw1(<8 x i16> %x, <8 x i16> %y) {
   %a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
@@ -13,10 +13,10 @@ define <8 x i16> @phaddw1(<8 x i16> %x, <8 x i16> %y) {
   ret <8 x i16> %r
 }
 
-; SSSE3: phaddw2:
+; SSSE3-LABEL: phaddw2:
 ; SSSE3-NOT: vphaddw
 ; SSSE3: phaddw
-; AVX: phaddw2:
+; AVX-LABEL: phaddw2:
 ; AVX: vphaddw
 define <8 x i16> @phaddw2(<8 x i16> %x, <8 x i16> %y) {
   %a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 2, i32 5, i32 6, i32 9, i32 10, i32 13, i32 14>
@@ -25,10 +25,10 @@ define <8 x i16> @phaddw2(<8 x i16> %x, <8 x i16> %y) {
   ret <8 x i16> %r
 }
 
-; SSSE3: phaddd1:
+; SSSE3-LABEL: phaddd1:
 ; SSSE3-NOT: vphaddd
 ; SSSE3: phaddd
-; AVX: phaddd1:
+; AVX-LABEL: phaddd1:
 ; AVX: vphaddd
 define <4 x i32> @phaddd1(<4 x i32> %x, <4 x i32> %y) {
   %a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -37,10 +37,10 @@ define <4 x i32> @phaddd1(<4 x i32> %x, <4 x i32> %y) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phaddd2:
+; SSSE3-LABEL: phaddd2:
 ; SSSE3-NOT: vphaddd
 ; SSSE3: phaddd
-; AVX: phaddd2:
+; AVX-LABEL: phaddd2:
 ; AVX: vphaddd
 define <4 x i32> @phaddd2(<4 x i32> %x, <4 x i32> %y) {
   %a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
@@ -49,10 +49,10 @@ define <4 x i32> @phaddd2(<4 x i32> %x, <4 x i32> %y) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phaddd3:
+; SSSE3-LABEL: phaddd3:
 ; SSSE3-NOT: vphaddd
 ; SSSE3: phaddd
-; AVX: phaddd3:
+; AVX-LABEL: phaddd3:
 ; AVX: vphaddd
 define <4 x i32> @phaddd3(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
@@ -61,10 +61,10 @@ define <4 x i32> @phaddd3(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phaddd4:
+; SSSE3-LABEL: phaddd4:
 ; SSSE3-NOT: vphaddd
 ; SSSE3: phaddd
-; AVX: phaddd4:
+; AVX-LABEL: phaddd4:
 ; AVX: vphaddd
 define <4 x i32> @phaddd4(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
@@ -73,10 +73,10 @@ define <4 x i32> @phaddd4(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phaddd5:
+; SSSE3-LABEL: phaddd5:
 ; SSSE3-NOT: vphaddd
 ; SSSE3: phaddd
-; AVX: phaddd5:
+; AVX-LABEL: phaddd5:
 ; AVX: vphaddd
 define <4 x i32> @phaddd5(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
@@ -85,10 +85,10 @@ define <4 x i32> @phaddd5(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phaddd6:
+; SSSE3-LABEL: phaddd6:
 ; SSSE3-NOT: vphaddd
 ; SSSE3: phaddd
-; AVX: phaddd6:
+; AVX-LABEL: phaddd6:
 ; AVX: vphaddd
 define <4 x i32> @phaddd6(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
@@ -97,10 +97,10 @@ define <4 x i32> @phaddd6(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phaddd7:
+; SSSE3-LABEL: phaddd7:
 ; SSSE3-NOT: vphaddd
 ; SSSE3: phaddd
-; AVX: phaddd7:
+; AVX-LABEL: phaddd7:
 ; AVX: vphaddd
 define <4 x i32> @phaddd7(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
@@ -109,10 +109,10 @@ define <4 x i32> @phaddd7(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phsubw1:
+; SSSE3-LABEL: phsubw1:
 ; SSSE3-NOT: vphsubw
 ; SSSE3: phsubw
-; AVX: phsubw1:
+; AVX-LABEL: phsubw1:
 ; AVX: vphsubw
 define <8 x i16> @phsubw1(<8 x i16> %x, <8 x i16> %y) {
   %a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
@@ -121,10 +121,10 @@ define <8 x i16> @phsubw1(<8 x i16> %x, <8 x i16> %y) {
   ret <8 x i16> %r
 }
 
-; SSSE3: phsubd1:
+; SSSE3-LABEL: phsubd1:
 ; SSSE3-NOT: vphsubd
 ; SSSE3: phsubd
-; AVX: phsubd1:
+; AVX-LABEL: phsubd1:
 ; AVX: vphsubd
 define <4 x i32> @phsubd1(<4 x i32> %x, <4 x i32> %y) {
   %a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -133,10 +133,10 @@ define <4 x i32> @phsubd1(<4 x i32> %x, <4 x i32> %y) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phsubd2:
+; SSSE3-LABEL: phsubd2:
 ; SSSE3-NOT: vphsubd
 ; SSSE3: phsubd
-; AVX: phsubd2:
+; AVX-LABEL: phsubd2:
 ; AVX: vphsubd
 define <4 x i32> @phsubd2(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
@@ -145,10 +145,10 @@ define <4 x i32> @phsubd2(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phsubd3:
+; SSSE3-LABEL: phsubd3:
 ; SSSE3-NOT: vphsubd
 ; SSSE3: phsubd
-; AVX: phsubd3:
+; AVX-LABEL: phsubd3:
 ; AVX: vphsubd
 define <4 x i32> @phsubd3(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
@@ -157,10 +157,10 @@ define <4 x i32> @phsubd3(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phsubd4:
+; SSSE3-LABEL: phsubd4:
 ; SSSE3-NOT: vphsubd
 ; SSSE3: phsubd
-; AVX: phsubd4:
+; AVX-LABEL: phsubd4:
 ; AVX: vphsubd
 define <4 x i32> @phsubd4(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
diff --git a/test/CodeGen/X86/phys_subreg_coalesce-3.ll b/test/CodeGen/X86/phys_subreg_coalesce-3.ll
index 2a20e7a..6eb97c3 100644
--- a/test/CodeGen/X86/phys_subreg_coalesce-3.ll
+++ b/test/CodeGen/X86/phys_subreg_coalesce-3.ll
@@ -7,7 +7,7 @@
 ; 336L		%vreg15<def> = SAR32rCL %vreg15, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg15
 
 define void @foo(i32* nocapture %quadrant, i32* nocapture %ptr, i32 %bbSize, i32 %bbStart, i32 %shifts) nounwind ssp {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 entry:
   %j.03 = add i32 %bbSize, -1                     ; <i32> [#uses=2]
   %0 = icmp sgt i32 %j.03, -1                     ; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/popcnt.ll b/test/CodeGen/X86/popcnt.ll
index 430214c..e9350de 100644
--- a/test/CodeGen/X86/popcnt.ll
+++ b/test/CodeGen/X86/popcnt.ll
@@ -3,7 +3,7 @@
 define i8 @cnt8(i8 %x) nounwind readnone {
   %cnt = tail call i8 @llvm.ctpop.i8(i8 %x)
   ret i8 %cnt
-; CHECK: cnt8:
+; CHECK-LABEL: cnt8:
 ; CHECK: popcntw
 ; CHECK: ret
 }
@@ -11,7 +11,7 @@ define i8 @cnt8(i8 %x) nounwind readnone {
 define i16 @cnt16(i16 %x) nounwind readnone {
   %cnt = tail call i16 @llvm.ctpop.i16(i16 %x)
   ret i16 %cnt
-; CHECK: cnt16:
+; CHECK-LABEL: cnt16:
 ; CHECK: popcntw
 ; CHECK: ret
 }
@@ -19,7 +19,7 @@ define i16 @cnt16(i16 %x) nounwind readnone {
 define i32 @cnt32(i32 %x) nounwind readnone {
   %cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
   ret i32 %cnt
-; CHECK: cnt32:
+; CHECK-LABEL: cnt32:
 ; CHECK: popcntl
 ; CHECK: ret
 }
@@ -27,7 +27,7 @@ define i32 @cnt32(i32 %x) nounwind readnone {
 define i64 @cnt64(i64 %x) nounwind readnone {
   %cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
   ret i64 %cnt
-; CHECK: cnt64:
+; CHECK-LABEL: cnt64:
 ; CHECK: popcntq
 ; CHECK: ret
 }
diff --git a/test/CodeGen/X86/postra-licm.ll b/test/CodeGen/X86/postra-licm.ll
index 01d6cbe..946b836 100644
--- a/test/CodeGen/X86/postra-licm.ll
+++ b/test/CodeGen/X86/postra-licm.ll
@@ -16,7 +16,7 @@
 @.str24 = external constant [4 x i8], align 1     ; <[4 x i8]*> [#uses=1]
 
 define i32 @t1(i32 %c, i8** nocapture %v) nounwind ssp {
-; X86-32: t1:
+; X86-32-LABEL: t1:
 entry:
   br i1 undef, label %bb, label %bb3
 
@@ -146,7 +146,7 @@ declare i32 @strcmp(i8* nocapture, i8* nocapture) nounwind readonly
 @map_4_to_16 = external constant [16 x i16], align 32 ; <[16 x i16]*> [#uses=2]
 
 define void @t2(i8* nocapture %bufp, i8* nocapture %data, i32 %dsize) nounwind ssp {
-; X86-64: t2:
+; X86-64-LABEL: t2:
 entry:
   br i1 undef, label %return, label %bb.nph
 
diff --git a/test/CodeGen/X86/pr12360.ll b/test/CodeGen/X86/pr12360.ll
index f29e50e..8b30596 100644
--- a/test/CodeGen/X86/pr12360.ll
+++ b/test/CodeGen/X86/pr12360.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
 
 define zeroext i1 @f1(i8* %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: movb	(%rdi), %al
 ; CHECK-NEXT: ret
 
@@ -12,7 +12,7 @@ entry:
 }
 
 define zeroext i1 @f2(i8* %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: movb	(%rdi), %al
 ; CHECK-NEXT: ret
 
@@ -27,7 +27,7 @@ entry:
 
 ; check that we don't build a "trunc" from i1 to i1, which would assert.
 define zeroext i1 @f3(i1 %x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 
 entry:
   %tobool = icmp ne i1 %x, 0
@@ -36,7 +36,7 @@ entry:
 
 ; check that we don't build a trunc when other bits are needed
 define zeroext i1 @f4(i32 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: and
 
 entry:
diff --git a/test/CodeGen/X86/pr13209.ll b/test/CodeGen/X86/pr13209.ll
index 1c93163..8e5eca2 100644
--- a/test/CodeGen/X86/pr13209.ll
+++ b/test/CodeGen/X86/pr13209.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s
 
-; CHECK: pr13209:
+; CHECK-LABEL: pr13209:
 ; CHECK-NOT: mov
 ; CHECK: .size pr13209
 
diff --git a/test/CodeGen/X86/pr16031.ll b/test/CodeGen/X86/pr16031.ll
index 4721173..ab0b5ef 100644
--- a/test/CodeGen/X86/pr16031.ll
+++ b/test/CodeGen/X86/pr16031.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=corei7-avx | FileCheck %s
 
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK: pushl %esi
 ; CHECK-NEXT: movl  $-12, %eax
 ; CHECK-NEXT: movl  $-1, %edx
diff --git a/test/CodeGen/X86/pr2182.ll b/test/CodeGen/X86/pr2182.ll
index 02a3605..94429b2 100644
--- a/test/CodeGen/X86/pr2182.ll
+++ b/test/CodeGen/X86/pr2182.ll
@@ -7,7 +7,7 @@ target triple = "i386-apple-darwin8"
 @x = weak global i32 0          ; <i32*> [#uses=8]
 
 define void @loop_2() nounwind  {
-; CHECK: loop_2:
+; CHECK-LABEL: loop_2:
 ; CHECK-NOT: ret
 ; CHECK: addl $3, (%{{.*}})
 ; CHECK-NEXT: addl $3, (%{{.*}})
diff --git a/test/CodeGen/X86/pr3216.ll b/test/CodeGen/X86/pr3216.ll
index 63676d9..a4a4821 100644
--- a/test/CodeGen/X86/pr3216.ll
+++ b/test/CodeGen/X86/pr3216.ll
@@ -3,7 +3,7 @@
 @foo = global i8 127
 
 define i32 @main() nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK-NOT: ret
 ; CHECK: sar{{.}} $5
 ; CHECK: ret
diff --git a/test/CodeGen/X86/private.ll b/test/CodeGen/X86/private.ll
index 557bbd2..c02d193 100644
--- a/test/CodeGen/X86/private.ll
+++ b/test/CodeGen/X86/private.ll
@@ -13,7 +13,7 @@ define i32 @bar() {
 	%1 = load i32* @baz, align 4
         ret i32 %1
 
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: callq .Lfoo
 ; CHECK: movl	.Lbaz(%rip)
 }
diff --git a/test/CodeGen/X86/promote-i16.ll b/test/CodeGen/X86/promote-i16.ll
index 3c91d74..963bc1c 100644
--- a/test/CodeGen/X86/promote-i16.ll
+++ b/test/CodeGen/X86/promote-i16.ll
@@ -2,7 +2,7 @@
 
 define signext i16 @foo(i16 signext %x) nounwind {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NOT: movzwl
 ; CHECK: movswl 4(%esp), %eax
 ; CHECK: xorl $21998, %eax
@@ -12,7 +12,7 @@ entry:
 
 define signext i16 @bar(i16 signext %x) nounwind {
 entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK-NOT: movzwl
 ; CHECK: movswl 4(%esp), %eax
 ; CHECK: xorl $-10770, %eax
diff --git a/test/CodeGen/X86/rdrand.ll b/test/CodeGen/X86/rdrand.ll
index 0fd9916..1b16a2d 100644
--- a/test/CodeGen/X86/rdrand.ll
+++ b/test/CodeGen/X86/rdrand.ll
@@ -9,7 +9,7 @@ define i32 @_rdrand16_step(i16* %random_val) {
   store i16 %randval, i16* %random_val
   %isvalid = extractvalue {i16, i32} %call, 1
   ret i32 %isvalid
-; CHECK: _rdrand16_step:
+; CHECK-LABEL: _rdrand16_step:
 ; CHECK: rdrandw	%ax
 ; CHECK: movw	%ax, (%r[[A0:di|cx]])
 ; CHECK: movzwl	%ax, %ecx
@@ -24,7 +24,7 @@ define i32 @_rdrand32_step(i32* %random_val) {
   store i32 %randval, i32* %random_val
   %isvalid = extractvalue {i32, i32} %call, 1
   ret i32 %isvalid
-; CHECK: _rdrand32_step:
+; CHECK-LABEL: _rdrand32_step:
 ; CHECK: rdrandl	%e[[T0:[a-z]+]]
 ; CHECK: movl	%e[[T0]], (%r[[A0]])
 ; CHECK: movl	$1, %eax
@@ -38,7 +38,7 @@ define i32 @_rdrand64_step(i64* %random_val) {
   store i64 %randval, i64* %random_val
   %isvalid = extractvalue {i64, i32} %call, 1
   ret i32 %isvalid
-; CHECK: _rdrand64_step:
+; CHECK-LABEL: _rdrand64_step:
 ; CHECK: rdrandq	%r[[T1:[a-z]+]]
 ; CHECK: movq	%r[[T1]], (%r[[A0]])
 ; CHECK: movl	$1, %eax
@@ -54,7 +54,7 @@ define i32 @CSE() nounwind {
  %v2 = extractvalue { i32, i32 } %rand2, 0
  %add = add i32 %v2, %v1
  ret i32 %add
-; CHECK: CSE:
+; CHECK-LABEL: CSE:
 ; CHECK: rdrandl
 ; CHECK: rdrandl
 }
@@ -78,7 +78,7 @@ while.body:                                       ; preds = %entry, %while.body
 
 while.end:                                        ; preds = %while.body, %entry
   ret void
-; CHECK: loop:
+; CHECK-LABEL: loop:
 ; CHECK-NOT: rdrandl
 ; CHECK: This Inner Loop Header: Depth=1
 ; CHECK: rdrandl
diff --git a/test/CodeGen/X86/rdseed.ll b/test/CodeGen/X86/rdseed.ll
index 409da62..edc5069 100644
--- a/test/CodeGen/X86/rdseed.ll
+++ b/test/CodeGen/X86/rdseed.ll
@@ -10,7 +10,7 @@ define i32 @_rdseed16_step(i16* %random_val) {
   store i16 %randval, i16* %random_val
   %isvalid = extractvalue {i16, i32} %call, 1
   ret i32 %isvalid
-; CHECK: _rdseed16_step:
+; CHECK-LABEL: _rdseed16_step:
 ; CHECK: rdseedw	%ax
 ; CHECK: movw	%ax, (%r[[A0:di|cx]])
 ; CHECK: movzwl	%ax, %ecx
@@ -25,7 +25,7 @@ define i32 @_rdseed32_step(i32* %random_val) {
   store i32 %randval, i32* %random_val
   %isvalid = extractvalue {i32, i32} %call, 1
   ret i32 %isvalid
-; CHECK: _rdseed32_step:
+; CHECK-LABEL: _rdseed32_step:
 ; CHECK: rdseedl	%e[[T0:[a-z]+]]
 ; CHECK: movl	%e[[T0]], (%r[[A0]])
 ; CHECK: movl	$1, %eax
@@ -39,7 +39,7 @@ define i32 @_rdseed64_step(i64* %random_val) {
   store i64 %randval, i64* %random_val
   %isvalid = extractvalue {i64, i32} %call, 1
   ret i32 %isvalid
-; CHECK: _rdseed64_step:
+; CHECK-LABEL: _rdseed64_step:
 ; CHECK: rdseedq	%r[[T1:[a-z]+]]
 ; CHECK: movq	%r[[T1]], (%r[[A0]])
 ; CHECK: movl	$1, %eax
diff --git a/test/CodeGen/X86/red-zone.ll b/test/CodeGen/X86/red-zone.ll
index d99a7a4..cce71f5 100644
--- a/test/CodeGen/X86/red-zone.ll
+++ b/test/CodeGen/X86/red-zone.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s
 
 ; First without noredzone.
-; CHECK: f0:
+; CHECK-LABEL: f0:
 ; CHECK: -4(%rsp)
 ; CHECK: -4(%rsp)
 ; CHECK: ret
@@ -12,7 +12,7 @@ entry:
 }
 
 ; Then with noredzone.
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: subq $4, %rsp
 ; CHECK: (%rsp)
 ; CHECK: (%rsp)
diff --git a/test/CodeGen/X86/red-zone2.ll b/test/CodeGen/X86/red-zone2.ll
index 3e9c790..c7e855b 100644
--- a/test/CodeGen/X86/red-zone2.ll
+++ b/test/CodeGen/X86/red-zone2.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s
-; CHECK: f0:
+; CHECK-LABEL: f0:
 ; CHECK: subq
 ; CHECK: addq
 
diff --git a/test/CodeGen/X86/remat-mov-0.ll b/test/CodeGen/X86/remat-mov-0.ll
index f89cd33..9e8d8f6 100644
--- a/test/CodeGen/X86/remat-mov-0.ll
+++ b/test/CodeGen/X86/remat-mov-0.ll
@@ -5,7 +5,7 @@
 
 declare void @foo(i64 %p)
 
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: xorl %e[[A0:di|cx]], %e
 ; CHECK: xorl %e[[A0]], %e[[A0]]
 define void @bar() nounwind {
@@ -14,7 +14,7 @@ define void @bar() nounwind {
   ret void
 }
 
-; CHECK: bat:
+; CHECK-LABEL: bat:
 ; CHECK: movq $-1, %r[[A0]]
 ; CHECK: movq $-1, %r[[A0]]
 define void @bat() nounwind {
@@ -23,7 +23,7 @@ define void @bat() nounwind {
   ret void
 }
 
-; CHECK: bau:
+; CHECK-LABEL: bau:
 ; CHECK: movl $1, %e[[A0]]
 ; CHECK: movl $1, %e[[A0]]
 define void @bau() nounwind {
diff --git a/test/CodeGen/X86/ret-mmx.ll b/test/CodeGen/X86/ret-mmx.ll
index 778e472..091fd53 100644
--- a/test/CodeGen/X86/ret-mmx.ll
+++ b/test/CodeGen/X86/ret-mmx.ll
@@ -8,7 +8,7 @@ entry:
 	%call = call <1 x i64> @return_v1di()		; <<1 x i64>> [#uses=0]
 	store <1 x i64> %call, <1 x i64>* @g_v1di
         ret void
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: callq
 ; CHECK-NEXT: movq	_g_v1di
 ; CHECK-NEXT: movq	%rax,
@@ -18,21 +18,21 @@ declare <1 x i64> @return_v1di()
 
 define <1 x i64> @t2() nounwind {
 	ret <1 x i64> <i64 1>
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: movl	$1
 ; CHECK-NEXT: ret
 }
 
 define <2 x i32> @t3() nounwind {
 	ret <2 x i32> <i32 1, i32 0>
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: movl $1
 ; CHECK: movd {{.*}}, %xmm0
 }
 
 define double @t4() nounwind {
 	ret double bitcast (<2 x i32> <i32 1, i32 0> to double)
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: movl $1
 ; CHECK: movd {{.*}}, %xmm0
 }
diff --git a/test/CodeGen/X86/rot16.ll b/test/CodeGen/X86/rot16.ll
index de23dcb..0293f4e 100644
--- a/test/CodeGen/X86/rot16.ll
+++ b/test/CodeGen/X86/rot16.ll
@@ -2,7 +2,7 @@
 
 define i16 @foo(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: rolw %cl
 	%0 = shl i16 %x, %z
 	%1 = sub i16 16, %z
@@ -13,7 +13,7 @@ entry:
 
 define i16 @bar(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: shldw %cl
 	%0 = shl i16 %y, %z
 	%1 = sub i16 16, %z
@@ -24,7 +24,7 @@ entry:
 
 define i16 @un(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: un:
+; CHECK-LABEL: un:
 ; CHECK: rorw %cl
 	%0 = lshr i16 %x, %z
 	%1 = sub i16 16, %z
@@ -35,7 +35,7 @@ entry:
 
 define i16 @bu(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: bu:
+; CHECK-LABEL: bu:
 ; CHECK: shrdw
 	%0 = lshr i16 %y, %z
 	%1 = sub i16 16, %z
@@ -46,7 +46,7 @@ entry:
 
 define i16 @xfoo(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: xfoo:
+; CHECK-LABEL: xfoo:
 ; CHECK: rolw $5
 	%0 = lshr i16 %x, 11
 	%1 = shl i16 %x, 5
@@ -56,7 +56,7 @@ entry:
 
 define i16 @xbar(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: xbar:
+; CHECK-LABEL: xbar:
 ; CHECK: shldw $5
 	%0 = shl i16 %y, 5
 	%1 = lshr i16 %x, 11
@@ -66,7 +66,7 @@ entry:
 
 define i16 @xun(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: xun:
+; CHECK-LABEL: xun:
 ; CHECK: rolw $11
 	%0 = lshr i16 %x, 5
 	%1 = shl i16 %x, 11
@@ -76,7 +76,7 @@ entry:
 
 define i16 @xbu(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: xbu:
+; CHECK-LABEL: xbu:
 ; CHECK: shldw $11
 	%0 = lshr i16 %y, 5
 	%1 = shl i16 %x, 11
diff --git a/test/CodeGen/X86/rot32.ll b/test/CodeGen/X86/rot32.ll
index e95a734..7bdd606 100644
--- a/test/CodeGen/X86/rot32.ll
+++ b/test/CodeGen/X86/rot32.ll
@@ -3,7 +3,7 @@
 
 define i32 @foo(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: roll %cl
 	%0 = shl i32 %x, %z
 	%1 = sub i32 32, %z
@@ -14,7 +14,7 @@ entry:
 
 define i32 @bar(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: shldl %cl
 	%0 = shl i32 %y, %z
 	%1 = sub i32 32, %z
@@ -25,7 +25,7 @@ entry:
 
 define i32 @un(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: un:
+; CHECK-LABEL: un:
 ; CHECK: rorl %cl
 	%0 = lshr i32 %x, %z
 	%1 = sub i32 32, %z
@@ -36,7 +36,7 @@ entry:
 
 define i32 @bu(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: bu:
+; CHECK-LABEL: bu:
 ; CHECK: shrdl %cl
 	%0 = lshr i32 %y, %z
 	%1 = sub i32 32, %z
@@ -47,9 +47,9 @@ entry:
 
 define i32 @xfoo(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: xfoo:
+; CHECK-LABEL: xfoo:
 ; CHECK: roll $7
-; BMI2: xfoo:
+; BMI2-LABEL: xfoo:
 ; BMI2: rorxl $25
 	%0 = lshr i32 %x, 25
 	%1 = shl i32 %x, 7
@@ -59,7 +59,7 @@ entry:
 
 define i32 @xfoop(i32* %p) nounwind readnone {
 entry:
-; BMI2: xfoop:
+; BMI2-LABEL: xfoop:
 ; BMI2: rorxl $25, ({{.+}}), %{{.+}}
 	%x = load i32* %p
 	%a = lshr i32 %x, 25
@@ -70,7 +70,7 @@ entry:
 
 define i32 @xbar(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: xbar:
+; CHECK-LABEL: xbar:
 ; CHECK: shldl $7
 	%0 = shl i32 %y, 7
 	%1 = lshr i32 %x, 25
@@ -80,9 +80,9 @@ entry:
 
 define i32 @xun(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: xun:
+; CHECK-LABEL: xun:
 ; CHECK: roll $25
-; BMI2: xun:
+; BMI2-LABEL: xun:
 ; BMI2: rorxl $7
 	%0 = lshr i32 %x, 7
 	%1 = shl i32 %x, 25
@@ -92,7 +92,7 @@ entry:
 
 define i32 @xunp(i32* %p) nounwind readnone {
 entry:
-; BMI2: xunp:
+; BMI2-LABEL: xunp:
 ; BMI2: rorxl $7, ({{.+}}), %{{.+}}
 	%x = load i32* %p
 	%a = lshr i32 %x, 7
@@ -103,7 +103,7 @@ entry:
 
 define i32 @xbu(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: xbu:
+; CHECK-LABEL: xbu:
 ; CHECK: shldl
 	%0 = lshr i32 %y, 7
 	%1 = shl i32 %x, 25
diff --git a/test/CodeGen/X86/rot64.ll b/test/CodeGen/X86/rot64.ll
index 7fa982d..e19a35d 100644
--- a/test/CodeGen/X86/rot64.ll
+++ b/test/CodeGen/X86/rot64.ll
@@ -43,7 +43,7 @@ entry:
 
 define i64 @xfoo(i64 %x, i64 %y, i64 %z) nounwind readnone {
 entry:
-; BMI2: xfoo:
+; BMI2-LABEL: xfoo:
 ; BMI2: rorxq $57
 	%0 = lshr i64 %x, 57
 	%1 = shl i64 %x, 7
@@ -53,7 +53,7 @@ entry:
 
 define i64 @xfoop(i64* %p) nounwind readnone {
 entry:
-; BMI2: xfoop:
+; BMI2-LABEL: xfoop:
 ; BMI2: rorxq $57, ({{.+}}), %{{.+}}
 	%x = load i64* %p
 	%a = lshr i64 %x, 57
@@ -72,7 +72,7 @@ entry:
 
 define i64 @xun(i64 %x, i64 %y, i64 %z) nounwind readnone {
 entry:
-; BMI2: xun:
+; BMI2-LABEL: xun:
 ; BMI2: rorxq $7
 	%0 = lshr i64 %x, 7
 	%1 = shl i64 %x, 57
@@ -82,7 +82,7 @@ entry:
 
 define i64 @xunp(i64* %p) nounwind readnone {
 entry:
-; BMI2: xunp:
+; BMI2-LABEL: xunp:
 ; BMI2: rorxq $7, ({{.+}}), %{{.+}}
 	%x = load i64* %p
 	%a = lshr i64 %x, 7
diff --git a/test/CodeGen/X86/rounding-ops.ll b/test/CodeGen/X86/rounding-ops.ll
index 51fcf64..ace31cf 100644
--- a/test/CodeGen/X86/rounding-ops.ll
+++ b/test/CodeGen/X86/rounding-ops.ll
@@ -5,10 +5,10 @@ define float @test1(float %x) nounwind  {
   %call = tail call float @floorf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-SSE: test1:
+; CHECK-SSE-LABEL: test1:
 ; CHECK-SSE: roundss $1
 
-; CHECK-AVX: test1:
+; CHECK-AVX-LABEL: test1:
 ; CHECK-AVX: vroundss $1
 }
 
@@ -18,10 +18,10 @@ define double @test2(double %x) nounwind  {
   %call = tail call double @floor(double %x) nounwind readnone
   ret double %call
 
-; CHECK-SSE: test2:
+; CHECK-SSE-LABEL: test2:
 ; CHECK-SSE: roundsd $1
 
-; CHECK-AVX: test2:
+; CHECK-AVX-LABEL: test2:
 ; CHECK-AVX: vroundsd $1
 }
 
@@ -31,10 +31,10 @@ define float @test3(float %x) nounwind  {
   %call = tail call float @nearbyintf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-SSE: test3:
+; CHECK-SSE-LABEL: test3:
 ; CHECK-SSE: roundss $12
 
-; CHECK-AVX: test3:
+; CHECK-AVX-LABEL: test3:
 ; CHECK-AVX: vroundss $12
 }
 
@@ -44,10 +44,10 @@ define double @test4(double %x) nounwind  {
   %call = tail call double @nearbyint(double %x) nounwind readnone
   ret double %call
 
-; CHECK-SSE: test4:
+; CHECK-SSE-LABEL: test4:
 ; CHECK-SSE: roundsd $12
 
-; CHECK-AVX: test4:
+; CHECK-AVX-LABEL: test4:
 ; CHECK-AVX: vroundsd $12
 }
 
@@ -57,10 +57,10 @@ define float @test5(float %x) nounwind  {
   %call = tail call float @ceilf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-SSE: test5:
+; CHECK-SSE-LABEL: test5:
 ; CHECK-SSE: roundss $2
 
-; CHECK-AVX: test5:
+; CHECK-AVX-LABEL: test5:
 ; CHECK-AVX: vroundss $2
 }
 
@@ -70,10 +70,10 @@ define double @test6(double %x) nounwind  {
   %call = tail call double @ceil(double %x) nounwind readnone
   ret double %call
 
-; CHECK-SSE: test6:
+; CHECK-SSE-LABEL: test6:
 ; CHECK-SSE: roundsd $2
 
-; CHECK-AVX: test6:
+; CHECK-AVX-LABEL: test6:
 ; CHECK-AVX: vroundsd $2
 }
 
@@ -83,10 +83,10 @@ define float @test7(float %x) nounwind  {
   %call = tail call float @rintf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-SSE: test7:
+; CHECK-SSE-LABEL: test7:
 ; CHECK-SSE: roundss $4
 
-; CHECK-AVX: test7:
+; CHECK-AVX-LABEL: test7:
 ; CHECK-AVX: vroundss $4
 }
 
@@ -96,10 +96,10 @@ define double @test8(double %x) nounwind  {
   %call = tail call double @rint(double %x) nounwind readnone
   ret double %call
 
-; CHECK-SSE: test8:
+; CHECK-SSE-LABEL: test8:
 ; CHECK-SSE: roundsd $4
 
-; CHECK-AVX: test8:
+; CHECK-AVX-LABEL: test8:
 ; CHECK-AVX: vroundsd $4
 }
 
@@ -109,10 +109,10 @@ define float @test9(float %x) nounwind  {
   %call = tail call float @truncf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-SSE: test9:
+; CHECK-SSE-LABEL: test9:
 ; CHECK-SSE: roundss $3
 
-; CHECK-AVX: test9:
+; CHECK-AVX-LABEL: test9:
 ; CHECK-AVX: vroundss $3
 }
 
@@ -122,10 +122,10 @@ define double @test10(double %x) nounwind  {
   %call = tail call double @trunc(double %x) nounwind readnone
   ret double %call
 
-; CHECK-SSE: test10:
+; CHECK-SSE-LABEL: test10:
 ; CHECK-SSE: roundsd $3
 
-; CHECK-AVX: test10:
+; CHECK-AVX-LABEL: test10:
 ; CHECK-AVX: vroundsd $3
 }
 
diff --git a/test/CodeGen/X86/segmented-stacks.ll b/test/CodeGen/X86/segmented-stacks.ll
index 5407b87..08a98ef 100644
--- a/test/CodeGen/X86/segmented-stacks.ll
+++ b/test/CodeGen/X86/segmented-stacks.ll
@@ -32,7 +32,7 @@ define void @test_basic() {
         call void @dummy_use (i32* %mem, i32 10)
 	ret void
 
-; X32-Linux:       test_basic:
+; X32-Linux-LABEL:       test_basic:
 
 ; X32-Linux:       cmpl %gs:48, %esp
 ; X32-Linux-NEXT:  ja      .LBB0_2
@@ -42,7 +42,7 @@ define void @test_basic() {
 ; X32-Linux-NEXT:  calll __morestack
 ; X32-Linux-NEXT:  ret
 
-; X64-Linux:       test_basic:
+; X64-Linux-LABEL:       test_basic:
 
 ; X64-Linux:       cmpq %fs:112, %rsp
 ; X64-Linux-NEXT:  ja      .LBB0_2
@@ -52,7 +52,7 @@ define void @test_basic() {
 ; X64-Linux-NEXT:  callq __morestack
 ; X64-Linux-NEXT:  ret
 
-; X32-Darwin:      test_basic:
+; X32-Darwin-LABEL:      test_basic:
 
 ; X32-Darwin:      movl $432, %ecx
 ; X32-Darwin-NEXT: cmpl %gs:(%ecx), %esp
@@ -63,7 +63,7 @@ define void @test_basic() {
 ; X32-Darwin-NEXT: calll ___morestack
 ; X32-Darwin-NEXT: ret
 
-; X64-Darwin:      test_basic:
+; X64-Darwin-LABEL:      test_basic:
 
 ; X64-Darwin:      cmpq %gs:816, %rsp
 ; X64-Darwin-NEXT: ja      LBB0_2
@@ -73,7 +73,7 @@ define void @test_basic() {
 ; X64-Darwin-NEXT: callq ___morestack
 ; X64-Darwin-NEXT: ret
 
-; X32-MinGW:       test_basic:
+; X32-MinGW-LABEL:       test_basic:
 
 ; X32-MinGW:       cmpl %fs:20, %esp
 ; X32-MinGW-NEXT:  ja      LBB0_2
@@ -83,7 +83,7 @@ define void @test_basic() {
 ; X32-MinGW-NEXT:  calll ___morestack
 ; X32-MinGW-NEXT:  ret
 
-; X64-FreeBSD:       test_basic:
+; X64-FreeBSD-LABEL:       test_basic:
 
 ; X64-FreeBSD:       cmpq %fs:24, %rsp
 ; X64-FreeBSD-NEXT:  ja      .LBB0_2
@@ -224,7 +224,7 @@ define fastcc void @test_fastcc() {
         call void @dummy_use (i32* %mem, i32 10)
         ret void
 
-; X32-Linux:       test_fastcc:
+; X32-Linux-LABEL:       test_fastcc:
 
 ; X32-Linux:       cmpl %gs:48, %esp
 ; X32-Linux-NEXT:  ja      .LBB3_2
@@ -234,7 +234,7 @@ define fastcc void @test_fastcc() {
 ; X32-Linux-NEXT:  calll __morestack
 ; X32-Linux-NEXT:  ret
 
-; X64-Linux:       test_fastcc:
+; X64-Linux-LABEL:       test_fastcc:
 
 ; X64-Linux:       cmpq %fs:112, %rsp
 ; X64-Linux-NEXT:  ja      .LBB3_2
@@ -244,7 +244,7 @@ define fastcc void @test_fastcc() {
 ; X64-Linux-NEXT:  callq __morestack
 ; X64-Linux-NEXT:  ret
 
-; X32-Darwin:      test_fastcc:
+; X32-Darwin-LABEL:      test_fastcc:
 
 ; X32-Darwin:      movl $432, %eax
 ; X32-Darwin-NEXT: cmpl %gs:(%eax), %esp
@@ -255,7 +255,7 @@ define fastcc void @test_fastcc() {
 ; X32-Darwin-NEXT: calll ___morestack
 ; X32-Darwin-NEXT: ret
 
-; X64-Darwin:      test_fastcc:
+; X64-Darwin-LABEL:      test_fastcc:
 
 ; X64-Darwin:      cmpq %gs:816, %rsp
 ; X64-Darwin-NEXT: ja      LBB3_2
@@ -265,7 +265,7 @@ define fastcc void @test_fastcc() {
 ; X64-Darwin-NEXT: callq ___morestack
 ; X64-Darwin-NEXT: ret
 
-; X32-MinGW:       test_fastcc:
+; X32-MinGW-LABEL:       test_fastcc:
 
 ; X32-MinGW:       cmpl %fs:20, %esp
 ; X32-MinGW-NEXT:  ja      LBB3_2
@@ -275,7 +275,7 @@ define fastcc void @test_fastcc() {
 ; X32-MinGW-NEXT:  calll ___morestack
 ; X32-MinGW-NEXT:  ret
 
-; X64-FreeBSD:       test_fastcc:
+; X64-FreeBSD-LABEL:       test_fastcc:
 
 ; X64-FreeBSD:       cmpq %fs:24, %rsp
 ; X64-FreeBSD-NEXT:  ja      .LBB3_2
@@ -292,7 +292,7 @@ define fastcc void @test_fastcc_large() {
         call void @dummy_use (i32* %mem, i32 0)
         ret void
 
-; X32-Linux:       test_fastcc_large:
+; X32-Linux-LABEL:       test_fastcc_large:
 
 ; X32-Linux:       leal -40012(%esp), %eax
 ; X32-Linux-NEXT:  cmpl %gs:48, %eax
@@ -303,7 +303,7 @@ define fastcc void @test_fastcc_large() {
 ; X32-Linux-NEXT:  calll __morestack
 ; X32-Linux-NEXT:  ret
 
-; X64-Linux:       test_fastcc_large:
+; X64-Linux-LABEL:       test_fastcc_large:
 
 ; X64-Linux:       leaq -40008(%rsp), %r11
 ; X64-Linux-NEXT:  cmpq %fs:112, %r11
@@ -314,7 +314,7 @@ define fastcc void @test_fastcc_large() {
 ; X64-Linux-NEXT:  callq __morestack
 ; X64-Linux-NEXT:  ret
 
-; X32-Darwin:      test_fastcc_large:
+; X32-Darwin-LABEL:      test_fastcc_large:
 
 ; X32-Darwin:      leal -40012(%esp), %eax
 ; X32-Darwin-NEXT: movl $432, %ecx
@@ -326,7 +326,7 @@ define fastcc void @test_fastcc_large() {
 ; X32-Darwin-NEXT: calll ___morestack
 ; X32-Darwin-NEXT: ret
 
-; X64-Darwin:      test_fastcc_large:
+; X64-Darwin-LABEL:      test_fastcc_large:
 
 ; X64-Darwin:      leaq -40008(%rsp), %r11
 ; X64-Darwin-NEXT: cmpq %gs:816, %r11
@@ -337,7 +337,7 @@ define fastcc void @test_fastcc_large() {
 ; X64-Darwin-NEXT: callq ___morestack
 ; X64-Darwin-NEXT: ret
 
-; X32-MinGW:       test_fastcc_large:
+; X32-MinGW-LABEL:       test_fastcc_large:
 
 ; X32-MinGW:       leal -40008(%esp), %eax
 ; X32-MinGW-NEXT:  cmpl %fs:20, %eax
@@ -348,7 +348,7 @@ define fastcc void @test_fastcc_large() {
 ; X32-MinGW-NEXT:  calll ___morestack
 ; X32-MinGW-NEXT:  ret
 
-; X64-FreeBSD:       test_fastcc_large:
+; X64-FreeBSD-LABEL:       test_fastcc_large:
 
 ; X64-FreeBSD:       leaq -40008(%rsp), %r11
 ; X64-FreeBSD-NEXT:  cmpq %fs:24, %r11
@@ -368,7 +368,7 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) {
 
 ; This is testing that the Mac implementation preserves ecx
 
-; X32-Darwin:      test_fastcc_large_with_ecx_arg:
+; X32-Darwin-LABEL:      test_fastcc_large_with_ecx_arg:
 
 ; X32-Darwin:      leal -40012(%esp), %eax
 ; X32-Darwin-NEXT: pushl %ecx
diff --git a/test/CodeGen/X86/setcc.ll b/test/CodeGen/X86/setcc.ll
index c37e15d..2454af9 100644
--- a/test/CodeGen/X86/setcc.ll
+++ b/test/CodeGen/X86/setcc.ll
@@ -6,7 +6,7 @@
 
 define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: seta %al
 ; CHECK: movzbl %al, %eax
 ; CHECK: shll $5, %eax
@@ -17,7 +17,7 @@ entry:
 
 define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: sbbl %eax, %eax
 ; CHECK: andl $32, %eax
   %0 = icmp ult i16 %x, 26                        ; <i1> [#uses=1]
@@ -27,7 +27,7 @@ entry:
 
 define i64 @t3(i64 %x) nounwind readnone ssp {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: sbbq %rax, %rax
 ; CHECK: andq $64, %rax
   %0 = icmp ult i64 %x, 18                        ; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/sext-i1.ll b/test/CodeGen/X86/sext-i1.ll
index 574769b..64de0ae 100644
--- a/test/CodeGen/X86/sext-i1.ll
+++ b/test/CodeGen/X86/sext-i1.ll
@@ -5,11 +5,11 @@
 
 define i32 @t1(i32 %x) nounwind readnone ssp {
 entry:
-; 32: t1:
+; 32-LABEL: t1:
 ; 32: cmpl $1
 ; 32: sbbl
 
-; 64: t1:
+; 64-LABEL: t1:
 ; 64: cmpl $1
 ; 64: sbbl
   %0 = icmp eq i32 %x, 0
@@ -19,11 +19,11 @@ entry:
 
 define i32 @t2(i32 %x) nounwind readnone ssp {
 entry:
-; 32: t2:
+; 32-LABEL: t2:
 ; 32: cmpl $1
 ; 32: sbbl
 
-; 64: t2:
+; 64-LABEL: t2:
 ; 64: cmpl $1
 ; 64: sbbl
   %0 = icmp eq i32 %x, 0
@@ -36,13 +36,13 @@ entry:
 
 define i32 @t3() nounwind readonly {
 entry:
-; 32: t3:
+; 32-LABEL: t3:
 ; 32: cmpl $1
 ; 32: sbbl
 ; 32: cmpl
 ; 32: xorl
 
-; 64: t3:
+; 64-LABEL: t3:
 ; 64: cmpl $1
 ; 64: sbbq
 ; 64: cmpq
diff --git a/test/CodeGen/X86/sext-subreg.ll b/test/CodeGen/X86/sext-subreg.ll
index a128af9..e0c8ff9 100644
--- a/test/CodeGen/X86/sext-subreg.ll
+++ b/test/CodeGen/X86/sext-subreg.ll
@@ -2,7 +2,7 @@
 ; rdar://7529457
 
 define i64 @t(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movslq %e{{.*}}, %rax
 ; CHECK: movq %rax
 ; CHECK: movl %eax
diff --git a/test/CodeGen/X86/shift-and.ll b/test/CodeGen/X86/shift-and.ll
index 1de9151..d487368 100644
--- a/test/CodeGen/X86/shift-and.ll
+++ b/test/CodeGen/X86/shift-and.ll
@@ -2,11 +2,11 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s --check-prefix=X64
 
 define i32 @t1(i32 %t, i32 %val) nounwind {
-; X32: t1:
+; X32-LABEL: t1:
 ; X32-NOT: andl
 ; X32: shll
 
-; X64: t1:
+; X64-LABEL: t1:
 ; X64-NOT: andl
 ; X64: shll
        %shamt = and i32 %t, 31
@@ -15,11 +15,11 @@ define i32 @t1(i32 %t, i32 %val) nounwind {
 }
 
 define i32 @t2(i32 %t, i32 %val) nounwind {
-; X32: t2:
+; X32-LABEL: t2:
 ; X32-NOT: andl
 ; X32: shll
 
-; X64: t2:
+; X64-LABEL: t2:
 ; X64-NOT: andl
 ; X64: shll
        %shamt = and i32 %t, 63
@@ -30,11 +30,11 @@ define i32 @t2(i32 %t, i32 %val) nounwind {
 @X = internal global i16 0
 
 define void @t3(i16 %t) nounwind {
-; X32: t3:
+; X32-LABEL: t3:
 ; X32-NOT: andl
 ; X32: sarw
 
-; X64: t3:
+; X64-LABEL: t3:
 ; X64-NOT: andl
 ; X64: sarw
        %shamt = and i16 %t, 31
@@ -45,7 +45,7 @@ define void @t3(i16 %t) nounwind {
 }
 
 define i64 @t4(i64 %t, i64 %val) nounwind {
-; X64: t4:
+; X64-LABEL: t4:
 ; X64-NOT: and
 ; X64: shrq
        %shamt = and i64 %t, 63
@@ -54,7 +54,7 @@ define i64 @t4(i64 %t, i64 %val) nounwind {
 }
 
 define i64 @t5(i64 %t, i64 %val) nounwind {
-; X64: t5:
+; X64-LABEL: t5:
 ; X64-NOT: and
 ; X64: shrq
        %shamt = and i64 %t, 191
@@ -66,7 +66,7 @@ define i64 @t5(i64 %t, i64 %val) nounwind {
 ; rdar://11866926
 define i64 @t6(i64 %key, i64* nocapture %val) nounwind {
 entry:
-; X64: t6:
+; X64-LABEL: t6:
 ; X64-NOT: movabsq
 ; X64: decq
 ; X64: andq
diff --git a/test/CodeGen/X86/shift-codegen.ll b/test/CodeGen/X86/shift-codegen.ll
index 7d961e8..88b8610 100644
--- a/test/CodeGen/X86/shift-codegen.ll
+++ b/test/CodeGen/X86/shift-codegen.ll
@@ -8,7 +8,7 @@ target triple = "i686-apple-darwin8"
 
 
 define void @fn1() {
-; CHECK: fn1:
+; CHECK-LABEL: fn1:
 ; CHECK-NOT: ret
 ; CHECK-NOT: lea
 ; CHECK: shll $3
@@ -24,7 +24,7 @@ define void @fn1() {
 }
 
 define i32 @fn2(i32 %X, i32 %Y) {
-; CHECK: fn2:
+; CHECK-LABEL: fn2:
 ; CHECK-NOT: ret
 ; CHECK-NOT: lea
 ; CHECK: shll $3
diff --git a/test/CodeGen/X86/shl-anyext.ll b/test/CodeGen/X86/shl-anyext.ll
index 10d489b..0a5d047 100644
--- a/test/CodeGen/X86/shl-anyext.ll
+++ b/test/CodeGen/X86/shl-anyext.ll
@@ -17,7 +17,7 @@ if.end523:                                        ; preds = %if.end453
   ret void
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 
 declare void @bar(i64)
 
diff --git a/test/CodeGen/X86/shl_elim.ll b/test/CodeGen/X86/shl_elim.ll
index e99ecac..4762b13 100644
--- a/test/CodeGen/X86/shl_elim.ll
+++ b/test/CodeGen/X86/shl_elim.ll
@@ -8,7 +8,7 @@ define i32 @test1(i64 %a) nounwind {
         %tmp456 = sext i16 %tmp45 to i32                ; <i32> [#uses=1]
         ret i32 %tmp456
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: movl 8(%esp), %eax
 ; CHECK: shrl %eax
 ; CHECK: cwtl
diff --git a/test/CodeGen/X86/sibcall-2.ll b/test/CodeGen/X86/sibcall-2.ll
index f8a7465..1b9d2db 100644
--- a/test/CodeGen/X86/sibcall-2.ll
+++ b/test/CodeGen/X86/sibcall-2.ll
@@ -5,10 +5,10 @@
 
 define void @t1(i8* nocapture %value) nounwind {
 entry:
-; 32: t1:
+; 32-LABEL: t1:
 ; 32: jmpl *4(%esp)
 
-; 64: t1:
+; 64-LABEL: t1:
 ; 64: jmpq *%rdi
   %0 = bitcast i8* %value to void ()*
   tail call void %0() nounwind
@@ -17,10 +17,10 @@ entry:
 
 define void @t2(i32 %a, i8* nocapture %value) nounwind {
 entry:
-; 32: t2:
+; 32-LABEL: t2:
 ; 32: jmpl *8(%esp)
 
-; 64: t2:
+; 64-LABEL: t2:
 ; 64: jmpq *%rsi
   %0 = bitcast i8* %value to void ()*
   tail call void %0() nounwind
@@ -29,10 +29,10 @@ entry:
 
 define void @t3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i8* nocapture %value) nounwind {
 entry:
-; 32: t3:
+; 32-LABEL: t3:
 ; 32: jmpl *28(%esp)
 
-; 64: t3:
+; 64-LABEL: t3:
 ; 64: jmpq *8(%rsp)
   %0 = bitcast i8* %value to void ()*
   tail call void %0() nounwind
@@ -41,10 +41,10 @@ entry:
 
 define void @t4(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i8* nocapture %value) nounwind {
 entry:
-; 32: t4:
+; 32-LABEL: t4:
 ; 32: jmpl *32(%esp)
 
-; 64: t4:
+; 64-LABEL: t4:
 ; 64: jmpq *16(%rsp)
   %0 = bitcast i8* %value to void ()*
   tail call void %0() nounwind
diff --git a/test/CodeGen/X86/sibcall-3.ll b/test/CodeGen/X86/sibcall-3.ll
index f97abe0..9fcb460 100644
--- a/test/CodeGen/X86/sibcall-3.ll
+++ b/test/CodeGen/X86/sibcall-3.ll
@@ -2,14 +2,14 @@
 ; PR7193
 
 define void @t1(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: calll 0
   tail call void null(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind
   ret void
 }
 
 define void @t2(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: jmpl
   tail call void null(i8* inreg %dst, i8* inreg %src) nounwind
   ret void
diff --git a/test/CodeGen/X86/sibcall-4.ll b/test/CodeGen/X86/sibcall-4.ll
index 1499e66..980b0f7 100644
--- a/test/CodeGen/X86/sibcall-4.ll
+++ b/test/CodeGen/X86/sibcall-4.ll
@@ -3,7 +3,7 @@
 
 define cc10 void @t(i32* %Base_Arg, i32* %Sp_Arg, i32* %Hp_Arg, i32 %R1_Arg) nounwind {
 cm1:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: jmpl *%eax
   %nm3 = getelementptr i32* %Sp_Arg, i32 1
   %nm9 = load i32* %Sp_Arg
diff --git a/test/CodeGen/X86/sibcall-5.ll b/test/CodeGen/X86/sibcall-5.ll
index 937817e..c479030 100644
--- a/test/CodeGen/X86/sibcall-5.ll
+++ b/test/CodeGen/X86/sibcall-5.ll
@@ -7,20 +7,20 @@
 
 define double @foo(double %a) nounwind readonly ssp {
 entry:
-; X32: foo:
+; X32-LABEL: foo:
 ; X32: jmp _sin$stub
 
-; X64: foo:
+; X64-LABEL: foo:
 ; X64: jmp _sin
   %0 = tail call double @sin(double %a) nounwind readonly
   ret double %0
 }
 
 define float @bar(float %a) nounwind readonly ssp {
-; X32: bar:
+; X32-LABEL: bar:
 ; X32: jmp _sinf$stub
 
-; X64: bar:
+; X64-LABEL: bar:
 ; X64: jmp _sinf
 entry:
   %0 = tail call float @sinf(float %a) nounwind readonly
diff --git a/test/CodeGen/X86/sibcall.ll b/test/CodeGen/X86/sibcall.ll
index de98cb4..7b774f6 100644
--- a/test/CodeGen/X86/sibcall.ll
+++ b/test/CodeGen/X86/sibcall.ll
@@ -3,10 +3,10 @@
 
 define void @t1(i32 %x) nounwind ssp {
 entry:
-; 32: t1:
+; 32-LABEL: t1:
 ; 32: jmp {{_?}}foo
 
-; 64: t1:
+; 64-LABEL: t1:
 ; 64: jmp {{_?}}foo
   tail call void @foo() nounwind
   ret void
@@ -16,10 +16,10 @@ declare void @foo()
 
 define void @t2() nounwind ssp {
 entry:
-; 32: t2:
+; 32-LABEL: t2:
 ; 32: jmp {{_?}}foo2
 
-; 64: t2:
+; 64-LABEL: t2:
 ; 64: jmp {{_?}}foo2
   %0 = tail call i32 @foo2() nounwind
   ret void
@@ -29,10 +29,10 @@ declare i32 @foo2()
 
 define void @t3() nounwind ssp {
 entry:
-; 32: t3:
+; 32-LABEL: t3:
 ; 32: jmp {{_?}}foo3
 
-; 64: t3:
+; 64-LABEL: t3:
 ; 64: jmp {{_?}}foo3
   %0 = tail call i32 @foo3() nounwind
   ret void
@@ -42,11 +42,11 @@ declare i32 @foo3()
 
 define void @t4(void (i32)* nocapture %x) nounwind ssp {
 entry:
-; 32: t4:
+; 32-LABEL: t4:
 ; 32: calll *
 ; FIXME: gcc can generate a tailcall for this. But it's tricky.
 
-; 64: t4:
+; 64-LABEL: t4:
 ; 64-NOT: call
 ; 64: jmpq *
   tail call void %x(i32 0) nounwind
@@ -55,11 +55,11 @@ entry:
 
 define void @t5(void ()* nocapture %x) nounwind ssp {
 entry:
-; 32: t5:
+; 32-LABEL: t5:
 ; 32-NOT: call
 ; 32: jmpl *4(%esp)
 
-; 64: t5:
+; 64-LABEL: t5:
 ; 64-NOT: call
 ; 64: jmpq *%rdi
   tail call void %x() nounwind
@@ -68,11 +68,11 @@ entry:
 
 define i32 @t6(i32 %x) nounwind ssp {
 entry:
-; 32: t6:
+; 32-LABEL: t6:
 ; 32: calll {{_?}}t6
 ; 32: jmp {{_?}}bar
 
-; 64: t6:
+; 64-LABEL: t6:
 ; 64: jmp {{_?}}t6
 ; 64: jmp {{_?}}bar
   %0 = icmp slt i32 %x, 10
@@ -92,10 +92,10 @@ declare i32 @bar(i32)
 
 define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind ssp {
 entry:
-; 32: t7:
+; 32-LABEL: t7:
 ; 32: jmp {{_?}}bar2
 
-; 64: t7:
+; 64-LABEL: t7:
 ; 64: jmp {{_?}}bar2
   %0 = tail call i32 @bar2(i32 %a, i32 %b, i32 %c) nounwind
   ret i32 %0
@@ -105,10 +105,10 @@ declare i32 @bar2(i32, i32, i32)
 
 define signext i16 @t8() nounwind ssp {
 entry:
-; 32: t8:
+; 32-LABEL: t8:
 ; 32: calll {{_?}}bar3
 
-; 64: t8:
+; 64-LABEL: t8:
 ; 64: callq {{_?}}bar3
   %0 = tail call signext i16 @bar3() nounwind      ; <i16> [#uses=1]
   ret i16 %0
@@ -118,10 +118,10 @@ declare signext i16 @bar3()
 
 define signext i16 @t9(i32 (i32)* nocapture %x) nounwind ssp {
 entry:
-; 32: t9:
+; 32-LABEL: t9:
 ; 32: calll *
 
-; 64: t9:
+; 64-LABEL: t9:
 ; 64: callq *
   %0 = bitcast i32 (i32)* %x to i16 (i32)*
   %1 = tail call signext i16 %0(i32 0) nounwind
@@ -130,10 +130,10 @@ entry:
 
 define void @t10() nounwind ssp {
 entry:
-; 32: t10:
+; 32-LABEL: t10:
 ; 32: calll
 
-; 64: t10:
+; 64-LABEL: t10:
 ; 64: callq
   %0 = tail call i32 @foo4() noreturn nounwind
   unreachable
@@ -145,14 +145,14 @@ define i32 @t11(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind ssp {
 ; In 32-bit mode, it's emitting a bunch of dead loads that are not being
 ; eliminated currently.
 
-; 32: t11:
+; 32-LABEL: t11:
 ; 32-NOT: subl ${{[0-9]+}}, %esp
 ; 32: je
 ; 32-NOT: movl
 ; 32-NOT: addl ${{[0-9]+}}, %esp
 ; 32: jmp {{_?}}foo5
 
-; 64: t11:
+; 64-LABEL: t11:
 ; 64-NOT: subq ${{[0-9]+}}, %esp
 ; 64-NOT: addq ${{[0-9]+}}, %esp
 ; 64: jmp {{_?}}foo5
@@ -173,12 +173,12 @@ declare i32 @foo5(i32, i32, i32, i32, i32)
 %struct.t = type { i32, i32, i32, i32, i32 }
 
 define i32 @t12(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind ssp {
-; 32: t12:
+; 32-LABEL: t12:
 ; 32-NOT: subl ${{[0-9]+}}, %esp
 ; 32-NOT: addl ${{[0-9]+}}, %esp
 ; 32: jmp {{_?}}foo6
 
-; 64: t12:
+; 64-LABEL: t12:
 ; 64-NOT: subq ${{[0-9]+}}, %esp
 ; 64-NOT: addq ${{[0-9]+}}, %esp
 ; 64: jmp {{_?}}foo6
@@ -201,12 +201,12 @@ declare i32 @foo6(i32, i32, %struct.t* byval align 4)
 %struct.cp = type { float, float, float, float, float }
 
 define %struct.ns* @t13(%struct.cp* %yy) nounwind ssp {
-; 32: t13:
+; 32-LABEL: t13:
 ; 32-NOT: jmp
 ; 32: calll
 ; 32: ret
 
-; 64: t13:
+; 64-LABEL: t13:
 ; 64-NOT: jmp
 ; 64: callq
 ; 64: ret
@@ -226,7 +226,7 @@ declare fastcc %struct.ns* @foo7(%struct.cp* byval align 4, i8 signext) nounwind
 
 define void @t14(%struct.__block_literal_2* nocapture %.block_descriptor) nounwind ssp {
 entry:
-; 64: t14:
+; 64-LABEL: t14:
 ; 64: movq 32(%rdi)
 ; 64-NOT: movq 16(%rdi)
 ; 64: jmpq *16({{%rdi|%rax}})
@@ -245,11 +245,11 @@ entry:
 %struct.foo = type { [4 x i32] }
 
 define void @t15(%struct.foo* noalias sret %agg.result) nounwind  {
-; 32: t15:
+; 32-LABEL: t15:
 ; 32: calll {{_?}}f
 ; 32: ret $4
 
-; 64: t15:
+; 64-LABEL: t15:
 ; 64: callq {{_?}}f
 ; 64: ret
   tail call fastcc void @f(%struct.foo* noalias sret %agg.result) nounwind
@@ -260,11 +260,11 @@ declare void @f(%struct.foo* noalias sret) nounwind
 
 define void @t16() nounwind ssp {
 entry:
-; 32: t16:
+; 32-LABEL: t16:
 ; 32: calll {{_?}}bar4
 ; 32: fstp
 
-; 64: t16:
+; 64-LABEL: t16:
 ; 64: jmp {{_?}}bar4
   %0 = tail call double @bar4() nounwind
   ret void
@@ -275,10 +275,10 @@ declare double @bar4()
 ; rdar://6283267
 define void @t17() nounwind ssp {
 entry:
-; 32: t17:
+; 32-LABEL: t17:
 ; 32: jmp {{_?}}bar5
 
-; 64: t17:
+; 64-LABEL: t17:
 ; 64: xorl %eax, %eax
 ; 64: jmp {{_?}}bar5
   tail call void (...)* @bar5() nounwind
@@ -290,11 +290,11 @@ declare void @bar5(...)
 ; rdar://7774847
 define void @t18() nounwind ssp {
 entry:
-; 32: t18:
+; 32-LABEL: t18:
 ; 32: calll {{_?}}bar6
 ; 32: fstp %st(0)
 
-; 64: t18:
+; 64-LABEL: t18:
 ; 64: xorl %eax, %eax
 ; 64: jmp {{_?}}bar6
   %0 = tail call double (...)* @bar6() nounwind
@@ -305,7 +305,7 @@ declare double @bar6(...)
 
 define void @t19() alignstack(32) nounwind {
 entry:
-; CHECK: t19:
+; CHECK-LABEL: t19:
 ; CHECK: andl $-32
 ; CHECK: calll {{_?}}foo
   tail call void @foo() nounwind
@@ -318,11 +318,11 @@ entry:
 
 define double @t20(double %x) nounwind {
 entry:
-; 32: t20:
+; 32-LABEL: t20:
 ; 32: calll {{_?}}foo20
 ; 32: fldl (%esp)
 
-; 64: t20:
+; 64-LABEL: t20:
 ; 64: jmp {{_?}}foo20
   %0 = tail call fastcc double @foo20(double %x) nounwind
   ret double %0
diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll
index 2aca5b8..0741635 100644
--- a/test/CodeGen/X86/sink-hoist.ll
+++ b/test/CodeGen/X86/sink-hoist.ll
@@ -5,7 +5,7 @@
 ; evaluated, however with MachineSink we can sink the other side so
 ; that it's conditionally evaluated.
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NEXT: testb $1, %dil
 ; CHECK-NEXT: jne
 ; CHECK-NEXT: divsd
@@ -24,7 +24,7 @@ define double @foo(double %x, double %y, i1 %c) nounwind {
 ; the conditional branch.
 ; rdar://8454886
 
-; CHECK: split:
+; CHECK-LABEL: split:
 ; CHECK-NEXT: testb $1, %dil
 ; CHECK-NEXT: jne
 ; CHECK-NEXT: movaps
@@ -40,7 +40,7 @@ define double @split(double %x, double %y, i1 %c) nounwind {
 
 ; Hoist floating-point constant-pool loads out of loops.
 
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: movsd
 ; CHECK: align
 define void @bar(double* nocapture %p, i64 %n) nounwind {
@@ -87,7 +87,7 @@ return:
 
 ; Codegen should hoist and CSE these constants.
 
-; CHECK: vv:
+; CHECK-LABEL: vv:
 ; CHECK: LCPI3_0(%rip), %xmm0
 ; CHECK: LCPI3_1(%rip), %xmm1
 ; CHECK: LCPI3_2(%rip), %xmm2
@@ -151,7 +151,7 @@ declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
 ; CodeGen should use the correct register class when extracting
 ; a load from a zero-extending load for hoisting.
 
-; CHECK: default_get_pch_validity:
+; CHECK-LABEL: default_get_pch_validity:
 ; CHECK: movl cl_options_count(%rip), %ecx
 
 @cl_options_count = external constant i32         ; <i32*> [#uses=2]
diff --git a/test/CodeGen/X86/splat-scalar-load.ll b/test/CodeGen/X86/splat-scalar-load.ll
index 980f18c..4d59b9c 100644
--- a/test/CodeGen/X86/splat-scalar-load.ll
+++ b/test/CodeGen/X86/splat-scalar-load.ll
@@ -3,7 +3,7 @@
 
 define <2 x i64> @t2() nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: pshufd	$85, (%esp), %xmm0
   %array = alloca [8 x float], align 4
   %arrayidx = getelementptr inbounds [8 x float]* %array, i32 0, i32 1
diff --git a/test/CodeGen/X86/sse-align-12.ll b/test/CodeGen/X86/sse-align-12.ll
index 71a42f4..2351fd6 100644
--- a/test/CodeGen/X86/sse-align-12.ll
+++ b/test/CodeGen/X86/sse-align-12.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86-64 -mcpu=nehalem | FileCheck %s
 
-; CHECK: a:
+; CHECK-LABEL: a:
 ; CHECK: movdqu
 ; CHECK: pshufd
 define <4 x float> @a(<4 x float>* %y) nounwind {
@@ -16,7 +16,7 @@ define <4 x float> @a(<4 x float>* %y) nounwind {
   ret <4 x float> %s
 }
 
-; CHECK: b:
+; CHECK-LABEL: b:
 ; CHECK: movups
 ; CHECK: unpckhps
 define <4 x float> @b(<4 x float>* %y, <4 x float> %z) nounwind {
@@ -32,7 +32,7 @@ define <4 x float> @b(<4 x float>* %y, <4 x float> %z) nounwind {
   ret <4 x float> %s
 }
 
-; CHECK: c:
+; CHECK-LABEL: c:
 ; CHECK: movupd
 ; CHECK: shufpd
 define <2 x double> @c(<2 x double>* %y) nounwind {
@@ -44,7 +44,7 @@ define <2 x double> @c(<2 x double>* %y) nounwind {
   ret <2 x double> %r
 }
 
-; CHECK: d:
+; CHECK-LABEL: d:
 ; CHECK: movupd
 ; CHECK: unpckhpd
 define <2 x double> @d(<2 x double>* %y, <2 x double> %z) nounwind {
diff --git a/test/CodeGen/X86/sse-align-2.ll b/test/CodeGen/X86/sse-align-2.ll
index 22cd772..98e75b5 100644
--- a/test/CodeGen/X86/sse-align-2.ll
+++ b/test/CodeGen/X86/sse-align-2.ll
@@ -6,7 +6,7 @@ define <4 x float> @foo(<4 x float>* %p, <4 x float> %x) nounwind {
   ret <4 x float> %z
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: movups
 ; CHECK: ret
 
@@ -16,6 +16,6 @@ define <2 x double> @bar(<2 x double>* %p, <2 x double> %x) nounwind {
   ret <2 x double> %z
 }
 
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: movupd
 ; CHECK: ret
diff --git a/test/CodeGen/X86/sse-commute.ll b/test/CodeGen/X86/sse-commute.ll
index 336bf06..1800a6e 100644
--- a/test/CodeGen/X86/sse-commute.ll
+++ b/test/CodeGen/X86/sse-commute.ll
@@ -3,7 +3,7 @@
 ; Commute the comparison to avoid a move.
 ; PR7500.
 
-; CHECK: a:
+; CHECK-LABEL: a:
 ; CHECK-NOT: mov
 ; CHECK:     pcmpeqd
 define <2 x double> @a(<2 x double>, <2 x double>) nounwind readnone {
diff --git a/test/CodeGen/X86/sse-minmax.ll b/test/CodeGen/X86/sse-minmax.ll
index 0ba0215..7a2ea6b 100644
--- a/test/CodeGen/X86/sse-minmax.ll
+++ b/test/CodeGen/X86/sse-minmax.ll
@@ -12,13 +12,13 @@
 ;  _y: use -0.0 instead of %y
 ; _inverse : swap the arms of the select.
 
-; CHECK:      ogt:
+; CHECK-LABEL:      ogt:
 ; CHECK-NEXT: maxsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ogt:
+; UNSAFE-LABEL:      ogt:
 ; UNSAFE-NEXT: maxsd %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ogt:
+; FINITE-LABEL:      ogt:
 ; FINITE-NEXT: maxsd %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @ogt(double %x, double %y) nounwind {
@@ -27,13 +27,13 @@ define double @ogt(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      olt:
+; CHECK-LABEL:      olt:
 ; CHECK-NEXT: minsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      olt:
+; UNSAFE-LABEL:      olt:
 ; UNSAFE-NEXT: minsd %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      olt:
+; FINITE-LABEL:      olt:
 ; FINITE-NEXT: minsd %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @olt(double %x, double %y) nounwind {
@@ -42,14 +42,14 @@ define double @olt(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ogt_inverse:
+; CHECK-LABEL:      ogt_inverse:
 ; CHECK-NEXT: minsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ogt_inverse:
+; UNSAFE-LABEL:      ogt_inverse:
 ; UNSAFE-NEXT: minsd  %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ogt_inverse:
+; FINITE-LABEL:      ogt_inverse:
 ; FINITE-NEXT: minsd  %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -59,14 +59,14 @@ define double @ogt_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      olt_inverse:
+; CHECK-LABEL:      olt_inverse:
 ; CHECK-NEXT: maxsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      olt_inverse:
+; UNSAFE-LABEL:      olt_inverse:
 ; UNSAFE-NEXT: maxsd  %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      olt_inverse:
+; FINITE-LABEL:      olt_inverse:
 ; FINITE-NEXT: maxsd  %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -76,12 +76,12 @@ define double @olt_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      oge:
+; CHECK-LABEL:      oge:
 ; CHECK-NEXT: ucomisd %xmm1, %xmm0
-; UNSAFE:      oge:
+; UNSAFE-LABEL:      oge:
 ; UNSAFE-NEXT: maxsd	%xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      oge:
+; FINITE-LABEL:      oge:
 ; FINITE-NEXT: maxsd	%xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @oge(double %x, double %y) nounwind {
@@ -90,11 +90,11 @@ define double @oge(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ole:
+; CHECK-LABEL:      ole:
 ; CHECK-NEXT: ucomisd %xmm0, %xmm1
-; UNSAFE:      ole:
+; UNSAFE-LABEL:      ole:
 ; UNSAFE-NEXT: minsd %xmm1, %xmm0
-; FINITE:      ole:
+; FINITE-LABEL:      ole:
 ; FINITE-NEXT: minsd %xmm1, %xmm0
 define double @ole(double %x, double %y) nounwind {
   %c = fcmp ole double %x, %y
@@ -102,12 +102,12 @@ define double @ole(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      oge_inverse:
+; CHECK-LABEL:      oge_inverse:
 ; CHECK-NEXT: ucomisd %xmm1, %xmm0
-; UNSAFE:      oge_inverse:
+; UNSAFE-LABEL:      oge_inverse:
 ; UNSAFE-NEXT: minsd %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      oge_inverse:
+; FINITE-LABEL:      oge_inverse:
 ; FINITE-NEXT: minsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -117,12 +117,12 @@ define double @oge_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ole_inverse:
+; CHECK-LABEL:      ole_inverse:
 ; CHECK-NEXT: ucomisd %xmm0, %xmm1
-; UNSAFE:      ole_inverse:
+; UNSAFE-LABEL:      ole_inverse:
 ; UNSAFE-NEXT: maxsd %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ole_inverse:
+; FINITE-LABEL:      ole_inverse:
 ; FINITE-NEXT: maxsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -132,16 +132,16 @@ define double @ole_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ogt_x:
+; CHECK-LABEL:      ogt_x:
 ; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; CHECK-NEXT: maxsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ogt_x:
+; UNSAFE-LABEL:      ogt_x:
 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ogt_x:
+; FINITE-LABEL:      ogt_x:
 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; FINITE-NEXT: maxsd %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -151,16 +151,16 @@ define double @ogt_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      olt_x:
+; CHECK-LABEL:      olt_x:
 ; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; CHECK-NEXT: minsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      olt_x:
+; UNSAFE-LABEL:      olt_x:
 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      olt_x:
+; FINITE-LABEL:      olt_x:
 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; FINITE-NEXT: minsd %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -170,17 +170,17 @@ define double @olt_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ogt_inverse_x:
+; CHECK-LABEL:      ogt_inverse_x:
 ; CHECK-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; CHECK-NEXT: minsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ogt_inverse_x:
+; UNSAFE-LABEL:      ogt_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd  %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ogt_inverse_x:
+; FINITE-LABEL:      ogt_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; FINITE-NEXT: minsd  %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -191,17 +191,17 @@ define double @ogt_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      olt_inverse_x:
+; CHECK-LABEL:      olt_inverse_x:
 ; CHECK-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; CHECK-NEXT: maxsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      olt_inverse_x:
+; UNSAFE-LABEL:      olt_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd  %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      olt_inverse_x:
+; FINITE-LABEL:      olt_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; FINITE-NEXT: maxsd  %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -212,14 +212,14 @@ define double @olt_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      oge_x:
+; CHECK-LABEL:      oge_x:
 ; CHECK:      ucomisd %xmm1, %xmm0
-; UNSAFE:      oge_x:
+; UNSAFE-LABEL:      oge_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd   %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      oge_x:
+; FINITE-LABEL:      oge_x:
 ; FINITE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; FINITE-NEXT: maxsd   %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -229,14 +229,14 @@ define double @oge_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ole_x:
+; CHECK-LABEL:      ole_x:
 ; CHECK:      ucomisd %xmm0, %xmm1
-; UNSAFE:      ole_x:
+; UNSAFE-LABEL:      ole_x:
 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ole_x:
+; FINITE-LABEL:      ole_x:
 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; FINITE-NEXT: minsd %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -246,14 +246,14 @@ define double @ole_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      oge_inverse_x:
+; CHECK-LABEL:      oge_inverse_x:
 ; CHECK:      ucomisd %xmm
-; UNSAFE:      oge_inverse_x:
+; UNSAFE-LABEL:      oge_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd   %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      oge_inverse_x:
+; FINITE-LABEL:      oge_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; FINITE-NEXT: minsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -264,14 +264,14 @@ define double @oge_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ole_inverse_x:
+; CHECK-LABEL:      ole_inverse_x:
 ; CHECK:      ucomisd %xmm
-; UNSAFE:      ole_inverse_x:
+; UNSAFE-LABEL:      ole_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd   %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ole_inverse_x:
+; FINITE-LABEL:      ole_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; FINITE-NEXT: maxsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -282,12 +282,12 @@ define double @ole_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ugt:
+; CHECK-LABEL:      ugt:
 ; CHECK:      ucomisd %xmm0, %xmm1
-; UNSAFE:      ugt:
+; UNSAFE-LABEL:      ugt:
 ; UNSAFE-NEXT: maxsd   %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ugt:
+; FINITE-LABEL:      ugt:
 ; FINITE-NEXT: maxsd   %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @ugt(double %x, double %y) nounwind {
@@ -296,12 +296,12 @@ define double @ugt(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ult:
+; CHECK-LABEL:      ult:
 ; CHECK:      ucomisd %xmm1, %xmm0
-; UNSAFE:      ult:
+; UNSAFE-LABEL:      ult:
 ; UNSAFE-NEXT: minsd   %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ult:
+; FINITE-LABEL:      ult:
 ; FINITE-NEXT: minsd   %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @ult(double %x, double %y) nounwind {
@@ -310,12 +310,12 @@ define double @ult(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ugt_inverse:
+; CHECK-LABEL:      ugt_inverse:
 ; CHECK:      ucomisd %xmm0, %xmm1
-; UNSAFE:      ugt_inverse:
+; UNSAFE-LABEL:      ugt_inverse:
 ; UNSAFE-NEXT: minsd   %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ugt_inverse:
+; FINITE-LABEL:      ugt_inverse:
 ; FINITE-NEXT: minsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -325,12 +325,12 @@ define double @ugt_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ult_inverse:
+; CHECK-LABEL:      ult_inverse:
 ; CHECK:      ucomisd %xmm1, %xmm0
-; UNSAFE:      ult_inverse:
+; UNSAFE-LABEL:      ult_inverse:
 ; UNSAFE-NEXT: maxsd   %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ult_inverse:
+; FINITE-LABEL:      ult_inverse:
 ; FINITE-NEXT: maxsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -340,14 +340,14 @@ define double @ult_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      uge:
+; CHECK-LABEL:      uge:
 ; CHECK-NEXT: maxsd   %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      uge:
+; UNSAFE-LABEL:      uge:
 ; UNSAFE-NEXT: maxsd   %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      uge:
+; FINITE-LABEL:      uge:
 ; FINITE-NEXT: maxsd   %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @uge(double %x, double %y) nounwind {
@@ -356,14 +356,14 @@ define double @uge(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ule:
+; CHECK-LABEL:      ule:
 ; CHECK-NEXT: minsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ule:
+; UNSAFE-LABEL:      ule:
 ; UNSAFE-NEXT: minsd   %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ule:
+; FINITE-LABEL:      ule:
 ; FINITE-NEXT: minsd   %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @ule(double %x, double %y) nounwind {
@@ -372,13 +372,13 @@ define double @ule(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      uge_inverse:
+; CHECK-LABEL:      uge_inverse:
 ; CHECK-NEXT: minsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      uge_inverse:
+; UNSAFE-LABEL:      uge_inverse:
 ; UNSAFE-NEXT: minsd %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      uge_inverse:
+; FINITE-LABEL:      uge_inverse:
 ; FINITE-NEXT: minsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -388,13 +388,13 @@ define double @uge_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ule_inverse:
+; CHECK-LABEL:      ule_inverse:
 ; CHECK-NEXT: maxsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ule_inverse:
+; UNSAFE-LABEL:      ule_inverse:
 ; UNSAFE-NEXT: maxsd %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ule_inverse:
+; FINITE-LABEL:      ule_inverse:
 ; FINITE-NEXT: maxsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -404,14 +404,14 @@ define double @ule_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ugt_x:
+; CHECK-LABEL:      ugt_x:
 ; CHECK:      ucomisd %xmm0, %xmm1
-; UNSAFE:      ugt_x:
+; UNSAFE-LABEL:      ugt_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd   %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ugt_x:
+; FINITE-LABEL:      ugt_x:
 ; FINITE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; FINITE-NEXT: maxsd   %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -421,14 +421,14 @@ define double @ugt_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ult_x:
+; CHECK-LABEL:      ult_x:
 ; CHECK:      ucomisd %xmm1, %xmm0
-; UNSAFE:      ult_x:
+; UNSAFE-LABEL:      ult_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd   %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ult_x:
+; FINITE-LABEL:      ult_x:
 ; FINITE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; FINITE-NEXT: minsd   %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -438,14 +438,14 @@ define double @ult_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ugt_inverse_x:
+; CHECK-LABEL:      ugt_inverse_x:
 ; CHECK:      ucomisd %xmm
-; UNSAFE:      ugt_inverse_x:
+; UNSAFE-LABEL:      ugt_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd   %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ugt_inverse_x:
+; FINITE-LABEL:      ugt_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; FINITE-NEXT: minsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -456,14 +456,14 @@ define double @ugt_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ult_inverse_x:
+; CHECK-LABEL:      ult_inverse_x:
 ; CHECK:      ucomisd %xmm
-; UNSAFE:      ult_inverse_x:
+; UNSAFE-LABEL:      ult_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd   %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ult_inverse_x:
+; FINITE-LABEL:      ult_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; FINITE-NEXT: maxsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -474,17 +474,17 @@ define double @ult_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      uge_x:
+; CHECK-LABEL:      uge_x:
 ; CHECK-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; CHECK-NEXT: maxsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      uge_x:
+; UNSAFE-LABEL:      uge_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd  %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      uge_x:
+; FINITE-LABEL:      uge_x:
 ; FINITE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; FINITE-NEXT: maxsd  %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -494,17 +494,17 @@ define double @uge_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ule_x:
+; CHECK-LABEL:      ule_x:
 ; CHECK-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; CHECK-NEXT: minsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ule_x:
+; UNSAFE-LABEL:      ule_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd  %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ule_x:
+; FINITE-LABEL:      ule_x:
 ; FINITE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; FINITE-NEXT: minsd  %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -514,16 +514,16 @@ define double @ule_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      uge_inverse_x:
+; CHECK-LABEL:      uge_inverse_x:
 ; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; CHECK-NEXT: minsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      uge_inverse_x:
+; UNSAFE-LABEL:      uge_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      uge_inverse_x:
+; FINITE-LABEL:      uge_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; FINITE-NEXT: minsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -534,16 +534,16 @@ define double @uge_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ule_inverse_x:
+; CHECK-LABEL:      ule_inverse_x:
 ; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; CHECK-NEXT: maxsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ule_inverse_x:
+; UNSAFE-LABEL:      ule_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ule_inverse_x:
+; FINITE-LABEL:      ule_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; FINITE-NEXT: maxsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -554,13 +554,13 @@ define double @ule_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ogt_y:
+; CHECK-LABEL:      ogt_y:
 ; CHECK-NEXT: maxsd {{[^,]*}}, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ogt_y:
+; UNSAFE-LABEL:      ogt_y:
 ; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ogt_y:
+; FINITE-LABEL:      ogt_y:
 ; FINITE-NEXT: maxsd {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @ogt_y(double %x) nounwind {
@@ -569,13 +569,13 @@ define double @ogt_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      olt_y:
+; CHECK-LABEL:      olt_y:
 ; CHECK-NEXT: minsd {{[^,]*}}, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      olt_y:
+; UNSAFE-LABEL:      olt_y:
 ; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      olt_y:
+; FINITE-LABEL:      olt_y:
 ; FINITE-NEXT: minsd {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @olt_y(double %x) nounwind {
@@ -584,15 +584,15 @@ define double @olt_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ogt_inverse_y:
+; CHECK-LABEL:      ogt_inverse_y:
 ; CHECK-NEXT: movsd  {{[^,]*}}, %xmm1
 ; CHECK-NEXT: minsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ogt_inverse_y:
+; UNSAFE-LABEL:      ogt_inverse_y:
 ; UNSAFE-NEXT: minsd  {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ogt_inverse_y:
+; FINITE-LABEL:      ogt_inverse_y:
 ; FINITE-NEXT: movsd  {{[^,]*}}, %xmm1
 ; FINITE-NEXT: minsd  %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -603,15 +603,15 @@ define double @ogt_inverse_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      olt_inverse_y:
+; CHECK-LABEL:      olt_inverse_y:
 ; CHECK-NEXT: movsd  {{[^,]*}}, %xmm1
 ; CHECK-NEXT: maxsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      olt_inverse_y:
+; UNSAFE-LABEL:      olt_inverse_y:
 ; UNSAFE-NEXT: maxsd  {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      olt_inverse_y:
+; FINITE-LABEL:      olt_inverse_y:
 ; FINITE-NEXT: movsd  {{[^,]*}}, %xmm1
 ; FINITE-NEXT: maxsd  %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -622,12 +622,12 @@ define double @olt_inverse_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      oge_y:
+; CHECK-LABEL:      oge_y:
 ; CHECK:      ucomisd %xmm1, %xmm0
-; UNSAFE:      oge_y:
+; UNSAFE-LABEL:      oge_y:
 ; UNSAFE-NEXT: maxsd   {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      oge_y:
+; FINITE-LABEL:      oge_y:
 ; FINITE-NEXT: maxsd   {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @oge_y(double %x) nounwind {
@@ -636,12 +636,12 @@ define double @oge_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ole_y:
+; CHECK-LABEL:      ole_y:
 ; CHECK:      ucomisd %xmm0, %xmm1
-; UNSAFE:      ole_y:
+; UNSAFE-LABEL:      ole_y:
 ; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ole_y:
+; FINITE-LABEL:      ole_y:
 ; FINITE-NEXT: minsd {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @ole_y(double %x) nounwind {
@@ -650,12 +650,12 @@ define double @ole_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      oge_inverse_y:
+; CHECK-LABEL:      oge_inverse_y:
 ; CHECK:      ucomisd %xmm
-; UNSAFE:      oge_inverse_y:
+; UNSAFE-LABEL:      oge_inverse_y:
 ; UNSAFE-NEXT: minsd   {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      oge_inverse_y:
+; FINITE-LABEL:      oge_inverse_y:
 ; FINITE-NEXT: movsd   {{[^,]*}}, %xmm1
 ; FINITE-NEXT: minsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -666,12 +666,12 @@ define double @oge_inverse_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ole_inverse_y:
+; CHECK-LABEL:      ole_inverse_y:
 ; CHECK:      ucomisd %xmm
-; UNSAFE:      ole_inverse_y:
+; UNSAFE-LABEL:      ole_inverse_y:
 ; UNSAFE-NEXT: maxsd   {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ole_inverse_y:
+; FINITE-LABEL:      ole_inverse_y:
 ; FINITE-NEXT: movsd   {{[^,]*}}, %xmm1
 ; FINITE-NEXT: maxsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -682,12 +682,12 @@ define double @ole_inverse_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ugt_y:
+; CHECK-LABEL:      ugt_y:
 ; CHECK:      ucomisd %xmm0, %xmm1
-; UNSAFE:      ugt_y:
+; UNSAFE-LABEL:      ugt_y:
 ; UNSAFE-NEXT: maxsd   {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ugt_y:
+; FINITE-LABEL:      ugt_y:
 ; FINITE-NEXT: maxsd   {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @ugt_y(double %x) nounwind {
@@ -696,12 +696,12 @@ define double @ugt_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ult_y:
+; CHECK-LABEL:      ult_y:
 ; CHECK:      ucomisd %xmm1, %xmm0
-; UNSAFE:      ult_y:
+; UNSAFE-LABEL:      ult_y:
 ; UNSAFE-NEXT: minsd   {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ult_y:
+; FINITE-LABEL:      ult_y:
 ; FINITE-NEXT: minsd   {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @ult_y(double %x) nounwind {
@@ -710,12 +710,12 @@ define double @ult_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ugt_inverse_y:
+; CHECK-LABEL:      ugt_inverse_y:
 ; CHECK:      ucomisd %xmm
-; UNSAFE:      ugt_inverse_y:
+; UNSAFE-LABEL:      ugt_inverse_y:
 ; UNSAFE-NEXT: minsd   {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ugt_inverse_y:
+; FINITE-LABEL:      ugt_inverse_y:
 ; FINITE-NEXT: movsd   {{[^,]*}}, %xmm1
 ; FINITE-NEXT: minsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -726,12 +726,12 @@ define double @ugt_inverse_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ult_inverse_y:
+; CHECK-LABEL:      ult_inverse_y:
 ; CHECK:      ucomisd %xmm
-; UNSAFE:      ult_inverse_y:
+; UNSAFE-LABEL:      ult_inverse_y:
 ; UNSAFE-NEXT: maxsd   {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ult_inverse_y:
+; FINITE-LABEL:      ult_inverse_y:
 ; FINITE-NEXT: movsd   {{[^,]*}}, %xmm1
 ; FINITE-NEXT: maxsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -742,15 +742,15 @@ define double @ult_inverse_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      uge_y:
+; CHECK-LABEL:      uge_y:
 ; CHECK-NEXT: movsd  {{[^,]*}}, %xmm1
 ; CHECK-NEXT: maxsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      uge_y:
+; UNSAFE-LABEL:      uge_y:
 ; UNSAFE-NEXT: maxsd  {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      uge_y:
+; FINITE-LABEL:      uge_y:
 ; FINITE-NEXT: maxsd  {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @uge_y(double %x) nounwind {
@@ -759,15 +759,15 @@ define double @uge_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ule_y:
+; CHECK-LABEL:      ule_y:
 ; CHECK-NEXT: movsd  {{[^,]*}}, %xmm1
 ; CHECK-NEXT: minsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ule_y:
+; UNSAFE-LABEL:      ule_y:
 ; UNSAFE-NEXT: minsd  {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ule_y:
+; FINITE-LABEL:      ule_y:
 ; FINITE-NEXT: minsd  {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @ule_y(double %x) nounwind {
@@ -776,13 +776,13 @@ define double @ule_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      uge_inverse_y:
+; CHECK-LABEL:      uge_inverse_y:
 ; CHECK-NEXT: minsd {{[^,]*}}, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      uge_inverse_y:
+; UNSAFE-LABEL:      uge_inverse_y:
 ; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      uge_inverse_y:
+; FINITE-LABEL:      uge_inverse_y:
 ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
 ; FINITE-NEXT: minsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -793,13 +793,13 @@ define double @uge_inverse_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ule_inverse_y:
+; CHECK-LABEL:      ule_inverse_y:
 ; CHECK-NEXT: maxsd {{[^,]*}}, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ule_inverse_y:
+; UNSAFE-LABEL:      ule_inverse_y:
 ; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ule_inverse_y:
+; FINITE-LABEL:      ule_inverse_y:
 ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
 ; FINITE-NEXT: maxsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -811,11 +811,11 @@ define double @ule_inverse_y(double %x) nounwind {
 }
 ; Test a few more misc. cases.
 
-; CHECK: clampTo3k_a:
+; CHECK-LABEL: clampTo3k_a:
 ; CHECK: minsd
-; UNSAFE: clampTo3k_a:
+; UNSAFE-LABEL: clampTo3k_a:
 ; UNSAFE: minsd
-; FINITE: clampTo3k_a:
+; FINITE-LABEL: clampTo3k_a:
 ; FINITE: minsd
 define double @clampTo3k_a(double %x) nounwind readnone {
 entry:
@@ -824,11 +824,11 @@ entry:
   ret double %x_addr.0
 }
 
-; CHECK: clampTo3k_b:
+; CHECK-LABEL: clampTo3k_b:
 ; CHECK: minsd
-; UNSAFE: clampTo3k_b:
+; UNSAFE-LABEL: clampTo3k_b:
 ; UNSAFE: minsd
-; FINITE: clampTo3k_b:
+; FINITE-LABEL: clampTo3k_b:
 ; FINITE: minsd
 define double @clampTo3k_b(double %x) nounwind readnone {
 entry:
@@ -837,11 +837,11 @@ entry:
   ret double %x_addr.0
 }
 
-; CHECK: clampTo3k_c:
+; CHECK-LABEL: clampTo3k_c:
 ; CHECK: maxsd
-; UNSAFE: clampTo3k_c:
+; UNSAFE-LABEL: clampTo3k_c:
 ; UNSAFE: maxsd
-; FINITE: clampTo3k_c:
+; FINITE-LABEL: clampTo3k_c:
 ; FINITE: maxsd
 define double @clampTo3k_c(double %x) nounwind readnone {
 entry:
@@ -850,11 +850,11 @@ entry:
   ret double %x_addr.0
 }
 
-; CHECK: clampTo3k_d:
+; CHECK-LABEL: clampTo3k_d:
 ; CHECK: maxsd
-; UNSAFE: clampTo3k_d:
+; UNSAFE-LABEL: clampTo3k_d:
 ; UNSAFE: maxsd
-; FINITE: clampTo3k_d:
+; FINITE-LABEL: clampTo3k_d:
 ; FINITE: maxsd
 define double @clampTo3k_d(double %x) nounwind readnone {
 entry:
@@ -863,11 +863,11 @@ entry:
   ret double %x_addr.0
 }
 
-; CHECK: clampTo3k_e:
+; CHECK-LABEL: clampTo3k_e:
 ; CHECK: maxsd
-; UNSAFE: clampTo3k_e:
+; UNSAFE-LABEL: clampTo3k_e:
 ; UNSAFE: maxsd
-; FINITE: clampTo3k_e:
+; FINITE-LABEL: clampTo3k_e:
 ; FINITE: maxsd
 define double @clampTo3k_e(double %x) nounwind readnone {
 entry:
@@ -876,11 +876,11 @@ entry:
   ret double %x_addr.0
 }
 
-; CHECK: clampTo3k_f:
+; CHECK-LABEL: clampTo3k_f:
 ; CHECK: maxsd
-; UNSAFE: clampTo3k_f:
+; UNSAFE-LABEL: clampTo3k_f:
 ; UNSAFE: maxsd
-; FINITE: clampTo3k_f:
+; FINITE-LABEL: clampTo3k_f:
 ; FINITE: maxsd
 define double @clampTo3k_f(double %x) nounwind readnone {
 entry:
@@ -889,11 +889,11 @@ entry:
   ret double %x_addr.0
 }
 
-; CHECK: clampTo3k_g:
+; CHECK-LABEL: clampTo3k_g:
 ; CHECK: minsd
-; UNSAFE: clampTo3k_g:
+; UNSAFE-LABEL: clampTo3k_g:
 ; UNSAFE: minsd
-; FINITE: clampTo3k_g:
+; FINITE-LABEL: clampTo3k_g:
 ; FINITE: minsd
 define double @clampTo3k_g(double %x) nounwind readnone {
 entry:
@@ -902,11 +902,11 @@ entry:
   ret double %x_addr.0
 }
 
-; CHECK: clampTo3k_h:
+; CHECK-LABEL: clampTo3k_h:
 ; CHECK: minsd
-; UNSAFE: clampTo3k_h:
+; UNSAFE-LABEL: clampTo3k_h:
 ; UNSAFE: minsd
-; FINITE: clampTo3k_h:
+; FINITE-LABEL: clampTo3k_h:
 ; FINITE: minsd
 define double @clampTo3k_h(double %x) nounwind readnone {
 entry:
@@ -915,7 +915,7 @@ entry:
   ret double %x_addr.0
 }
 
-; UNSAFE: maxpd:
+; UNSAFE-LABEL: maxpd:
 ; UNSAFE: maxpd
 define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) {
   %max_is_x = fcmp oge <2 x double> %x, %y
@@ -923,7 +923,7 @@ define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %max
 }
 
-; UNSAFE: minpd:
+; UNSAFE-LABEL: minpd:
 ; UNSAFE: minpd
 define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) {
   %min_is_x = fcmp ole <2 x double> %x, %y
@@ -931,7 +931,7 @@ define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %min
 }
 
-; UNSAFE: maxps:
+; UNSAFE-LABEL: maxps:
 ; UNSAFE: maxps
 define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) {
   %max_is_x = fcmp oge <4 x float> %x, %y
@@ -939,7 +939,7 @@ define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) {
   ret <4 x float> %max
 }
 
-; UNSAFE: minps:
+; UNSAFE-LABEL: minps:
 ; UNSAFE: minps
 define <4 x float> @minps(<4 x float> %x, <4 x float> %y) {
   %min_is_x = fcmp ole <4 x float> %x, %y
diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll
index 48638b3..4c95c9f 100644
--- a/test/CodeGen/X86/sse3.ll
+++ b/test/CodeGen/X86/sse3.ll
@@ -15,7 +15,7 @@ entry:
 	store <8 x i16> %tmp6, <8 x i16>* %dest
 	ret void
         
-; X64: t0:
+; X64-LABEL: t0:
 ; X64:	movdqa	(%rsi), %xmm0
 ; X64:	pslldq	$2, %xmm0
 ; X64:	movdqa	%xmm0, (%rdi)
@@ -28,7 +28,7 @@ define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 	%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
 	ret <8 x i16> %tmp3
         
-; X64: t1:
+; X64-LABEL: t1:
 ; X64: 	movdqa	(%rdi), %xmm0
 ; X64: 	pinsrw	$0, (%rsi), %xmm0
 ; X64: 	ret
@@ -37,7 +37,7 @@ define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) nounwind {
 	%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 9, i32 1, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7 >
 	ret <8 x i16> %tmp
-; X64: t2:
+; X64-LABEL: t2:
 ; X64:	pextrw	$1, %xmm1, %eax
 ; X64:	pinsrw	$0, %eax, %xmm0
 ; X64:	pinsrw	$3, %eax, %xmm0
@@ -47,7 +47,7 @@ define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) nounwind {
 define <8 x i16> @t3(<8 x i16> %A, <8 x i16> %B) nounwind {
 	%tmp = shufflevector <8 x i16> %A, <8 x i16> %A, <8 x i32> < i32 8, i32 3, i32 2, i32 13, i32 7, i32 6, i32 5, i32 4 >
 	ret <8 x i16> %tmp
-; X64: t3:
+; X64-LABEL: t3:
 ; X64: 	pextrw	$5, %xmm0, %eax
 ; X64: 	pshuflw	$44, %xmm0, %xmm0
 ; X64: 	pshufhw	$27, %xmm0, %xmm0
@@ -58,7 +58,7 @@ define <8 x i16> @t3(<8 x i16> %A, <8 x i16> %B) nounwind {
 define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind {
 	%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 7, i32 2, i32 3, i32 1, i32 5, i32 6, i32 5 >
 	ret <8 x i16> %tmp
-; X64: t4:
+; X64-LABEL: t4:
 ; X64: 	pextrw	$7, [[XMM0:%xmm[0-9]+]], %eax
 ; X64: 	pshufhw	$100, [[XMM0]], [[XMM1:%xmm[0-9]+]]
 ; X64: 	pinsrw	$1, %eax, [[XMM1]]
@@ -179,7 +179,7 @@ entry:
 	%tmp7 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 1, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
 	ret <8 x i16> %tmp7
 
-; X64: t11:
+; X64-LABEL: t11:
 ; X64:	movd	%xmm1, %eax
 ; X64:	movlhps	%xmm0, %xmm0
 ; X64:	pshuflw	$1, %xmm0, %xmm0
@@ -193,7 +193,7 @@ entry:
 	%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 0, i32 1, i32 undef, i32 undef, i32 3, i32 11, i32 undef , i32 undef >
 	ret <8 x i16> %tmp9
 
-; X64: t12:
+; X64-LABEL: t12:
 ; X64: 	pextrw	$3, %xmm1, %eax
 ; X64: 	movlhps	%xmm0, %xmm0
 ; X64: 	pshufhw	$3, %xmm0, %xmm0
@@ -206,7 +206,7 @@ define <8 x i16> @t13(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 entry:
 	%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 11, i32 3, i32 undef , i32 undef >
 	ret <8 x i16> %tmp9
-; X64: t13:
+; X64-LABEL: t13:
 ; X64: 	punpcklqdq	%xmm0, %xmm1
 ; X64: 	pextrw	$3, %xmm1, %eax
 ; X64: 	pshufd	$52, %xmm1, %xmm0
@@ -219,7 +219,7 @@ define <8 x i16> @t14(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 entry:
 	%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 2, i32 undef , i32 undef >
 	ret <8 x i16> %tmp9
-; X64: t14:
+; X64-LABEL: t14:
 ; X64: 	punpcklqdq	%xmm0, %xmm1
 ; X64: 	pshufhw	$8, %xmm1, %xmm0
 ; X64: 	ret
@@ -259,7 +259,7 @@ entry:
 ; rdar://8520311
 define <4 x i32> @t17() nounwind {
 entry:
-; X64: t17:
+; X64-LABEL: t17:
 ; X64:          movddup (%rax), %xmm0
   %tmp1 = load <4 x float>* undef, align 16
   %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
diff --git a/test/CodeGen/X86/sse41.ll b/test/CodeGen/X86/sse41.ll
index c6f9f0c..87b64e5 100644
--- a/test/CodeGen/X86/sse41.ll
+++ b/test/CodeGen/X86/sse41.ll
@@ -6,20 +6,20 @@
 define <4 x i32> @pinsrd_1(i32 %s, <4 x i32> %tmp) nounwind {
         %tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 1
         ret <4 x i32> %tmp1
-; X32: pinsrd_1:
+; X32-LABEL: pinsrd_1:
 ; X32:    pinsrd $1, 4(%esp), %xmm0
 
-; X64: pinsrd_1:
+; X64-LABEL: pinsrd_1:
 ; X64:    pinsrd $1, %edi, %xmm0
 }
 
 define <16 x i8> @pinsrb_1(i8 %s, <16 x i8> %tmp) nounwind {
         %tmp1 = insertelement <16 x i8> %tmp, i8 %s, i32 1
         ret <16 x i8> %tmp1
-; X32: pinsrb_1:
+; X32-LABEL: pinsrb_1:
 ; X32:    pinsrb $1, 4(%esp), %xmm0
 
-; X64: pinsrb_1:
+; X64-LABEL: pinsrb_1:
 ; X64:    pinsrb $1, %edi, %xmm0
 }
 
@@ -237,12 +237,12 @@ entry:
   %tmp11 = insertelement <2 x float> undef, float %add.r, i32 0
   %tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1
   ret <2 x float> %tmp9
-; X32: buildvector:
+; X32-LABEL: buildvector:
 ; X32-NOT: insertps $0
 ; X32: insertps $16
 ; X32-NOT: insertps $0
 ; X32: ret
-; X64: buildvector:
+; X64-LABEL: buildvector:
 ; X64-NOT: insertps $0
 ; X64: insertps $16
 ; X64-NOT: insertps $0
diff --git a/test/CodeGen/X86/sse_partial_update.ll b/test/CodeGen/X86/sse_partial_update.ll
index 655f758..2c16a55 100644
--- a/test/CodeGen/X86/sse_partial_update.ll
+++ b/test/CodeGen/X86/sse_partial_update.ll
@@ -8,7 +8,7 @@
 ; destination of rsqrtss are the same.
 define void @t1(<4 x float> %a) nounwind uwtable ssp {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: rsqrtss %xmm0, %xmm0
   %0 = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %a) nounwind
   %a.addr.0.extract = extractelement <4 x float> %0, i32 0
@@ -23,7 +23,7 @@ declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
 
 define void @t2(<4 x float> %a) nounwind uwtable ssp {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: rcpss %xmm0, %xmm0
   %0 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %a) nounwind
   %a.addr.0.extract = extractelement <4 x float> %0, i32 0
diff --git a/test/CodeGen/X86/stack-protector.ll b/test/CodeGen/X86/stack-protector.ll
index 6191ce6..a4dbbb9 100644
--- a/test/CodeGen/X86/stack-protector.ll
+++ b/test/CodeGen/X86/stack-protector.ll
@@ -24,19 +24,19 @@
 ; Requires no protector.
 define void @test1a(i8* %a) nounwind uwtable {
 entry:
-; LINUX-I386: test1a:
+; LINUX-I386-LABEL: test1a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test1a:
+; LINUX-X64-LABEL: test1a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test1a:
+; LINUX-KERNEL-X64-LABEL: test1a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test1a:
+; DARWIN-X64-LABEL: test1a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -55,23 +55,23 @@ entry:
 ; Requires protector.
 define void @test1b(i8* %a) nounwind uwtable ssp {
 entry:
-; LINUX-I386: test1b:
+; LINUX-I386-LABEL: test1b:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test1b:
+; LINUX-X64-LABEL: test1b:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test1b:
+; LINUX-KERNEL-X64-LABEL: test1b:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test1b:
+; DARWIN-X64-LABEL: test1b:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
 
-; OPENBSD-AMD64: test1b:
+; OPENBSD-AMD64-LABEL: test1b:
 ; OPENBSD-AMD64: movq __guard_local(%rip)
 ; OPENBSD-AMD64: callq __stack_smash_handler
   %a.addr = alloca i8*, align 8
@@ -90,19 +90,19 @@ entry:
 ; Requires protector.
 define void @test1c(i8* %a) nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test1c:
+; LINUX-I386-LABEL: test1c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test1c:
+; LINUX-X64-LABEL: test1c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test1c:
+; LINUX-KERNEL-X64-LABEL: test1c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test1c:
+; DARWIN-X64-LABEL: test1c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -121,19 +121,19 @@ entry:
 ; Requires protector.
 define void @test1d(i8* %a) nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test1d:
+; LINUX-I386-LABEL: test1d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test1d:
+; LINUX-X64-LABEL: test1d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test1d:
+; LINUX-KERNEL-X64-LABEL: test1d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test1d:
+; DARWIN-X64-LABEL: test1d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -152,19 +152,19 @@ entry:
 ; Requires no protector.
 define void @test2a(i8* %a) nounwind uwtable {
 entry:
-; LINUX-I386: test2a:
+; LINUX-I386-LABEL: test2a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test2a:
+; LINUX-X64-LABEL: test2a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test2a:
+; LINUX-KERNEL-X64-LABEL: test2a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test2a:
+; DARWIN-X64-LABEL: test2a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -185,19 +185,19 @@ entry:
 ; Requires protector.
 define void @test2b(i8* %a) nounwind uwtable ssp {
 entry:
-; LINUX-I386: test2b:
+; LINUX-I386-LABEL: test2b:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test2b:
+; LINUX-X64-LABEL: test2b:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test2b:
+; LINUX-KERNEL-X64-LABEL: test2b:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test2b:
+; DARWIN-X64-LABEL: test2b:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -218,19 +218,19 @@ entry:
 ; Requires protector.
 define void @test2c(i8* %a) nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test2c:
+; LINUX-I386-LABEL: test2c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test2c:
+; LINUX-X64-LABEL: test2c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test2c:
+; LINUX-KERNEL-X64-LABEL: test2c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test2c:
+; DARWIN-X64-LABEL: test2c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -251,19 +251,19 @@ entry:
 ; Requires protector.
 define void @test2d(i8* %a) nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test2d:
+; LINUX-I386-LABEL: test2d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test2d:
+; LINUX-X64-LABEL: test2d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test2d:
+; LINUX-KERNEL-X64-LABEL: test2d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test2d:
+; DARWIN-X64-LABEL: test2d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -284,19 +284,19 @@ entry:
 ; Requires no protector.
 define void @test3a(i8* %a) nounwind uwtable {
 entry:
-; LINUX-I386: test3a:
+; LINUX-I386-LABEL: test3a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test3a:
+; LINUX-X64-LABEL: test3a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test3a:
+; LINUX-KERNEL-X64-LABEL: test3a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test3a:
+; DARWIN-X64-LABEL: test3a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -315,19 +315,19 @@ entry:
 ; Requires no protector.
 define void @test3b(i8* %a) nounwind uwtable ssp {
 entry:
-; LINUX-I386: test3b:
+; LINUX-I386-LABEL: test3b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test3b:
+; LINUX-X64-LABEL: test3b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test3b:
+; LINUX-KERNEL-X64-LABEL: test3b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test3b:
+; DARWIN-X64-LABEL: test3b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -346,19 +346,19 @@ entry:
 ; Requires protector.
 define void @test3c(i8* %a) nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test3c:
+; LINUX-I386-LABEL: test3c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test3c:
+; LINUX-X64-LABEL: test3c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test3c:
+; LINUX-KERNEL-X64-LABEL: test3c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test3c:
+; DARWIN-X64-LABEL: test3c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -377,19 +377,19 @@ entry:
 ; Requires protector.
 define void @test3d(i8* %a) nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test3d:
+; LINUX-I386-LABEL: test3d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test3d:
+; LINUX-X64-LABEL: test3d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test3d:
+; LINUX-KERNEL-X64-LABEL: test3d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test3d:
+; DARWIN-X64-LABEL: test3d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -408,19 +408,19 @@ entry:
 ; Requires no protector.
 define void @test4a(i8* %a) nounwind uwtable {
 entry:
-; LINUX-I386: test4a:
+; LINUX-I386-LABEL: test4a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test4a:
+; LINUX-X64-LABEL: test4a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test4a:
+; LINUX-KERNEL-X64-LABEL: test4a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test4a:
+; DARWIN-X64-LABEL: test4a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -441,19 +441,19 @@ entry:
 ; Requires no protector.
 define void @test4b(i8* %a) nounwind uwtable ssp {
 entry:
-; LINUX-I386: test4b:
+; LINUX-I386-LABEL: test4b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test4b:
+; LINUX-X64-LABEL: test4b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test4b:
+; LINUX-KERNEL-X64-LABEL: test4b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test4b:
+; DARWIN-X64-LABEL: test4b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -474,19 +474,19 @@ entry:
 ; Requires protector.
 define void @test4c(i8* %a) nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test4c:
+; LINUX-I386-LABEL: test4c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test4c:
+; LINUX-X64-LABEL: test4c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test4c:
+; LINUX-KERNEL-X64-LABEL: test4c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test4c:
+; DARWIN-X64-LABEL: test4c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -507,19 +507,19 @@ entry:
 ; Requires protector.
 define void @test4d(i8* %a) nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test4d:
+; LINUX-I386-LABEL: test4d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test4d:
+; LINUX-X64-LABEL: test4d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test4d:
+; LINUX-KERNEL-X64-LABEL: test4d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test4d:
+; DARWIN-X64-LABEL: test4d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -540,19 +540,19 @@ entry:
 ; Requires no protector.
 define void @test5a(i8* %a) nounwind uwtable {
 entry:
-; LINUX-I386: test5a:
+; LINUX-I386-LABEL: test5a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test5a:
+; LINUX-X64-LABEL: test5a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test5a:
+; LINUX-KERNEL-X64-LABEL: test5a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test5a:
+; DARWIN-X64-LABEL: test5a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -567,19 +567,19 @@ entry:
 ; Requires no protector.
 define void @test5b(i8* %a) nounwind uwtable ssp {
 entry:
-; LINUX-I386: test5b:
+; LINUX-I386-LABEL: test5b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test5b:
+; LINUX-X64-LABEL: test5b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test5b:
+; LINUX-KERNEL-X64-LABEL: test5b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test5b:
+; DARWIN-X64-LABEL: test5b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -594,19 +594,19 @@ entry:
 ; Requires no protector.
 define void @test5c(i8* %a) nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test5c:
+; LINUX-I386-LABEL: test5c:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test5c:
+; LINUX-X64-LABEL: test5c:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test5c:
+; LINUX-KERNEL-X64-LABEL: test5c:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test5c:
+; DARWIN-X64-LABEL: test5c:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -621,19 +621,19 @@ entry:
 ; Requires protector.
 define void @test5d(i8* %a) nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test5d:
+; LINUX-I386-LABEL: test5d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test5d:
+; LINUX-X64-LABEL: test5d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test5d:
+; LINUX-KERNEL-X64-LABEL: test5d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test5d:
+; DARWIN-X64-LABEL: test5d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -648,19 +648,19 @@ entry:
 ; Requires no protector.
 define void @test6a() nounwind uwtable {
 entry:
-; LINUX-I386: test6a:
+; LINUX-I386-LABEL: test6a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test6a:
+; LINUX-X64-LABEL: test6a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test6a:
+; LINUX-KERNEL-X64-LABEL: test6a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test6a:
+; DARWIN-X64-LABEL: test6a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %retval = alloca i32, align 4
@@ -679,19 +679,19 @@ entry:
 ; Requires no protector.
 define void @test6b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test6b:
+; LINUX-I386-LABEL: test6b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test6b:
+; LINUX-X64-LABEL: test6b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test6b:
+; LINUX-KERNEL-X64-LABEL: test6b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test6b:
+; DARWIN-X64-LABEL: test6b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %retval = alloca i32, align 4
@@ -710,19 +710,19 @@ entry:
 ; Requires protector.
 define void @test6c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test6c:
+; LINUX-I386-LABEL: test6c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test6c:
+; LINUX-X64-LABEL: test6c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test6c:
+; LINUX-KERNEL-X64-LABEL: test6c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test6c:
+; DARWIN-X64-LABEL: test6c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %retval = alloca i32, align 4
@@ -741,19 +741,19 @@ entry:
 ; Requires protector.
 define void @test6d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test6d:
+; LINUX-I386-LABEL: test6d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test6d:
+; LINUX-X64-LABEL: test6d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test6d:
+; LINUX-KERNEL-X64-LABEL: test6d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test6d:
+; DARWIN-X64-LABEL: test6d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %retval = alloca i32, align 4
@@ -772,19 +772,19 @@ entry:
 ; Requires no protector.
 define void @test7a() nounwind uwtable readnone {
 entry:
-; LINUX-I386: test7a:
+; LINUX-I386-LABEL: test7a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test7a:
+; LINUX-X64-LABEL: test7a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test7a:
+; LINUX-KERNEL-X64-LABEL: test7a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test7a:
+; DARWIN-X64-LABEL: test7a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -798,19 +798,19 @@ entry:
 ; Requires no protector.
 define void @test7b() nounwind uwtable readnone ssp {
 entry:
-; LINUX-I386: test7b:
+; LINUX-I386-LABEL: test7b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test7b:
+; LINUX-X64-LABEL: test7b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test7b:
+; LINUX-KERNEL-X64-LABEL: test7b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test7b:
+; DARWIN-X64-LABEL: test7b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -824,19 +824,19 @@ entry:
 ; Requires protector.
 define void @test7c() nounwind uwtable readnone sspstrong {
 entry:
-; LINUX-I386: test7c:
+; LINUX-I386-LABEL: test7c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test7c:
+; LINUX-X64-LABEL: test7c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test7c:
+; LINUX-KERNEL-X64-LABEL: test7c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test7c:
+; DARWIN-X64-LABEL: test7c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -850,19 +850,19 @@ entry:
 ; Requires protector.
 define void @test7d() nounwind uwtable readnone sspreq {
 entry:
-; LINUX-I386: test7d:
+; LINUX-I386-LABEL: test7d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test7d:
+; LINUX-X64-LABEL: test7d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test7d:
+; LINUX-KERNEL-X64-LABEL: test7d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test7d:
+; DARWIN-X64-LABEL: test7d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -876,19 +876,19 @@ entry:
 ; Requires no protector.
 define void @test8a() nounwind uwtable {
 entry:
-; LINUX-I386: test8a:
+; LINUX-I386-LABEL: test8a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test8a:
+; LINUX-X64-LABEL: test8a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test8a:
+; LINUX-KERNEL-X64-LABEL: test8a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test8a:
+; DARWIN-X64-LABEL: test8a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %b = alloca i32, align 4
@@ -901,19 +901,19 @@ entry:
 ; Requires no protector.
 define void @test8b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test8b:
+; LINUX-I386-LABEL: test8b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test8b:
+; LINUX-X64-LABEL: test8b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test8b:
+; LINUX-KERNEL-X64-LABEL: test8b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test8b:
+; DARWIN-X64-LABEL: test8b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %b = alloca i32, align 4
@@ -926,19 +926,19 @@ entry:
 ; Requires protector.
 define void @test8c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test8c:
+; LINUX-I386-LABEL: test8c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test8c:
+; LINUX-X64-LABEL: test8c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test8c:
+; LINUX-KERNEL-X64-LABEL: test8c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test8c:
+; DARWIN-X64-LABEL: test8c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %b = alloca i32, align 4
@@ -951,19 +951,19 @@ entry:
 ; Requires protector.
 define void @test8d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test8d:
+; LINUX-I386-LABEL: test8d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test8d:
+; LINUX-X64-LABEL: test8d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test8d:
+; LINUX-KERNEL-X64-LABEL: test8d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test8d:
+; DARWIN-X64-LABEL: test8d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %b = alloca i32, align 4
@@ -976,19 +976,19 @@ entry:
 ; Requires no protector.
 define void @test9a() nounwind uwtable {
 entry:
-; LINUX-I386: test9a:
+; LINUX-I386-LABEL: test9a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test9a:
+; LINUX-X64-LABEL: test9a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test9a:
+; LINUX-KERNEL-X64-LABEL: test9a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test9a:
+; DARWIN-X64-LABEL: test9a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %x = alloca double, align 8
@@ -1005,19 +1005,19 @@ entry:
 ; Requires no protector.
 define void @test9b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test9b:
+; LINUX-I386-LABEL: test9b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test9b:
+; LINUX-X64-LABEL: test9b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test9b:
+; LINUX-KERNEL-X64-LABEL: test9b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test9b:
+; DARWIN-X64-LABEL: test9b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %x = alloca double, align 8
@@ -1034,19 +1034,19 @@ entry:
 ; Requires protector.
 define void @test9c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test9c:
+; LINUX-I386-LABEL: test9c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test9c:
+; LINUX-X64-LABEL: test9c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test9c:
+; LINUX-KERNEL-X64-LABEL: test9c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test9c:
+; DARWIN-X64-LABEL: test9c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %x = alloca double, align 8
@@ -1063,19 +1063,19 @@ entry:
 ; Requires protector.
 define void @test9d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test9d:
+; LINUX-I386-LABEL: test9d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test9d:
+; LINUX-X64-LABEL: test9d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test9d:
+; LINUX-KERNEL-X64-LABEL: test9d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test9d:
+; DARWIN-X64-LABEL: test9d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %x = alloca double, align 8
@@ -1092,19 +1092,19 @@ entry:
 ; Requires no protector.
 define void @test10a() nounwind uwtable {
 entry:
-; LINUX-I386: test10a:
+; LINUX-I386-LABEL: test10a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test10a:
+; LINUX-X64-LABEL: test10a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test10a:
+; LINUX-KERNEL-X64-LABEL: test10a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test10a:
+; DARWIN-X64-LABEL: test10a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %x = alloca double, align 8
@@ -1136,19 +1136,19 @@ if.end4:                                          ; preds = %if.else, %if.then3,
 ; Requires no protector.
 define void @test10b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test10b:
+; LINUX-I386-LABEL: test10b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test10b:
+; LINUX-X64-LABEL: test10b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test10b:
+; LINUX-KERNEL-X64-LABEL: test10b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test10b:
+; DARWIN-X64-LABEL: test10b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %x = alloca double, align 8
@@ -1180,19 +1180,19 @@ if.end4:                                          ; preds = %if.else, %if.then3,
 ; Requires protector.
 define void @test10c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test10c:
+; LINUX-I386-LABEL: test10c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test10c:
+; LINUX-X64-LABEL: test10c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test10c:
+; LINUX-KERNEL-X64-LABEL: test10c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test10c:
+; DARWIN-X64-LABEL: test10c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %x = alloca double, align 8
@@ -1224,19 +1224,19 @@ if.end4:                                          ; preds = %if.else, %if.then3,
 ; Requires protector.
 define void @test10d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test10d:
+; LINUX-I386-LABEL: test10d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test10d:
+; LINUX-X64-LABEL: test10d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test10d:
+; LINUX-KERNEL-X64-LABEL: test10d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test10d:
+; DARWIN-X64-LABEL: test10d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %x = alloca double, align 8
@@ -1268,19 +1268,19 @@ if.end4:                                          ; preds = %if.else, %if.then3,
 ; Requires no protector.
 define void @test11a() nounwind uwtable {
 entry:
-; LINUX-I386: test11a:
+; LINUX-I386-LABEL: test11a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test11a:
+; LINUX-X64-LABEL: test11a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test11a:
+; LINUX-KERNEL-X64-LABEL: test11a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test11a:
+; DARWIN-X64-LABEL: test11a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -1297,19 +1297,19 @@ entry:
 ; Requires no protector.
 define void @test11b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test11b:
+; LINUX-I386-LABEL: test11b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test11b:
+; LINUX-X64-LABEL: test11b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test11b:
+; LINUX-KERNEL-X64-LABEL: test11b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test11b:
+; DARWIN-X64-LABEL: test11b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -1326,19 +1326,19 @@ entry:
 ; Requires protector.
 define void @test11c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test11c:
+; LINUX-I386-LABEL: test11c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test11c:
+; LINUX-X64-LABEL: test11c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test11c:
+; LINUX-KERNEL-X64-LABEL: test11c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test11c:
+; DARWIN-X64-LABEL: test11c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -1355,19 +1355,19 @@ entry:
 ; Requires protector.
 define void @test11d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test11d:
+; LINUX-I386-LABEL: test11d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test11d:
+; LINUX-X64-LABEL: test11d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test11d:
+; LINUX-KERNEL-X64-LABEL: test11d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test11d:
+; DARWIN-X64-LABEL: test11d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -1384,19 +1384,19 @@ entry:
 ; Requires no protector.
 define void @test12a() nounwind uwtable {
 entry:
-; LINUX-I386: test12a:
+; LINUX-I386-LABEL: test12a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test12a:
+; LINUX-X64-LABEL: test12a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test12a:
+; LINUX-KERNEL-X64-LABEL: test12a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test12a:
+; DARWIN-X64-LABEL: test12a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -1412,19 +1412,19 @@ entry:
 ; Requires no protector.
 define void @test12b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test12b:
+; LINUX-I386-LABEL: test12b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test12b:
+; LINUX-X64-LABEL: test12b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test12b:
+; LINUX-KERNEL-X64-LABEL: test12b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test12b:
+; DARWIN-X64-LABEL: test12b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -1440,19 +1440,19 @@ entry:
 ; Requires protector.
 define void @test12c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test12c:
+; LINUX-I386-LABEL: test12c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test12c:
+; LINUX-X64-LABEL: test12c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test12c:
+; LINUX-KERNEL-X64-LABEL: test12c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test12c:
+; DARWIN-X64-LABEL: test12c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -1468,19 +1468,19 @@ entry:
 ; Requires protector.
 define void @test12d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test12d:
+; LINUX-I386-LABEL: test12d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test12d:
+; LINUX-X64-LABEL: test12d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test12d:
+; LINUX-KERNEL-X64-LABEL: test12d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test12d:
+; DARWIN-X64-LABEL: test12d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -1496,19 +1496,19 @@ entry:
 ; Requires no protector.
 define void @test13a() nounwind uwtable {
 entry:
-; LINUX-I386: test13a:
+; LINUX-I386-LABEL: test13a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test13a:
+; LINUX-X64-LABEL: test13a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test13a:
+; LINUX-KERNEL-X64-LABEL: test13a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test13a:
+; DARWIN-X64-LABEL: test13a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -1522,19 +1522,19 @@ entry:
 ; Requires no protector.
 define void @test13b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test13b:
+; LINUX-I386-LABEL: test13b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test13b:
+; LINUX-X64-LABEL: test13b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test13b:
+; LINUX-KERNEL-X64-LABEL: test13b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test13b:
+; DARWIN-X64-LABEL: test13b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -1548,19 +1548,19 @@ entry:
 ; Requires protector.
 define void @test13c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test13c:
+; LINUX-I386-LABEL: test13c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test13c:
+; LINUX-X64-LABEL: test13c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test13c:
+; LINUX-KERNEL-X64-LABEL: test13c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test13c:
+; DARWIN-X64-LABEL: test13c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -1574,19 +1574,19 @@ entry:
 ; Requires protector.
 define void @test13d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test13d:
+; LINUX-I386-LABEL: test13d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test13d:
+; LINUX-X64-LABEL: test13d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test13d:
+; LINUX-KERNEL-X64-LABEL: test13d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test13d:
+; DARWIN-X64-LABEL: test13d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -1600,19 +1600,19 @@ entry:
 ; Requires no protector.
 define void @test14a() nounwind uwtable {
 entry:
-; LINUX-I386: test14a:
+; LINUX-I386-LABEL: test14a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test14a:
+; LINUX-X64-LABEL: test14a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test14a:
+; LINUX-KERNEL-X64-LABEL: test14a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test14a:
+; DARWIN-X64-LABEL: test14a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -1626,19 +1626,19 @@ entry:
 ; Requires no protector.
 define void @test14b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test14b:
+; LINUX-I386-LABEL: test14b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test14b:
+; LINUX-X64-LABEL: test14b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test14b:
+; LINUX-KERNEL-X64-LABEL: test14b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test14b:
+; DARWIN-X64-LABEL: test14b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -1652,19 +1652,19 @@ entry:
 ; Requires protector.
 define void @test14c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test14c:
+; LINUX-I386-LABEL: test14c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test14c:
+; LINUX-X64-LABEL: test14c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test14c:
+; LINUX-KERNEL-X64-LABEL: test14c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test14c:
+; DARWIN-X64-LABEL: test14c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -1678,19 +1678,19 @@ entry:
 ; Requires protector.
 define void @test14d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test14d:
+; LINUX-I386-LABEL: test14d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test14d:
+; LINUX-X64-LABEL: test14d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test14d:
+; LINUX-KERNEL-X64-LABEL: test14d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test14d:
+; DARWIN-X64-LABEL: test14d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -1705,19 +1705,19 @@ entry:
 ; Requires no protector.
 define void @test15a() nounwind uwtable {
 entry:
-; LINUX-I386: test15a:
+; LINUX-I386-LABEL: test15a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test15a:
+; LINUX-X64-LABEL: test15a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test15a:
+; LINUX-KERNEL-X64-LABEL: test15a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test15a:
+; DARWIN-X64-LABEL: test15a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -1736,19 +1736,19 @@ entry:
 ; Requires no protector.
 define void @test15b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test15b:
+; LINUX-I386-LABEL: test15b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test15b:
+; LINUX-X64-LABEL: test15b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test15b:
+; LINUX-KERNEL-X64-LABEL: test15b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test15b:
+; DARWIN-X64-LABEL: test15b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -1767,19 +1767,19 @@ entry:
 ; Requires protector.
 define void @test15c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test15c:
+; LINUX-I386-LABEL: test15c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test15c:
+; LINUX-X64-LABEL: test15c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test15c:
+; LINUX-KERNEL-X64-LABEL: test15c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test15c:
+; DARWIN-X64-LABEL: test15c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -1798,19 +1798,19 @@ entry:
 ; Requires protector.
 define void @test15d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test15d:
+; LINUX-I386-LABEL: test15d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test15d:
+; LINUX-X64-LABEL: test15d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test15d:
+; LINUX-KERNEL-X64-LABEL: test15d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test15d:
+; DARWIN-X64-LABEL: test15d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -1829,19 +1829,19 @@ entry:
 ; Requires no protector.
 define void @test16a() nounwind uwtable {
 entry:
-; LINUX-I386: test16a:
+; LINUX-I386-LABEL: test16a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test16a:
+; LINUX-X64-LABEL: test16a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test16a:
+; LINUX-KERNEL-X64-LABEL: test16a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test16a:
+; DARWIN-X64-LABEL: test16a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -1857,19 +1857,19 @@ entry:
 ; Requires no protector.
 define void @test16b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test16b:
+; LINUX-I386-LABEL: test16b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test16b:
+; LINUX-X64-LABEL: test16b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test16b:
+; LINUX-KERNEL-X64-LABEL: test16b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test16b:
+; DARWIN-X64-LABEL: test16b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -1885,19 +1885,19 @@ entry:
 ; Requires protector.
 define void @test16c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test16c:
+; LINUX-I386-LABEL: test16c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test16c:
+; LINUX-X64-LABEL: test16c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test16c:
+; LINUX-KERNEL-X64-LABEL: test16c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test16c:
+; DARWIN-X64-LABEL: test16c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -1913,19 +1913,19 @@ entry:
 ; Requires protector.
 define void @test16d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test16d:
+; LINUX-I386-LABEL: test16d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test16d:
+; LINUX-X64-LABEL: test16d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test16d:
+; LINUX-KERNEL-X64-LABEL: test16d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test16d:
+; DARWIN-X64-LABEL: test16d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -1940,19 +1940,19 @@ entry:
 ; Requires no protector.
 define void @test17a() nounwind uwtable {
 entry:
-; LINUX-I386: test17a:
+; LINUX-I386-LABEL: test17a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test17a:
+; LINUX-X64-LABEL: test17a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test17a:
+; LINUX-KERNEL-X64-LABEL: test17a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test17a:
+; DARWIN-X64-LABEL: test17a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.vec, align 16
@@ -1967,19 +1967,19 @@ entry:
 ; Requires no protector.
 define void @test17b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test17b:
+; LINUX-I386-LABEL: test17b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test17b:
+; LINUX-X64-LABEL: test17b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test17b:
+; LINUX-KERNEL-X64-LABEL: test17b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test17b:
+; DARWIN-X64-LABEL: test17b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.vec, align 16
@@ -1994,19 +1994,19 @@ entry:
 ; Requires protector.
 define void @test17c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test17c:
+; LINUX-I386-LABEL: test17c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test17c:
+; LINUX-X64-LABEL: test17c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test17c:
+; LINUX-KERNEL-X64-LABEL: test17c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test17c:
+; DARWIN-X64-LABEL: test17c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.vec, align 16
@@ -2021,19 +2021,19 @@ entry:
 ; Requires protector.
 define void @test17d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test17d:
+; LINUX-I386-LABEL: test17d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test17d:
+; LINUX-X64-LABEL: test17d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test17d:
+; LINUX-KERNEL-X64-LABEL: test17d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test17d:
+; DARWIN-X64-LABEL: test17d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.vec, align 16
@@ -2048,19 +2048,19 @@ entry:
 ; Requires no protector.
 define i32 @test18a() uwtable {
 entry:
-; LINUX-I386: test18a:
+; LINUX-I386-LABEL: test18a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test18a:
+; LINUX-X64-LABEL: test18a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test18a:
+; LINUX-KERNEL-X64-LABEL: test18a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test18a:
+; DARWIN-X64-LABEL: test18a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -2084,19 +2084,19 @@ lpad:
 ; Requires no protector.
 define i32 @test18b() uwtable ssp {
 entry:
-; LINUX-I386: test18b:
+; LINUX-I386-LABEL: test18b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test18b:
+; LINUX-X64-LABEL: test18b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test18b:
+; LINUX-KERNEL-X64-LABEL: test18b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test18b:
+; DARWIN-X64-LABEL: test18b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -2120,19 +2120,19 @@ lpad:
 ; Requires protector.
 define i32 @test18c() uwtable sspstrong {
 entry:
-; LINUX-I386: test18c:
+; LINUX-I386-LABEL: test18c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test18c:
+; LINUX-X64-LABEL: test18c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test18c:
+; LINUX-KERNEL-X64-LABEL: test18c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test18c:
+; DARWIN-X64-LABEL: test18c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -2156,19 +2156,19 @@ lpad:
 ; Requires protector.
 define i32 @test18d() uwtable sspreq {
 entry:
-; LINUX-I386: test18d:
+; LINUX-I386-LABEL: test18d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test18d:
+; LINUX-X64-LABEL: test18d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test18d:
+; LINUX-KERNEL-X64-LABEL: test18d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test18d:
+; DARWIN-X64-LABEL: test18d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -2193,19 +2193,19 @@ lpad:
 ; Requires no protector.
 define i32 @test19a() uwtable {
 entry:
-; LINUX-I386: test19a:
+; LINUX-I386-LABEL: test19a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test19a:
+; LINUX-X64-LABEL: test19a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test19a:
+; LINUX-KERNEL-X64-LABEL: test19a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test19a:
+; DARWIN-X64-LABEL: test19a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -2232,19 +2232,19 @@ lpad:
 ; Requires no protector.
 define i32 @test19b() uwtable ssp {
 entry:
-; LINUX-I386: test19b:
+; LINUX-I386-LABEL: test19b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test19b:
+; LINUX-X64-LABEL: test19b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test19b:
+; LINUX-KERNEL-X64-LABEL: test19b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test19b:
+; DARWIN-X64-LABEL: test19b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -2271,19 +2271,19 @@ lpad:
 ; Requires protector.
 define i32 @test19c() uwtable sspstrong {
 entry:
-; LINUX-I386: test19c:
+; LINUX-I386-LABEL: test19c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test19c:
+; LINUX-X64-LABEL: test19c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test19c:
+; LINUX-KERNEL-X64-LABEL: test19c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test19c:
+; DARWIN-X64-LABEL: test19c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -2310,19 +2310,19 @@ lpad:
 ; Requires protector.
 define i32 @test19d() uwtable sspreq {
 entry:
-; LINUX-I386: test19d:
+; LINUX-I386-LABEL: test19d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test19d:
+; LINUX-X64-LABEL: test19d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test19d:
+; LINUX-KERNEL-X64-LABEL: test19d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test19d:
+; DARWIN-X64-LABEL: test19d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -2348,19 +2348,19 @@ lpad:
 ; Requires no protector.
 define void @test20a() nounwind uwtable {
 entry:
-; LINUX-I386: test20a:
+; LINUX-I386-LABEL: test20a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test20a:
+; LINUX-X64-LABEL: test20a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test20a:
+; LINUX-KERNEL-X64-LABEL: test20a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test20a:
+; DARWIN-X64-LABEL: test20a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32*, align 8
@@ -2378,19 +2378,19 @@ entry:
 ; Requires no protector.
 define void @test20b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test20b:
+; LINUX-I386-LABEL: test20b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test20b:
+; LINUX-X64-LABEL: test20b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test20b:
+; LINUX-KERNEL-X64-LABEL: test20b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test20b:
+; DARWIN-X64-LABEL: test20b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32*, align 8
@@ -2408,19 +2408,19 @@ entry:
 ; Requires protector.
 define void @test20c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test20c:
+; LINUX-I386-LABEL: test20c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test20c:
+; LINUX-X64-LABEL: test20c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test20c:
+; LINUX-KERNEL-X64-LABEL: test20c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test20c:
+; DARWIN-X64-LABEL: test20c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32*, align 8
@@ -2438,19 +2438,19 @@ entry:
 ; Requires protector.
 define void @test20d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test20d:
+; LINUX-I386-LABEL: test20d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test20d:
+; LINUX-X64-LABEL: test20d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test20d:
+; LINUX-KERNEL-X64-LABEL: test20d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test20d:
+; DARWIN-X64-LABEL: test20d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32*, align 8
@@ -2468,19 +2468,19 @@ entry:
 ; Requires no protector.
 define void @test21a() nounwind uwtable {
 entry:
-; LINUX-I386: test21a:
+; LINUX-I386-LABEL: test21a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test21a:
+; LINUX-X64-LABEL: test21a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test21a:
+; LINUX-KERNEL-X64-LABEL: test21a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test21a:
+; DARWIN-X64-LABEL: test21a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32*, align 8
@@ -2499,19 +2499,19 @@ entry:
 ; Requires no protector.
 define void @test21b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test21b:
+; LINUX-I386-LABEL: test21b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test21b:
+; LINUX-X64-LABEL: test21b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test21b:
+; LINUX-KERNEL-X64-LABEL: test21b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test21b:
+; DARWIN-X64-LABEL: test21b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32*, align 8
@@ -2530,19 +2530,19 @@ entry:
 ; Requires protector.
 define void @test21c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test21c:
+; LINUX-I386-LABEL: test21c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test21c:
+; LINUX-X64-LABEL: test21c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test21c:
+; LINUX-KERNEL-X64-LABEL: test21c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test21c:
+; DARWIN-X64-LABEL: test21c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32*, align 8
@@ -2561,19 +2561,19 @@ entry:
 ; Requires protector.
 define void @test21d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test21d:
+; LINUX-I386-LABEL: test21d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test21d:
+; LINUX-X64-LABEL: test21d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test21d:
+; LINUX-KERNEL-X64-LABEL: test21d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test21d:
+; DARWIN-X64-LABEL: test21d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32*, align 8
@@ -2592,19 +2592,19 @@ entry:
 ; Requires no protector.
 define signext i8 @test22a() nounwind uwtable {
 entry:
-; LINUX-I386: test22a:
+; LINUX-I386-LABEL: test22a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test22a:
+; LINUX-X64-LABEL: test22a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test22a:
+; LINUX-KERNEL-X64-LABEL: test22a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test22a:
+; DARWIN-X64-LABEL: test22a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca %class.A, align 1
@@ -2619,19 +2619,19 @@ entry:
 ; Requires no protector.
 define signext i8 @test22b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test22b:
+; LINUX-I386-LABEL: test22b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test22b:
+; LINUX-X64-LABEL: test22b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test22b:
+; LINUX-KERNEL-X64-LABEL: test22b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test22b:
+; DARWIN-X64-LABEL: test22b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca %class.A, align 1
@@ -2646,19 +2646,19 @@ entry:
 ; Requires protector.
 define signext i8 @test22c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test22c:
+; LINUX-I386-LABEL: test22c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test22c:
+; LINUX-X64-LABEL: test22c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test22c:
+; LINUX-KERNEL-X64-LABEL: test22c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test22c:
+; DARWIN-X64-LABEL: test22c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca %class.A, align 1
@@ -2673,19 +2673,19 @@ entry:
 ; Requires protector.
 define signext i8 @test22d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test22d:
+; LINUX-I386-LABEL: test22d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test22d:
+; LINUX-X64-LABEL: test22d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test22d:
+; LINUX-KERNEL-X64-LABEL: test22d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test22d:
+; DARWIN-X64-LABEL: test22d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca %class.A, align 1
@@ -2700,19 +2700,19 @@ entry:
 ; Requires no protector.
 define signext i8 @test23a() nounwind uwtable {
 entry:
-; LINUX-I386: test23a:
+; LINUX-I386-LABEL: test23a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test23a:
+; LINUX-X64-LABEL: test23a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test23a:
+; LINUX-KERNEL-X64-LABEL: test23a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test23a:
+; DARWIN-X64-LABEL: test23a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %x = alloca %struct.deep, align 1
@@ -2731,19 +2731,19 @@ entry:
 ; Requires no protector.
 define signext i8 @test23b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test23b:
+; LINUX-I386-LABEL: test23b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test23b:
+; LINUX-X64-LABEL: test23b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test23b:
+; LINUX-KERNEL-X64-LABEL: test23b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test23b:
+; DARWIN-X64-LABEL: test23b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %x = alloca %struct.deep, align 1
@@ -2762,19 +2762,19 @@ entry:
 ; Requires protector.
 define signext i8 @test23c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test23c:
+; LINUX-I386-LABEL: test23c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test23c:
+; LINUX-X64-LABEL: test23c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test23c:
+; LINUX-KERNEL-X64-LABEL: test23c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test23c:
+; DARWIN-X64-LABEL: test23c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %x = alloca %struct.deep, align 1
@@ -2793,19 +2793,19 @@ entry:
 ; Requires protector.
 define signext i8 @test23d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test23d:
+; LINUX-I386-LABEL: test23d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test23d:
+; LINUX-X64-LABEL: test23d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test23d:
+; LINUX-KERNEL-X64-LABEL: test23d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test23d:
+; DARWIN-X64-LABEL: test23d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %x = alloca %struct.deep, align 1
@@ -2824,19 +2824,19 @@ entry:
 ; Requires no protector.
 define void @test24a(i32 %n) nounwind uwtable {
 entry:
-; LINUX-I386: test24a:
+; LINUX-I386-LABEL: test24a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test24a:
+; LINUX-X64-LABEL: test24a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test24a:
+; LINUX-KERNEL-X64-LABEL: test24a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test24a:
+; DARWIN-X64-LABEL: test24a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %n.addr = alloca i32, align 4
@@ -2855,19 +2855,19 @@ entry:
 ; Requires protector.
 define void @test24b(i32 %n) nounwind uwtable ssp {
 entry:
-; LINUX-I386: test24b:
+; LINUX-I386-LABEL: test24b:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test24b:
+; LINUX-X64-LABEL: test24b:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test24b:
+; LINUX-KERNEL-X64-LABEL: test24b:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test24b:
+; DARWIN-X64-LABEL: test24b:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %n.addr = alloca i32, align 4
@@ -2886,19 +2886,19 @@ entry:
 ; Requires protector.
 define void @test24c(i32 %n) nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test24c:
+; LINUX-I386-LABEL: test24c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test24c:
+; LINUX-X64-LABEL: test24c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test24c:
+; LINUX-KERNEL-X64-LABEL: test24c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test24c:
+; DARWIN-X64-LABEL: test24c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %n.addr = alloca i32, align 4
@@ -2917,19 +2917,19 @@ entry:
 ; Requires protector.
 define void @test24d(i32 %n) nounwind uwtable sspreq  {
 entry:
-; LINUX-I386: test24d:
+; LINUX-I386-LABEL: test24d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test24d:
+; LINUX-X64-LABEL: test24d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test24d:
+; LINUX-KERNEL-X64-LABEL: test24d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test24d:
+; DARWIN-X64-LABEL: test24d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %n.addr = alloca i32, align 4
@@ -2948,19 +2948,19 @@ entry:
 ; Requires no protector.
 define i32 @test25a() nounwind uwtable {
 entry:
-; LINUX-I386: test25a:
+; LINUX-I386-LABEL: test25a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test25a:
+; LINUX-X64-LABEL: test25a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test25a:
+; LINUX-KERNEL-X64-LABEL: test25a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test25a:
+; DARWIN-X64-LABEL: test25a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca [4 x i32], align 16
@@ -2974,19 +2974,19 @@ entry:
 ; Requires no protector, except for Darwin which _does_ require a protector.
 define i32 @test25b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test25b:
+; LINUX-I386-LABEL: test25b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test25b:
+; LINUX-X64-LABEL: test25b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test25b:
+; LINUX-KERNEL-X64-LABEL: test25b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test25b:
+; DARWIN-X64-LABEL: test25b:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca [4 x i32], align 16
@@ -3000,19 +3000,19 @@ entry:
 ; Requires protector.
 define i32 @test25c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test25c:
+; LINUX-I386-LABEL: test25c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test25c:
+; LINUX-X64-LABEL: test25c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test25c:
+; LINUX-KERNEL-X64-LABEL: test25c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test25c:
+; DARWIN-X64-LABEL: test25c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca [4 x i32], align 16
@@ -3026,19 +3026,19 @@ entry:
 ; Requires protector.
 define i32 @test25d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test25d:
+; LINUX-I386-LABEL: test25d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test25d:
+; LINUX-X64-LABEL: test25d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test25d:
+; LINUX-KERNEL-X64-LABEL: test25d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test25d:
+; DARWIN-X64-LABEL: test25d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca [4 x i32], align 16
@@ -3054,19 +3054,19 @@ entry:
 ; Requires no protector.
 define void @test26() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test26:
+; LINUX-I386-LABEL: test26:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test26:
+; LINUX-X64-LABEL: test26:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test26:
+; LINUX-KERNEL-X64-LABEL: test26:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test26:
+; DARWIN-X64-LABEL: test26:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.nest, align 4
@@ -3085,19 +3085,19 @@ entry:
 ; Requires protector.
 define i32 @test27(i32 %arg) nounwind uwtable sspstrong {
 bb:
-; LINUX-I386: test27:
+; LINUX-I386-LABEL: test27:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test27:
+; LINUX-X64-LABEL: test27:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test27:
+; LINUX-KERNEL-X64-LABEL: test27:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test27:
+; DARWIN-X64-LABEL: test27:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %tmp = alloca %struct.small*, align 8
diff --git a/test/CodeGen/X86/stdcall-notailcall.ll b/test/CodeGen/X86/stdcall-notailcall.ll
index 8e33c30..8f522cd 100644
--- a/test/CodeGen/X86/stdcall-notailcall.ll
+++ b/test/CodeGen/X86/stdcall-notailcall.ll
@@ -2,7 +2,7 @@
 
 %struct.I = type { i32 (...)** }
 define x86_stdcallcc void @bar(%struct.I* nocapture %this) ssp align 2 {
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK-NOT: jmp
 ; CHECK: ret $4
 entry:
diff --git a/test/CodeGen/X86/store_op_load_fold.ll b/test/CodeGen/X86/store_op_load_fold.ll
index 41b0a9c..bbeb744 100644
--- a/test/CodeGen/X86/store_op_load_fold.ll
+++ b/test/CodeGen/X86/store_op_load_fold.ll
@@ -5,7 +5,7 @@
 @X = internal global i16 0              ; <i16*> [#uses=2]
 
 define void @foo() nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NOT: mov
 ; CHECK: add
 ; CHECK-NEXT: ret
diff --git a/test/CodeGen/X86/sub-with-overflow.ll b/test/CodeGen/X86/sub-with-overflow.ll
index db8313c..baaee35 100644
--- a/test/CodeGen/X86/sub-with-overflow.ll
+++ b/test/CodeGen/X86/sub-with-overflow.ll
@@ -18,7 +18,7 @@ overflow:
   %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
 
-; CHECK: func1:
+; CHECK-LABEL: func1:
 ; CHECK: subl 20(%esp)
 ; CHECK-NEXT: jno
 }
@@ -38,7 +38,7 @@ carry:
   %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
 
-; CHECK: func2:
+; CHECK-LABEL: func2:
 ; CHECK: subl 20(%esp)
 ; CHECK-NEXT: jae
 }
@@ -53,7 +53,7 @@ entry:
   %obit = extractvalue {i32, i1} %t, 1
   ret i1 %obit
 
-; CHECK: func3:
+; CHECK-LABEL: func3:
 ; CHECK: decl
 ; CHECK-NEXT: seto
 }
diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll
index 75a728c..73d93ff 100644
--- a/test/CodeGen/X86/tail-opts.ll
+++ b/test/CodeGen/X86/tail-opts.ll
@@ -13,7 +13,7 @@ declare i1 @qux()
 ; BranchFolding should tail-merge the stores since they all precede
 ; direct branches to the same place.
 
-; CHECK: tail_merge_me:
+; CHECK-LABEL: tail_merge_me:
 ; CHECK-NOT:  GHJK
 ; CHECK:      movl $0, GHJK(%rip)
 ; CHECK-NEXT: movl $1, HABC(%rip)
@@ -60,7 +60,7 @@ declare i8* @choose(i8*, i8*)
 ; BranchFolding should tail-duplicate the indirect jump to avoid
 ; redundant branching.
 
-; CHECK: tail_duplicate_me:
+; CHECK-LABEL: tail_duplicate_me:
 ; CHECK:      movl $0, GHJK(%rip)
 ; CHECK-NEXT: jmpq *%r
 ; CHECK:      movl $0, GHJK(%rip)
@@ -107,7 +107,7 @@ altret:
 ; BranchFolding shouldn't try to merge the tails of two blocks
 ; with only a branch in common, regardless of the fallthrough situation.
 
-; CHECK: dont_merge_oddly:
+; CHECK-LABEL: dont_merge_oddly:
 ; CHECK-NOT:   ret
 ; CHECK:        ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
 ; CHECK-NEXT:   jbe .LBB2_3
@@ -153,7 +153,7 @@ bb30:
 ; Do any-size tail-merging when two candidate blocks will both require
 ; an unconditional jump to complete a two-way conditional branch.
 
-; CHECK: c_expand_expr_stmt:
+; CHECK-LABEL: c_expand_expr_stmt:
 ;
 ; This test only works when register allocation happens to use %rax for both
 ; load addresses.
@@ -275,7 +275,7 @@ declare fastcc %union.tree_node* @default_conversion(%union.tree_node*) nounwind
 ; instructions are involved. This function should have only
 ; one ret instruction.
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK:        callq func
 ; CHECK-NEXT: .LBB4_2:
 ; CHECK-NEXT:   popq
@@ -298,7 +298,7 @@ declare void @func()
 
 ; one - One instruction may be tail-duplicated even with optsize.
 
-; CHECK: one:
+; CHECK-LABEL: one:
 ; CHECK: movl $0, XYZ(%rip)
 ; CHECK: movl $0, XYZ(%rip)
 
@@ -335,7 +335,7 @@ return:
 ; tail instead of one. This is too much to be merged, given
 ; the optsize attribute.
 
-; CHECK: two:
+; CHECK-LABEL: two:
 ; CHECK-NOT: XYZ
 ; CHECK: ret
 ; CHECK: movl $0, XYZ(%rip)
@@ -374,7 +374,7 @@ return:
 ; two_nosize - Same as two, but without the optsize attribute.
 ; Now two instructions are enough to be tail-duplicated.
 
-; CHECK: two_nosize:
+; CHECK-LABEL: two_nosize:
 ; CHECK: movl $0, XYZ(%rip)
 ; CHECK: movl $1, XYZ(%rip)
 ; CHECK: movl $0, XYZ(%rip)
@@ -412,7 +412,7 @@ return:
 ; Tail-merging should merge the two ret instructions since one side
 ; can fall-through into the ret and the other side has to branch anyway.
 
-; CHECK: TESTE:
+; CHECK-LABEL: TESTE:
 ; CHECK: ret
 ; CHECK-NOT: ret
 ; CHECK: size TESTE
diff --git a/test/CodeGen/X86/tailcall-cgp-dup.ll b/test/CodeGen/X86/tailcall-cgp-dup.ll
index a80b90f..a51bc88 100644
--- a/test/CodeGen/X86/tailcall-cgp-dup.ll
+++ b/test/CodeGen/X86/tailcall-cgp-dup.ll
@@ -4,7 +4,7 @@
 ; rdar://9147433
 
 define i32 @foo(i32 %x) nounwind ssp {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 entry:
   switch i32 %x, label %return [
     i32 1, label %sw.bb
@@ -69,7 +69,7 @@ declare i8* @bar(i8*) uwtable optsize noinline ssp
 
 define hidden %0* @thingWithValue(i8* %self) uwtable ssp {
 entry:
-; CHECK: thingWithValue:
+; CHECK-LABEL: thingWithValue:
 ; CHECK: jmp _bar
   br i1 undef, label %if.then.i, label %if.else.i
 
diff --git a/test/CodeGen/X86/tailcallbyval64.ll b/test/CodeGen/X86/tailcallbyval64.ll
index 7621602..75a6d87 100644
--- a/test/CodeGen/X86/tailcallbyval64.ll
+++ b/test/CodeGen/X86/tailcallbyval64.ll
@@ -3,7 +3,7 @@
 ; FIXME: Win64 does not support byval.
 
 ; Expect the entry point.
-; CHECK: tailcaller:
+; CHECK-LABEL: tailcaller:
 
 ; Expect 2 rep;movs because of tail call byval lowering.
 ; CHECK: rep;
diff --git a/test/CodeGen/X86/tailcallfp2.ll b/test/CodeGen/X86/tailcallfp2.ll
index 04c4e95..9ef0d27 100644
--- a/test/CodeGen/X86/tailcallfp2.ll
+++ b/test/CodeGen/X86/tailcallfp2.ll
@@ -3,7 +3,7 @@
 declare i32 @putchar(i32)
 
 define fastcc i32 @checktail(i32 %x, i32* %f, i32 %g) nounwind {
-; CHECK: checktail:
+; CHECK-LABEL: checktail:
         %tmp1 = icmp sgt i32 %x, 0
         br i1 %tmp1, label %if-then, label %if-else
 
diff --git a/test/CodeGen/X86/test-shrink.ll b/test/CodeGen/X86/test-shrink.ll
index 5bc28ec..c9b76c8 100644
--- a/test/CodeGen/X86/test-shrink.ll
+++ b/test/CodeGen/X86/test-shrink.ll
@@ -2,10 +2,10 @@
 ; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s --check-prefix=CHECK-64
 ; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32
 
-; CHECK-64: g64xh:
+; CHECK-64-LABEL: g64xh:
 ; CHECK-64:   testb $8, {{%ah|%ch}}
 ; CHECK-64:   ret
-; CHECK-32: g64xh:
+; CHECK-32-LABEL: g64xh:
 ; CHECK-32:   testb $8, %ah
 ; CHECK-32:   ret
 define void @g64xh(i64 inreg %x) nounwind {
@@ -19,10 +19,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g64xl:
+; CHECK-64-LABEL: g64xl:
 ; CHECK-64:   testb $8, [[A0L:%dil|%cl]]
 ; CHECK-64:   ret
-; CHECK-32: g64xl:
+; CHECK-32-LABEL: g64xl:
 ; CHECK-32:   testb $8, %al
 ; CHECK-32:   ret
 define void @g64xl(i64 inreg %x) nounwind {
@@ -36,10 +36,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g32xh:
+; CHECK-64-LABEL: g32xh:
 ; CHECK-64:   testb $8, {{%ah|%ch}}
 ; CHECK-64:   ret
-; CHECK-32: g32xh:
+; CHECK-32-LABEL: g32xh:
 ; CHECK-32:   testb $8, %ah
 ; CHECK-32:   ret
 define void @g32xh(i32 inreg %x) nounwind {
@@ -53,10 +53,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g32xl:
+; CHECK-64-LABEL: g32xl:
 ; CHECK-64:   testb $8, [[A0L]]
 ; CHECK-64:   ret
-; CHECK-32: g32xl:
+; CHECK-32-LABEL: g32xl:
 ; CHECK-32:   testb $8, %al
 ; CHECK-32:   ret
 define void @g32xl(i32 inreg %x) nounwind {
@@ -70,10 +70,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g16xh:
+; CHECK-64-LABEL: g16xh:
 ; CHECK-64:   testb $8, {{%ah|%ch}}
 ; CHECK-64:   ret
-; CHECK-32: g16xh:
+; CHECK-32-LABEL: g16xh:
 ; CHECK-32:   testb $8, %ah
 ; CHECK-32:   ret
 define void @g16xh(i16 inreg %x) nounwind {
@@ -87,10 +87,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g16xl:
+; CHECK-64-LABEL: g16xl:
 ; CHECK-64:   testb $8, [[A0L]]
 ; CHECK-64:   ret
-; CHECK-32: g16xl:
+; CHECK-32-LABEL: g16xl:
 ; CHECK-32:   testb $8, %al
 ; CHECK-32:   ret
 define void @g16xl(i16 inreg %x) nounwind {
@@ -104,10 +104,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g64x16:
+; CHECK-64-LABEL: g64x16:
 ; CHECK-64:   testw $-32640, %[[A0W:di|cx]]
 ; CHECK-64:   ret
-; CHECK-32: g64x16:
+; CHECK-32-LABEL: g64x16:
 ; CHECK-32:   testw $-32640, %ax
 ; CHECK-32:   ret
 define void @g64x16(i64 inreg %x) nounwind {
@@ -121,10 +121,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g32x16:
+; CHECK-64-LABEL: g32x16:
 ; CHECK-64:   testw $-32640, %[[A0W]]
 ; CHECK-64:   ret
-; CHECK-32: g32x16:
+; CHECK-32-LABEL: g32x16:
 ; CHECK-32:   testw $-32640, %ax
 ; CHECK-32:   ret
 define void @g32x16(i32 inreg %x) nounwind {
@@ -138,10 +138,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g64x32:
+; CHECK-64-LABEL: g64x32:
 ; CHECK-64:   testl $268468352, %e[[A0W]]
 ; CHECK-64:   ret
-; CHECK-32: g64x32:
+; CHECK-32-LABEL: g64x32:
 ; CHECK-32:   testl $268468352, %eax
 ; CHECK-32:   ret
 define void @g64x32(i64 inreg %x) nounwind {
diff --git a/test/CodeGen/X86/tls-local-dynamic.ll b/test/CodeGen/X86/tls-local-dynamic.ll
index c5fd16b..4841e52 100644
--- a/test/CodeGen/X86/tls-local-dynamic.ll
+++ b/test/CodeGen/X86/tls-local-dynamic.ll
@@ -10,7 +10,7 @@ entry:
   ret i32* @x
 ; FIXME: This function uses a single thread-local variable,
 ; so we might want to fall back to general-dynamic here.
-; CHECK:       get_x:
+; CHECK-LABEL:       get_x:
 ; CHECK:       leaq x@TLSLD(%rip), %rdi
 ; CHECK-NEXT:  callq __tls_get_addr@PLT
 ; CHECK:       x@DTPOFF
@@ -26,7 +26,7 @@ entry:
   %cmp = icmp eq i32 %i, 1
   br i1 %cmp, label %return, label %if.else
 ; This bb does not access TLS, so should not call __tls_get_addr.
-; CHECK:       f:
+; CHECK-LABEL:       f:
 ; CHECK-NOT:   __tls_get_addr
 ; CHECK:       je
 
diff --git a/test/CodeGen/X86/tls-models.ll b/test/CodeGen/X86/tls-models.ll
index 7c527e2..8e3e958 100644
--- a/test/CodeGen/X86/tls-models.ll
+++ b/test/CodeGen/X86/tls-models.ll
@@ -25,15 +25,15 @@ entry:
   ret i32* @external_gd
 
   ; Non-PIC code can use initial-exec, PIC code has to use general dynamic.
-  ; X64:     f1:
+  ; X64-LABEL:     f1:
   ; X64:     external_gd@GOTTPOFF
-  ; X32:     f1:
+  ; X32-LABEL:     f1:
   ; X32:     external_gd@INDNTPOFF
-  ; X64_PIC: f1:
+  ; X64_PIC-LABEL: f1:
   ; X64_PIC: external_gd@TLSGD
-  ; X32_PIC: f1:
+  ; X32_PIC-LABEL: f1:
   ; X32_PIC: external_gd@TLSGD
-  ; DARWIN:  f1:
+  ; DARWIN-LABEL:  f1:
   ; DARWIN:  _external_gd@TLVP
 }
 
@@ -42,15 +42,15 @@ entry:
   ret i32* @internal_gd
 
   ; Non-PIC code can use local exec, PIC code can use local dynamic.
-  ; X64:     f2:
+  ; X64-LABEL:     f2:
   ; X64:     internal_gd@TPOFF
-  ; X32:     f2:
+  ; X32-LABEL:     f2:
   ; X32:     internal_gd@NTPOFF
-  ; X64_PIC: f2:
+  ; X64_PIC-LABEL: f2:
   ; X64_PIC: internal_gd@TLSLD
-  ; X32_PIC: f2:
+  ; X32_PIC-LABEL: f2:
   ; X32_PIC: internal_gd@TLSLDM
-  ; DARWIN:  f2:
+  ; DARWIN-LABEL:  f2:
   ; DARWIN:  _internal_gd@TLVP
 }
 
@@ -62,15 +62,15 @@ entry:
   ret i32* @external_ld
 
   ; Non-PIC code can use initial exec, PIC code use local dynamic as specified.
-  ; X64:     f3:
+  ; X64-LABEL:     f3:
   ; X64:     external_ld@GOTTPOFF
-  ; X32:     f3:
+  ; X32-LABEL:     f3:
   ; X32:     external_ld@INDNTPOFF
-  ; X64_PIC: f3:
+  ; X64_PIC-LABEL: f3:
   ; X64_PIC: external_ld@TLSLD
-  ; X32_PIC: f3:
+  ; X32_PIC-LABEL: f3:
   ; X32_PIC: external_ld@TLSLDM
-  ; DARWIN:  f3:
+  ; DARWIN-LABEL:  f3:
   ; DARWIN:  _external_ld@TLVP
 }
 
@@ -79,15 +79,15 @@ entry:
   ret i32* @internal_ld
 
   ; Non-PIC code can use local exec, PIC code can use local dynamic.
-  ; X64:     f4:
+  ; X64-LABEL:     f4:
   ; X64:     internal_ld@TPOFF
-  ; X32:     f4:
+  ; X32-LABEL:     f4:
   ; X32:     internal_ld@NTPOFF
-  ; X64_PIC: f4:
+  ; X64_PIC-LABEL: f4:
   ; X64_PIC: internal_ld@TLSLD
-  ; X32_PIC: f4:
+  ; X32_PIC-LABEL: f4:
   ; X32_PIC: internal_ld@TLSLDM
-  ; DARWIN:  f4:
+  ; DARWIN-LABEL:  f4:
   ; DARWIN:  _internal_ld@TLVP
 }
 
@@ -99,15 +99,15 @@ entry:
   ret i32* @external_ie
 
   ; Non-PIC and PIC code will use initial exec as specified.
-  ; X64:     f5:
+  ; X64-LABEL:     f5:
   ; X64:     external_ie@GOTTPOFF
-  ; X32:     f5:
+  ; X32-LABEL:     f5:
   ; X32:     external_ie@INDNTPOFF
-  ; X64_PIC: f5:
+  ; X64_PIC-LABEL: f5:
   ; X64_PIC: external_ie@GOTTPOFF
-  ; X32_PIC: f5:
+  ; X32_PIC-LABEL: f5:
   ; X32_PIC: external_ie@GOTNTPOFF
-  ; DARWIN:  f5:
+  ; DARWIN-LABEL:  f5:
   ; DARWIN:  _external_ie@TLVP
 }
 
@@ -116,15 +116,15 @@ entry:
   ret i32* @internal_ie
 
   ; Non-PIC code can use local exec, PIC code use initial exec as specified.
-  ; X64:     f6:
+  ; X64-LABEL:     f6:
   ; X64:     internal_ie@TPOFF
-  ; X32:     f6:
+  ; X32-LABEL:     f6:
   ; X32:     internal_ie@NTPOFF
-  ; X64_PIC: f6:
+  ; X64_PIC-LABEL: f6:
   ; X64_PIC: internal_ie@GOTTPOFF
-  ; X32_PIC: f6:
+  ; X32_PIC-LABEL: f6:
   ; X32_PIC: internal_ie@GOTNTPOFF
-  ; DARWIN:  f6:
+  ; DARWIN-LABEL:  f6:
   ; DARWIN:  _internal_ie@TLVP
 }
 
@@ -136,15 +136,15 @@ entry:
   ret i32* @external_le
 
   ; Non-PIC and PIC code will use local exec as specified.
-  ; X64:     f7:
+  ; X64-LABEL:     f7:
   ; X64:     external_le@TPOFF
-  ; X32:     f7:
+  ; X32-LABEL:     f7:
   ; X32:     external_le@NTPOFF
-  ; X64_PIC: f7:
+  ; X64_PIC-LABEL: f7:
   ; X64_PIC: external_le@TPOFF
-  ; X32_PIC: f7:
+  ; X32_PIC-LABEL: f7:
   ; X32_PIC: external_le@NTPOFF
-  ; DARWIN:  f7:
+  ; DARWIN-LABEL:  f7:
   ; DARWIN:  _external_le@TLVP
 }
 
@@ -153,14 +153,14 @@ entry:
   ret i32* @internal_le
 
   ; Non-PIC and PIC code will use local exec as specified.
-  ; X64:     f8:
+  ; X64-LABEL:     f8:
   ; X64:     internal_le@TPOFF
-  ; X32:     f8:
+  ; X32-LABEL:     f8:
   ; X32:     internal_le@NTPOFF
-  ; X64_PIC: f8:
+  ; X64_PIC-LABEL: f8:
   ; X64_PIC: internal_le@TPOFF
-  ; X32_PIC: f8:
+  ; X32_PIC-LABEL: f8:
   ; X32_PIC: internal_le@NTPOFF
-  ; DARWIN:  f8:
+  ; DARWIN-LABEL:  f8:
   ; DARWIN:  _internal_le@TLVP
 }
diff --git a/test/CodeGen/X86/tls-pic.ll b/test/CodeGen/X86/tls-pic.ll
index b823f0a..0c79da6 100644
--- a/test/CodeGen/X86/tls-pic.ll
+++ b/test/CodeGen/X86/tls-pic.ll
@@ -11,11 +11,11 @@ entry:
 	ret i32 %tmp1
 }
 
-; X32: f1:
+; X32-LABEL: f1:
 ; X32:   leal i@TLSGD(,%ebx), %eax
 ; X32:   calll ___tls_get_addr@PLT
 
-; X64: f1:
+; X64-LABEL: f1:
 ; X64:   leaq i@TLSGD(%rip), %rdi
 ; X64:   callq __tls_get_addr@PLT
 
@@ -27,11 +27,11 @@ entry:
 	ret i32* @i
 }
 
-; X32: f2:
+; X32-LABEL: f2:
 ; X32:   leal i@TLSGD(,%ebx), %eax
 ; X32:   calll ___tls_get_addr@PLT
 
-; X64: f2:
+; X64-LABEL: f2:
 ; X64:   leaq i@TLSGD(%rip), %rdi
 ; X64:   callq __tls_get_addr@PLT
 
@@ -43,11 +43,11 @@ entry:
 	ret i32 %tmp1
 }
 
-; X32: f3:
+; X32-LABEL: f3:
 ; X32:   leal	i@TLSGD(,%ebx), %eax
 ; X32:   calll ___tls_get_addr@PLT
 
-; X64: f3:
+; X64-LABEL: f3:
 ; X64:   leaq i@TLSGD(%rip), %rdi
 ; X64:   callq __tls_get_addr@PLT
 
@@ -57,11 +57,11 @@ entry:
 	ret i32* @i
 }
 
-; X32: f4:
+; X32-LABEL: f4:
 ; X32:   leal	i@TLSGD(,%ebx), %eax
 ; X32:   calll ___tls_get_addr@PLT
 
-; X64: f4:
+; X64-LABEL: f4:
 ; X64:   leaq i@TLSGD(%rip), %rdi
 ; X64:   callq __tls_get_addr@PLT
 
@@ -74,13 +74,13 @@ entry:
 	ret i32 %add
 }
 
-; X32:    f5:
+; X32-LABEL:    f5:
 ; X32:      leal {{[jk]}}@TLSLDM(%ebx)
 ; X32: calll ___tls_get_addr@PLT
 ; X32: movl {{[jk]}}@DTPOFF(%e
 ; X32: addl {{[jk]}}@DTPOFF(%e
 
-; X64:    f5:
+; X64-LABEL:    f5:
 ; X64:      leaq {{[jk]}}@TLSLD(%rip), %rdi
 ; X64: callq	__tls_get_addr@PLT
 ; X64: movl {{[jk]}}@DTPOFF(%r
diff --git a/test/CodeGen/X86/tls-pie.ll b/test/CodeGen/X86/tls-pie.ll
index 3fca9f5..d1e09c2 100644
--- a/test/CodeGen/X86/tls-pie.ll
+++ b/test/CodeGen/X86/tls-pie.ll
@@ -7,10 +7,10 @@
 @i2 = external thread_local global i32
 
 define i32 @f1() {
-; X32: f1:
+; X32-LABEL: f1:
 ; X32:      movl %gs:i@NTPOFF, %eax
 ; X32-NEXT: ret
-; X64: f1:
+; X64-LABEL: f1:
 ; X64:      movl %fs:i@TPOFF, %eax
 ; X64-NEXT: ret
 
@@ -20,11 +20,11 @@ entry:
 }
 
 define i32* @f2() {
-; X32: f2:
+; X32-LABEL: f2:
 ; X32:      movl %gs:0, %eax
 ; X32-NEXT: leal i@NTPOFF(%eax), %eax
 ; X32-NEXT: ret
-; X64: f2:
+; X64-LABEL: f2:
 ; X64:      movq %fs:0, %rax
 ; X64-NEXT: leaq i@TPOFF(%rax), %rax
 ; X64-NEXT: ret
@@ -34,7 +34,7 @@ entry:
 }
 
 define i32 @f3() {
-; X32: f3:
+; X32-LABEL: f3:
 ; X32:      calll .L{{[0-9]+}}$pb
 ; X32-NEXT: .L{{[0-9]+}}$pb:
 ; X32-NEXT: popl %eax
@@ -43,7 +43,7 @@ define i32 @f3() {
 ; X32-NEXT: movl i2@GOTNTPOFF(%eax), %eax
 ; X32-NEXT: movl %gs:(%eax), %eax
 ; X32-NEXT: ret
-; X64: f3:
+; X64-LABEL: f3:
 ; X64:      movq i2@GOTTPOFF(%rip), %rax
 ; X64-NEXT: movl %fs:(%rax), %eax
 ; X64-NEXT: ret
@@ -54,7 +54,7 @@ entry:
 }
 
 define i32* @f4() {
-; X32: f4:
+; X32-LABEL: f4:
 ; X32:      calll .L{{[0-9]+}}$pb
 ; X32-NEXT: .L{{[0-9]+}}$pb:
 ; X32-NEXT: popl %ecx
@@ -63,7 +63,7 @@ define i32* @f4() {
 ; X32-NEXT: movl %gs:0, %eax
 ; X32-NEXT: addl i2@GOTNTPOFF(%ecx), %eax
 ; X32-NEXT: ret
-; X64: f4:
+; X64-LABEL: f4:
 ; X64:      movq %fs:0, %rax
 ; X64-NEXT: addq i2@GOTTPOFF(%rip), %rax
 ; X64-NEXT: ret
diff --git a/test/CodeGen/X86/tls.ll b/test/CodeGen/X86/tls.ll
index 8cdecd8..24284e5 100644
--- a/test/CodeGen/X86/tls.ll
+++ b/test/CodeGen/X86/tls.ll
@@ -12,19 +12,19 @@
 @b1 = thread_local global i8 0
 
 define i32 @f1() {
-; X32_LINUX: f1:
+; X32_LINUX-LABEL: f1:
 ; X32_LINUX:      movl %gs:i1@NTPOFF, %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f1:
+; X64_LINUX-LABEL: f1:
 ; X64_LINUX:      movl %fs:i1@TPOFF, %eax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f1:
+; X32_WIN-LABEL: f1:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: movl _i1@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f1:
+; X64_WIN-LABEL: f1:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -37,21 +37,21 @@ entry:
 }
 
 define i32* @f2() {
-; X32_LINUX: f2:
+; X32_LINUX-LABEL: f2:
 ; X32_LINUX:      movl %gs:0, %eax
 ; X32_LINUX-NEXT: leal i1@NTPOFF(%eax), %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f2:
+; X64_LINUX-LABEL: f2:
 ; X64_LINUX:      movq %fs:0, %rax
 ; X64_LINUX-NEXT: leaq i1@TPOFF(%rax), %rax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f2:
+; X32_WIN-LABEL: f2:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: leal _i1@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f2:
+; X64_WIN-LABEL: f2:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -63,21 +63,21 @@ entry:
 }
 
 define i32 @f3() nounwind {
-; X32_LINUX: f3:
+; X32_LINUX-LABEL: f3:
 ; X32_LINUX:      movl i2@INDNTPOFF, %eax
 ; X32_LINUX-NEXT: movl %gs:(%eax), %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f3:
+; X64_LINUX-LABEL: f3:
 ; X64_LINUX:      movq i2@GOTTPOFF(%rip), %rax
 ; X64_LINUX-NEXT: movl %fs:(%rax), %eax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f3:
+; X32_WIN-LABEL: f3:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: movl _i2@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f3:
+; X64_WIN-LABEL: f3:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -90,21 +90,21 @@ entry:
 }
 
 define i32* @f4() {
-; X32_LINUX: f4:
+; X32_LINUX-LABEL: f4:
 ; X32_LINUX:      movl %gs:0, %eax
 ; X32_LINUX-NEXT: addl i2@INDNTPOFF, %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f4:
+; X64_LINUX-LABEL: f4:
 ; X64_LINUX:      movq %fs:0, %rax
 ; X64_LINUX-NEXT: addq i2@GOTTPOFF(%rip), %rax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f4:
+; X32_WIN-LABEL: f4:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: leal _i2@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f4:
+; X64_WIN-LABEL: f4:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -116,19 +116,19 @@ entry:
 }
 
 define i32 @f5() nounwind {
-; X32_LINUX: f5:
+; X32_LINUX-LABEL: f5:
 ; X32_LINUX:      movl %gs:i3@NTPOFF, %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f5:
+; X64_LINUX-LABEL: f5:
 ; X64_LINUX:      movl %fs:i3@TPOFF, %eax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f5:
+; X32_WIN-LABEL: f5:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: movl _i3@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f5:
+; X64_WIN-LABEL: f5:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -141,21 +141,21 @@ entry:
 }
 
 define i32* @f6() {
-; X32_LINUX: f6:
+; X32_LINUX-LABEL: f6:
 ; X32_LINUX:      movl %gs:0, %eax
 ; X32_LINUX-NEXT: leal i3@NTPOFF(%eax), %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f6:
+; X64_LINUX-LABEL: f6:
 ; X64_LINUX:      movq %fs:0, %rax
 ; X64_LINUX-NEXT: leaq i3@TPOFF(%rax), %rax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f6:
+; X32_WIN-LABEL: f6:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: leal _i3@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f6:
+; X64_WIN-LABEL: f6:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -167,10 +167,10 @@ entry:
 }
 
 define i32 @f7() {
-; X32_LINUX: f7:
+; X32_LINUX-LABEL: f7:
 ; X32_LINUX:      movl %gs:i4@NTPOFF, %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f7:
+; X64_LINUX-LABEL: f7:
 ; X64_LINUX:      movl %fs:i4@TPOFF, %eax
 ; X64_LINUX-NEXT: ret
 
@@ -180,11 +180,11 @@ entry:
 }
 
 define i32* @f8() {
-; X32_LINUX: f8:
+; X32_LINUX-LABEL: f8:
 ; X32_LINUX:      movl %gs:0, %eax
 ; X32_LINUX-NEXT: leal i4@NTPOFF(%eax), %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f8:
+; X64_LINUX-LABEL: f8:
 ; X64_LINUX:      movq %fs:0, %rax
 ; X64_LINUX-NEXT: leaq i4@TPOFF(%rax), %rax
 ; X64_LINUX-NEXT: ret
@@ -194,10 +194,10 @@ entry:
 }
 
 define i32 @f9() {
-; X32_LINUX: f9:
+; X32_LINUX-LABEL: f9:
 ; X32_LINUX:      movl %gs:i5@NTPOFF, %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f9:
+; X64_LINUX-LABEL: f9:
 ; X64_LINUX:      movl %fs:i5@TPOFF, %eax
 ; X64_LINUX-NEXT: ret
 
@@ -207,11 +207,11 @@ entry:
 }
 
 define i32* @f10() {
-; X32_LINUX: f10:
+; X32_LINUX-LABEL: f10:
 ; X32_LINUX:      movl %gs:0, %eax
 ; X32_LINUX-NEXT: leal i5@NTPOFF(%eax), %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f10:
+; X64_LINUX-LABEL: f10:
 ; X64_LINUX:      movq %fs:0, %rax
 ; X64_LINUX-NEXT: leaq i5@TPOFF(%rax), %rax
 ; X64_LINUX-NEXT: ret
@@ -221,23 +221,23 @@ entry:
 }
 
 define i16 @f11() {
-; X32_LINUX: f11:
+; X32_LINUX-LABEL: f11:
 ; X32_LINUX:      movzwl %gs:s1@NTPOFF, %eax
 ; Why is this kill line here, but no where else?
 ; X32_LINUX-NEXT: # kill
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f11:
+; X64_LINUX-LABEL: f11:
 ; X64_LINUX:      movzwl %fs:s1@TPOFF, %eax
 ; X64_LINUX-NEXT: # kill
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f11:
+; X32_WIN-LABEL: f11:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: movzwl _s1@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: # kill
 ; X32_WIN-NEXT: ret
-; X64_WIN: f11:
+; X64_WIN-LABEL: f11:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -251,19 +251,19 @@ entry:
 }
 
 define i32 @f12() {
-; X32_LINUX: f12:
+; X32_LINUX-LABEL: f12:
 ; X32_LINUX:      movswl %gs:s1@NTPOFF, %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f12:
+; X64_LINUX-LABEL: f12:
 ; X64_LINUX:      movswl %fs:s1@TPOFF, %eax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f12:
+; X32_WIN-LABEL: f12:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: movswl _s1@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f12:
+; X64_WIN-LABEL: f12:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -277,19 +277,19 @@ entry:
 }
 
 define i8 @f13() {
-; X32_LINUX: f13:
+; X32_LINUX-LABEL: f13:
 ; X32_LINUX:      movb %gs:b1@NTPOFF, %al
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f13:
+; X64_LINUX-LABEL: f13:
 ; X64_LINUX:      movb %fs:b1@TPOFF, %al
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f13:
+; X32_WIN-LABEL: f13:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: movb _b1@SECREL32(%eax), %al
 ; X32_WIN-NEXT: ret
-; X64_WIN: f13:
+; X64_WIN-LABEL: f13:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -302,19 +302,19 @@ entry:
 }
 
 define i32 @f14() {
-; X32_LINUX: f14:
+; X32_LINUX-LABEL: f14:
 ; X32_LINUX:      movsbl %gs:b1@NTPOFF, %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f14:
+; X64_LINUX-LABEL: f14:
 ; X64_LINUX:      movsbl %fs:b1@TPOFF, %eax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f14:
+; X32_WIN-LABEL: f14:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: movsbl _b1@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f14:
+; X64_WIN-LABEL: f14:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
diff --git a/test/CodeGen/X86/tlv-1.ll b/test/CodeGen/X86/tlv-1.ll
index f970011..66e2f81 100644
--- a/test/CodeGen/X86/tlv-1.ll
+++ b/test/CodeGen/X86/tlv-1.ll
@@ -5,7 +5,7 @@
 @c = external thread_local global %struct.A, align 4
 
 define void @main() nounwind ssp {
-; CHECK: main:
+; CHECK-LABEL: main:
 entry:
   call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds (%struct.A* @c, i32 0, i32 0, i32 0), i8 0, i64 60, i32 1, i1 false)
   unreachable  
diff --git a/test/CodeGen/X86/umul-with-overflow.ll b/test/CodeGen/X86/umul-with-overflow.ll
index 52d1dc2..ba5a790 100644
--- a/test/CodeGen/X86/umul-with-overflow.ll
+++ b/test/CodeGen/X86/umul-with-overflow.ll
@@ -6,7 +6,7 @@ define zeroext i1 @a(i32 %x)  nounwind {
   %obil = extractvalue {i32, i1} %res, 1
   ret i1 %obil
   
-; CHECK: a:
+; CHECK-LABEL: a:
 ; CHECK: mull
 ; CHECK: seto %al
 ; CHECK: movzbl	%al, %eax
diff --git a/test/CodeGen/X86/unwind-init.ll b/test/CodeGen/X86/unwind-init.ll
index e34178d..d0915e2 100644
--- a/test/CodeGen/X86/unwind-init.ll
+++ b/test/CodeGen/X86/unwind-init.ll
@@ -12,7 +12,7 @@ define void @calls_unwind_init() {
   ret void
 }
 
-; X8664: calls_unwind_init:
+; X8664-LABEL: calls_unwind_init:
 ; X8664: pushq %rbp
 ; X8664: pushq %r15
 ; X8664: pushq %r14
@@ -25,7 +25,7 @@ define void @calls_unwind_init() {
 ; X8664: popq %r14
 ; X8664: popq %r15
 
-; X8632: calls_unwind_init:
+; X8632-LABEL: calls_unwind_init:
 ; X8632: pushl %ebp
 ; X8632: pushl %ebx
 ; X8632: pushl %edi
diff --git a/test/CodeGen/X86/vec-sign.ll b/test/CodeGen/X86/vec-sign.ll
index 31b9c2e..b3d85fd 100644
--- a/test/CodeGen/X86/vec-sign.ll
+++ b/test/CodeGen/X86/vec-sign.ll
@@ -2,7 +2,7 @@
 
 define <4 x i32> @signd(<4 x i32> %a, <4 x i32> %b) nounwind {
 entry:
-; CHECK: signd:
+; CHECK-LABEL: signd:
 ; CHECK: psignd
 ; CHECK-NOT: sub
 ; CHECK: ret
@@ -17,7 +17,7 @@ entry:
 
 define <4 x i32> @blendvb(<4 x i32> %b, <4 x i32> %a, <4 x i32> %c) nounwind {
 entry:
-; CHECK: blendvb:
+; CHECK-LABEL: blendvb:
 ; CHECK: pblendvb
 ; CHECK: ret
   %b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
diff --git a/test/CodeGen/X86/vec_insert-2.ll b/test/CodeGen/X86/vec_insert-2.ll
index dee91fd..bfac1ba 100644
--- a/test/CodeGen/X86/vec_insert-2.ll
+++ b/test/CodeGen/X86/vec_insert-2.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | FileCheck --check-prefix=X64 %s
 
 define <4 x float> @t1(float %s, <4 x float> %tmp) nounwind {
-; X32: t1:
+; X32-LABEL: t1:
 ; X32: shufps $36
 ; X32: ret
 
@@ -11,7 +11,7 @@ define <4 x float> @t1(float %s, <4 x float> %tmp) nounwind {
 }
 
 define <4 x i32> @t2(i32 %s, <4 x i32> %tmp) nounwind {
-; X32: t2:
+; X32-LABEL: t2:
 ; X32: shufps $36
 ; X32: ret
 
@@ -20,11 +20,11 @@ define <4 x i32> @t2(i32 %s, <4 x i32> %tmp) nounwind {
 }
 
 define <2 x double> @t3(double %s, <2 x double> %tmp) nounwind {
-; X32: t3:
+; X32-LABEL: t3:
 ; X32: movhpd
 ; X32: ret
 
-; X64: t3:
+; X64-LABEL: t3:
 ; X64: unpcklpd
 ; X64: ret
 
@@ -33,7 +33,7 @@ define <2 x double> @t3(double %s, <2 x double> %tmp) nounwind {
 }
 
 define <8 x i16> @t4(i16 %s, <8 x i16> %tmp) nounwind {
-; X32: t4:
+; X32-LABEL: t4:
 ; X32: pinsrw
 ; X32: ret
 
diff --git a/test/CodeGen/X86/vec_insert-5.ll b/test/CodeGen/X86/vec_insert-5.ll
index bd4a06d..5cb9f69 100644
--- a/test/CodeGen/X86/vec_insert-5.ll
+++ b/test/CodeGen/X86/vec_insert-5.ll
@@ -9,7 +9,7 @@ define void  @t1(i32 %a, x86_mmx* %P) nounwind {
        store x86_mmx %tmp23, x86_mmx* %P
        ret void
 
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK-NOT: %mm
 ; CHECK: shll $12
 ; CHECK-NOT: %mm
@@ -20,7 +20,7 @@ define <4 x float> @t2(<4 x float>* %P) nounwind {
         %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 4, i32 4, i32 4, i32 0 >
         ret <4 x float> %tmp2
 
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: pslldq $12
 }
 
@@ -29,7 +29,7 @@ define <4 x float> @t3(<4 x float>* %P) nounwind {
         %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 2, i32 3, i32 4, i32 4 >
         ret <4 x float> %tmp2
 
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: psrldq $8
 }
 
@@ -38,7 +38,7 @@ define <4 x float> @t4(<4 x float>* %P) nounwind {
         %tmp2 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp1, <4 x i32> < i32 7, i32 0, i32 0, i32 0 >
         ret <4 x float> %tmp2
 
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: psrldq $12
 }
 
@@ -46,7 +46,7 @@ define <16 x i8> @t5(<16 x i8> %x) nounwind {
         %s = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 17>
         ret <16 x i8> %s
 
-; CHECK: t5:
+; CHECK-LABEL: t5:
 ; CHECK: psrldq $1
 }
 
@@ -54,7 +54,7 @@ define <16 x i8> @t6(<16 x i8> %x) nounwind {
         %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
         ret <16 x i8> %s
 
-; CHECK: t6:
+; CHECK-LABEL: t6:
 ; CHECK: palignr $1
 }
 
@@ -62,6 +62,6 @@ define <16 x i8> @t7(<16 x i8> %x) nounwind {
         %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2>
         ret <16 x i8> %s
 
-; CHECK: t7:
+; CHECK-LABEL: t7:
 ; CHECK: pslldq $13
 }
diff --git a/test/CodeGen/X86/vec_shuffle-14.ll b/test/CodeGen/X86/vec_shuffle-14.ll
index 94da5d3..95e9a18 100644
--- a/test/CodeGen/X86/vec_shuffle-14.ll
+++ b/test/CodeGen/X86/vec_shuffle-14.ll
@@ -7,10 +7,10 @@ entry:
 	%tmp6 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp, <4 x i32> < i32 4, i32 1, i32 2, i32 3 >		; <<4 x i32>> [#uses=1]
 	ret <4 x i32> %tmp6
 
-; X86-32: t1:
+; X86-32-LABEL: t1:
 ; X86-32: movd	4(%esp), %xmm0
 
-; X86-64: t1:
+; X86-64-LABEL: t1:
 ; X86-64: movd	%e{{..}}, %xmm0
 }
 
@@ -20,10 +20,10 @@ entry:
 	%tmp6 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %tmp, <2 x i32> < i32 2, i32 1 >		; <<4 x i32>> [#uses=1]
 	ret <2 x i64> %tmp6
 
-; X86-32: t2:
+; X86-32-LABEL: t2:
 ; X86-32: movq	4(%esp), %xmm0
 
-; X86-64: t2:
+; X86-64-LABEL: t2:
 ; X86-64: movd	%r{{..}}, %xmm0
 }
 
@@ -35,11 +35,11 @@ entry:
 	%tmp8 = bitcast <4 x i32> %tmp7 to <2 x i64>		; <<2 x i64>> [#uses=1]
 	ret <2 x i64> %tmp8
 
-; X86-32: t3:
+; X86-32-LABEL: t3:
 ; X86-32: movl	4(%esp)
 ; X86-32: movq
 
-; X86-64: t3:
+; X86-64-LABEL: t3:
 ; X86-64: movq	({{.*}}), %xmm0
 }
 
@@ -50,10 +50,10 @@ entry:
 	%tmp7 = bitcast <4 x i32> %tmp6 to <2 x i64>		; <<2 x i64>> [#uses=1]
 	ret <2 x i64> %tmp7
 
-; X86-32: t4:
+; X86-32-LABEL: t4:
 ; X86-32: movq %xmm0, %xmm0
 
-; X86-64: t4:
+; X86-64-LABEL: t4:
 ; X86-64: movq {{.*}}, %xmm0
 }
 
@@ -62,9 +62,9 @@ entry:
 	%tmp6 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %a, <2 x i32> < i32 2, i32 1 >		; <<4 x i32>> [#uses=1]
 	ret <2 x i64> %tmp6
 
-; X86-32: t5:
+; X86-32-LABEL: t5:
 ; X86-32: movq %xmm0, %xmm0
 
-; X86-64: t5:
+; X86-64-LABEL: t5:
 ; X86-64: movq {{.*}}, %xmm0
 }
diff --git a/test/CodeGen/X86/vec_shuffle-16.ll b/test/CodeGen/X86/vec_shuffle-16.ll
index 09d4c1a..9aeb942 100644
--- a/test/CodeGen/X86/vec_shuffle-16.ll
+++ b/test/CodeGen/X86/vec_shuffle-16.ll
@@ -1,8 +1,8 @@
 ; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse,-sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse
 ; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse2
 
-; sse:  t1:
-; sse2: t1:
+; sse-LABEL:  t1:
+; sse2-LABEL: t1:
 define <4 x float> @t1(<4 x float> %a, <4 x float> %b) nounwind  {
 ; sse: shufps
 ; sse2: pshufd
@@ -11,8 +11,8 @@ define <4 x float> @t1(<4 x float> %a, <4 x float> %b) nounwind  {
         ret <4 x float> %tmp1
 }
 
-; sse:  t2:
-; sse2: t2:
+; sse-LABEL:  t2:
+; sse2-LABEL: t2:
 define <4 x float> @t2(<4 x float> %A, <4 x float> %B) nounwind {
 ; sse: shufps
 ; sse2: pshufd
@@ -21,8 +21,8 @@ define <4 x float> @t2(<4 x float> %A, <4 x float> %B) nounwind {
 	ret <4 x float> %tmp
 }
 
-; sse:  t3:
-; sse2: t3:
+; sse-LABEL:  t3:
+; sse2-LABEL: t3:
 define <4 x float> @t3(<4 x float> %A, <4 x float> %B) nounwind {
 ; sse: shufps
 ; sse2: pshufd
@@ -31,8 +31,8 @@ define <4 x float> @t3(<4 x float> %A, <4 x float> %B) nounwind {
 	ret <4 x float> %tmp
 }
 
-; sse:  t4:
-; sse2: t4:
+; sse-LABEL:  t4:
+; sse2-LABEL: t4:
 define <4 x float> @t4(<4 x float> %A, <4 x float> %B) nounwind {
 
 ; sse: shufps
diff --git a/test/CodeGen/X86/vec_shuffle-39.ll b/test/CodeGen/X86/vec_shuffle-39.ll
index ee8d2d5..1560454 100644
--- a/test/CodeGen/X86/vec_shuffle-39.ll
+++ b/test/CodeGen/X86/vec_shuffle-39.ll
@@ -3,7 +3,7 @@
 
 define <4 x float> @t1(<4 x float> %a, <1 x i64>* nocapture %p) nounwind {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: movlps (%rdi), %xmm0
 ; CHECK: ret
   %p.val = load <1 x i64>* %p, align 1
@@ -15,7 +15,7 @@ entry:
 
 define <4 x float> @t1a(<4 x float> %a, <1 x i64>* nocapture %p) nounwind {
 entry:
-; CHECK: t1a:
+; CHECK-LABEL: t1a:
 ; CHECK: movlps (%rdi), %xmm0
 ; CHECK: ret
   %0 = bitcast <1 x i64>* %p to double*
@@ -28,7 +28,7 @@ entry:
 
 define void @t2(<1 x i64>* nocapture %p, <4 x float> %a) nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: movlps %xmm0, (%rdi)
 ; CHECK: ret
   %cast.i = bitcast <4 x float> %a to <2 x i64>
@@ -40,7 +40,7 @@ entry:
 
 define void @t2a(<1 x i64>* nocapture %p, <4 x float> %a) nounwind {
 entry:
-; CHECK: t2a:
+; CHECK-LABEL: t2a:
 ; CHECK: movlps %xmm0, (%rdi)
 ; CHECK: ret
   %0 = bitcast <1 x i64>* %p to double*
@@ -53,7 +53,7 @@ entry:
 ; rdar://10436044
 define <2 x double> @t3() nounwind readonly {
 bb:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: punpcklqdq %xmm1, %xmm0
 ; CHECK: movq (%rax), %xmm1
 ; CHECK: movsd %xmm1, %xmm0
@@ -71,7 +71,7 @@ bb:
 ; rdar://10450317
 define <2 x i64> @t4() nounwind readonly {
 bb:
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: punpcklqdq %xmm0, %xmm1
 ; CHECK: movq (%rax), %xmm0
 ; CHECK: movsd %xmm1, %xmm0
diff --git a/test/CodeGen/X86/vec_splat-3.ll b/test/CodeGen/X86/vec_splat-3.ll
index cf0ecf4..60e3005 100644
--- a/test/CodeGen/X86/vec_splat-3.ll
+++ b/test/CodeGen/X86/vec_splat-3.ll
@@ -5,7 +5,7 @@ define <8 x i16> @shuf_8i16_0(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 0, i32 undef, i32 undef, i32 0, i32 undef, i32 undef, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_0:
+; CHECK-LABEL: shuf_8i16_0:
 ; CHECK: pshuflw $0
 }
 
@@ -13,7 +13,7 @@ define <8 x i16> @shuf_8i16_1(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_1:
+; CHECK-LABEL: shuf_8i16_1:
 ; CHECK: pshuflw $5
 }
 
@@ -21,7 +21,7 @@ define <8 x i16> @shuf_8i16_2(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_2:
+; CHECK-LABEL: shuf_8i16_2:
 ; CHECK: punpcklwd
 ; CHECK-NEXT: pshufd $-86
 }
@@ -30,7 +30,7 @@ define <8 x i16> @shuf_8i16_3(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 3, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_3:
+; CHECK-LABEL: shuf_8i16_3:
 ; CHECK: pshuflw $15
 }
 
@@ -38,7 +38,7 @@ define <8 x i16> @shuf_8i16_4(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 4, i32 undef, i32 undef, i32 undef, i32 4, i32 undef, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_4:
+; CHECK-LABEL: shuf_8i16_4:
 ; CHECK: movhlps
 }
 
@@ -46,7 +46,7 @@ define <8 x i16> @shuf_8i16_5(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 5, i32 undef, i32 undef, i32 5, i32 undef, i32 undef, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_5:
+; CHECK-LABEL: shuf_8i16_5:
 ; CHECK: punpckhwd
 ; CHECK-NEXT: pshufd $85
 }
@@ -55,7 +55,7 @@ define <8 x i16> @shuf_8i16_6(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 6, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_6:
+; CHECK-LABEL: shuf_8i16_6:
 ; CHECK: punpckhwd
 ; CHECK-NEXT: pshufd $-86
 }
@@ -64,7 +64,7 @@ define <8 x i16> @shuf_8i16_7(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 7, i32 undef, i32 undef, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_7:
+; CHECK-LABEL: shuf_8i16_7:
 ; CHECK: punpckhwd
 ; CHECK-NEXT: pshufd $-1
 }
@@ -74,7 +74,7 @@ define <16 x i8> @shuf_16i8_8(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 0, i32 undef, i32 undef, i32 0, i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_8:
+; CHECK-LABEL: shuf_16i8_8:
 ; CHECK: punpcklbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $0
@@ -84,7 +84,7 @@ define <16 x i8> @shuf_16i8_9(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef >
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_9:
+; CHECK-LABEL: shuf_16i8_9:
 ; CHECK: punpcklbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $85
@@ -94,7 +94,7 @@ define <16 x i8> @shuf_16i8_10(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_10:
+; CHECK-LABEL: shuf_16i8_10:
 ; CHECK: punpcklbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $-86
@@ -104,7 +104,7 @@ define <16 x i8> @shuf_16i8_11(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 3, i32 undef, i32 undef, i32 3, i32 undef, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_11:
+; CHECK-LABEL: shuf_16i8_11:
 ; CHECK: punpcklbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $-1
@@ -115,7 +115,7 @@ define <16 x i8> @shuf_16i8_12(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 4, i32 undef, i32 undef, i32 undef, i32 4, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef >
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_12:
+; CHECK-LABEL: shuf_16i8_12:
 ; CHECK: pshufd $5
 }
 
@@ -123,7 +123,7 @@ define <16 x i8> @shuf_16i8_13(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 5, i32 undef, i32 undef, i32 5, i32 undef, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_13:
+; CHECK-LABEL: shuf_16i8_13:
 ; CHECK: punpcklbw
 ; CHECK-NEXT: punpckhbw
 ; CHECK-NEXT: pshufd $85
@@ -133,7 +133,7 @@ define <16 x i8> @shuf_16i8_14(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 6, i32 undef, i32 undef, i32 6, i32 undef, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_14:
+; CHECK-LABEL: shuf_16i8_14:
 ; CHECK: punpcklbw
 ; CHECK-NEXT: punpckhbw
 ; CHECK-NEXT: pshufd $-86
@@ -143,7 +143,7 @@ define <16 x i8> @shuf_16i8_15(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 7, i32 undef, i32 undef, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef >
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_15:
+; CHECK-LABEL: shuf_16i8_15:
 ; CHECK: punpcklbw
 ; CHECK-NEXT: punpckhbw
 ; CHECK-NEXT: pshufd $-1
@@ -153,7 +153,7 @@ define <16 x i8> @shuf_16i8_16(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 8, i32 undef, i32 undef, i32 8, i32 undef, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_16:
+; CHECK-LABEL: shuf_16i8_16:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $0
@@ -163,7 +163,7 @@ define <16 x i8> @shuf_16i8_17(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 9, i32 undef, i32 undef, i32 9, i32 undef, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_17:
+; CHECK-LABEL: shuf_16i8_17:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $85
@@ -173,7 +173,7 @@ define <16 x i8> @shuf_16i8_18(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 10, i32 undef, i32 undef, i32 10, i32 undef, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_18:
+; CHECK-LABEL: shuf_16i8_18:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $-86
@@ -183,7 +183,7 @@ define <16 x i8> @shuf_16i8_19(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 11, i32 undef, i32 undef, i32 11, i32 undef, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_19:
+; CHECK-LABEL: shuf_16i8_19:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $-1
@@ -193,7 +193,7 @@ define <16 x i8> @shuf_16i8_20(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 12, i32 undef, i32 undef, i32 12, i32 undef, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_20:
+; CHECK-LABEL: shuf_16i8_20:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpckhbw
 ; CHECK-NEXT: pshufd $0
@@ -203,7 +203,7 @@ define <16 x i8> @shuf_16i8_21(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 13, i32 undef, i32 undef, i32 13, i32 undef, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_21:
+; CHECK-LABEL: shuf_16i8_21:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpckhbw
 ; CHECK-NEXT: pshufd $85
@@ -213,7 +213,7 @@ define <16 x i8> @shuf_16i8_22(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 14, i32 undef, i32 undef, i32 14, i32 undef, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_22:
+; CHECK-LABEL: shuf_16i8_22:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpckhbw
 ; CHECK-NEXT: pshufd $-86
@@ -223,7 +223,7 @@ define <16 x i8> @shuf_16i8_23(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 15, i32 undef, i32 undef, i32 15, i32 undef, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_23:
+; CHECK-LABEL: shuf_16i8_23:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpckhbw
 ; CHECK-NEXT: pshufd $-1
diff --git a/test/CodeGen/X86/vector-gep.ll b/test/CodeGen/X86/vector-gep.ll
index ec93ce0..b87d844 100644
--- a/test/CodeGen/X86/vector-gep.ll
+++ b/test/CodeGen/X86/vector-gep.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86 -mcpu=corei7-avx | FileCheck %s
 ; RUN: opt -instsimplify -disable-output < %s
 
-;CHECK: AGEP0:
+;CHECK-LABEL: AGEP0:
 define <4 x i32*> @AGEP0(i32* %ptr) nounwind {
 entry:
   %vecinit.i = insertelement <4 x i32*> undef, i32* %ptr, i32 0
@@ -16,7 +16,7 @@ entry:
 ;CHECK: ret
 }
 
-;CHECK: AGEP1:
+;CHECK-LABEL: AGEP1:
 define i32 @AGEP1(<4 x i32*> %param) nounwind {
 entry:
 ;CHECK: padd
@@ -27,7 +27,7 @@ entry:
 ;CHECK: ret
 }
 
-;CHECK: AGEP2:
+;CHECK-LABEL: AGEP2:
 define i32 @AGEP2(<4 x i32*> %param, <4 x i32> %off) nounwind {
 entry:
 ;CHECK: pslld $2
@@ -39,7 +39,7 @@ entry:
 ;CHECK: ret
 }
 
-;CHECK: AGEP3:
+;CHECK-LABEL: AGEP3:
 define <4 x i32*> @AGEP3(<4 x i32*> %param, <4 x i32> %off) nounwind {
 entry:
 ;CHECK: pslld $2
@@ -51,7 +51,7 @@ entry:
 ;CHECK: ret
 }
 
-;CHECK: AGEP4:
+;CHECK-LABEL: AGEP4:
 define <4 x i16*> @AGEP4(<4 x i16*> %param, <4 x i32> %off) nounwind {
 entry:
 ; Multiply offset by two (add it to itself).
@@ -63,7 +63,7 @@ entry:
 ;CHECK: ret
 }
 
-;CHECK: AGEP5:
+;CHECK-LABEL: AGEP5:
 define <4 x i8*> @AGEP5(<4 x i8*> %param, <4 x i8> %off) nounwind {
 entry:
 ;CHECK: paddd
@@ -74,7 +74,7 @@ entry:
 
 
 ; The size of each element is 1 byte. No need to multiply by element size.
-;CHECK: AGEP6:
+;CHECK-LABEL: AGEP6:
 define <4 x i8*> @AGEP6(<4 x i8*> %param, <4 x i32> %off) nounwind {
 entry:
 ;CHECK-NOT: pslld
diff --git a/test/CodeGen/X86/vshift-1.ll b/test/CodeGen/X86/vshift-1.ll
index e775750..b6e4b5b 100644
--- a/test/CodeGen/X86/vshift-1.ll
+++ b/test/CodeGen/X86/vshift-1.ll
@@ -5,7 +5,7 @@
 
 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
 entry:
-; CHECK: shift1a:
+; CHECK-LABEL: shift1a:
 ; CHECK: psllq
   %shl = shl <2 x i64> %val, < i64 32, i64 32 >
   store <2 x i64> %shl, <2 x i64>* %dst
@@ -14,7 +14,7 @@ entry:
 
 define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
 entry:
-; CHECK: shift1b:
+; CHECK-LABEL: shift1b:
 ; CHECK: movd
 ; CHECK: psllq
   %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
@@ -27,7 +27,7 @@ entry:
 
 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
 entry:
-; CHECK: shift2a:
+; CHECK-LABEL: shift2a:
 ; CHECK: pslld
   %shl = shl <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
   store <4 x i32> %shl, <4 x i32>* %dst
@@ -36,7 +36,7 @@ entry:
 
 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
 entry:
-; CHECK: shift2b:
+; CHECK-LABEL: shift2b:
 ; CHECK: movd
 ; CHECK: pslld
   %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
@@ -50,7 +50,7 @@ entry:
 
 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
 entry:
-; CHECK: shift3a:
+; CHECK-LABEL: shift3a:
 ; CHECK: psllw
   %shl = shl <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
   store <8 x i16> %shl, <8 x i16>* %dst
@@ -60,7 +60,7 @@ entry:
 ; Make sure the shift amount is properly zero extended.
 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
 entry:
-; CHECK: shift3b:
+; CHECK-LABEL: shift3b:
 ; CHECK: movzwl
 ; CHECK: movd
 ; CHECK-NEXT: psllw
diff --git a/test/CodeGen/X86/vshift-2.ll b/test/CodeGen/X86/vshift-2.ll
index 9496893..0b1597c 100644
--- a/test/CodeGen/X86/vshift-2.ll
+++ b/test/CodeGen/X86/vshift-2.ll
@@ -5,7 +5,7 @@
 
 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
 entry:
-; CHECK: shift1a:
+; CHECK-LABEL: shift1a:
 ; CHECK: psrlq
   %lshr = lshr <2 x i64> %val, < i64 32, i64 32 >
   store <2 x i64> %lshr, <2 x i64>* %dst
@@ -14,7 +14,7 @@ entry:
 
 define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
 entry:
-; CHECK: shift1b:
+; CHECK-LABEL: shift1b:
 ; CHECK: movd
 ; CHECK: psrlq
   %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
@@ -26,7 +26,7 @@ entry:
 
 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
 entry:
-; CHECK: shift2a:
+; CHECK-LABEL: shift2a:
 ; CHECK: psrld
   %lshr = lshr <4 x i32> %val, < i32 17, i32 17, i32 17, i32 17 >
   store <4 x i32> %lshr, <4 x i32>* %dst
@@ -35,7 +35,7 @@ entry:
 
 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
 entry:
-; CHECK: shift2b:
+; CHECK-LABEL: shift2b:
 ; CHECK: movd
 ; CHECK: psrld
   %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
@@ -50,7 +50,7 @@ entry:
 
 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
 entry:
-; CHECK: shift3a:
+; CHECK-LABEL: shift3a:
 ; CHECK: psrlw
   %lshr = lshr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
   store <8 x i16> %lshr, <8 x i16>* %dst
@@ -60,7 +60,7 @@ entry:
 ; properly zero extend the shift amount
 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
 entry:
-; CHECK: shift3b:
+; CHECK-LABEL: shift3b:
 ; CHECK: movzwl
 ; CHECK: movd
 ; CHECK: psrlw
diff --git a/test/CodeGen/X86/vshift-3.ll b/test/CodeGen/X86/vshift-3.ll
index b2b48b9..9b484a7 100644
--- a/test/CodeGen/X86/vshift-3.ll
+++ b/test/CodeGen/X86/vshift-3.ll
@@ -8,7 +8,7 @@
 ; shift1a can't use a packed shift
 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
 entry:
-; CHECK: shift1a:
+; CHECK-LABEL: shift1a:
 ; CHECK: sarl
   %ashr = ashr <2 x i64> %val, < i64 32, i64 32 >
   store <2 x i64> %ashr, <2 x i64>* %dst
@@ -17,7 +17,7 @@ entry:
 
 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
 entry:
-; CHECK: shift2a:
+; CHECK-LABEL: shift2a:
 ; CHECK: psrad	$5
   %ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
   store <4 x i32> %ashr, <4 x i32>* %dst
@@ -26,7 +26,7 @@ entry:
 
 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
 entry:
-; CHECK: shift2b:
+; CHECK-LABEL: shift2b:
 ; CHECK: movd
 ; CHECK: psrad
   %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
@@ -40,7 +40,7 @@ entry:
 
 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
 entry:
-; CHECK: shift3a:
+; CHECK-LABEL: shift3a:
 ; CHECK: psraw	$5
   %ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
   store <8 x i16> %ashr, <8 x i16>* %dst
@@ -49,7 +49,7 @@ entry:
 
 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
 entry:
-; CHECK: shift3b:
+; CHECK-LABEL: shift3b:
 ; CHECK: movzwl
 ; CHECK: movd
 ; CHECK: psraw
diff --git a/test/CodeGen/X86/vshift-4.ll b/test/CodeGen/X86/vshift-4.ll
index 8e24fda..c597c25 100644
--- a/test/CodeGen/X86/vshift-4.ll
+++ b/test/CodeGen/X86/vshift-4.ll
@@ -5,7 +5,7 @@
 
 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
 entry:
-; CHECK: shift1a:
+; CHECK-LABEL: shift1a:
 ; CHECK: psllq
   %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
   %shl = shl <2 x i64> %val, %shamt
@@ -16,7 +16,7 @@ entry:
 ; shift1b can't use a packed shift
 define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
 entry:
-; CHECK: shift1b:
+; CHECK-LABEL: shift1b:
 ; CHECK: shll
   %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
   %shl = shl <2 x i64> %val, %shamt
@@ -26,7 +26,7 @@ entry:
 
 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
 entry:
-; CHECK: shift2a:
+; CHECK-LABEL: shift2a:
 ; CHECK: pslld
   %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %shl = shl <4 x i32> %val, %shamt
@@ -36,7 +36,7 @@ entry:
 
 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
 entry:
-; CHECK: shift2b:
+; CHECK-LABEL: shift2b:
 ; CHECK: pslld
   %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
   %shl = shl <4 x i32> %val, %shamt
@@ -46,7 +46,7 @@ entry:
 
 define void @shift2c(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
 entry:
-; CHECK: shift2c:
+; CHECK-LABEL: shift2c:
 ; CHECK: pslld
   %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %shl = shl <4 x i32> %val, %shamt
@@ -56,7 +56,7 @@ entry:
 
 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
 entry:
-; CHECK: shift3a:
+; CHECK-LABEL: shift3a:
 ; CHECK: movzwl
 ; CHECK: psllw
   %shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
@@ -67,7 +67,7 @@ entry:
 
 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
 entry:
-; CHECK: shift3b:
+; CHECK-LABEL: shift3b:
 ; CHECK: movzwl
 ; CHECK: psllw
   %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
diff --git a/test/CodeGen/X86/vshift-5.ll b/test/CodeGen/X86/vshift-5.ll
index f6c311d..562e520 100644
--- a/test/CodeGen/X86/vshift-5.ll
+++ b/test/CodeGen/X86/vshift-5.ll
@@ -4,7 +4,7 @@
 
 define void @shift5a(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
 entry:
-; CHECK: shift5a:
+; CHECK-LABEL: shift5a:
 ; CHECK: movd
 ; CHECK: pslld
   %amt = load i32* %pamt 
@@ -18,7 +18,7 @@ entry:
 
 define void @shift5b(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
 entry:
-; CHECK: shift5b:
+; CHECK-LABEL: shift5b:
 ; CHECK: movd
 ; CHECK: psrad
   %amt = load i32* %pamt 
@@ -32,7 +32,7 @@ entry:
 
 define void @shift5c(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
 entry:
-; CHECK: shift5c:
+; CHECK-LABEL: shift5c:
 ; CHECK: movd
 ; CHECK: pslld
   %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
@@ -45,7 +45,7 @@ entry:
 
 define void @shift5d(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
 entry:
-; CHECK: shift5d:
+; CHECK-LABEL: shift5d:
 ; CHECK: movd
 ; CHECK: psrad
   %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
diff --git a/test/CodeGen/X86/widen_extract-1.ll b/test/CodeGen/X86/widen_extract-1.ll
index 8672742..c4fe43a 100644
--- a/test/CodeGen/X86/widen_extract-1.ll
+++ b/test/CodeGen/X86/widen_extract-1.ll
@@ -3,7 +3,7 @@
 
 define void @convert(<2 x double>* %dst.addr, <3 x double> %src)  {
 entry:
-; CHECK: convert:
+; CHECK-LABEL: convert:
 ; CHECK: unpcklpd {{%xmm[0-7]}}, {{%xmm[0-7]}}
 ; CHECK-NEXT: movapd
   %val = shufflevector <3 x double> %src, <3 x double> undef, <2 x i32> < i32 0, i32 1>
diff --git a/test/CodeGen/X86/widen_load-2.ll b/test/CodeGen/X86/widen_load-2.ll
index 224898c..2781dcf 100644
--- a/test/CodeGen/X86/widen_load-2.ll
+++ b/test/CodeGen/X86/widen_load-2.ll
@@ -148,7 +148,7 @@ define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) no
 	ret void
 }
 
-; CHECK: add31i8:
+; CHECK-LABEL: add31i8:
 %i8vec31 = type <31 x i8>
 define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind {
 ; CHECK: movdqa
diff --git a/test/CodeGen/X86/widen_shuffle-1.ll b/test/CodeGen/X86/widen_shuffle-1.ll
index 7bebb27..c7d2044 100644
--- a/test/CodeGen/X86/widen_shuffle-1.ll
+++ b/test/CodeGen/X86/widen_shuffle-1.ll
@@ -3,7 +3,7 @@
 ; widening shuffle v3float and then a add
 define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
 entry:
-; CHECK: shuf:
+; CHECK-LABEL: shuf:
 ; CHECK: extractps
 ; CHECK: extractps
 	%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2>
@@ -17,7 +17,7 @@ entry:
 ; widening shuffle v3float with a different mask and then a add
 define void @shuf2(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
 entry:
-; CHECK: shuf2:
+; CHECK-LABEL: shuf2:
 ; CHECK: extractps
 ; CHECK: extractps
 	%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2>
@@ -32,7 +32,7 @@ entry:
 ; opA with opB, the DAG will produce new operations with opA.
 define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) nounwind {
 entry:
-; CHECK: shuf3:
+; CHECK-LABEL: shuf3:
 ; CHECK: shufps
   %shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
   %tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> 
@@ -52,7 +52,7 @@ entry:
 
 ; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS
 define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone {
-; CHECK: shuf4:
+; CHECK-LABEL: shuf4:
 ; CHECK-NOT: punpckldq
   %vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i8> %vshuf
@@ -61,7 +61,7 @@ define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone {
 
 ; PR11389: another CONCAT_VECTORS case
 define void @shuf5(<8 x i8>* %p) nounwind {
-; CHECK: shuf5:
+; CHECK-LABEL: shuf5:
   %v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   store <8 x i8> %v, <8 x i8>* %p, align 8
   ret void
diff --git a/test/CodeGen/X86/win64_vararg.ll b/test/CodeGen/X86/win64_vararg.ll
index 52bc509..74b7cea 100644
--- a/test/CodeGen/X86/win64_vararg.ll
+++ b/test/CodeGen/X86/win64_vararg.ll
@@ -19,7 +19,7 @@ entry:
 
 declare void @llvm.va_start(i8*) nounwind
 
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: pushq
 ; CHECK: leaq 56(%rsp),
 define i8* @f5(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, ...) nounwind {
@@ -30,7 +30,7 @@ entry:
   ret i8* %ap1
 }
 
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: pushq
 ; CHECK: leaq 48(%rsp),
 define i8* @f4(i64 %a0, i64 %a1, i64 %a2, i64 %a3, ...) nounwind {
@@ -41,7 +41,7 @@ entry:
   ret i8* %ap1
 }
 
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: pushq
 ; CHECK: leaq 40(%rsp),
 define i8* @f3(i64 %a0, i64 %a1, i64 %a2, ...) nounwind {
diff --git a/test/CodeGen/X86/x86-64-and-mask.ll b/test/CodeGen/X86/x86-64-and-mask.ll
index 1de406c..e8c628d 100644
--- a/test/CodeGen/X86/x86-64-and-mask.ll
+++ b/test/CodeGen/X86/x86-64-and-mask.ll
@@ -14,7 +14,7 @@ entry:
 }
 
 ; This copy can't be coalesced away because it needs the implicit zero-extend.
-; CHECK: bbb:
+; CHECK-LABEL: bbb:
 ; CHECK: movl %edi, %edi
 
 define void @bbb(i64 %x) nounwind {
@@ -26,7 +26,7 @@ define void @bbb(i64 %x) nounwind {
 ; This should use a 32-bit and with implicit zero-extension, not a 64-bit and
 ; with a separate mov to materialize the mask.
 ; rdar://7527390
-; CHECK: ccc:
+; CHECK-LABEL: ccc:
 ; CHECK: andl $-1048593, %edi
 
 declare void @foo(i64 %x) nounwind
@@ -38,7 +38,7 @@ define void @ccc(i64 %x) nounwind {
 }
 
 ; This requires a mov and a 64-bit and.
-; CHECK: ddd:
+; CHECK-LABEL: ddd:
 ; CHECK: movabsq $4294967296, %r
 ; CHECK: andq %rax, %rdi
 
diff --git a/test/CodeGen/X86/x86-64-sret-return.ll b/test/CodeGen/X86/x86-64-sret-return.ll
index bc8a543..2d00114 100644
--- a/test/CodeGen/X86/x86-64-sret-return.ll
+++ b/test/CodeGen/X86/x86-64-sret-return.ll
@@ -4,11 +4,11 @@
 
 %struct.foo = type { [4 x i64] }
 
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: movq %rdi, %rax
 
 ; For the x32 ABI, pointers are 32-bit so 32-bit instructions will be used
-; X32ABI: bar:
+; X32ABI-LABEL: bar:
 ; X32ABI: movl %edi, %eax
 
 define void @bar(%struct.foo* noalias sret  %agg.result, %struct.foo* %d) nounwind  {
@@ -60,11 +60,11 @@ return:		; preds = %entry
 	ret void
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: movq %rdi, %rax
 
 ; For the x32 ABI, pointers are 32-bit so 32-bit instructions will be used
-; X32ABI: foo:
+; X32ABI-LABEL: foo:
 ; X32ABI: movl %edi, %eax
 
 define void @foo({ i64 }* noalias nocapture sret %agg.result) nounwind {
diff --git a/test/CodeGen/X86/x86-shifts.ll b/test/CodeGen/X86/x86-shifts.ll
index 20bccab..af57e5c 100644
--- a/test/CodeGen/X86/x86-shifts.ll
+++ b/test/CodeGen/X86/x86-shifts.ll
@@ -156,7 +156,7 @@ entry:
 define <16 x i8> @shl9(<16 x i8> %A) nounwind {
   %B = shl <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <16 x i8> %B
-; CHECK: shl9:
+; CHECK-LABEL: shl9:
 ; CHECK: psllw $3
 ; CHECK: pand
 ; CHECK: ret
@@ -165,7 +165,7 @@ define <16 x i8> @shl9(<16 x i8> %A) nounwind {
 define <16 x i8> @shr9(<16 x i8> %A) nounwind {
   %B = lshr <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <16 x i8> %B
-; CHECK: shr9:
+; CHECK-LABEL: shr9:
 ; CHECK: psrlw $3
 ; CHECK: pand
 ; CHECK: ret
@@ -174,7 +174,7 @@ define <16 x i8> @shr9(<16 x i8> %A) nounwind {
 define <16 x i8> @sra_v16i8_7(<16 x i8> %A) nounwind {
   %B = ashr <16 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
   ret <16 x i8> %B
-; CHECK: sra_v16i8_7:
+; CHECK-LABEL: sra_v16i8_7:
 ; CHECK: pxor
 ; CHECK: pcmpgtb
 ; CHECK: ret
@@ -183,7 +183,7 @@ define <16 x i8> @sra_v16i8_7(<16 x i8> %A) nounwind {
 define <16 x i8> @sra_v16i8(<16 x i8> %A) nounwind {
   %B = ashr <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <16 x i8> %B
-; CHECK: sra_v16i8:
+; CHECK-LABEL: sra_v16i8:
 ; CHECK: psrlw $3
 ; CHECK: pand
 ; CHECK: pxor
diff --git a/test/CodeGen/X86/xmulo.ll b/test/CodeGen/X86/xmulo.ll
index 486dafe..71efac4 100644
--- a/test/CodeGen/X86/xmulo.ll
+++ b/test/CodeGen/X86/xmulo.ll
@@ -8,7 +8,7 @@ declare i32 @printf(i8*, ...)
 @.str = private unnamed_addr constant [10 x i8] c"%llx, %d\0A\00", align 1
 
 define i32 @t1() nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK:  movl $0, 12(%esp)
 ; CHECK:  movl $0, 8(%esp)
 ; CHECK:  movl $72, 4(%esp)
@@ -22,7 +22,7 @@ define i32 @t1() nounwind {
 }
 
 define i32 @t2() nounwind {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK:  movl $0, 12(%esp)
 ; CHECK:  movl $0, 8(%esp)
 ; CHECK:  movl $0, 4(%esp)
@@ -36,7 +36,7 @@ define i32 @t2() nounwind {
 }
 
 define i32 @t3() nounwind {
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK:  movl $1, 12(%esp)
 ; CHECK:  movl $-1, 8(%esp)
 ; CHECK:  movl $-9, 4(%esp)
diff --git a/test/CodeGen/X86/xor-icmp.ll b/test/CodeGen/X86/xor-icmp.ll
index fd1b006..dd1fcca 100644
--- a/test/CodeGen/X86/xor-icmp.ll
+++ b/test/CodeGen/X86/xor-icmp.ll
@@ -4,14 +4,14 @@
 
 define i32 @t(i32 %a, i32 %b) nounwind ssp {
 entry:
-; X32:     t:
+; X32-LABEL:     t:
 ; X32:     xorb
 ; X32-NOT: andb
 ; X32-NOT: shrb
 ; X32:     testb $64
 ; X32:     je
 
-; X64:     t:
+; X64-LABEL:     t:
 ; X64-NOT: setne
 ; X64:     xorl
 ; X64:     testb $64
@@ -37,7 +37,7 @@ declare i32 @foo(...)
 declare i32 @bar(...)
 
 define i32 @t2(i32 %x, i32 %y) nounwind ssp {
-; X32: t2:
+; X32-LABEL: t2:
 ; X32: cmpl
 ; X32: sete
 ; X32: cmpl
@@ -45,7 +45,7 @@ define i32 @t2(i32 %x, i32 %y) nounwind ssp {
 ; X32-NOT: xor
 ; X32: je
 
-; X64: t2:
+; X64-LABEL: t2:
 ; X64: testl
 ; X64: sete
 ; X64: testl
diff --git a/test/CodeGen/X86/zero-remat.ll b/test/CodeGen/X86/zero-remat.ll
index 5d25a2d..e3c3c5e 100644
--- a/test/CodeGen/X86/zero-remat.ll
+++ b/test/CodeGen/X86/zero-remat.ll
@@ -11,12 +11,12 @@ define double @foo() nounwind {
   call void @bar(double 0.0)
   ret double 0.0
 
-;CHECK-32: foo:
+;CHECK-32-LABEL: foo:
 ;CHECK-32: call
 ;CHECK-32: fldz
 ;CHECK-32: ret
 
-;CHECK-64: foo:
+;CHECK-64-LABEL: foo:
 ;CHECK-64: xorps
 ;CHECK-64: call
 ;CHECK-64: xorps
@@ -28,12 +28,12 @@ define float @foof() nounwind {
   call void @barf(float 0.0)
   ret float 0.0
 
-;CHECK-32: foof:
+;CHECK-32-LABEL: foof:
 ;CHECK-32: call
 ;CHECK-32: fldz
 ;CHECK-32: ret
 
-;CHECK-64: foof:
+;CHECK-64-LABEL: foof:
 ;CHECK-64: xorps
 ;CHECK-64: call
 ;CHECK-64: xorps
diff --git a/test/CodeGen/X86/zext-extract_subreg.ll b/test/CodeGen/X86/zext-extract_subreg.ll
index 7fa0574..43e79c7 100644
--- a/test/CodeGen/X86/zext-extract_subreg.ll
+++ b/test/CodeGen/X86/zext-extract_subreg.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
 
 define void @t() nounwind ssp {
-; CHECK: t:
+; CHECK-LABEL: t:
 entry:
   br i1 undef, label %return, label %if.end.i
 
diff --git a/test/CodeGen/X86/zext-shl.ll b/test/CodeGen/X86/zext-shl.ll
index 928848e..ac3ecc8 100644
--- a/test/CodeGen/X86/zext-shl.ll
+++ b/test/CodeGen/X86/zext-shl.ll
@@ -2,7 +2,7 @@
 
 define i32 @t1(i8 zeroext %x) nounwind readnone ssp {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: shll
 ; CHECK-NOT: movzwl
 ; CHECK: ret
@@ -14,7 +14,7 @@ entry:
 
 define i32 @t2(i8 zeroext %x) nounwind readnone ssp {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: shrl
 ; CHECK-NOT: movzwl
 ; CHECK: ret
diff --git a/test/CodeGen/X86/zext-trunc.ll b/test/CodeGen/X86/zext-trunc.ll
index b9ffbe8..32afd6b 100644
--- a/test/CodeGen/X86/zext-trunc.ll
+++ b/test/CodeGen/X86/zext-trunc.ll
@@ -2,7 +2,7 @@
 ; rdar://7570931
 
 define i64 @foo(i64 %a, i64 %b) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: leal
 ; CHECK-NOT: movl
 ; CHECK: ret
diff --git a/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll b/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll
index 84e21e4..2a04963 100644
--- a/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll
+++ b/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll
@@ -13,7 +13,7 @@ allocas:
   call void @llvm.stackrestore(i8* %0)
   ret void
 }
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: ldaw [[REGISTER:r[0-9]+]], {{r[0-9]+}}[-r1]
 ; CHECK: set sp, [[REGISTER]]
 ; CHECK: extsp 1
diff --git a/test/CodeGen/XCore/2011-08-01-VarargsBug.ll b/test/CodeGen/XCore/2011-08-01-VarargsBug.ll
index 2076057..6445a8f 100644
--- a/test/CodeGen/XCore/2011-08-01-VarargsBug.ll
+++ b/test/CodeGen/XCore/2011-08-01-VarargsBug.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=xcore | FileCheck %s
 define void @_Z1fz(...) {
 entry:
-; CHECK: _Z1fz:
+; CHECK-LABEL: _Z1fz:
 ; CHECK: extsp 3
 ; CHECK: stw r[[REG:[0-3]{1,1}]]
 ; CHECK: , sp{{\[}}[[REG]]{{\]}}
diff --git a/test/CodeGen/XCore/addsub64.ll b/test/CodeGen/XCore/addsub64.ll
index d062480..89271ce 100644
--- a/test/CodeGen/XCore/addsub64.ll
+++ b/test/CodeGen/XCore/addsub64.ll
@@ -27,7 +27,7 @@ entry:
 	%3 = add i64 %2, %a
 	ret i64 %3
 }
-; CHECK: maccu:
+; CHECK-LABEL: maccu:
 ; CHECK: maccu r1, r0, r3, r2
 ; CHECK-NEXT: retsp 0
 
@@ -39,7 +39,7 @@ entry:
 	%3 = add i64 %2, %a
 	ret i64 %3
 }
-; CHECK: maccs:
+; CHECK-LABEL: maccs:
 ; CHECK: maccs r1, r0, r3, r2
 ; CHECK-NEXT: retsp 0
 
@@ -54,6 +54,6 @@ entry:
 	%6 = add i64 %5, %3
 	ret i64 %6
 }
-; CHECK: lmul:
+; CHECK-LABEL: lmul:
 ; CHECK: lmul r1, r0, r1, r0, r2, r3
 ; CHECK-NEXT: retsp 0
diff --git a/test/CodeGen/XCore/aliases.ll b/test/CodeGen/XCore/aliases.ll
index d83b246..d4da63c 100644
--- a/test/CodeGen/XCore/aliases.ll
+++ b/test/CodeGen/XCore/aliases.ll
@@ -7,7 +7,7 @@ declare void @a_val() nounwind
 @b = alias i32* @b_val
 @c = alias i32* @c_val
 
-; CHECK: a_addr:
+; CHECK-LABEL: a_addr:
 ; CHECK: ldap r11, a
 ; CHECK: retsp
 define void ()* @a_addr() nounwind {
@@ -15,7 +15,7 @@ entry:
   ret void ()* @a
 }
 
-; CHECK: b_addr:
+; CHECK-LABEL: b_addr:
 ; CHECK: ldaw r11, cp[b]
 ; CHECK: retsp
 define i32 *@b_addr() nounwind {
@@ -23,7 +23,7 @@ entry:
   ret i32* @b
 }
 
-; CHECK: c_addr:
+; CHECK-LABEL: c_addr:
 ; CHECK: ldaw r0, dp[c]
 ; CHECK: retsp
 define i32 *@c_addr() nounwind {
diff --git a/test/CodeGen/XCore/ashr.ll b/test/CodeGen/XCore/ashr.ll
index 03b6b1f..2752f52 100644
--- a/test/CodeGen/XCore/ashr.ll
+++ b/test/CodeGen/XCore/ashr.ll
@@ -3,21 +3,21 @@ define i32 @ashr(i32 %a, i32 %b) {
 	%1 = ashr i32 %a, %b
 	ret i32 %1
 }
-; CHECK: ashr:
+; CHECK-LABEL: ashr:
 ; CHECK-NEXT: ashr r0, r0, r1
 
 define i32 @ashri1(i32 %a) {
 	%1 = ashr i32 %a, 24
 	ret i32 %1
 }
-; CHECK: ashri1:
+; CHECK-LABEL: ashri1:
 ; CHECK-NEXT: ashr r0, r0, 24
 
 define i32 @ashri2(i32 %a) {
 	%1 = ashr i32 %a, 31
 	ret i32 %1
 }
-; CHECK: ashri2:
+; CHECK-LABEL: ashri2:
 ; CHECK-NEXT: ashr r0, r0, 32
 
 define i32 @f1(i32 %a) {
@@ -28,7 +28,7 @@ less:
 not_less:
 	ret i32 17
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NEXT: ashr r0, r0, 32
 ; CHECK-NEXT: bt r0
 
@@ -40,7 +40,7 @@ greater:
 not_greater:
 	ret i32 17
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NEXT: ashr r0, r0, 32
 ; CHECK-NEXT: bt r0
 
@@ -49,7 +49,7 @@ define i32 @f3(i32 %a) {
 	%2 = select i1 %1, i32 10, i32 17
 	ret i32 %2
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NEXT: ashr r0, r0, 32
 ; CHECK-NEXT: bt r0
 ; CHECK-NEXT: ldc r0, 17
@@ -60,7 +60,7 @@ define i32 @f4(i32 %a) {
 	%2 = select i1 %1, i32 10, i32 17
 	ret i32 %2
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NEXT: ashr r0, r0, 32
 ; CHECK-NEXT: bt r0
 ; CHECK-NEXT: ldc r0, 10
@@ -71,6 +71,6 @@ define i32 @f5(i32 %a) {
 	%2 = zext i1 %1 to i32
 	ret i32 %2
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NEXT: ashr r0, r0, 32
 ; CHECK-NEXT: eq r0, r0, 0
diff --git a/test/CodeGen/XCore/bigstructret.ll b/test/CodeGen/XCore/bigstructret.ll
index 56af930..877c571 100644
--- a/test/CodeGen/XCore/bigstructret.ll
+++ b/test/CodeGen/XCore/bigstructret.ll
@@ -12,7 +12,7 @@ entry:
   %3 = insertvalue %0 %2, i32 24601, 3
   ret %0 %3
 }
-; CHECK: ReturnBigStruct:
+; CHECK-LABEL: ReturnBigStruct:
 ; CHECK: ldc r0, 12
 ; CHECK: ldc r1, 24
 ; CHECK: ldc r2, 48
@@ -29,7 +29,7 @@ entry:
   %4 = insertvalue %1 %3, i32 4321, 4
   ret %1 %4
 }
-; CHECK: ReturnBigStruct2:
+; CHECK-LABEL: ReturnBigStruct2:
 ; CHECK: ldc r1, 4321
 ; CHECK: stw r1, r0[4]
 ; CHECK: ldc r1, 24601
diff --git a/test/CodeGen/XCore/constants.ll b/test/CodeGen/XCore/constants.ll
index 1e064f3..c289bf9 100644
--- a/test/CodeGen/XCore/constants.ll
+++ b/test/CodeGen/XCore/constants.ll
@@ -3,7 +3,7 @@
 ; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4
 ; CHECK: .LCPI0_0:
 ; CHECK: .long 12345678
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: ldw r0, cp[.LCPI0_0]
 define i32 @f() {
 entry:
@@ -12,7 +12,7 @@ entry:
 
 define i32 @g() {
 entry:
-; CHECK: g:
+; CHECK-LABEL: g:
 ; CHECK: mkmsk r0, 1
 ; CHECK: retsp 0
   ret i32 1;
diff --git a/test/CodeGen/XCore/events.ll b/test/CodeGen/XCore/events.ll
index 30a6ec3..672669b 100644
--- a/test/CodeGen/XCore/events.ll
+++ b/test/CodeGen/XCore/events.ll
@@ -6,7 +6,7 @@ declare i8* @llvm.xcore.checkevent(i8*)
 declare void @llvm.xcore.clre()
 
 define i32 @f(i8 addrspace(1)* %r) nounwind {
-; CHECK: f:
+; CHECK-LABEL: f:
 entry:
 ; CHECK: clre
   call void @llvm.xcore.clre()
@@ -25,7 +25,7 @@ ret:
 }
 
 define i32 @g(i8 addrspace(1)* %r) nounwind {
-; CHECK: g:
+; CHECK-LABEL: g:
 entry:
 ; CHECK: clre
   call void @llvm.xcore.clre()
diff --git a/test/CodeGen/XCore/float-intrinsics.ll b/test/CodeGen/XCore/float-intrinsics.ll
index 69a40f3..5882036 100644
--- a/test/CodeGen/XCore/float-intrinsics.ll
+++ b/test/CodeGen/XCore/float-intrinsics.ll
@@ -11,7 +11,7 @@ declare double @llvm.sin.f64(double)
 declare double @llvm.sqrt.f64(double)
 
 define double @cos(double %F) {
-; CHECK: cos:
+; CHECK-LABEL: cos:
 ; CHECK: bl cos
         %result = call double @llvm.cos.f64(double %F)
 	ret double %result
@@ -19,7 +19,7 @@ define double @cos(double %F) {
 
 declare float @llvm.cos.f32(float)
 
-; CHECK: cosf:
+; CHECK-LABEL: cosf:
 ; CHECK: bl cosf
 define float @cosf(float %F) {
         %result = call float @llvm.cos.f32(float %F)
@@ -27,7 +27,7 @@ define float @cosf(float %F) {
 }
 
 define double @exp(double %F) {
-; CHECK: exp:
+; CHECK-LABEL: exp:
 ; CHECK: bl exp
         %result = call double @llvm.exp.f64(double %F)
 	ret double %result
@@ -36,14 +36,14 @@ define double @exp(double %F) {
 declare float @llvm.exp.f32(float)
 
 define float @expf(float %F) {
-; CHECK: expf:
+; CHECK-LABEL: expf:
 ; CHECK: bl expf
         %result = call float @llvm.exp.f32(float %F)
 	ret float %result
 }
 
 define double @exp2(double %F) {
-; CHECK: exp2:
+; CHECK-LABEL: exp2:
 ; CHECK: bl exp2
         %result = call double @llvm.exp2.f64(double %F)
 	ret double %result
@@ -52,14 +52,14 @@ define double @exp2(double %F) {
 declare float @llvm.exp2.f32(float)
 
 define float @exp2f(float %F) {
-; CHECK: exp2f:
+; CHECK-LABEL: exp2f:
 ; CHECK: bl exp2f
         %result = call float @llvm.exp2.f32(float %F)
 	ret float %result
 }
 
 define double @log(double %F) {
-; CHECK: log:
+; CHECK-LABEL: log:
 ; CHECK: bl log
         %result = call double @llvm.log.f64(double %F)
 	ret double %result
@@ -68,14 +68,14 @@ define double @log(double %F) {
 declare float @llvm.log.f32(float)
 
 define float @logf(float %F) {
-; CHECK: logf:
+; CHECK-LABEL: logf:
 ; CHECK: bl logf
         %result = call float @llvm.log.f32(float %F)
 	ret float %result
 }
 
 define double @log10(double %F) {
-; CHECK: log10:
+; CHECK-LABEL: log10:
 ; CHECK: bl log10
         %result = call double @llvm.log10.f64(double %F)
 	ret double %result
@@ -84,14 +84,14 @@ define double @log10(double %F) {
 declare float @llvm.log10.f32(float)
 
 define float @log10f(float %F) {
-; CHECK: log10f:
+; CHECK-LABEL: log10f:
 ; CHECK: bl log10f
         %result = call float @llvm.log10.f32(float %F)
 	ret float %result
 }
 
 define double @log2(double %F) {
-; CHECK: log2:
+; CHECK-LABEL: log2:
 ; CHECK: bl log2
         %result = call double @llvm.log2.f64(double %F)
 	ret double %result
@@ -100,14 +100,14 @@ define double @log2(double %F) {
 declare float @llvm.log2.f32(float)
 
 define float @log2f(float %F) {
-; CHECK: log2f:
+; CHECK-LABEL: log2f:
 ; CHECK: bl log2f
         %result = call float @llvm.log2.f32(float %F)
 	ret float %result
 }
 
 define double @pow(double %F, double %power) {
-; CHECK: pow:
+; CHECK-LABEL: pow:
 ; CHECK: bl pow
         %result = call double @llvm.pow.f64(double %F, double %power)
 	ret double %result
@@ -116,14 +116,14 @@ define double @pow(double %F, double %power) {
 declare float @llvm.pow.f32(float, float)
 
 define float @powf(float %F, float %power) {
-; CHECK: powf:
+; CHECK-LABEL: powf:
 ; CHECK: bl powf
         %result = call float @llvm.pow.f32(float %F, float %power)
 	ret float %result
 }
 
 define double @powi(double %F, i32 %power) {
-; CHECK: powi:
+; CHECK-LABEL: powi:
 ; CHECK: bl __powidf2
         %result = call double @llvm.powi.f64(double %F, i32 %power)
 	ret double %result
@@ -132,14 +132,14 @@ define double @powi(double %F, i32 %power) {
 declare float @llvm.powi.f32(float, i32)
 
 define float @powif(float %F, i32 %power) {
-; CHECK: powif:
+; CHECK-LABEL: powif:
 ; CHECK: bl __powisf2
         %result = call float @llvm.powi.f32(float %F, i32 %power)
 	ret float %result
 }
 
 define double @sin(double %F) {
-; CHECK: sin:
+; CHECK-LABEL: sin:
 ; CHECK: bl sin
         %result = call double @llvm.sin.f64(double %F)
 	ret double %result
@@ -148,14 +148,14 @@ define double @sin(double %F) {
 declare float @llvm.sin.f32(float)
 
 define float @sinf(float %F) {
-; CHECK: sinf:
+; CHECK-LABEL: sinf:
 ; CHECK: bl sinf
         %result = call float @llvm.sin.f32(float %F)
 	ret float %result
 }
 
 define double @sqrt(double %F) {
-; CHECK: sqrt:
+; CHECK-LABEL: sqrt:
 ; CHECK: bl sqrt
         %result = call double @llvm.sqrt.f64(double %F)
 	ret double %result
@@ -164,7 +164,7 @@ define double @sqrt(double %F) {
 declare float @llvm.sqrt.f32(float)
 
 define float @sqrtf(float %F) {
-; CHECK: sqrtf:
+; CHECK-LABEL: sqrtf:
 ; CHECK: bl sqrtf
         %result = call float @llvm.sqrt.f32(float %F)
 	ret float %result
diff --git a/test/CodeGen/XCore/globals.ll b/test/CodeGen/XCore/globals.ll
index 7487561..dfa5de6 100644
--- a/test/CodeGen/XCore/globals.ll
+++ b/test/CodeGen/XCore/globals.ll
@@ -2,21 +2,21 @@
 
 define i32 *@addr_G1() {
 entry:
-; CHECK: addr_G1:
+; CHECK-LABEL: addr_G1:
 ; CHECK: ldaw r0, dp[G1]
 	ret i32* @G1
 }
 
 define i32 *@addr_G2() {
 entry:
-; CHECK: addr_G2:
+; CHECK-LABEL: addr_G2:
 ; CHECK: ldaw r0, dp[G2]
 	ret i32* @G2
 }
 
 define i32 *@addr_G3() {
 entry:
-; CHECK: addr_G3:
+; CHECK-LABEL: addr_G3:
 ; CHECK: ldaw r11, cp[G3]
 ; CHECK: mov r0, r11
 	ret i32* @G3
@@ -24,14 +24,14 @@ entry:
 
 define i32 **@addr_G4() {
 entry:
-; CHECK: addr_G4:
+; CHECK-LABEL: addr_G4:
 ; CHECK: ldaw r0, dp[G4]
 	ret i32** @G4
 }
 
 define i32 **@addr_G5() {
 entry:
-; CHECK: addr_G5:
+; CHECK-LABEL: addr_G5:
 ; CHECK: ldaw r11, cp[G5]
 ; CHECK: mov r0, r11
 	ret i32** @G5
@@ -39,14 +39,14 @@ entry:
 
 define i32 **@addr_G6() {
 entry:
-; CHECK: addr_G6:
+; CHECK-LABEL: addr_G6:
 ; CHECK: ldaw r0, dp[G6]
 	ret i32** @G6
 }
 
 define i32 **@addr_G7() {
 entry:
-; CHECK: addr_G7:
+; CHECK-LABEL: addr_G7:
 ; CHECK: ldaw r11, cp[G7]
 ; CHECK: mov r0, r11
 	ret i32** @G7
@@ -54,7 +54,7 @@ entry:
 
 define i32 *@addr_G8() {
 entry:
-; CHECK: addr_G8:
+; CHECK-LABEL: addr_G8:
 ; CHECK: ldaw r0, dp[G8]
 	ret i32* @G8
 }
diff --git a/test/CodeGen/XCore/indirectbr.ll b/test/CodeGen/XCore/indirectbr.ll
index 9269002..d7758ea 100644
--- a/test/CodeGen/XCore/indirectbr.ll
+++ b/test/CodeGen/XCore/indirectbr.ll
@@ -4,7 +4,7 @@
 @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
 
 define internal i32 @foo(i32 %i) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 entry:
   %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2]
   %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1]
diff --git a/test/CodeGen/XCore/ladd_lsub_combine.ll b/test/CodeGen/XCore/ladd_lsub_combine.ll
index cd89966..b75e30d 100644
--- a/test/CodeGen/XCore/ladd_lsub_combine.ll
+++ b/test/CodeGen/XCore/ladd_lsub_combine.ll
@@ -8,7 +8,7 @@ entry:
 	%2 = add i64 %1, %0		; <i64> [#uses=1]
 	ret i64 %2
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldc r2, 0
 ; CHECK-NEXT: ladd r1, r0, r1, r0, r2
 ; CHECK-NEXT: retsp 0
@@ -21,7 +21,7 @@ entry:
 	%2 = sub i64 %1, %0		; <i64> [#uses=1]
 	ret i64 %2
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldc r2, 0
 ; CHECK-NEXT: lsub r1, r0, r1, r0, r2
 ; CHECK-NEXT: neg r1, r1
@@ -34,7 +34,7 @@ entry:
 	%1 = add i64 %x, %0		; <i64> [#uses=1]
 	ret i64 %1
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ldc r3, 0
 ; CHECK-NEXT: ladd r2, r0, r0, r2, r3
 ; CHECK-NEXT: add r1, r1, r2
@@ -47,7 +47,7 @@ entry:
 	%1 = add i64 %0, %y		; <i64> [#uses=1]
 	ret i64 %1
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldc r3, 0
 ; CHECK-NEXT: ladd r1, r0, r0, r1, r3
 ; CHECK-NEXT: add r1, r2, r1
@@ -60,7 +60,7 @@ entry:
 	%1 = sub i64 %x, %0		; <i64> [#uses=1]
 	ret i64 %1
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldc r3, 0
 ; CHECK-NEXT: lsub r2, r0, r0, r2, r3
 ; CHECK-NEXT: sub r1, r1, r2
diff --git a/test/CodeGen/XCore/licm-ldwcp.ll b/test/CodeGen/XCore/licm-ldwcp.ll
index 794c6bb..f98c0eb 100644
--- a/test/CodeGen/XCore/licm-ldwcp.ll
+++ b/test/CodeGen/XCore/licm-ldwcp.ll
@@ -2,7 +2,7 @@
 
 ; MachineLICM should hoist the LDWCP out of the loop.
 
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK-NEXT: ldw [[REG:r[0-9]+]], cp[.LCPI0_0]
 ; CHECK-NEXT: .LBB0_1:
 ; CHECK-NEXT: stw [[REG]], r0[0]
diff --git a/test/CodeGen/XCore/load.ll b/test/CodeGen/XCore/load.ll
index 729fdef..0622f1c 100644
--- a/test/CodeGen/XCore/load.ll
+++ b/test/CodeGen/XCore/load.ll
@@ -2,7 +2,7 @@
 
 define i32 @load32(i32* %p, i32 %offset) nounwind {
 entry:
-; CHECK: load32:
+; CHECK-LABEL: load32:
 ; CHECK: ldw r0, r0[r1]
 	%0 = getelementptr i32* %p, i32 %offset
 	%1 = load i32* %0, align 4
@@ -11,7 +11,7 @@ entry:
 
 define i32 @load32_imm(i32* %p) nounwind {
 entry:
-; CHECK: load32_imm:
+; CHECK-LABEL: load32_imm:
 ; CHECK: ldw r0, r0[11]
 	%0 = getelementptr i32* %p, i32 11
 	%1 = load i32* %0, align 4
@@ -20,7 +20,7 @@ entry:
 
 define i32 @load16(i16* %p, i32 %offset) nounwind {
 entry:
-; CHECK: load16:
+; CHECK-LABEL: load16:
 ; CHECK: ld16s r0, r0[r1]
 ; CHECK-NOT: sext
 	%0 = getelementptr i16* %p, i32 %offset
@@ -31,7 +31,7 @@ entry:
 
 define i32 @load8(i8* %p, i32 %offset) nounwind {
 entry:
-; CHECK: load8:
+; CHECK-LABEL: load8:
 ; CHECK: ld8u r0, r0[r1]
 ; CHECK-NOT: zext
 	%0 = getelementptr i8* %p, i32 %offset
@@ -43,7 +43,7 @@ entry:
 @GConst = external constant i32
 define i32 @load_cp() nounwind {
 entry:
-; CHECK: load_cp:
+; CHECK-LABEL: load_cp:
 ; CHECK: ldw r0, cp[GConst]
   %0 = load i32* @GConst
   ret i32 %0
diff --git a/test/CodeGen/XCore/misc-intrinsics.ll b/test/CodeGen/XCore/misc-intrinsics.ll
index 6d39d77..30d7493 100644
--- a/test/CodeGen/XCore/misc-intrinsics.ll
+++ b/test/CodeGen/XCore/misc-intrinsics.ll
@@ -10,56 +10,56 @@ declare i32 @llvm.xcore.geted()
 declare i32 @llvm.xcore.getet()
 
 define i32 @bitrev(i32 %val) {
-; CHECK: bitrev:
+; CHECK-LABEL: bitrev:
 ; CHECK: bitrev r0, r0
 	%result = call i32 @llvm.xcore.bitrev(i32 %val)
 	ret i32 %result
 }
 
 define i32 @crc32(i32 %crc, i32 %data, i32 %poly) {
-; CHECK: crc32:
+; CHECK-LABEL: crc32:
 ; CHECK: crc32 r0, r1, r2
 	%result = call i32 @llvm.xcore.crc32(i32 %crc, i32 %data, i32 %poly)
 	ret i32 %result
 }
 
 define %0 @crc8(i32 %crc, i32 %data, i32 %poly) {
-; CHECK: crc8:
+; CHECK-LABEL: crc8:
 ; CHECK: crc8 r0, r1, r1, r2
 	%result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly)
 	ret %0 %result
 }
 
 define i32 @zext(i32 %a, i32 %b) {
-; CHECK: zext:
+; CHECK-LABEL: zext:
 ; CHECK: zext r0, r1
 	%result = call i32 @llvm.xcore.zext(i32 %a, i32 %b)
 	ret i32 %result
 }
 
 define i32 @zexti(i32 %a) {
-; CHECK: zexti:
+; CHECK-LABEL: zexti:
 ; CHECK: zext r0, 4
 	%result = call i32 @llvm.xcore.zext(i32 %a, i32 4)
 	ret i32 %result
 }
 
 define i32 @sext(i32 %a, i32 %b) {
-; CHECK: sext:
+; CHECK-LABEL: sext:
 ; CHECK: sext r0, r1
 	%result = call i32 @llvm.xcore.sext(i32 %a, i32 %b)
 	ret i32 %result
 }
 
 define i32 @sexti(i32 %a) {
-; CHECK: sexti:
+; CHECK-LABEL: sexti:
 ; CHECK: sext r0, 4
 	%result = call i32 @llvm.xcore.sext(i32 %a, i32 4)
 	ret i32 %result
 }
 
 define i32 @geted() {
-; CHECK: geted:
+; CHECK-LABEL: geted:
 ; CHECK: get r11, ed
 ; CHECK-NEXT: mov r0, r11
 	%result = call i32 @llvm.xcore.geted()
@@ -67,7 +67,7 @@ define i32 @geted() {
 }
 
 define i32 @getet() {
-; CHECK: getet:
+; CHECK-LABEL: getet:
 ; CHECK: get r11, et
 ; CHECK-NEXT: mov r0, r11
 	%result = call i32 @llvm.xcore.getet()
diff --git a/test/CodeGen/XCore/mkmsk.ll b/test/CodeGen/XCore/mkmsk.ll
index 377612b..bcec32d 100644
--- a/test/CodeGen/XCore/mkmsk.ll
+++ b/test/CodeGen/XCore/mkmsk.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=xcore | FileCheck %s
 
 define i32 @f(i32) nounwind {
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: mkmsk r0, r0
 ; CHECK-NEXT: retsp 0
 entry:
diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll
index 3d373b1..cfc9855 100644
--- a/test/CodeGen/XCore/mul64.ll
+++ b/test/CodeGen/XCore/mul64.ll
@@ -7,7 +7,7 @@ entry:
 	%2 = mul i64 %1, %0
 	ret i64 %2
 }
-; CHECK: umul_lohi:
+; CHECK-LABEL: umul_lohi:
 ; CHECK: ldc [[REG:r[0-9]+]], 0
 ; CHECK-NEXT: lmul {{.*}}, [[REG]], [[REG]]
 ; CHECK-NEXT: retsp 0
@@ -19,7 +19,7 @@ entry:
 	%2 = mul i64 %1, %0
 	ret i64 %2
 }
-; CHECK: smul_lohi:
+; CHECK-LABEL: smul_lohi:
 ; CHECK: ldc
 ; CHECK-NEXT: mov
 ; CHECK-NEXT: maccs
@@ -30,7 +30,7 @@ entry:
 	%0 = mul i64 %a, %b
 	ret i64 %0
 }
-; CHECK: mul64:
+; CHECK-LABEL: mul64:
 ; CHECK: ldc
 ; CHECK-NEXT: lmul
 ; CHECK-NEXT: mul
@@ -42,7 +42,7 @@ entry:
 	%1 = mul i64 %a, %0
 	ret i64 %1
 }
-; CHECK: mul64_2:
+; CHECK-LABEL: mul64_2:
 ; CHECK: ldc
 ; CHECK-NEXT: lmul
 ; CHECK-NEXT: mul
diff --git a/test/CodeGen/XCore/offset_folding.ll b/test/CodeGen/XCore/offset_folding.ll
index 30edfe6..8085a0f 100644
--- a/test/CodeGen/XCore/offset_folding.ll
+++ b/test/CodeGen/XCore/offset_folding.ll
@@ -5,7 +5,7 @@
 
 define i32 *@f1() nounwind {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldaw r11, cp[a+4]
 ; CHECK: mov r0, r11
 	%0 = getelementptr [0 x i32]* @a, i32 0, i32 1
@@ -14,7 +14,7 @@ entry:
 
 define i32 *@f2() nounwind {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldaw r0, dp[b+4]
 	%0 = getelementptr [0 x i32]* @b, i32 0, i32 1
 	ret i32* %0
@@ -25,7 +25,7 @@ entry:
 
 define i32 *@f3() nounwind {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ldaw r11, cp[a]
 ; CHECK: sub r0, r11, 4
 	%0 = getelementptr [0 x i32]* @a, i32 0, i32 -1
@@ -34,7 +34,7 @@ entry:
 
 define i32 *@f4() nounwind {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldaw [[REG:r[0-9]+]], dp[b]
 ; CHECK: sub r0, [[REG]], 4
 	%0 = getelementptr [0 x i32]* @b, i32 0, i32 -1
diff --git a/test/CodeGen/XCore/private.ll b/test/CodeGen/XCore/private.ll
index 80b7db4..474448a 100644
--- a/test/CodeGen/XCore/private.ll
+++ b/test/CodeGen/XCore/private.ll
@@ -10,7 +10,7 @@ define private void @foo() {
 @baz = private global i32 4
 
 define i32 @bar() {
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: bl .Lfoo
 ; CHECK: ldw r0, dp[.Lbaz]
         call void @foo()
diff --git a/test/CodeGen/XCore/ps-intrinsics.ll b/test/CodeGen/XCore/ps-intrinsics.ll
index 92b26c7..02609ed 100644
--- a/test/CodeGen/XCore/ps-intrinsics.ll
+++ b/test/CodeGen/XCore/ps-intrinsics.ll
@@ -3,7 +3,7 @@ declare i32 @llvm.xcore.getps(i32)
 declare void @llvm.xcore.setps(i32, i32)
 
 define i32 @getps(i32 %reg) nounwind {
-; CHECK: getps:
+; CHECK-LABEL: getps:
 ; CHECK: get r0, ps[r0]
 	%result = call i32 @llvm.xcore.getps(i32 %reg)
 	ret i32 %result
@@ -11,7 +11,7 @@ define i32 @getps(i32 %reg) nounwind {
 
 
 define void @setps(i32 %reg, i32 %value) nounwind {
-; CHECK: setps:
+; CHECK-LABEL: setps:
 ; CHECK: set ps[r0], r1
 	call void @llvm.xcore.setps(i32 %reg, i32 %value)
 	ret void
diff --git a/test/CodeGen/XCore/resources.ll b/test/CodeGen/XCore/resources.ll
index 74511ad..5385010 100644
--- a/test/CodeGen/XCore/resources.ll
+++ b/test/CodeGen/XCore/resources.ll
@@ -29,147 +29,147 @@ declare i32 @llvm.xcore.peek.p1i8(i8 addrspace(1)* %r)
 declare i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r)
 
 define i8 addrspace(1)* @getr() {
-; CHECK: getr:
+; CHECK-LABEL: getr:
 ; CHECK: getr r0, 5
 	%result = call i8 addrspace(1)* @llvm.xcore.getr.p1i8(i32 5)
 	ret i8 addrspace(1)* %result
 }
 
 define void @freer(i8 addrspace(1)* %r) {
-; CHECK: freer:
+; CHECK-LABEL: freer:
 ; CHECK: freer res[r0]
 	call void @llvm.xcore.freer.p1i8(i8 addrspace(1)* %r)
 	ret void
 }
 
 define i32 @in(i8 addrspace(1)* %r) {
-; CHECK: in:
+; CHECK-LABEL: in:
 ; CHECK: in r0, res[r0]
 	%result = call i32 @llvm.xcore.in.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
 }
 
 define i32 @int(i8 addrspace(1)* %r) {
-; CHECK: int:
+; CHECK-LABEL: int:
 ; CHECK: int r0, res[r0]
 	%result = call i32 @llvm.xcore.int.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
 }
 
 define i32 @inct(i8 addrspace(1)* %r) {
-; CHECK: inct:
+; CHECK-LABEL: inct:
 ; CHECK: inct r0, res[r0]
 	%result = call i32 @llvm.xcore.inct.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
 }
 
 define void @out(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: out:
+; CHECK-LABEL: out:
 ; CHECK: out res[r0], r1
 	call void @llvm.xcore.out.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define void @outt(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: outt:
+; CHECK-LABEL: outt:
 ; CHECK: outt res[r0], r1
 	call void @llvm.xcore.outt.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define void @outct(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: outct:
+; CHECK-LABEL: outct:
 ; CHECK: outct res[r0], r1
 	call void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define void @outcti(i8 addrspace(1)* %r) {
-; CHECK: outcti:
+; CHECK-LABEL: outcti:
 ; CHECK: outct res[r0], 11
 	call void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 11)
 	ret void
 }
 
 define void @chkct(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: chkct:
+; CHECK-LABEL: chkct:
 ; CHECK: chkct res[r0], r1
 	call void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define void @chkcti(i8 addrspace(1)* %r) {
-; CHECK: chkcti:
+; CHECK-LABEL: chkcti:
 ; CHECK: chkct res[r0], 11
 	call void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 11)
 	ret void
 }
 
 define void @setd(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: setd:
+; CHECK-LABEL: setd:
 ; CHECK: setd res[r0], r1
 	call void @llvm.xcore.setd.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define void @setc(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: setc:
+; CHECK-LABEL: setc:
 ; CHECK: setc res[r0], r1
 	call void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define void @setci(i8 addrspace(1)* %r) {
-; CHECK: setci:
+; CHECK-LABEL: setci:
 ; CHECK: setc res[r0], 2
 	call void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 2)
 	ret void
 }
 
 define i32 @inshr(i32 %value, i8 addrspace(1)* %r) {
-; CHECK: inshr:
+; CHECK-LABEL: inshr:
 ; CHECK: inshr r0, res[r1]
 	%result = call i32 @llvm.xcore.inshr.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret i32 %result
 }
 
 define i32 @outshr(i32 %value, i8 addrspace(1)* %r) {
-; CHECK: outshr:
+; CHECK-LABEL: outshr:
 ; CHECK: outshr res[r1], r0
 	%result = call i32 @llvm.xcore.outshr.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret i32 %result
 }
 
 define void @setpt(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: setpt:
+; CHECK-LABEL: setpt:
 ; CHECK: setpt res[r0], r1
 	call void @llvm.xcore.setpt.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define i32 @getts(i8 addrspace(1)* %r) {
-; CHECK: getts:
+; CHECK-LABEL: getts:
 ; CHECK: getts r0, res[r0]
 	%result = call i32 @llvm.xcore.getts.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
 }
 
 define void @syncr(i8 addrspace(1)* %r) {
-; CHECK: syncr:
+; CHECK-LABEL: syncr:
 ; CHECK: syncr res[r0]
 	call void @llvm.xcore.syncr.p1i8(i8 addrspace(1)* %r)
 	ret void
 }
 
 define void @settw(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: settw:
+; CHECK-LABEL: settw:
 ; CHECK: settw res[r0], r1
 	call void @llvm.xcore.settw.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define void @setv(i8 addrspace(1)* %r, i8* %p) {
-; CHECK: setv:
+; CHECK-LABEL: setv:
 ; CHECK: mov r11, r1
 ; CHECK-NEXT: setv res[r0], r11
 	call void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* %p)
@@ -177,7 +177,7 @@ define void @setv(i8 addrspace(1)* %r, i8* %p) {
 }
 
 define void @setev(i8 addrspace(1)* %r, i8* %p) {
-; CHECK: setev:
+; CHECK-LABEL: setev:
 ; CHECK: mov r11, r1
 ; CHECK-NEXT: setev res[r0], r11
 	call void @llvm.xcore.setev.p1i8(i8 addrspace(1)* %r, i8* %p)
@@ -185,7 +185,7 @@ define void @setev(i8 addrspace(1)* %r, i8* %p) {
 }
 
 define void @eeu(i8 addrspace(1)* %r) {
-; CHECK: eeu:
+; CHECK-LABEL: eeu:
 ; CHECK: eeu res[r0]
 	call void @llvm.xcore.eeu.p1i8(i8 addrspace(1)* %r)
 	ret void
@@ -213,14 +213,14 @@ define void @setpsc(i8 addrspace(1)* %r, i32 %value) {
 }
 
 define i32 @peek(i8 addrspace(1)* %r) {
-; CHECK: peek:
+; CHECK-LABEL: peek:
 ; CHECK: peek r0, res[r0]
 	%result = call i32 @llvm.xcore.peek.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
 }
 
 define i32 @endin(i8 addrspace(1)* %r) {
-; CHECK: endin:
+; CHECK-LABEL: endin:
 ; CHECK: endin r0, res[r0]
 	%result = call i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
diff --git a/test/CodeGen/XCore/sext.ll b/test/CodeGen/XCore/sext.ll
index 9cd4ad6..b3e66ec 100644
--- a/test/CodeGen/XCore/sext.ll
+++ b/test/CodeGen/XCore/sext.ll
@@ -4,7 +4,7 @@ define i32 @sext1(i32 %a) {
 	%2 = sext i1 %1 to i32
 	ret i32 %2
 }
-; CHECK: sext1:
+; CHECK-LABEL: sext1:
 ; CHECK: sext r0, 1
 
 define i32 @sext2(i32 %a) {
@@ -12,7 +12,7 @@ define i32 @sext2(i32 %a) {
 	%2 = sext i2 %1 to i32
 	ret i32 %2
 }
-; CHECK: sext2:
+; CHECK-LABEL: sext2:
 ; CHECK: sext r0, 2
 
 define i32 @sext8(i32 %a) {
@@ -20,7 +20,7 @@ define i32 @sext8(i32 %a) {
 	%2 = sext i8 %1 to i32
 	ret i32 %2
 }
-; CHECK: sext8:
+; CHECK-LABEL: sext8:
 ; CHECK: sext r0, 8
 
 define i32 @sext16(i32 %a) {
@@ -28,5 +28,5 @@ define i32 @sext16(i32 %a) {
 	%2 = sext i16 %1 to i32
 	ret i32 %2
 }
-; CHECK: sext16:
+; CHECK-LABEL: sext16:
 ; CHECK: sext r0, 16
diff --git a/test/CodeGen/XCore/sr-intrinsics.ll b/test/CodeGen/XCore/sr-intrinsics.ll
index e12ed03..2c4175d 100644
--- a/test/CodeGen/XCore/sr-intrinsics.ll
+++ b/test/CodeGen/XCore/sr-intrinsics.ll
@@ -3,7 +3,7 @@ declare void @llvm.xcore.setsr(i32)
 declare void @llvm.xcore.clrsr(i32)
 
 define void @setsr() nounwind {
-; CHECK: setsr:
+; CHECK-LABEL: setsr:
 ; CHECK: setsr 128
 	call void @llvm.xcore.setsr(i32 128)
 	ret void
@@ -11,7 +11,7 @@ define void @setsr() nounwind {
 
 
 define void @clrsr() nounwind {
-; CHECK: clrsr:
+; CHECK-LABEL: clrsr:
 ; CHECK: clrsr 128
 	call void @llvm.xcore.clrsr(i32 128)
 	ret void
diff --git a/test/CodeGen/XCore/store.ll b/test/CodeGen/XCore/store.ll
index 836b125..87553d8 100644
--- a/test/CodeGen/XCore/store.ll
+++ b/test/CodeGen/XCore/store.ll
@@ -2,7 +2,7 @@
 
 define void @store32(i32* %p, i32 %offset, i32 %val) nounwind {
 entry:
-; CHECK: store32:
+; CHECK-LABEL: store32:
 ; CHECK: stw r2, r0[r1]
 	%0 = getelementptr i32* %p, i32 %offset
 	store i32 %val, i32* %0, align 4
@@ -11,7 +11,7 @@ entry:
 
 define void @store32_imm(i32* %p, i32 %val) nounwind {
 entry:
-; CHECK: store32_imm:
+; CHECK-LABEL: store32_imm:
 ; CHECK: stw r1, r0[11]
 	%0 = getelementptr i32* %p, i32 11
 	store i32 %val, i32* %0, align 4
@@ -20,7 +20,7 @@ entry:
 
 define void @store16(i16* %p, i32 %offset, i16 %val) nounwind {
 entry:
-; CHECK: store16:
+; CHECK-LABEL: store16:
 ; CHECK: st16 r2, r0[r1]
 	%0 = getelementptr i16* %p, i32 %offset
 	store i16 %val, i16* %0, align 2
@@ -29,7 +29,7 @@ entry:
 
 define void @store8(i8* %p, i32 %offset, i8 %val) nounwind {
 entry:
-; CHECK: store8:
+; CHECK-LABEL: store8:
 ; CHECK: st8 r2, r0[r1]
 	%0 = getelementptr i8* %p, i32 %offset
 	store i8 %val, i8* %0, align 1
diff --git a/test/CodeGen/XCore/threads.ll b/test/CodeGen/XCore/threads.ll
index a0558e3..9602623 100644
--- a/test/CodeGen/XCore/threads.ll
+++ b/test/CodeGen/XCore/threads.ll
@@ -11,56 +11,56 @@ declare void @llvm.xcore.initcp.p1i8(i8 addrspace(1)* %r, i8* %value)
 declare void @llvm.xcore.initdp.p1i8(i8 addrspace(1)* %r, i8* %value)
 
 define i8 addrspace(1)* @getst(i8 addrspace(1)* %r) {
-; CHECK: getst:
+; CHECK-LABEL: getst:
 ; CHECK: getst r0, res[r0]
         %result = call i8 addrspace(1)* @llvm.xcore.getst.p1i8.p1i8(i8 addrspace(1)* %r)
         ret i8 addrspace(1)* %result
 }
 
 define void @ssync() {
-; CHECK: ssync:
+; CHECK-LABEL: ssync:
 ; CHECK: ssync
 	call void @llvm.xcore.ssync()
 	ret void
 }
 
 define void @mjoin(i8 addrspace(1)* %r) {
-; CHECK: mjoin:
+; CHECK-LABEL: mjoin:
 ; CHECK: mjoin res[r0]
 	call void @llvm.xcore.mjoin.p1i8(i8 addrspace(1)* %r)
 	ret void
 }
 
 define void @initsp(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initsp:
+; CHECK-LABEL: initsp:
 ; CHECK: init t[r0]:sp, r1
         call void @llvm.xcore.initsp.p1i8(i8 addrspace(1)* %t, i8* %src)
         ret void
 }
 
 define void @initpc(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initpc:
+; CHECK-LABEL: initpc:
 ; CHECK: init t[r0]:pc, r1
         call void @llvm.xcore.initpc.p1i8(i8 addrspace(1)* %t, i8* %src)
         ret void
 }
 
 define void @initlr(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initlr:
+; CHECK-LABEL: initlr:
 ; CHECK: init t[r0]:lr, r1
         call void @llvm.xcore.initlr.p1i8(i8 addrspace(1)* %t, i8* %src)
         ret void
 }
 
 define void @initcp(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initcp:
+; CHECK-LABEL: initcp:
 ; CHECK: init t[r0]:cp, r1
         call void @llvm.xcore.initcp.p1i8(i8 addrspace(1)* %t, i8* %src)
         ret void
 }
 
 define void @initdp(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initdp:
+; CHECK-LABEL: initdp:
 ; CHECK: init t[r0]:dp, r1
         call void @llvm.xcore.initdp.p1i8(i8 addrspace(1)* %t, i8* %src)
         ret void
diff --git a/test/CodeGen/XCore/tls.ll b/test/CodeGen/XCore/tls.ll
index ed41afa..648d611 100644
--- a/test/CodeGen/XCore/tls.ll
+++ b/test/CodeGen/XCore/tls.ll
@@ -2,7 +2,7 @@
 
 define i32 *@addr_G() {
 entry:
-; CHECK: addr_G:
+; CHECK-LABEL: addr_G:
 ; CHECK: get r11, id
 	ret i32* @G
 }
diff --git a/test/CodeGen/XCore/trampoline.ll b/test/CodeGen/XCore/trampoline.ll
index 6b42134..7ca331a 100644
--- a/test/CodeGen/XCore/trampoline.ll
+++ b/test/CodeGen/XCore/trampoline.ll
@@ -4,7 +4,7 @@
 
 define void @f() nounwind {
 entry:
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: ldap r11, g.1101
 ; CHECK: stw r11, sp[7]
   %TRAMP.23 = alloca [20 x i8], align 2
diff --git a/test/CodeGen/XCore/unaligned_load.ll b/test/CodeGen/XCore/unaligned_load.ll
index 772a847..b8b8827 100644
--- a/test/CodeGen/XCore/unaligned_load.ll
+++ b/test/CodeGen/XCore/unaligned_load.ll
@@ -10,7 +10,7 @@ entry:
 }
 
 ; Half word aligned load.
-; CHECK: align2:
+; CHECK-LABEL: align2:
 ; CHECK: ld16s
 ; CHECK: ld16s
 ; CHECK: or
@@ -23,7 +23,7 @@ entry:
 @a = global [5 x i8] zeroinitializer, align 4
 
 ; Constant offset from word aligned base.
-; CHECK: align3:
+; CHECK-LABEL: align3:
 ; CHECK: ldw {{r[0-9]+}}, dp
 ; CHECK: ldw {{r[0-9]+}}, dp
 ; CHECK: or
diff --git a/test/CodeGen/XCore/unaligned_store.ll b/test/CodeGen/XCore/unaligned_store.ll
index 94e1852..27b4280 100644
--- a/test/CodeGen/XCore/unaligned_store.ll
+++ b/test/CodeGen/XCore/unaligned_store.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=xcore | FileCheck %s
 
 ; Byte aligned store.
-; CHECK: align1:
+; CHECK-LABEL: align1:
 ; CHECK: bl __misaligned_store
 define void @align1(i32* %p, i32 %val) nounwind {
 entry:
diff --git a/test/CodeGen/XCore/unaligned_store_combine.ll b/test/CodeGen/XCore/unaligned_store_combine.ll
index c997b78..d1f4e6c 100644
--- a/test/CodeGen/XCore/unaligned_store_combine.ll
+++ b/test/CodeGen/XCore/unaligned_store_combine.ll
@@ -4,7 +4,7 @@
 ; of size 8
 define void @f(i64* %dst, i64* %src) nounwind {
 entry:
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: ldc r2, 8
 ; CHECK: bl memmove
 	%0 = load i64* %src, align 1