diff options
author | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-08-10 22:49:54 +0000 |
---|---|---|
committer | Stephen Hines <srhines@google.com> | 2014-08-26 17:59:36 -0700 |
commit | cddb0cfe383207ccec0cc797db401854e5f0c672 (patch) | |
tree | 05365f8aa7cc271ec765c9e2a0423542f235c99d | |
parent | 63045274494a5adfedbd4de7280386948f7ca9b9 (diff) | |
download | external_llvm-cddb0cfe383207ccec0cc797db401854e5f0c672.zip external_llvm-cddb0cfe383207ccec0cc797db401854e5f0c672.tar.gz external_llvm-cddb0cfe383207ccec0cc797db401854e5f0c672.tar.bz2 |
Add support for scalarizing cttz_zero_undef
Follow up to r214266. Add missing case in ScalarizeVectorResult() for
cttz_zero_undef.
Differential Revision: http://reviews.llvm.org/D4813
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215330 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 1 | ||||
-rw-r--r-- | test/CodeGen/Mips/cttz-v.ll | 37 |
2 files changed, 38 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index dd98ffd..71240fc 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -72,6 +72,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { case ISD::CTLZ_ZERO_UNDEF: case ISD::CTPOP: case ISD::CTTZ: + case ISD::CTTZ_ZERO_UNDEF: case ISD::FABS: case ISD::FCEIL: case ISD::FCOS: diff --git a/test/CodeGen/Mips/cttz-v.ll b/test/CodeGen/Mips/cttz-v.ll new file mode 100644 index 0000000..9470441 --- /dev/null +++ b/test/CodeGen/Mips/cttz-v.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64 + +declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1) + +define <2 x i32> @cttzv2i32(<2 x i32> %x) { +entry: +; MIPS32-DAG: addiu $[[R0:[0-9]+]], $4, -1 +; MIPS32-DAG: not $[[R1:[0-9]+]], $4 +; MIPS32-DAG: and $[[R2:[0-9]+]], $[[R1]], $[[R0]] +; MIPS32-DAG: clz $[[R3:[0-9]+]], $[[R2]] +; MIPS32-DAG: addiu $[[R4:[0-9]+]], $zero, 32 +; MIPS32-DAG: subu $2, $[[R4]], $[[R3]] +; MIPS32-DAG: addiu $[[R5:[0-9]+]], $5, -1 +; MIPS32-DAG: not $[[R6:[0-9]+]], $5 +; MIPS32-DAG: and $[[R7:[0-9]+]], $[[R6]], $[[R5]] +; MIPS32-DAG: clz $[[R8:[0-9]+]], $[[R7]] +; MIPS32-DAG: jr $ra +; MIPS32-DAG: subu $3, $[[R4]], $[[R8]] + +; MIPS64-DAG: addiu $[[R0:[0-9]+]], $4, -1 +; MIPS64-DAG: not $[[R1:[0-9]+]], $4 +; MIPS64-DAG: and $[[R2:[0-9]+]], $[[R1]], $[[R0]] +; MIPS64-DAG: clz $[[R3:[0-9]+]], $[[R2]] +; MIPS64-DAG: addiu $[[R4:[0-9]+]], $zero, 32 +; MIPS64-DAG: subu $2, $[[R4]], $[[R3]] +; MIPS64-DAG: addiu $[[R5:[0-9]+]], $5, -1 +; MIPS64-DAG: not $[[R6:[0-9]+]], $5 +; MIPS64-DAG: and $[[R7:[0-9]+]], $[[R6]], $[[R5]] +; MIPS64-DAG: clz $[[R8:[0-9]+]], $[[R7]] +; MIPS64-DAG: jr $ra +; MIPS64-DAG: subu $3, $[[R4]], $[[R8]] + + %ret = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %x, i1 true) + ret <2 x i32> %ret +} + |