diff options
author | Reid Spencer <rspencer@reidspencer.com> | 2007-07-20 20:03:33 +0000 |
---|---|---|
committer | Reid Spencer <rspencer@reidspencer.com> | 2007-07-20 20:03:33 +0000 |
commit | 1cff40819c2d623e74d04f195e3c1dbbe3c35f39 (patch) | |
tree | 41c4f74e2196dee4ea688ac1010c8f5a08cc6b85 /docs | |
parent | 2067764e29dc2fd6d4d4b48940f41744eaff6d14 (diff) | |
download | external_llvm-1cff40819c2d623e74d04f195e3c1dbbe3c35f39.zip external_llvm-1cff40819c2d623e74d04f195e3c1dbbe3c35f39.tar.gz external_llvm-1cff40819c2d623e74d04f195e3c1dbbe3c35f39.tar.bz2 |
Silly HTML
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40117 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs')
-rw-r--r-- | docs/LangRef.html | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/docs/LangRef.html b/docs/LangRef.html index fa7fefa..a45aba8 100644 --- a/docs/LangRef.html +++ b/docs/LangRef.html @@ -5078,13 +5078,13 @@ declare void @llvm.memory.barrier( i1 <ll>, i1 <ls>, i1 <sl>, <p> The <tt>llvm.memory.barrier</tt> intrinsic requires four boolean arguments. Each argument enables a specific barrier as listed below. +</p> <ul> <li><tt>ll</tt>: load-load barrier</li> <li><tt>ls</tt>: load-store barrier</li> <li><tt>sl</tt>: store-load barrier</li> <li><tt>ss</tt>: store-store barrier</li> </ul> -</p> <h5>Semantics:</h5> <p> This intrinsic causes the system to enforce some ordering constraints upon @@ -5094,6 +5094,7 @@ declare void @llvm.memory.barrier( i1 <ll>, i1 <ls>, i1 <sl>, (f.ex. load-load, or store-load), all of the first operations preceding the barrier will complete before any of the second operations succeeding the barrier begin. Specifically the semantics for each pairing is as follows: +</p> <ul> <li><tt>ll</tt>: All loads before the barrier must complete before any load after the barrier begins.</li> @@ -5104,6 +5105,7 @@ declare void @llvm.memory.barrier( i1 <ll>, i1 <ls>, i1 <sl>, <li><tt>sl</tt>: All stores before the barrier must complete before any load after the barrier begins.</li> </ul> +<p> These semantics are applied with a logical "and" behavior when more than one is enabled in a single memory barrier intrinsic. </p> |