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authorRuchira Sasanka <sasanka@students.uiuc.edu>2001-11-03 17:14:13 +0000
committerRuchira Sasanka <sasanka@students.uiuc.edu>2001-11-03 17:14:13 +0000
commit0d3ea0268f44f8fd4ddf7a15f3624b384b0691db (patch)
tree82362a3c8f133647a8428e61db57a79a550616f2 /include/llvm/Target
parentef1b0cb9a5abc13750f67366d99a04d6bf7a2404 (diff)
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Moved InsertCallerSaveInstr to the SparcRegInfo.cpp and made machine independent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1107 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/Target')
-rw-r--r--include/llvm/Target/MachineInstrInfo.h4
-rw-r--r--include/llvm/Target/TargetInstrInfo.h4
-rw-r--r--include/llvm/Target/TargetRegInfo.h9
3 files changed, 10 insertions, 7 deletions
diff --git a/include/llvm/Target/MachineInstrInfo.h b/include/llvm/Target/MachineInstrInfo.h
index d0294ca..696738a 100644
--- a/include/llvm/Target/MachineInstrInfo.h
+++ b/include/llvm/Target/MachineInstrInfo.h
@@ -166,13 +166,13 @@ public:
|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG
|| getDescriptor(opCode).iclass & M_STORE_FLAG;
}
- bool isDummyPhiInstr(MachineOpCode opCode) const {
+ bool isDummyPhiInstr(const MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
}
// delete this later *******
- bool isPhi(MachineOpCode opCode) { return isDummyPhiInstr(opCode); }
+ bool isPhi(const MachineOpCode opCode) { return isDummyPhiInstr(opCode); }
// Check if an instruction can be issued before its operands are ready,
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index d0294ca..696738a 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -166,13 +166,13 @@ public:
|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG
|| getDescriptor(opCode).iclass & M_STORE_FLAG;
}
- bool isDummyPhiInstr(MachineOpCode opCode) const {
+ bool isDummyPhiInstr(const MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
}
// delete this later *******
- bool isPhi(MachineOpCode opCode) { return isDummyPhiInstr(opCode); }
+ bool isPhi(const MachineOpCode opCode) { return isDummyPhiInstr(opCode); }
// Check if an instruction can be issued before its operands are ready,
diff --git a/include/llvm/Target/TargetRegInfo.h b/include/llvm/Target/TargetRegInfo.h
index 73dc0ce..9983629 100644
--- a/include/llvm/Target/TargetRegInfo.h
+++ b/include/llvm/Target/TargetRegInfo.h
@@ -142,14 +142,17 @@ public:
cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg,
const int RegType) const=0;
- virtual MachineInstr *
- cpReg2MemMI(const unsigned SrcReg, const unsigned DestPtrReg,
+ virtual MachineInstr *
+ cpReg2MemMI(const unsigned SrcReg, const unsigned DestPtrReg,
const int Offset, const int RegType) const=0;
- virtual MachineInstr *
+ virtual MachineInstr *
cpMem2RegMI(const unsigned SrcPtrReg, const int Offset,
const unsigned DestReg, const int RegType) const=0;
+ virtual MachineInstr *cpValue2Value( Value *Src, Value *Dest) const=0;
+
+
virtual bool isRegVolatile(const int RegClassID, const int Reg) const=0;