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| author | Preston Gurd <preston.gurd@intel.com> | 2012-09-04 18:22:17 +0000 |
|---|---|---|
| committer | Preston Gurd <preston.gurd@intel.com> | 2012-09-04 18:22:17 +0000 |
| commit | 2e2efd960056bbb7e4bbd843c8de55116d52aa7d (patch) | |
| tree | 664f06659d0c01493523f47689a78ec7199dcce3 /include/llvm/Target | |
| parent | e20cf3d14997c3511e264748c59687a801caa6ed (diff) | |
| download | external_llvm-2e2efd960056bbb7e4bbd843c8de55116d52aa7d.zip external_llvm-2e2efd960056bbb7e4bbd843c8de55116d52aa7d.tar.gz external_llvm-2e2efd960056bbb7e4bbd843c8de55116d52aa7d.tar.bz2 | |
Generic Bypass Slow Div
- CodeGenPrepare pass for identifying div/rem ops
- Backend specifies the type mapping using addBypassSlowDivType
- Enabled only for Intel Atom with O2 32-bit -> 8-bit
- Replace IDIV with instructions which test its value and use DIVB if the value
is positive and less than 256.
- In the case when the quotient and remainder of a divide are used a DIV
and a REM instruction will be present in the IR. In the non-Atom case
they are both lowered to IDIVs and CSE removes the redundant IDIV instruction,
using the quotient and remainder from the first IDIV. However,
due to this optimization CSE is not able to eliminate redundant
IDIV instructions because they are located in different basic blocks.
This is overcome by calculating both the quotient (DIV) and remainder (REM)
in each basic block that is inserted by the optimization and reusing the result
values when a subsequent DIV or REM instruction uses the same operands.
- Test cases check for the presents of the optimization when calculating
either the quotient, remainder, or both.
Patch by Tyler Nowicki!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/Target')
| -rw-r--r-- | include/llvm/Target/TargetLowering.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index b8c070b..ef63422 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -25,6 +25,7 @@ #include "llvm/CallingConv.h" #include "llvm/InlineAsm.h" #include "llvm/Attributes.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/Support/CallSite.h" #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/RuntimeLibcalls.h" @@ -154,6 +155,16 @@ public: /// a sequence of several shifts, adds, and multiplies for this target. bool isIntDivCheap() const { return IntDivIsCheap; } + /// isSlowDivBypassed - Returns true if target has indicated at least one + /// type should be bypassed. + bool isSlowDivBypassed() const { return !BypassSlowDivTypes.empty(); } + + /// getBypassSlowDivTypes - Returns map of slow types for division or + /// remainder with corresponding fast types + const DenseMap<Type *, Type *> &getBypassSlowDivTypes() const { + return BypassSlowDivTypes; + } + /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of /// srl/add/sra. bool isPow2DivCheap() const { return Pow2DivIsCheap; } @@ -1055,6 +1066,11 @@ protected: /// of instructions not containing an integer divide. void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } + /// addBypassSlowDivType - Tells the code generator which types to bypass. + void addBypassSlowDivType(Type *slow_type, Type *fast_type) { + BypassSlowDivTypes[slow_type] = fast_type; + } + /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate /// srl/add/sra for a signed divide by power of two, and let the target handle /// it. @@ -1772,6 +1788,12 @@ private: /// set to true unconditionally. bool IntDivIsCheap; + /// BypassSlowDivTypes - Tells the code generator to bypass slow divide or + /// remainder instructions. For example, SlowDivBypass[i32,u8] tells the code + /// generator to bypass 32-bit signed integer div/rem with an 8-bit unsigned + /// integer div/rem when the operands are positive and less than 256. + DenseMap <Type *, Type *> BypassSlowDivTypes; + /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate /// srl/add/sra for a signed divide by power of two, and let the target handle /// it. |