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author | Evan Cheng <evan.cheng@apple.com> | 2009-06-18 02:04:01 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-06-18 02:04:01 +0000 |
commit | f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4 (patch) | |
tree | 03b4831fb34e361de779ebe31c14b6007245bff3 /include | |
parent | 063989455d9ce10e61e2c617394d403218b3ec03 (diff) | |
download | external_llvm-f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4.zip external_llvm-f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4.tar.gz external_llvm-f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4.tar.bz2 |
- Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73671 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/Target/TargetRegisterInfo.h | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index 9da1134..91e8f80 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -523,7 +523,7 @@ public: /// register class in the form of a pair of TargetRegisterClass iterators. virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> getAllocationOrder(const TargetRegisterClass *RC, - std::pair<unsigned,unsigned> Hint, + unsigned HintType, unsigned HintReg, const MachineFunction &MF) const { return std::make_pair(RC->allocation_order_begin(MF), RC->allocation_order_end(MF)); @@ -531,13 +531,24 @@ public: /// ResolveRegAllocHint - Resolves the specified register allocation hint /// to a physical register. Returns the physical register if it is successful. - unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, - const MachineFunction &MF) const { + virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, + const MachineFunction &MF) const { if (Type == 0 && Reg && isPhysicalRegister(Reg)) return Reg; return 0; } + /// UpdateRegAllocHint - A callback to allow target a chance to update + /// register allocation hints when a register is "changed" (e.g. coalesced) + /// to another register. e.g. On ARM, some virtual registers should target + /// register pairs, if one of pair is coalesced to another register, the + /// allocation hint of the other half of the pair should be changed to point + /// to the new register. + virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, + MachineFunction &MF) const { + // Do nothing. + } + /// targetHandlesStackFrameRounding - Returns true if the target is /// responsible for rounding up the stack frame (probably at emitPrologue /// time). |