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authorEvan Cheng <evan.cheng@apple.com>2009-05-28 23:52:18 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-05-28 23:52:18 +0000
commitd3c76bb6fc3c066286850e91b8bf03484ea2a56e (patch)
treeddc9f96ae7a0778351a62a3c122511d14e8d304c /lib/CodeGen/SelectionDAG
parent2265ba071762b461ed1e65ebd73f596a98208f60 (diff)
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Do not try to create a MVT type of width 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72557 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG')
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 3bc9cf0..4c1710d 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4937,6 +4937,8 @@ SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
if (Opc == ISD::AND)
Imm ^= APInt::getAllOnesValue(BitWidth);
+ if (Imm == 0 || Imm.isAllOnesValue())
+ return SDValue();
unsigned ShAmt = Imm.countTrailingZeros();
unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
unsigned NewBW = NextPowerOf2(MSB - ShAmt);