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authorEric Christopher <echristo@apple.com>2010-08-19 15:35:27 +0000
committerEric Christopher <echristo@apple.com>2010-08-19 15:35:27 +0000
commit979e0a141487a4cd8538dffbe09eca544acf14c7 (patch)
treec64e28a379e508580b0112879d6dcebb172d883d /lib/Target/ARM/ARMFastISel.cpp
parent44cbde85badb60c7078e37e14575c15e671521b1 (diff)
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Silence warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111518 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMFastISel.cpp')
-rw-r--r--lib/Target/ARM/ARMFastISel.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index 211e319..6dbf0fc 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -137,7 +137,7 @@ ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
// Do we optionally set a predicate? Preds is size > 0 iff the predicate
// defines CPSR. All other OptionalDefines in ARM are the CCR register.
- bool CPSR;
+ bool CPSR = false;
if (DefinesOptionalPredicate(MI, &CPSR)) {
if (CPSR)
AddDefaultT1CC(MIB);