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| author | Johnny Chen <johnny.chen@apple.com> | 2010-03-24 19:47:14 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2010-03-24 19:47:14 +0000 |
| commit | 2fadd6b221893595a7a86eb4b03f5aeadb6088fc (patch) | |
| tree | dba2eb579ecb28d3207b4aec767ff73c739cfb2f /lib/Target/ARM/ARMInstrNEON.td | |
| parent | 16e02097d283159c240996185a8b20f4ea46ccfc (diff) | |
| download | external_llvm-2fadd6b221893595a7a86eb4b03f5aeadb6088fc.zip external_llvm-2fadd6b221893595a7a86eb4b03f5aeadb6088fc.tar.gz external_llvm-2fadd6b221893595a7a86eb4b03f5aeadb6088fc.tar.bz2 | |
Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.
NVCVTFrm will later be used to describe "vcvt with fractional bits".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99415 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrNEON.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 33 |
1 files changed, 9 insertions, 24 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 7f0fdad..57da366 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -853,41 +853,26 @@ def SubReg_i32_lane : SDNodeXForm<imm, [{ // Instruction Classes //===----------------------------------------------------------------------===// -// Same as N2V except that it doesn't pass a default N2RegFrm to NDataI. -class N2V2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, - bits<5> op11_7, bit op6, bit op4, - dag oops, dag iops, Format f, InstrItinClass itin, - string opc, string dt, string asm, string cstr, list<dag> pattern> - : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { - let Inst{24-23} = op24_23; - let Inst{21-20} = op21_20; - let Inst{19-18} = op19_18; - let Inst{17-16} = op17_16; - let Inst{11-7} = op11_7; - let Inst{6} = op6; - let Inst{4} = op4; -} - // Basic 2-register operations: single-, double- and quad-register. // This is used for NVCVTFrm form. class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode> - : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, - (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NVCVTFrm, - IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>; + : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, + (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), + IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>; class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode> - : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst), - (ins DPR:$src), NVCVTFrm, IIC_VUNAD, OpcodeStr, Dt,"$dst, $src","", - [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>; + : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst), + (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt,"$dst, $src", "", + [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>; class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode> - : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst), - (ins QPR:$src), NVCVTFrm, IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src","", - [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>; + : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst), + (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src", "", + [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>; // Basic 2-register intrinsics, both double- and quad-register. class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, |