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authorEvan Cheng <evan.cheng@apple.com>2010-09-08 22:57:08 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-09-08 22:57:08 +0000
commit7602acbf3b90af995606e199d68510b856c8e7e7 (patch)
tree13a1d083b98c9bdb8180e81167543031672a0436 /lib/Target/ARM/ARMScheduleA9.td
parent90b54547d9fcc381f8ec92c32756ad4da43ed9aa (diff)
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Fix LDM_RET schedule itinery.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113435 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA9.td')
-rw-r--r--lib/Target/ARM/ARMScheduleA9.td6
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td
index df2f896..4a764cc 100644
--- a/lib/Target/ARM/ARMScheduleA9.td
+++ b/lib/Target/ARM/ARMScheduleA9.td
@@ -107,6 +107,12 @@ def CortexA9Itineraries : ProcessorItineraries<
InstrItinData<IIC_iLoadm , [InstrStage<1, [A9_Pipe1]>,
InstrStage<1, [A9_LSPipe]>]>,
+ //
+ // Load multiple plus branch
+ InstrItinData<IIC_iLoadmBr , [InstrStage<1, [A9_Pipe1]>,
+ InstrStage<1, [A9_LSPipe]>,
+ InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>,
+
// Integer store pipeline
///
// Immediate offset