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| author | Evan Cheng <evan.cheng@apple.com> | 2009-08-11 09:37:40 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-08-11 09:37:40 +0000 |
| commit | 195c71b472d3f83c1051d2b87f4e93cc928b6ec9 (patch) | |
| tree | dba01389e024e6acd7b66ff614b8e7b1278a2bc2 /lib/Target/ARM/Thumb2SizeReduction.cpp | |
| parent | 3a21425dbe09c7ac85e6b156f82184dd6132435a (diff) | |
| download | external_llvm-195c71b472d3f83c1051d2b87f4e93cc928b6ec9.zip external_llvm-195c71b472d3f83c1051d2b87f4e93cc928b6ec9.tar.gz external_llvm-195c71b472d3f83c1051d2b87f4e93cc928b6ec9.tar.bz2 | |
Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78659 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Thumb2SizeReduction.cpp')
| -rw-r--r-- | lib/Target/ARM/Thumb2SizeReduction.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/ARM/Thumb2SizeReduction.cpp b/lib/Target/ARM/Thumb2SizeReduction.cpp index 2812cd3..a9fb95a 100644 --- a/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -94,7 +94,7 @@ namespace { { ARM::t2LDRBs, ARM::tLDRB, 0, 0, 0, 1, 0, 0,0, 1 }, { ARM::t2LDRHi12,ARM::tLDRH, 0, 5, 0, 1, 0, 0,0, 1 }, { ARM::t2LDRHs, ARM::tLDRH, 0, 0, 0, 1, 0, 0,0, 1 }, - { ARM::t2LDRSBs,ARM::tLDR, 0, 0, 0, 1, 0, 0,0, 1 }, + { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 1 }, { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 1 }, { ARM::t2STRi12,ARM::tSTR, 0, 5, 0, 1, 0, 0,0, 1 }, { ARM::t2STRs, ARM::tSTR, 0, 0, 0, 1, 0, 0,0, 1 }, @@ -248,10 +248,12 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, if (Entry.NarrowOpc1 != ARM::tLDRSB && Entry.NarrowOpc1 != ARM::tLDRSH) { // tLDRSB and tLDRSH do not have an immediate offset field. On the other // hand, it must have an offset register. - assert(OffsetReg && "Invalid so_reg load / store address!"); // FIXME: Remove this special case. MIB.addImm(OffsetImm/Scale); } + + assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); + MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); // Transfer the rest of operands. |