Let me introduce you to the early stages of the llvm backend for the alpha processor

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19764 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 43 insertions, 0 deletions

diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
new file mode 100644
index 0000000..3ca0ebd
--- /dev/null
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
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+//===- AlphaInstrInfo.cpp - Alpha Instruction Information ---*- C++ -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+//
+// This file contains the Alpha implementation of the TargetInstrInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Alpha.h"
+#include "AlphaInstrInfo.h"
+#include "AlphaGenInstrInfo.inc"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include <iostream>
+using namespace llvm;
+
+AlphaInstrInfo::AlphaInstrInfo()
+  : TargetInstrInfo(AlphaInsts, sizeof(AlphaInsts)/sizeof(AlphaInsts[0])) { }
+
+
+bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
+                                 unsigned& sourceReg,
+                                 unsigned& destReg) const {
+  //assert(0 && "TODO");
+  MachineOpCode oc = MI.getOpcode();
+  if (oc == Alpha::BIS) {  // or r1, r2, r2
+    assert(MI.getNumOperands() == 3 &&
+           MI.getOperand(0).isRegister() &&
+           MI.getOperand(1).isRegister() &&
+           MI.getOperand(2).isRegister() &&
+           "invalid Alpha BIS instruction!");
+    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
+      sourceReg = MI.getOperand(1).getReg();
+      destReg = MI.getOperand(0).getReg();
+      return true;
+    }
+  }
+  return false;
+}