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| author | Chris Lattner <sabre@nondot.org> | 2007-12-30 20:49:49 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2007-12-30 20:49:49 +0000 |
| commit | a96056a6649e5df71d673e058aa559b80df273ec (patch) | |
| tree | 87d9f35ded3a067f2d7aa4d17bfe0e362fb0f17d /lib/Target/Alpha/AlphaLLRP.cpp | |
| parent | 3a36a9e9c5f3a14eaa95e5c33e611eaed84203d4 (diff) | |
| download | external_llvm-a96056a6649e5df71d673e058aa559b80df273ec.zip external_llvm-a96056a6649e5df71d673e058aa559b80df273ec.tar.gz external_llvm-a96056a6649e5df71d673e058aa559b80df273ec.tar.bz2 | |
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaLLRP.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaLLRP.cpp | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp index 79d03c6..15d12c7 100644 --- a/lib/Target/Alpha/AlphaLLRP.cpp +++ b/lib/Target/Alpha/AlphaLLRP.cpp @@ -67,11 +67,9 @@ namespace { case Alpha::STW: case Alpha::STB: case Alpha::STT: case Alpha::STS: if (MI->getOperand(2).getReg() == Alpha::R30) { - if (prev[0] - && prev[0]->getOperand(2).getReg() == - MI->getOperand(2).getReg() - && prev[0]->getOperand(1).getImmedValue() == - MI->getOperand(1).getImmedValue()) { + if (prev[0] && + prev[0]->getOperand(2).getReg() == MI->getOperand(2).getReg()&& + prev[0]->getOperand(1).getImm() == MI->getOperand(1).getImm()){ prev[0] = prev[1]; prev[1] = prev[2]; prev[2] = 0; @@ -83,8 +81,8 @@ namespace { } else if (prev[1] && prev[1]->getOperand(2).getReg() == MI->getOperand(2).getReg() - && prev[1]->getOperand(1).getImmedValue() == - MI->getOperand(1).getImmedValue()) { + && prev[1]->getOperand(1).getImm() == + MI->getOperand(1).getImm()) { prev[0] = prev[2]; prev[1] = prev[2] = 0; BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) @@ -98,8 +96,8 @@ namespace { } else if (prev[2] && prev[2]->getOperand(2).getReg() == MI->getOperand(2).getReg() - && prev[2]->getOperand(1).getImmedValue() == - MI->getOperand(1).getImmedValue()) { + && prev[2]->getOperand(1).getImm() == + MI->getOperand(1).getImm()) { prev[0] = prev[1] = prev[2] = 0; BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); |