Replace the SubRegSet tablegen class with a less error-prone mechanism.

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 4 insertions, 24 deletions

diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.td b/lib/Target/Blackfin/BlackfinRegisterInfo.td
index 8379ce7..e1cfae9 100644
--- a/lib/Target/Blackfin/BlackfinRegisterInfo.td
+++ b/lib/Target/Blackfin/BlackfinRegisterInfo.td
@@ -19,6 +19,7 @@ let Namespace = "BF" in {
 def lo16 : SubRegIndex;
 def hi16 : SubRegIndex;
 def lo32 : SubRegIndex;
+def hi32 : SubRegIndex;
 }
 
 // Registers are identified with 3-bit group and 3-bit ID numbers.
@@ -49,6 +50,7 @@ class Ri<bits<3> group, bits<3> num, string n> : BlackfinReg<n> {
 // Ra 40-bit accumulator registers
 class Ra<bits<3> num, string n, list<Register> subs> : BlackfinReg<n> {
   let SubRegs = subs;
+  let SubRegIndices = [hi32, lo32];
   let Group = 4;
   let Num = num;
 }
@@ -63,6 +65,7 @@ multiclass Rss<bits<3> group, bits<3> num, string n> {
 class Rii<bits<3> group, bits<3> num, string n, list<Register> subs>
       : BlackfinReg<n> {
   let SubRegs = subs;
+  let SubRegIndices = [hi16, lo16];
   let Group = group;
   let Num = num;
 }
@@ -173,7 +176,7 @@ def RETN : Ri<7, 5, "retn">,  DwarfRegNum<[38]>;
 def RETE : Ri<7, 6, "rete">,  DwarfRegNum<[39]>;
 
 def ASTAT   : Ri<4, 6, "astat">,   DwarfRegNum<[40]> {
-  let SubRegs = [AZ, AN, CC, NCC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS];
+  let Aliases = [AZ, AN, CC, NCC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS];
 }
 
 def SEQSTAT : Ri<7, 1, "seqstat">, DwarfRegNum<[41]>;
@@ -191,29 +194,6 @@ def LC1 : Ri<6, 3, "lc1">, DwarfRegNum<[47]>;
 def LB0 : Ri<6, 2, "lb0">, DwarfRegNum<[48]>;
 def LB1 : Ri<6, 5, "lb1">, DwarfRegNum<[49]>;
 
-def : SubRegSet<lo16,
-    [R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,
-     P0,  P1,  P2,  P3,  P4,  P5,  SP,  FP,
-     I0,  I1,  I2,  I3,  M0,  M1,  M2,  M3,
-     B0,  B1,  B2,  B3,  L0,  L1,  L2,  L3],
-    [R0L, R1L, R2L, R3L, R4L, R5L, R6L, R7L,
-     P0L, P1L, P2L, P3L, P4L, P5L, SPL, FPL,
-     I0L, I1L, I2L, I3L, M0L, M1L, M2L, M3L,
-     B0L, B1L, B2L, B3L, L0L, L1L, L2L, L3L]>;
-
-def : SubRegSet<hi16,
-    [R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,
-     P0,  P1,  P2,  P3,  P4,  P5,  SP,  FP,
-     I0,  I1,  I2,  I3,  M0,  M1,  M2,  M3,
-     B0,  B1,  B2,  B3,  L0,  L1,  L2,  L3],
-    [R0H, R1H, R2H, R3H, R4H, R5H, R6H, R7H,
-     P0H, P1H, P2H, P3H, P4H, P5H, SPH, FPH,
-     I0H, I1H, I2H, I3H, M0H, M1H, M2H, M3H,
-     B0H, B1H, B2H, B3H, L0H, L1H, L2H, L3H]>;
-
-def : SubRegSet<lo16, [A0, A0W, A1, A1W], [A0L, A0L, A1L, A1L]>;
-def : SubRegSet<hi16, [A0, A0W, A1, A1W], [A0H, A0H, A1H, A1H]>;
-
 // Register classes.
 def D16 : RegisterClass<"BF", [i16], 16,
     [R0H, R0L, R1H, R1L, R2H, R2L, R3H, R3L,