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authorDan Gohman <gohman@apple.com>2010-04-15 17:20:57 +0000
committerDan Gohman <gohman@apple.com>2010-04-15 17:20:57 +0000
commit82bcd236937b378e56e46bdde9c17a3ea3377068 (patch)
treeac218b3e03d059501343f314dd189ad7b87b2cc6 /lib/Target/PowerPC
parentb35798347ea87b8b6d36155b211016a7769f01ab (diff)
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EnablePPC64RS and EnablePPC32RS are used in multiple files, so they
can't be static. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101377 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC')
-rw-r--r--lib/Target/PowerPC/PPCInstrInfo.cpp5
-rw-r--r--lib/Target/PowerPC/PPCRegisterInfo.cpp10
2 files changed, 11 insertions, 4 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index bc45c22..9a26ad8 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -24,10 +24,13 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/MC/MCAsmInfo.h"
-using namespace llvm;
+namespace llvm {
extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
+}
+
+using namespace llvm;
PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
: TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index b488af5..889acde 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -43,7 +43,6 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
-using namespace llvm;
// FIXME This disables some code that aligns the stack to a boundary
// bigger than the default (16 bytes on Darwin) when there is a stack local
@@ -56,14 +55,19 @@ using namespace llvm;
#define ALIGN_STACK 0
// FIXME (64-bit): Eventually enable by default.
-static cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
+namespace llvm {
+cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
cl::init(false),
cl::desc("Enable PPC32 register scavenger"),
cl::Hidden);
-static cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
+cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
cl::init(false),
cl::desc("Enable PPC64 register scavenger"),
cl::Hidden);
+}
+
+using namespace llvm;
+
#define EnableRegisterScavenging \
((EnablePPC32RS && !Subtarget.isPPC64()) || \
(EnablePPC64RS && Subtarget.isPPC64()))