First patch in the direction of splitting MachineCodeEmitter in two subclasses:

JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 129 insertions, 53 deletions

diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h
index 78c970e..c844e21 100644
--- a/lib/Target/PowerPC/PPC.h
+++ b/lib/Target/PowerPC/PPC.h
@@ -33,6 +33,8 @@ FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
                                       CodeGenOpt::Level OptLevel, bool Verbose);
 FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
                                        MachineCodeEmitter &MCE);
+FunctionPass *createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
+                                       JITCodeEmitter &MCE);
 } // end namespace llvm;
 
 // Defines symbolic names for PowerPC registers.  This defines a mapping from
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index f80442f..c3be878 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -18,6 +18,7 @@
 #include "llvm/Module.h"
 #include "llvm/PassManager.h"
 #include "llvm/CodeGen/MachineCodeEmitter.h"
+#include "llvm/CodeGen/JITCodeEmitter.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
@@ -28,18 +29,36 @@
 using namespace llvm;
 
 namespace {
-  class VISIBILITY_HIDDEN PPCCodeEmitter : public MachineFunctionPass {
+  class PPCCodeEmitter {
     TargetMachine &TM;
     MachineCodeEmitter &MCE;
+  public:
+    PPCCodeEmitter( TargetMachine &tm, MachineCodeEmitter &mce) : 
+        TM( tm), MCE( mce) {}
+
+    /// getBinaryCodeForInstr - This function, generated by the
+    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
+    /// machine instructions.
+
+    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
+
+    /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
+
+    unsigned getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO);
 
     /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
     /// its address in the function into this pointer.
+
     void *MovePCtoLROffset;
-    
-    /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
-    ///
-    unsigned getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO);
-    
+  };
+
+  template <class machineCodeEmitter>
+  class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
+      public PPCCodeEmitter
+  {
+    TargetMachine &TM;
+    machineCodeEmitter &MCE;
+
     void getAnalysisUsage(AnalysisUsage &AU) const {
       AU.addRequired<MachineModuleInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
@@ -47,8 +66,8 @@ namespace {
 
   public:
     static char ID;
-    PPCCodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
-      : MachineFunctionPass(&ID), TM(T), MCE(M) {}
+    Emitter(TargetMachine &tm, machineCodeEmitter &mce)
+      : MachineFunctionPass(&ID), PPCCodeEmitter( tm, mce), TM(tm), MCE(mce) {}
 
     const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
 
@@ -63,24 +82,26 @@ namespace {
     /// getValueBit - return the particular bit of Val
     ///
     unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; }
-
-    /// getBinaryCodeForInstr - This function, generated by the
-    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
-    /// machine instructions.
-    ///
-    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
   };
-  char PPCCodeEmitter::ID = 0;
-}
 
+  template <class machineCodeEmitter>
+    char Emitter<machineCodeEmitter>::ID = 0;
+}
+	
 /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
 /// to the specified MCE object.
 FunctionPass *llvm::createPPCCodeEmitterPass(PPCTargetMachine &TM,
-                                             MachineCodeEmitter &MCE) {
-  return new PPCCodeEmitter(TM, MCE);
+                                       MachineCodeEmitter &MCE) {
+  return new Emitter<MachineCodeEmitter>(TM, MCE);
+}
+
+FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
+                                             JITCodeEmitter &JCE) {
+  return new Emitter<JITCodeEmitter>(TM, JCE);
 }
 
-bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
+template <class machineCodeEmitter>
+bool Emitter<machineCodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
   assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
           MF.getTarget().getRelocationModel() != Reloc::Static) &&
          "JIT relocation model must be set to static or default!");
@@ -96,7 +117,8 @@ bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
   return false;
 }
 
-void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
+template <class machineCodeEmitter>
+void Emitter<machineCodeEmitter>::emitBasicBlock(MachineBasicBlock &MBB) {
   MCE.StartMachineBasicBlock(&MBB);
   
   for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
diff --git a/lib/Target/PowerPC/PPCJITInfo.cpp b/lib/Target/PowerPC/PPCJITInfo.cpp
index b5de318..035647e 100644
--- a/lib/Target/PowerPC/PPCJITInfo.cpp
+++ b/lib/Target/PowerPC/PPCJITInfo.cpp
@@ -16,7 +16,6 @@
 #include "PPCRelocations.h"
 #include "PPCTargetMachine.h"
 #include "llvm/Function.h"
-#include "llvm/CodeGen/MachineCodeEmitter.h"
 #include "llvm/System/Memory.h"
 #include "llvm/Support/Debug.h"
 using namespace llvm;
@@ -330,51 +329,51 @@ extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
 #endif
 
 void *PPCJITInfo::emitFunctionStub(const Function* F, void *Fn,
-                                   MachineCodeEmitter &MCE) {
+                                   JITCodeEmitter &JCE) {
   // If this is just a call to an external function, emit a branch instead of a
   // call.  The code is the same except for one bit of the last instruction.
   if (Fn != (void*)(intptr_t)PPC32CompilationCallback && 
       Fn != (void*)(intptr_t)PPC64CompilationCallback) {
-    MCE.startGVStub(F, 7*4);
-    intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
-    MCE.emitWordBE(0);
-    MCE.emitWordBE(0);
-    MCE.emitWordBE(0);
-    MCE.emitWordBE(0);
-    MCE.emitWordBE(0);
-    MCE.emitWordBE(0);
-    MCE.emitWordBE(0);
+    JCE.startGVStub(F, 7*4);
+    intptr_t Addr = (intptr_t)JCE.getCurrentPCValue();
+    JCE.emitWordBE(0);
+    JCE.emitWordBE(0);
+    JCE.emitWordBE(0);
+    JCE.emitWordBE(0);
+    JCE.emitWordBE(0);
+    JCE.emitWordBE(0);
+    JCE.emitWordBE(0);
     EmitBranchToAt(Addr, (intptr_t)Fn, false, is64Bit);
     sys::Memory::InvalidateInstructionCache((void*)Addr, 7*4);
-    return MCE.finishGVStub(F);
+    return JCE.finishGVStub(F);
   }
 
-  MCE.startGVStub(F, 10*4);
-  intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
+  JCE.startGVStub(F, 10*4);
+  intptr_t Addr = (intptr_t)JCE.getCurrentPCValue();
   if (is64Bit) {
-    MCE.emitWordBE(0xf821ffb1);     // stdu r1,-80(r1)
-    MCE.emitWordBE(0x7d6802a6);     // mflr r11
-    MCE.emitWordBE(0xf9610060);     // std r11, 96(r1)
+    JCE.emitWordBE(0xf821ffb1);     // stdu r1,-80(r1)
+    JCE.emitWordBE(0x7d6802a6);     // mflr r11
+    JCE.emitWordBE(0xf9610060);     // std r11, 96(r1)
   } else if (TM.getSubtargetImpl()->isMachoABI()){
-    MCE.emitWordBE(0x9421ffe0);     // stwu r1,-32(r1)
-    MCE.emitWordBE(0x7d6802a6);     // mflr r11
-    MCE.emitWordBE(0x91610028);     // stw r11, 40(r1)
+    JCE.emitWordBE(0x9421ffe0);     // stwu r1,-32(r1)
+    JCE.emitWordBE(0x7d6802a6);     // mflr r11
+    JCE.emitWordBE(0x91610028);     // stw r11, 40(r1)
   } else {
-    MCE.emitWordBE(0x9421ffe0);     // stwu r1,-32(r1)
-    MCE.emitWordBE(0x7d6802a6);     // mflr r11
-    MCE.emitWordBE(0x91610024);     // stw r11, 36(r1)
+    JCE.emitWordBE(0x9421ffe0);     // stwu r1,-32(r1)
+    JCE.emitWordBE(0x7d6802a6);     // mflr r11
+    JCE.emitWordBE(0x91610024);     // stw r11, 36(r1)
   }
-  intptr_t BranchAddr = (intptr_t)MCE.getCurrentPCValue();
-  MCE.emitWordBE(0);
-  MCE.emitWordBE(0);
-  MCE.emitWordBE(0);
-  MCE.emitWordBE(0);
-  MCE.emitWordBE(0);
-  MCE.emitWordBE(0);
-  MCE.emitWordBE(0);
+  intptr_t BranchAddr = (intptr_t)JCE.getCurrentPCValue();
+  JCE.emitWordBE(0);
+  JCE.emitWordBE(0);
+  JCE.emitWordBE(0);
+  JCE.emitWordBE(0);
+  JCE.emitWordBE(0);
+  JCE.emitWordBE(0);
+  JCE.emitWordBE(0);
   EmitBranchToAt(BranchAddr, (intptr_t)Fn, true, is64Bit);
   sys::Memory::InvalidateInstructionCache((void*)Addr, 10*4);
-  return MCE.finishGVStub(F);
+  return JCE.finishGVStub(F);
 }
 
 
diff --git a/lib/Target/PowerPC/PPCJITInfo.h b/lib/Target/PowerPC/PPCJITInfo.h
index c93a84a..2e25b29 100644
--- a/lib/Target/PowerPC/PPCJITInfo.h
+++ b/lib/Target/PowerPC/PPCJITInfo.h
@@ -15,6 +15,7 @@
 #define POWERPC_JITINFO_H
 
 #include "llvm/Target/TargetJITInfo.h"
+#include "llvm/CodeGen/JITCodeEmitter.h"
 
 namespace llvm {
   class PPCTargetMachine;
@@ -30,7 +31,7 @@ namespace llvm {
     }
 
     virtual void *emitFunctionStub(const Function* F, void *Fn,
-                                   MachineCodeEmitter &MCE);
+                                   JITCodeEmitter &JCE);
     virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
     virtual void relocate(void *Function, MachineRelocation *MR,
                           unsigned NumRelocs, unsigned char* GOTBase);
diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index bb17ea9..aeb451b 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -186,6 +186,38 @@ bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
   return false;
 }
 
+bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
+                                      CodeGenOpt::Level OptLevel,
+                                      bool DumpAsm, JITCodeEmitter &JCE) {
+  // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
+  // FIXME: This should be moved to TargetJITInfo!!
+  if (Subtarget.isPPC64()) {
+    // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
+    // instructions to materialize arbitrary global variable + function +
+    // constant pool addresses.
+    setRelocationModel(Reloc::PIC_);
+    // Temporary workaround for the inability of PPC64 JIT to handle jump
+    // tables.
+    DisableJumpTables = true;      
+  } else {
+    setRelocationModel(Reloc::Static);
+  }
+  
+  // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
+  // writing?
+  Subtarget.SetJITMode();
+  
+  // Machine code emitter pass for PowerPC.
+  PM.add(createPPCJITCodeEmitterPass(*this, JCE));
+  if (DumpAsm) {
+    assert(AsmPrinterCtor && "AsmPrinter was not linked in");
+    if (AsmPrinterCtor)
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+  }
+
+  return false;
+}
+
 bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
                                             CodeGenOpt::Level OptLevel,
                                             bool DumpAsm, MachineCodeEmitter &MCE) {
@@ -199,3 +231,18 @@ bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
 
   return false;
 }
+
+bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+                                            CodeGenOpt::Level OptLevel,
+                                            bool DumpAsm, JITCodeEmitter &JCE) {
+  // Machine code emitter pass for PowerPC.
+  PM.add(createPPCJITCodeEmitterPass(*this, JCE));
+  if (DumpAsm) {
+    assert(AsmPrinterCtor && "AsmPrinter was not linked in");
+    if (AsmPrinterCtor)
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+  }
+
+  return false;
+}
+
diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h
index efdf918..086d2f4 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/lib/Target/PowerPC/PPCTargetMachine.h
@@ -84,9 +84,14 @@ public:
                                   bool Verbose, raw_ostream &Out);
   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
                               bool DumpAsm, MachineCodeEmitter &MCE);
+  virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
+                              bool DumpAsm, JITCodeEmitter &JCE);
   virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
                                     CodeGenOpt::Level OptLevel,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+                                    CodeGenOpt::Level OptLevel,
+                                    bool DumpAsm, JITCodeEmitter &JCE);
   virtual bool getEnableTailMergeDefault() const;
 };