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authorOwen Anderson <resistor@mac.com>2013-05-22 06:36:09 +0000
committerOwen Anderson <resistor@mac.com>2013-05-22 06:36:09 +0000
commitf9c3ea31db080e361a96df0b11cee3e835c6a6a1 (patch)
treea676931a842752bfef3c04a264032181a30689d0 /lib/Target/R600/AMDGPUInstrInfo.td
parent6cfed36338d7728076ddbc1331908b887a4302d3 (diff)
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Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182450 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/AMDGPUInstrInfo.td')
-rw-r--r--lib/Target/R600/AMDGPUInstrInfo.td2
1 files changed, 0 insertions, 2 deletions
diff --git a/lib/Target/R600/AMDGPUInstrInfo.td b/lib/Target/R600/AMDGPUInstrInfo.td
index a0a3410..48d89dd 100644
--- a/lib/Target/R600/AMDGPUInstrInfo.td
+++ b/lib/Target/R600/AMDGPUInstrInfo.td
@@ -65,8 +65,6 @@ def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
// e is rounding error
def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
-def fpow : SDNode<"ISD::FPOW", SDTFPBinOp>;
-
def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
[SDNPHasChain, SDNPMayLoad]>;