diff options
author | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
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committer | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
commit | ebe69fe11e48d322045d5949c83283927a0d790b (patch) | |
tree | c92f1907a6b8006628a4b01615f38264d29834ea /lib/Target/Sparc | |
parent | b7d2e72b02a4cb8034f32f8247a2558d2434e121 (diff) | |
download | external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.zip external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.gz external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.bz2 |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
Diffstat (limited to 'lib/Target/Sparc')
-rw-r--r-- | lib/Target/Sparc/AsmParser/SparcAsmParser.cpp | 5 | ||||
-rw-r--r-- | lib/Target/Sparc/DelaySlotFiller.cpp | 17 | ||||
-rw-r--r-- | lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp | 4 | ||||
-rw-r--r-- | lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp | 4 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcAsmPrinter.cpp | 12 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcFrameLowering.cpp | 7 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcISelDAGToDAG.cpp | 15 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcISelLowering.cpp | 52 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcISelLowering.h | 8 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.td | 18 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcSubtarget.cpp | 30 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcSubtarget.h | 2 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcTargetMachine.cpp | 37 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcTargetMachine.h | 2 |
14 files changed, 99 insertions, 114 deletions
diff --git a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index d0b362c..551189c 100644 --- a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -393,9 +393,6 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm); switch (MatchResult) { - default: - break; - case Match_Success: { Inst.setLoc(IDLoc); Out.EmitInstruction(Inst, STI); @@ -422,7 +419,7 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_MnemonicFail: return Error(IDLoc, "invalid instruction mnemonic"); } - return true; + llvm_unreachable("Implement any new match types added!"); } bool SparcAsmParser:: diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp index 28369fd..38bff44 100644 --- a/lib/Target/Sparc/DelaySlotFiller.cpp +++ b/lib/Target/Sparc/DelaySlotFiller.cpp @@ -45,10 +45,7 @@ namespace { const SparcSubtarget *Subtarget; static char ID; - Filler(TargetMachine &tm) - : MachineFunctionPass(ID), TM(tm), - Subtarget(&TM.getSubtarget<SparcSubtarget>()) { - } + Filler(TargetMachine &tm) : MachineFunctionPass(ID), TM(tm) {} const char *getPassName() const override { return "SPARC Delay Slot Filler"; @@ -57,6 +54,7 @@ namespace { bool runOnMachineBasicBlock(MachineBasicBlock &MBB); bool runOnMachineFunction(MachineFunction &F) override { bool Changed = false; + Subtarget = &F.getSubtarget<SparcSubtarget>(); // This pass invalidates liveness information when it reorders // instructions to fill delay slot. @@ -109,8 +107,8 @@ FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) { /// bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; - - const TargetInstrInfo *TII = TM.getSubtargetImpl()->getInstrInfo(); + Subtarget = &MBB.getParent()->getSubtarget<SparcSubtarget>(); + const TargetInstrInfo *TII = Subtarget->getInstrInfo(); for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) { MachineBasicBlock::iterator MI = I; @@ -187,7 +185,7 @@ Filler::findDelayInstr(MachineBasicBlock &MBB, if (J->getOpcode() == SP::RESTORErr || J->getOpcode() == SP::RESTOREri) { // change retl to ret. - slot->setDesc(TM.getSubtargetImpl()->getInstrInfo()->get(SP::RET)); + slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET)); return J; } } @@ -329,8 +327,7 @@ void Filler::insertDefsUses(MachineBasicBlock::iterator MI, bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) { // Check Reg and all aliased Registers. - for (MCRegAliasIterator AI(Reg, TM.getSubtargetImpl()->getRegisterInfo(), - true); + for (MCRegAliasIterator AI(Reg, Subtarget->getRegisterInfo(), true); AI.isValid(); ++AI) if (RegSet.count(*AI)) return true; @@ -483,7 +480,7 @@ bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB, if (PrevInst->isBundledWithSucc()) return false; - const TargetInstrInfo *TII = TM.getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = Subtarget->getInstrInfo(); switch (PrevInst->getOpcode()) { default: break; diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp index 3a9c987..6767e4b 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp @@ -42,9 +42,7 @@ SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) { SunStyleELFSectionSwitchSyntax = true; UsesELFSectionDirectiveForBSS = true; - if (TheTriple.getOS() == llvm::Triple::Solaris || - TheTriple.getOS() == llvm::Triple::OpenBSD) - UseIntegratedAssembler = true; + UseIntegratedAssembler = true; } const MCExpr* diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp index eea9626..5128843 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp @@ -31,8 +31,8 @@ STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); namespace { class SparcMCCodeEmitter : public MCCodeEmitter { - SparcMCCodeEmitter(const SparcMCCodeEmitter &) LLVM_DELETED_FUNCTION; - void operator=(const SparcMCCodeEmitter &) LLVM_DELETED_FUNCTION; + SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete; + void operator=(const SparcMCCodeEmitter &) = delete; MCContext &Ctx; public: diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp index 6432003..0439f9d 100644 --- a/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -43,8 +43,9 @@ namespace { *OutStreamer.getTargetStreamer()); } public: - explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) - : AsmPrinter(TM, Streamer) {} + explicit SparcAsmPrinter(TargetMachine &TM, + std::unique_ptr<MCStreamer> Streamer) + : AsmPrinter(TM, std::move(Streamer)) {} const char *getPassName() const override { return "Sparc Assembly Printer"; @@ -277,7 +278,7 @@ void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI) } void SparcAsmPrinter::EmitFunctionBodyStart() { - if (!TM.getSubtarget<SparcSubtarget>().is64Bit()) + if (!MF->getSubtarget<SparcSubtarget>().is64Bit()) return; const MachineRegisterInfo &MRI = MF->getRegInfo(); @@ -296,7 +297,7 @@ void SparcAsmPrinter::EmitFunctionBodyStart() { void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { - const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout(); + const DataLayout *DL = TM.getDataLayout(); const MachineOperand &MO = MI->getOperand (opNum); SparcMCExpr::VariantKind TF = (SparcMCExpr::VariantKind) MO.getTargetFlags(); @@ -450,8 +451,7 @@ void SparcAsmPrinter::EmitEndOfAsmFile(Module &M) { MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList(); if (!Stubs.empty()) { OutStreamer.SwitchSection(TLOFELF.getDataSection()); - unsigned PtrSize = - TM.getSubtargetImpl()->getDataLayout()->getPointerSize(0); + unsigned PtrSize = TM.getDataLayout()->getPointerSize(0); for (unsigned i = 0, e = Stubs.size(); i != e; ++i) { OutStreamer.EmitLabel(Stubs[i].first); OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(), PtrSize); diff --git a/lib/Target/Sparc/SparcFrameLowering.cpp b/lib/Target/Sparc/SparcFrameLowering.cpp index 1b67b4b..a065d3a 100644 --- a/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/lib/Target/Sparc/SparcFrameLowering.cpp @@ -103,9 +103,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF) const { SAVEri = SP::ADDri; SAVErr = SP::ADDrr; } - NumBytes = - -MF.getTarget().getSubtarget<SparcSubtarget>().getAdjustedFrameSize( - NumBytes); + NumBytes = -MF.getSubtarget<SparcSubtarget>().getAdjustedFrameSize(NumBytes); emitSPAdjustment(MF, MBB, MBBI, NumBytes, SAVErr, SAVEri); MachineModuleInfo &MMI = MF.getMMI(); @@ -168,8 +166,7 @@ void SparcFrameLowering::emitEpilogue(MachineFunction &MF, if (NumBytes == 0) return; - NumBytes = MF.getTarget().getSubtarget<SparcSubtarget>().getAdjustedFrameSize( - NumBytes); + NumBytes = MF.getSubtarget<SparcSubtarget>().getAdjustedFrameSize(NumBytes); emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri); } diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index b3b029e..9f03b04 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -32,13 +32,13 @@ namespace { class SparcDAGToDAGISel : public SelectionDAGISel { /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can /// make the right decision when generating code for different targets. - const SparcSubtarget &Subtarget; - SparcTargetMachine &TM; + const SparcSubtarget *Subtarget; public: - explicit SparcDAGToDAGISel(SparcTargetMachine &tm) - : SelectionDAGISel(tm), - Subtarget(tm.getSubtarget<SparcSubtarget>()), - TM(tm) { + explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(tm) {} + + bool runOnMachineFunction(MachineFunction &MF) override { + Subtarget = &MF.getSubtarget<SparcSubtarget>(); + return SelectionDAGISel::runOnMachineFunction(MF); } SDNode *Select(SDNode *N) override; @@ -66,8 +66,7 @@ private: } // end anonymous namespace SDNode* SparcDAGToDAGISel::getGlobalBaseReg() { - unsigned GlobalBaseReg = - TM.getSubtargetImpl()->getInstrInfo()->getGlobalBaseReg(MF); + unsigned GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF); return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy()).getNode(); } diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index e6a69d2..6774977 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -57,7 +57,7 @@ static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 }; // Try to get first reg. - if (unsigned Reg = State.AllocateReg(RegList, 6)) { + if (unsigned Reg = State.AllocateReg(RegList)) { State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); } else { // Assign whole thing in stack. @@ -68,7 +68,7 @@ static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, } // Try to get second reg. - if (unsigned Reg = State.AllocateReg(RegList, 6)) + if (unsigned Reg = State.AllocateReg(RegList)) State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); else State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, @@ -497,7 +497,7 @@ LowerFormalArguments_32(SDValue Chain, static const MCPhysReg ArgRegs[] = { SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 }; - unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); + unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs); const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; unsigned ArgOffset = CCInfo.getNextStackOffset(); if (NumAllocated == 6) @@ -914,8 +914,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, RegsToPass[i].second.getValueType())); // Add a register mask operand representing the call-preserved registers. - const SparcRegisterInfo *TRI = - getTargetMachine().getSubtarget<SparcSubtarget>().getRegisterInfo(); + const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo(); const uint32_t *Mask = ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CallConv) : TRI->getCallPreservedMask(CallConv)); @@ -1227,8 +1226,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, RegsToPass[i].second.getValueType())); // Add a register mask operand representing the call-preserved registers. - const SparcRegisterInfo *TRI = - getTargetMachine().getSubtarget<SparcSubtarget>().getRegisterInfo(); + const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo(); const uint32_t *Mask = ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv) : TRI->getCallPreservedMask(CLI.CallConv)); @@ -1365,10 +1363,9 @@ static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { } } -SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) - : TargetLowering(TM) { - Subtarget = &TM.getSubtarget<SparcSubtarget>(); - +SparcTargetLowering::SparcTargetLowering(TargetMachine &TM, + const SparcSubtarget &STI) + : TargetLowering(TM), Subtarget(&STI) { // Set up the register classes. addRegisterClass(MVT::i32, &SP::IntRegsRegClass); addRegisterClass(MVT::f32, &SP::FPRegsRegClass); @@ -1378,11 +1375,14 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) addRegisterClass(MVT::i64, &SP::I64RegsRegClass); // Turn FP extload into load/fextend - setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); - setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); + for (MVT VT : MVT::fp_valuetypes()) { + setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); + } // Sparc doesn't have i1 sign extending load - setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); + for (MVT VT : MVT::integer_valuetypes()) + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); // Turn FP truncstore into trunc + store. setTruncStoreAction(MVT::f64, MVT::f32, Expand); @@ -1669,7 +1669,7 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) setMinFunctionAlignment(2); - computeRegisterProperties(); + computeRegisterProperties(Subtarget->getRegisterInfo()); } const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { @@ -1904,10 +1904,8 @@ SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op, Ops.push_back(Callee); Ops.push_back(Symbol); Ops.push_back(DAG.getRegister(SP::O0, PtrVT)); - const uint32_t *Mask = getTargetMachine() - .getSubtargetImpl() - ->getRegisterInfo() - ->getCallPreservedMask(CallingConv::C); + const uint32_t *Mask = + Subtarget->getRegisterInfo()->getCallPreservedMask(CallingConv::C); assert(Mask && "Missing call preserved mask for calling convention"); Ops.push_back(DAG.getRegisterMask(Mask)); Ops.push_back(InFlag); @@ -2903,8 +2901,7 @@ MachineBasicBlock* SparcTargetLowering::expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB, unsigned BROpcode) const { - const TargetInstrInfo &TII = - *getTargetMachine().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); DebugLoc dl = MI->getDebugLoc(); unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); @@ -2965,8 +2962,7 @@ SparcTargetLowering::expandAtomicRMW(MachineInstr *MI, MachineBasicBlock *MBB, unsigned Opcode, unsigned CondCode) const { - const TargetInstrInfo &TII = - *getTargetMachine().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); DebugLoc DL = MI->getDebugLoc(); @@ -3134,8 +3130,9 @@ LowerAsmOperandForConstraint(SDValue Op, TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); } -std::pair<unsigned, const TargetRegisterClass*> -SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, +std::pair<unsigned, const TargetRegisterClass *> +SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, + const std::string &Constraint, MVT VT) const { if (Constraint.size() == 1) { switch (Constraint[0]) { @@ -3160,11 +3157,12 @@ SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, char regIdx = '0' + (intVal % 8); char tmp[] = { '{', regType, regIdx, '}', 0 }; std::string newConstraint = std::string(tmp); - return TargetLowering::getRegForInlineAsmConstraint(newConstraint, VT); + return TargetLowering::getRegForInlineAsmConstraint(TRI, newConstraint, + VT); } } - return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); + return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); } bool diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h index a62d569..8715326 100644 --- a/lib/Target/Sparc/SparcISelLowering.h +++ b/lib/Target/Sparc/SparcISelLowering.h @@ -54,7 +54,7 @@ namespace llvm { class SparcTargetLowering : public TargetLowering { const SparcSubtarget *Subtarget; public: - SparcTargetLowering(TargetMachine &TM); + SparcTargetLowering(TargetMachine &TM, const SparcSubtarget &STI); SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; /// computeKnownBitsForTargetNode - Determine which of the bits specified @@ -80,8 +80,10 @@ namespace llvm { std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const override; - std::pair<unsigned, const TargetRegisterClass*> - getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const override; + std::pair<unsigned, const TargetRegisterClass *> + getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, + const std::string &Constraint, + MVT VT) const override; bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; } diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index c320239..17daeca 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -22,38 +22,38 @@ include "SparcInstrFormats.td" //===----------------------------------------------------------------------===// // True when generating 32-bit code. -def Is32Bit : Predicate<"!Subtarget.is64Bit()">; +def Is32Bit : Predicate<"!Subtarget->is64Bit()">; // True when generating 64-bit code. This also implies HasV9. -def Is64Bit : Predicate<"Subtarget.is64Bit()">; +def Is64Bit : Predicate<"Subtarget->is64Bit()">; // HasV9 - This predicate is true when the target processor supports V9 // instructions. Note that the machine may be running in 32-bit mode. -def HasV9 : Predicate<"Subtarget.isV9()">, +def HasV9 : Predicate<"Subtarget->isV9()">, AssemblerPredicate<"FeatureV9">; // HasNoV9 - This predicate is true when the target doesn't have V9 // instructions. Use of this is just a hack for the isel not having proper // costs for V8 instructions that are more expensive than their V9 ones. -def HasNoV9 : Predicate<"!Subtarget.isV9()">; +def HasNoV9 : Predicate<"!Subtarget->isV9()">; // HasVIS - This is true when the target processor has VIS extensions. -def HasVIS : Predicate<"Subtarget.isVIS()">, +def HasVIS : Predicate<"Subtarget->isVIS()">, AssemblerPredicate<"FeatureVIS">; -def HasVIS2 : Predicate<"Subtarget.isVIS2()">, +def HasVIS2 : Predicate<"Subtarget->isVIS2()">, AssemblerPredicate<"FeatureVIS2">; -def HasVIS3 : Predicate<"Subtarget.isVIS3()">, +def HasVIS3 : Predicate<"Subtarget->isVIS3()">, AssemblerPredicate<"FeatureVIS3">; // HasHardQuad - This is true when the target processor supports quad floating // point instructions. -def HasHardQuad : Predicate<"Subtarget.hasHardQuad()">; +def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">; // UseDeprecatedInsts - This predicate is true when the target processor is a // V8, or when it is V9 but the V8 deprecated instructions are efficient enough // to use when appropriate. In either of these cases, the instruction selector // will pick deprecated instructions. -def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; +def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">; //===----------------------------------------------------------------------===// // Instruction Pattern Stuff diff --git a/lib/Target/Sparc/SparcSubtarget.cpp b/lib/Target/Sparc/SparcSubtarget.cpp index eea0c8c..ce1105f 100644 --- a/lib/Target/Sparc/SparcSubtarget.cpp +++ b/lib/Target/Sparc/SparcSubtarget.cpp @@ -26,32 +26,6 @@ using namespace llvm; void SparcSubtarget::anchor() { } -static std::string computeDataLayout(const SparcSubtarget &ST) { - // Sparc is big endian. - std::string Ret = "E-m:e"; - - // Some ABIs have 32bit pointers. - if (!ST.is64Bit()) - Ret += "-p:32:32"; - - // Alignments for 64 bit integers. - Ret += "-i64:64"; - - // On SparcV9 128 floats are aligned to 128 bits, on others only to 64. - // On SparcV9 registers can hold 64 or 32 bits, on others only 32. - if (ST.is64Bit()) - Ret += "-n32:64"; - else - Ret += "-f128:64-n32"; - - if (ST.is64Bit()) - Ret += "-S128"; - else - Ret += "-S64"; - - return Ret; -} - SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { IsV9 = false; @@ -79,8 +53,8 @@ SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, TargetMachine &TM, bool is64Bit) : SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), - DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))), - InstrInfo(*this), TLInfo(TM), TSInfo(DL), FrameLowering(*this) {} + InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), + TSInfo(*TM.getDataLayout()), FrameLowering(*this) {} int SparcSubtarget::getAdjustedFrameSize(int frameSize) const { diff --git a/lib/Target/Sparc/SparcSubtarget.h b/lib/Target/Sparc/SparcSubtarget.h index d503b2b..e6cf460 100644 --- a/lib/Target/Sparc/SparcSubtarget.h +++ b/lib/Target/Sparc/SparcSubtarget.h @@ -37,7 +37,6 @@ class SparcSubtarget : public SparcGenSubtargetInfo { bool Is64Bit; bool HasHardQuad; bool UsePopc; - const DataLayout DL; // Calculates type size & alignment SparcInstrInfo InstrInfo; SparcTargetLowering TLInfo; SparcSelectionDAGInfo TSInfo; @@ -60,7 +59,6 @@ public: const SparcSelectionDAGInfo *getSelectionDAGInfo() const override { return &TSInfo; } - const DataLayout *getDataLayout() const override { return &DL; } bool isV9() const { return IsV9; } bool isVIS() const { return IsVIS; } diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index 489bb69..1c423dc 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -14,7 +14,7 @@ #include "SparcTargetObjectFile.h" #include "Sparc.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/PassManager.h" +#include "llvm/IR/LegacyPassManager.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -24,6 +24,32 @@ extern "C" void LLVMInitializeSparcTarget() { RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target); } +static std::string computeDataLayout(bool is64Bit) { + // Sparc is big endian. + std::string Ret = "E-m:e"; + + // Some ABIs have 32bit pointers. + if (!is64Bit) + Ret += "-p:32:32"; + + // Alignments for 64 bit integers. + Ret += "-i64:64"; + + // On SparcV9 128 floats are aligned to 128 bits, on others only to 64. + // On SparcV9 registers can hold 64 or 32 bits, on others only 32. + if (is64Bit) + Ret += "-n32:64"; + else + Ret += "-f128:64-n32"; + + if (is64Bit) + Ret += "-S128"; + else + Ret += "-S64"; + + return Ret; +} + /// SparcTargetMachine ctor - Create an ILP32 architecture model /// SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, @@ -34,6 +60,7 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, bool is64bit) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), TLOF(make_unique<SparcELFTargetObjectFile>()), + DL(computeDataLayout(is64bit)), Subtarget(TT, CPU, FS, *this, is64bit) { initAsmInfo(); } @@ -53,7 +80,7 @@ public: void addIRPasses() override; bool addInstSelector() override; - bool addPreEmitPass() override; + void addPreEmitPass() override; }; } // namespace @@ -72,12 +99,8 @@ bool SparcPassConfig::addInstSelector() { return false; } -/// addPreEmitPass - This pass may be implemented by targets that want to run -/// passes immediately before machine code is emitted. This should return -/// true if -print-machineinstrs should print out the code after the passes. -bool SparcPassConfig::addPreEmitPass(){ +void SparcPassConfig::addPreEmitPass(){ addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine())); - return true; } void SparcV8TargetMachine::anchor() { } diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h index 096e7c8..4f93980 100644 --- a/lib/Target/Sparc/SparcTargetMachine.h +++ b/lib/Target/Sparc/SparcTargetMachine.h @@ -22,6 +22,7 @@ namespace llvm { class SparcTargetMachine : public LLVMTargetMachine { std::unique_ptr<TargetLoweringObjectFile> TLOF; + const DataLayout DL; SparcSubtarget Subtarget; public: SparcTargetMachine(const Target &T, StringRef TT, @@ -30,6 +31,7 @@ public: CodeGenOpt::Level OL, bool is64bit); ~SparcTargetMachine() override; + const DataLayout *getDataLayout() const override { return &DL; } const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; } // Pass Pipeline Configuration |