Split EVT into MVT and EVT, the former representing _just_ a primitive type, while

the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 107 insertions, 107 deletions

diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index a8357a1..11d1306 100644
--- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -107,19 +107,19 @@ namespace {
     /// getI8Imm - Return a target constant with the specified value, of type
     /// i8.
     inline SDValue getI8Imm(uint64_t Imm) {
-      return CurDAG->getTargetConstant(Imm, EVT::i8);
+      return CurDAG->getTargetConstant(Imm, MVT::i8);
     }
 
     /// getI16Imm - Return a target constant with the specified value, of type
     /// i16.
     inline SDValue getI16Imm(uint64_t Imm) {
-      return CurDAG->getTargetConstant(Imm, EVT::i16);
+      return CurDAG->getTargetConstant(Imm, MVT::i16);
     }
 
     /// getI32Imm - Return a target constant with the specified value, of type
     /// i32.
     inline SDValue getI32Imm(uint64_t Imm) {
-      return CurDAG->getTargetConstant(Imm, EVT::i32);
+      return CurDAG->getTargetConstant(Imm, MVT::i32);
     }
 
     // Include the pieces autogenerated from the target description.
@@ -353,7 +353,7 @@ void SystemZDAGToDAGISel::getAddressOperandsRI(const SystemZRRIAddressMode &AM,
     Base = AM.Base.Reg;
   else
     Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
-  Disp = CurDAG->getTargetConstant(AM.Disp, EVT::i64);
+  Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
 }
 
 void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
@@ -650,16 +650,16 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
 
     EVT ResVT;
     bool is32Bit = false;
-    switch (NVT.getSimpleVT()) {
+    switch (NVT.getSimpleVT().SimpleTy) {
       default: assert(0 && "Unsupported VT!");
-      case EVT::i32:
+      case MVT::i32:
         Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
-        ResVT = EVT::v2i64;
+        ResVT = MVT::v2i64;
         is32Bit = true;
         break;
-      case EVT::i64:
+      case MVT::i64:
         Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
-        ResVT = EVT::v2i64;
+        ResVT = MVT::v2i64;
         break;
     }
 
@@ -669,7 +669,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
     // Prepare the dividend
     SDNode *Dividend;
     if (is32Bit)
-      Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, EVT::i64, N0);
+      Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
     else
       Dividend = N0.getNode();
 
@@ -679,7 +679,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
     Dividend =
       CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
                             SDValue(Tmp, 0), SDValue(Dividend, 0),
-                            CurDAG->getTargetConstant(subreg_odd, EVT::i32));
+                            CurDAG->getTargetConstant(subreg_odd, MVT::i32));
 
     SDNode *Result;
     SDValue DivVal = SDValue(Dividend, 0);
@@ -699,7 +699,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
                                           dl, NVT,
                                           SDValue(Result, 0),
                                           CurDAG->getTargetConstant(SubRegIdx,
-                                                                    EVT::i32));
+                                                                    MVT::i32));
 
       ReplaceUses(Op.getValue(0), SDValue(Div, 0));
       #ifndef NDEBUG
@@ -716,7 +716,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
                                           dl, NVT,
                                           SDValue(Result, 0),
                                           CurDAG->getTargetConstant(SubRegIdx,
-                                                                    EVT::i32));
+                                                                    MVT::i32));
 
       ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
       #ifndef NDEBUG
@@ -739,18 +739,18 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
     EVT ResVT;
 
     bool is32Bit = false;
-    switch (NVT.getSimpleVT()) {
+    switch (NVT.getSimpleVT().SimpleTy) {
       default: assert(0 && "Unsupported VT!");
-      case EVT::i32:
+      case MVT::i32:
         Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
         ClrOpc = SystemZ::MOV64Pr0_even;
-        ResVT = EVT::v2i32;
+        ResVT = MVT::v2i32;
         is32Bit = true;
         break;
-      case EVT::i64:
+      case MVT::i64:
         Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
         ClrOpc = SystemZ::MOV128r0_even;
-        ResVT = EVT::v2i64;
+        ResVT = MVT::v2i64;
         break;
     }
 
@@ -768,7 +768,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
       Dividend =
         CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
                               SDValue(Tmp, 0), SDValue(Dividend, 0),
-                              CurDAG->getTargetConstant(SubRegIdx, EVT::i32));
+                              CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
     }
 
     // Zero out even subreg
@@ -793,7 +793,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
                                           dl, NVT,
                                           SDValue(Result, 0),
                                           CurDAG->getTargetConstant(SubRegIdx,
-                                                                    EVT::i32));
+                                                                    MVT::i32));
       ReplaceUses(Op.getValue(0), SDValue(Div, 0));
       #ifndef NDEBUG
       DOUT << std::string(Indent-2, ' ') << "=> ";
@@ -809,7 +809,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
                                           dl, NVT,
                                           SDValue(Result, 0),
                                           CurDAG->getTargetConstant(SubRegIdx,
-                                                                    EVT::i32));
+                                                                    MVT::i32));
       ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
       #ifndef NDEBUG
       DOUT << std::string(Indent-2, ' ') << "=> ";
diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp
index 6ffb434..279e22b 100644
--- a/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -44,14 +44,14 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
   RegInfo = TM.getRegisterInfo();
 
   // Set up the register classes.
-  addRegisterClass(EVT::i32,  SystemZ::GR32RegisterClass);
-  addRegisterClass(EVT::i64,  SystemZ::GR64RegisterClass);
-  addRegisterClass(EVT::v2i32,SystemZ::GR64PRegisterClass);
-  addRegisterClass(EVT::v2i64,SystemZ::GR128RegisterClass);
+  addRegisterClass(MVT::i32,  SystemZ::GR32RegisterClass);
+  addRegisterClass(MVT::i64,  SystemZ::GR64RegisterClass);
+  addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
+  addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
 
   if (!UseSoftFloat) {
-    addRegisterClass(EVT::f32, SystemZ::FP32RegisterClass);
-    addRegisterClass(EVT::f64, SystemZ::FP64RegisterClass);
+    addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
+    addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
 
     addLegalFPImmediate(APFloat(+0.0));  // lzer
     addLegalFPImmediate(APFloat(+0.0f)); // lzdr
@@ -63,92 +63,92 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
   computeRegisterProperties();
 
   // Set shifts properties
-  setShiftAmountType(EVT::i64);
+  setShiftAmountType(MVT::i64);
 
   // Provide all sorts of operation actions
-  setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
-  setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
-  setLoadExtAction(ISD::EXTLOAD,  EVT::i1, Promote);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+  setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
 
-  setLoadExtAction(ISD::SEXTLOAD, EVT::f32, Expand);
-  setLoadExtAction(ISD::ZEXTLOAD, EVT::f32, Expand);
-  setLoadExtAction(ISD::EXTLOAD,  EVT::f32, Expand);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
+  setLoadExtAction(ISD::EXTLOAD,  MVT::f32, Expand);
 
-  setLoadExtAction(ISD::SEXTLOAD, EVT::f64, Expand);
-  setLoadExtAction(ISD::ZEXTLOAD, EVT::f64, Expand);
-  setLoadExtAction(ISD::EXTLOAD,  EVT::f64, Expand);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
+  setLoadExtAction(ISD::EXTLOAD,  MVT::f64, Expand);
 
   setStackPointerRegisterToSaveRestore(SystemZ::R15D);
   setSchedulingPreference(SchedulingForLatency);
   setBooleanContents(ZeroOrOneBooleanContent);
 
-  setOperationAction(ISD::BR_JT,            EVT::Other, Expand);
-  setOperationAction(ISD::BRCOND,           EVT::Other, Expand);
-  setOperationAction(ISD::BR_CC,            EVT::i32, Custom);
-  setOperationAction(ISD::BR_CC,            EVT::i64, Custom);
-  setOperationAction(ISD::BR_CC,            EVT::f32, Custom);
-  setOperationAction(ISD::BR_CC,            EVT::f64, Custom);
-  setOperationAction(ISD::ConstantPool,     EVT::i32, Custom);
-  setOperationAction(ISD::ConstantPool,     EVT::i64, Custom);
-  setOperationAction(ISD::GlobalAddress,    EVT::i64, Custom);
-  setOperationAction(ISD::JumpTable,        EVT::i64, Custom);
-  setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64, Expand);
-
-  setOperationAction(ISD::SDIV,             EVT::i32, Expand);
-  setOperationAction(ISD::UDIV,             EVT::i32, Expand);
-  setOperationAction(ISD::SDIV,             EVT::i64, Expand);
-  setOperationAction(ISD::UDIV,             EVT::i64, Expand);
-  setOperationAction(ISD::SREM,             EVT::i32, Expand);
-  setOperationAction(ISD::UREM,             EVT::i32, Expand);
-  setOperationAction(ISD::SREM,             EVT::i64, Expand);
-  setOperationAction(ISD::UREM,             EVT::i64, Expand);
-
-  setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
-
-  setOperationAction(ISD::CTPOP,            EVT::i32, Expand);
-  setOperationAction(ISD::CTPOP,            EVT::i64, Expand);
-  setOperationAction(ISD::CTTZ,             EVT::i32, Expand);
-  setOperationAction(ISD::CTTZ,             EVT::i64, Expand);
-  setOperationAction(ISD::CTLZ,             EVT::i32, Promote);
-  setOperationAction(ISD::CTLZ,             EVT::i64, Legal);
+  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
+  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
+  setOperationAction(ISD::BR_CC,            MVT::i32, Custom);
+  setOperationAction(ISD::BR_CC,            MVT::i64, Custom);
+  setOperationAction(ISD::BR_CC,            MVT::f32, Custom);
+  setOperationAction(ISD::BR_CC,            MVT::f64, Custom);
+  setOperationAction(ISD::ConstantPool,     MVT::i32, Custom);
+  setOperationAction(ISD::ConstantPool,     MVT::i64, Custom);
+  setOperationAction(ISD::GlobalAddress,    MVT::i64, Custom);
+  setOperationAction(ISD::JumpTable,        MVT::i64, Custom);
+  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
+
+  setOperationAction(ISD::SDIV,             MVT::i32, Expand);
+  setOperationAction(ISD::UDIV,             MVT::i32, Expand);
+  setOperationAction(ISD::SDIV,             MVT::i64, Expand);
+  setOperationAction(ISD::UDIV,             MVT::i64, Expand);
+  setOperationAction(ISD::SREM,             MVT::i32, Expand);
+  setOperationAction(ISD::UREM,             MVT::i32, Expand);
+  setOperationAction(ISD::SREM,             MVT::i64, Expand);
+  setOperationAction(ISD::UREM,             MVT::i64, Expand);
+
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+
+  setOperationAction(ISD::CTPOP,            MVT::i32, Expand);
+  setOperationAction(ISD::CTPOP,            MVT::i64, Expand);
+  setOperationAction(ISD::CTTZ,             MVT::i32, Expand);
+  setOperationAction(ISD::CTTZ,             MVT::i64, Expand);
+  setOperationAction(ISD::CTLZ,             MVT::i32, Promote);
+  setOperationAction(ISD::CTLZ,             MVT::i64, Legal);
 
   // FIXME: Can we lower these 2 efficiently?
-  setOperationAction(ISD::SETCC,            EVT::i32, Expand);
-  setOperationAction(ISD::SETCC,            EVT::i64, Expand);
-  setOperationAction(ISD::SETCC,            EVT::f32, Expand);
-  setOperationAction(ISD::SETCC,            EVT::f64, Expand);
-  setOperationAction(ISD::SELECT,           EVT::i32, Expand);
-  setOperationAction(ISD::SELECT,           EVT::i64, Expand);
-  setOperationAction(ISD::SELECT,           EVT::f32, Expand);
-  setOperationAction(ISD::SELECT,           EVT::f64, Expand);
-  setOperationAction(ISD::SELECT_CC,        EVT::i32, Custom);
-  setOperationAction(ISD::SELECT_CC,        EVT::i64, Custom);
-  setOperationAction(ISD::SELECT_CC,        EVT::f32, Custom);
-  setOperationAction(ISD::SELECT_CC,        EVT::f64, Custom);
+  setOperationAction(ISD::SETCC,            MVT::i32, Expand);
+  setOperationAction(ISD::SETCC,            MVT::i64, Expand);
+  setOperationAction(ISD::SETCC,            MVT::f32, Expand);
+  setOperationAction(ISD::SETCC,            MVT::f64, Expand);
+  setOperationAction(ISD::SELECT,           MVT::i32, Expand);
+  setOperationAction(ISD::SELECT,           MVT::i64, Expand);
+  setOperationAction(ISD::SELECT,           MVT::f32, Expand);
+  setOperationAction(ISD::SELECT,           MVT::f64, Expand);
+  setOperationAction(ISD::SELECT_CC,        MVT::i32, Custom);
+  setOperationAction(ISD::SELECT_CC,        MVT::i64, Custom);
+  setOperationAction(ISD::SELECT_CC,        MVT::f32, Custom);
+  setOperationAction(ISD::SELECT_CC,        MVT::f64, Custom);
 
   // Funny enough: we don't have 64-bit signed versions of these stuff, but have
   // unsigned.
-  setOperationAction(ISD::MULHS,            EVT::i64, Expand);
-  setOperationAction(ISD::SMUL_LOHI,        EVT::i64, Expand);
+  setOperationAction(ISD::MULHS,            MVT::i64, Expand);
+  setOperationAction(ISD::SMUL_LOHI,        MVT::i64, Expand);
 
   // Lower some FP stuff
-  setOperationAction(ISD::FSIN,             EVT::f32, Expand);
-  setOperationAction(ISD::FSIN,             EVT::f64, Expand);
-  setOperationAction(ISD::FCOS,             EVT::f32, Expand);
-  setOperationAction(ISD::FCOS,             EVT::f64, Expand);
-  setOperationAction(ISD::FREM,             EVT::f32, Expand);
-  setOperationAction(ISD::FREM,             EVT::f64, Expand);
+  setOperationAction(ISD::FSIN,             MVT::f32, Expand);
+  setOperationAction(ISD::FSIN,             MVT::f64, Expand);
+  setOperationAction(ISD::FCOS,             MVT::f32, Expand);
+  setOperationAction(ISD::FCOS,             MVT::f64, Expand);
+  setOperationAction(ISD::FREM,             MVT::f32, Expand);
+  setOperationAction(ISD::FREM,             MVT::f64, Expand);
 
   // We have only 64-bit bitconverts
-  setOperationAction(ISD::BIT_CONVERT,      EVT::f32, Expand);
-  setOperationAction(ISD::BIT_CONVERT,      EVT::i32, Expand);
+  setOperationAction(ISD::BIT_CONVERT,      MVT::f32, Expand);
+  setOperationAction(ISD::BIT_CONVERT,      MVT::i32, Expand);
 
-  setOperationAction(ISD::UINT_TO_FP,       EVT::i32, Expand);
-  setOperationAction(ISD::UINT_TO_FP,       EVT::i64, Expand);
-  setOperationAction(ISD::FP_TO_UINT,       EVT::i32, Expand);
-  setOperationAction(ISD::FP_TO_UINT,       EVT::i64, Expand);
+  setOperationAction(ISD::UINT_TO_FP,       MVT::i32, Expand);
+  setOperationAction(ISD::UINT_TO_FP,       MVT::i64, Expand);
+  setOperationAction(ISD::FP_TO_UINT,       MVT::i32, Expand);
+  setOperationAction(ISD::FP_TO_UINT,       MVT::i64, Expand);
 
-  setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
 }
 
 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
@@ -242,21 +242,21 @@ SystemZTargetLowering::LowerCCCArguments(SDValue Chain,
     if (VA.isRegLoc()) {
       // Arguments passed in registers
       TargetRegisterClass *RC;
-      switch (LocVT.getSimpleVT()) {
+      switch (LocVT.getSimpleVT().SimpleTy) {
       default:
 #ifndef NDEBUG
         cerr << "LowerFormalArguments Unhandled argument type: "
-             << LocVT.getSimpleVT()
+             << LocVT.getSimpleVT().SimpleTy
              << "\n";
 #endif
         llvm_unreachable(0);
-      case EVT::i64:
+      case MVT::i64:
         RC = SystemZ::GR64RegisterClass;
         break;
-      case EVT::f32:
+      case MVT::f32:
         RC = SystemZ::FP32RegisterClass;
         break;
-      case EVT::f64:
+      case MVT::f64:
         RC = SystemZ::FP64RegisterClass;
         break;
       }
@@ -382,7 +382,7 @@ SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
   // Transform all store nodes into one single node because all store nodes are
   // independent of each other.
   if (!MemOpChains.empty())
-    Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
                         &MemOpChains[0], MemOpChains.size());
 
   // Build a sequence of copy-to-reg nodes chained together with token chain and
@@ -404,7 +404,7 @@ SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
 
   // Returns a chain & a flag for retval copy to use.
-  SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
+  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
   SmallVector<SDValue, 8> Ops;
   Ops.push_back(Chain);
   Ops.push_back(Callee);
@@ -530,10 +530,10 @@ SystemZTargetLowering::LowerReturn(SDValue Chain,
   }
 
   if (Flag.getNode())
-    return DAG.getNode(SystemZISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
+    return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
 
   // Return Void
-  return DAG.getNode(SystemZISD::RET_FLAG, dl, EVT::Other, Chain);
+  return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
 }
 
 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
@@ -608,11 +608,11 @@ SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
     break;
   }
 
-  SystemZCC = DAG.getConstant(TCC, EVT::i32);
+  SystemZCC = DAG.getConstant(TCC, MVT::i32);
 
   DebugLoc dl = LHS.getDebugLoc();
   return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
-                     dl, EVT::Flag, LHS, RHS);
+                     dl, MVT::Flag, LHS, RHS);
 }
 
 
@@ -641,7 +641,7 @@ SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
   SDValue SystemZCC;
   SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
 
-  SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::Flag);
+  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
   SmallVector<SDValue, 4> Ops;
   Ops.push_back(TrueV);
   Ops.push_back(FalseV);
diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td
index 0ee48c3..156cace 100644
--- a/lib/Target/SystemZ/SystemZOperands.td
+++ b/lib/Target/SystemZ/SystemZOperands.td
@@ -134,10 +134,10 @@ def i64hh16c : PatLeaf<(i64 imm), [{
 def immSExt16 : PatLeaf<(imm), [{
   // immSExt16 predicate - true if the immediate fits in a 16-bit sign extended
   // field.
-  if (N->getValueType(0) == EVT::i64) {
+  if (N->getValueType(0) == MVT::i64) {
     uint64_t val = N->getZExtValue();
     return ((int64_t)val == (int16_t)val);
-  } else if (N->getValueType(0) == EVT::i32) {
+  } else if (N->getValueType(0) == MVT::i32) {
     uint32_t val = N->getZExtValue();
     return ((int32_t)val == (int16_t)val);
   }