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author | Renato Golin <rengolin@systemcall.org> | 2012-12-20 13:52:11 +0000 |
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committer | Renato Golin <rengolin@systemcall.org> | 2012-12-20 13:52:11 +0000 |
commit | 332bd799512142e23d35105483520acbffff72c8 (patch) | |
tree | 3742278b357b08cc5c1935dec9be24a9af5b918f /lib/Target | |
parent | da5cd6a180f8174685aaa3fc0b92e171ec032f4c (diff) | |
download | external_llvm-332bd799512142e23d35105483520acbffff72c8.zip external_llvm-332bd799512142e23d35105483520acbffff72c8.tar.gz external_llvm-332bd799512142e23d35105483520acbffff72c8.tar.bz2 |
Adding support for llvm.arm.neon.vaddl[su].* and
llvm.arm.neon.vsub[su].* intrinsics.
Patch by Pete Couperus <pjcoup@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170694 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 18 | ||||
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.h | 8 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 44 |
3 files changed, 66 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 8034ce1..1105f41 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -1007,6 +1007,10 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { case ARMISD::VTBL2: return "ARMISD::VTBL2"; case ARMISD::VMULLs: return "ARMISD::VMULLs"; case ARMISD::VMULLu: return "ARMISD::VMULLu"; + case ARMISD::VADDLs: return "ARMISD::VADDLs"; + case ARMISD::VADDLu: return "ARMISD::VADDLu"; + case ARMISD::VSUBLs: return "ARMISD::VSUBLs"; + case ARMISD::VSUBLu: return "ARMISD::VSUBLu"; case ARMISD::UMLAL: return "ARMISD::UMLAL"; case ARMISD::SMLAL: return "ARMISD::SMLAL"; case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; @@ -2429,6 +2433,20 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), Op.getOperand(1), Op.getOperand(2)); } + case Intrinsic::arm_neon_vaddls: + case Intrinsic::arm_neon_vaddlu: { + unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vaddls) + ? ARMISD::VADDLs : ARMISD::VADDLu; + return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), + Op.getOperand(1), Op.getOperand(2)); + } + case Intrinsic::arm_neon_vsubls: + case Intrinsic::arm_neon_vsublu: { + unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vsubls) + ? ARMISD::VSUBLs: ARMISD::VSUBLu; + return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), + Op.getOperand(1), Op.getOperand(2)); + } } } diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index 61649a0..9cf835a 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -174,6 +174,14 @@ namespace llvm { VMULLs, // ...signed VMULLu, // ...unsigned + // Vector add long: + VADDLs, // ...signed + VADDLu, // ...unsigned + + // Vector subtract long: + VSUBLs, // ...signed + VSUBLu, // ...unsigned + UMLAL, // 64bit Unsigned Accumulate Multiply SMLAL, // 64bit Signed Accumulate Multiply diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 697a8d2..c853a45 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -534,10 +534,16 @@ def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>; def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>; def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>; -def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, - SDTCisSameAs<1, 2>]>; -def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>; -def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>; +def SDTARMVLONG2: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, + SDTCisSameAs<1, 2>]>; +def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVLONG2>; +def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVLONG2>; + +def NEONvaddls : SDNode<"ARMISD::VADDLs", SDTARMVLONG2>; +def NEONvaddlu : SDNode<"ARMISD::VADDLu", SDTARMVLONG2>; + +def NEONvsubls : SDNode<"ARMISD::VSUBLs", SDTARMVLONG2>; +def NEONvsublu : SDNode<"ARMISD::VSUBLu", SDTARMVLONG2>; def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>]>; @@ -3940,6 +3946,21 @@ defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, "vaddl", "s", add, sext, 1>; defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, "vaddl", "u", add, zext, 1>; + +def : Pat<(v4i32 (NEONvaddlu (v4i16 DPR:$src1), (v4i16 DPR:$src2))), + (v4i32 (VADDLuv4i32 DPR:$src1, DPR:$src2))>; +def : Pat<(v8i16 (NEONvaddlu (v8i8 DPR:$src1), (v8i8 DPR:$src2))), + (v8i16 (VADDLuv8i16 DPR:$src1, DPR:$src2))>; +def : Pat<(v2i64 (NEONvaddlu (v2i32 DPR:$src1), (v2i32 DPR:$src2))), + (v2i64 (VADDLuv2i64 DPR:$src1, DPR:$src2))>; + +def : Pat<(v4i32 (NEONvaddls (v4i16 DPR:$src1), (v4i16 DPR:$src2))), + (v4i32 (VADDLsv4i32 DPR:$src1, DPR:$src2))>; +def : Pat<(v8i16 (NEONvaddls (v8i8 DPR:$src1), (v8i8 DPR:$src2))), + (v8i16 (VADDLsv8i16 DPR:$src1, DPR:$src2))>; +def : Pat<(v2i64 (NEONvaddls (v2i32 DPR:$src1), (v2i32 DPR:$src2))), + (v2i64 (VADDLsv2i64 DPR:$src1, DPR:$src2))>; + // VADDW : Vector Add Wide (Q = Q + D) defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>; defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>; @@ -4230,6 +4251,21 @@ defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, "vsubl", "s", sub, sext, 0>; defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, "vsubl", "u", sub, zext, 0>; + +def : Pat<(v4i32 (NEONvsublu (v4i16 DPR:$src1), (v4i16 DPR:$src2))), + (v4i32 (VSUBLuv4i32 DPR:$src1, DPR:$src2))>; +def : Pat<(v8i16 (NEONvsublu (v8i8 DPR:$src1), (v8i8 DPR:$src2))), + (v8i16 (VSUBLuv8i16 DPR:$src1, DPR:$src2))>; +def : Pat<(v2i64 (NEONvsublu (v2i32 DPR:$src1), (v2i32 DPR:$src2))), + (v2i64 (VSUBLuv2i64 DPR:$src1, DPR:$src2))>; + +def : Pat<(v4i32 (NEONvsubls (v4i16 DPR:$src1), (v4i16 DPR:$src2))), + (v4i32 (VSUBLsv4i32 DPR:$src1, DPR:$src2))>; +def : Pat<(v8i16 (NEONvsubls (v8i8 DPR:$src1), (v8i8 DPR:$src2))), + (v8i16 (VSUBLsv8i16 DPR:$src1, DPR:$src2))>; +def : Pat<(v2i64 (NEONvsubls (v2i32 DPR:$src1), (v2i32 DPR:$src2))), + (v2i64 (VSUBLsv2i64 DPR:$src1, DPR:$src2))>; + // VSUBW : Vector Subtract Wide (Q = Q - D) defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>; defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>; |