Fixed spelling and grammar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8489 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 26 insertions, 26 deletions

diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp
index f5334d5..6d1fd14 100644
--- a/lib/Target/CBackend/CBackend.cpp
+++ b/lib/Target/CBackend/CBackend.cpp
@@ -886,7 +886,7 @@ void CWriter::printFunction(Function *F) {
     BasicBlock *Prev = BB->getPrev();
 
     // Don't print the label for the basic block if there are no uses, or if the
-    // only terminator use is the precessor basic block's terminator.  We have
+    // only terminator use is the predecessor basic block's terminator.  We have
     // to scan the use list because PHI nodes use basic blocks too but do not
     // require a label to be generated.
     //
@@ -1022,8 +1022,8 @@ void CWriter::printBranchToBlock(BasicBlock *CurBB, BasicBlock *Succ,
   }
 }
 
-// Brach instruction printing - Avoid printing out a brach to a basic block that
-// immediately succeeds the current one.
+// Branch instruction printing - Avoid printing out a branch to a basic block
+// that immediately succeeds the current one.
 //
 void CWriter::visitBranchInst(BranchInst &I) {
   if (I.isConditional()) {
@@ -1155,7 +1155,7 @@ void CWriter::visitCallInst(CallInst &I) {
 
       case LLVMIntrinsic::setjmp:
       case LLVMIntrinsic::sigsetjmp:
-        // This instrinsic should never exist in the program, but until we get
+        // This intrinsic should never exist in the program, but until we get
         // setjmp/longjmp transformations going on, we should codegen it to
         // something reasonable.  This will allow code that never calls longjmp
         // to work.
diff --git a/lib/Target/CBackend/Writer.cpp b/lib/Target/CBackend/Writer.cpp
index f5334d5..6d1fd14 100644
--- a/lib/Target/CBackend/Writer.cpp
+++ b/lib/Target/CBackend/Writer.cpp
@@ -886,7 +886,7 @@ void CWriter::printFunction(Function *F) {
     BasicBlock *Prev = BB->getPrev();
 
     // Don't print the label for the basic block if there are no uses, or if the
-    // only terminator use is the precessor basic block's terminator.  We have
+    // only terminator use is the predecessor basic block's terminator.  We have
     // to scan the use list because PHI nodes use basic blocks too but do not
     // require a label to be generated.
     //
@@ -1022,8 +1022,8 @@ void CWriter::printBranchToBlock(BasicBlock *CurBB, BasicBlock *Succ,
   }
 }
 
-// Brach instruction printing - Avoid printing out a brach to a basic block that
-// immediately succeeds the current one.
+// Branch instruction printing - Avoid printing out a branch to a basic block
+// that immediately succeeds the current one.
 //
 void CWriter::visitBranchInst(BranchInst &I) {
   if (I.isConditional()) {
@@ -1155,7 +1155,7 @@ void CWriter::visitCallInst(CallInst &I) {
 
       case LLVMIntrinsic::setjmp:
       case LLVMIntrinsic::sigsetjmp:
-        // This instrinsic should never exist in the program, but until we get
+        // This intrinsic should never exist in the program, but until we get
         // setjmp/longjmp transformations going on, we should codegen it to
         // something reasonable.  This will allow code that never calls longjmp
         // to work.
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 1e44e17..a04d4b8 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -104,7 +104,7 @@ PhyRegAlloc::~PhyRegAlloc() {
 } 
 
 //----------------------------------------------------------------------------
-// This method initally creates interference graphs (one in each reg class)
+// This method initially creates interference graphs (one in each reg class)
 // and IGNodeList (one in each IG). The actual nodes will be pushed later. 
 //----------------------------------------------------------------------------
 void PhyRegAlloc::createIGNodeListsAndIGs() {
@@ -145,7 +145,7 @@ void PhyRegAlloc::createIGNodeListsAndIGs() {
 
 //----------------------------------------------------------------------------
 // This method will add all interferences at for a given instruction.
-// Interence occurs only if the LR of Def (Inst or Arg) is of the same reg 
+// Interference occurs only if the LR of Def (Inst or Arg) is of the same reg 
 // class as that of live var. The live var passed to this function is the 
 // LVset AFTER the instruction
 //----------------------------------------------------------------------------
@@ -290,9 +290,9 @@ void PhyRegAlloc::buildInterferenceGraphs()
       bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
 
       if (isCallInst ) {
-	// set the isCallInterference flag of each live range wich extends
-	// accross this call instruction. This information is used by graph
-	// coloring algo to avoid allocating volatile colors to live ranges
+	// set the isCallInterference flag of each live range which extends
+	// across this call instruction. This information is used by graph
+	// coloring algorithm to avoid allocating volatile colors to live ranges
 	// that span across calls (since they have to be saved/restored)
 	//
 	setCallInterferences(MInst, &LVSetAI);
@@ -331,7 +331,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
   } // for all BBs in function
 
 
-  // add interferences for function arguments. Since there are no explict 
+  // add interferences for function arguments. Since there are no explicit 
   // defs in the function for args, we have to add them manually
   //  
   addInterferencesForArgs();          
@@ -343,7 +343,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
 
 
 //--------------------------------------------------------------------------
-// Pseudo instructions will be exapnded to multiple instructions by the
+// Pseudo-instructions will be expanded to multiple instructions by the
 // assembler. Consequently, all the opernds must get distinct registers.
 // Therefore, we mark all operands of a pseudo instruction as they interfere
 // with one another.
@@ -404,7 +404,7 @@ void PhyRegAlloc::addInterferencesForArgs() {
 
 //----------------------------------------------------------------------------
 // This method is called after register allocation is complete to set the
-// allocated reisters in the machine code. This code will add register numbers
+// allocated registers in the machine code. This code will add register numbers
 // to MachineOperands that contain a Value. Also it calls target specific
 // methods to produce caller saving instructions. At the end, it adds all
 // additional instructions produced by the register allocator to the 
@@ -722,7 +722,7 @@ void PhyRegAlloc::updateMachineCode()
 // if it contains many spilled operands. Each time it is called, it finds
 // a register which is not live at that instruction and also which is not
 // used by other spilled operands of the same instruction. Then it uses
-// this register temporarily to accomodate the spilled value.
+// this register temporarily to accommodate the spilled value.
 //----------------------------------------------------------------------------
 
 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR, 
@@ -835,7 +835,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
 
 
 //----------------------------------------------------------------------------
-// This method inserts caller saving/restoring instructons before/after
+// This method inserts caller saving/restoring instructions before/after
 // a call machine instruction. The caller saving/restoring instructions are
 // inserted like:
 //    ** caller saving instructions
@@ -1077,7 +1077,7 @@ int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
 
 //----------------------------------------------------------------------------
 // This method is called to get a new unused register that can be used
-// to accomodate a temporary value.  This method may be called several times
+// to accommodate a temporary value.  This method may be called several times
 // for a single machine instruction.  Each time it is called, it finds a
 // register which is not live at that instruction and also which is not used
 // by other spilled operands of the same instruction.  Return register number
@@ -1370,7 +1370,7 @@ void PhyRegAlloc::markUnusableSugColors()
 
 //----------------------------------------------------------------------------
 // The following method will set the stack offsets of the live ranges that
-// are decided to be spillled. This must be called just after coloring the
+// are decided to be spilled. This must be called just after coloring the
 // LRs using the graph coloring algo. For each live range that is spilled,
 // this method allocate a new spill position on the stack.
 //----------------------------------------------------------------------------
@@ -1450,8 +1450,8 @@ void PhyRegAlloc::allocateRegisters()
   for (unsigned rc=0; rc < NumOfRegClasses ; rc++)  
     RegClassList[rc]->colorAllRegs();    
 
-  // Atter graph coloring, if some LRs did not receive a color (i.e, spilled)
-  // a poistion for such spilled LRs
+  // After graph coloring, if some LRs did not receive a color (i.e, spilled)
+  // a position for such spilled LRs
   //
   allocateStackSpace4SpilledLRs();
 
diff --git a/lib/Target/SparcV9/RegAlloc/RegClass.cpp b/lib/Target/SparcV9/RegAlloc/RegClass.cpp
index d4bd714..12582cc 100644
--- a/lib/Target/SparcV9/RegAlloc/RegClass.cpp
+++ b/lib/Target/SparcV9/RegAlloc/RegClass.cpp
@@ -93,7 +93,7 @@ void RegClass::pushAllIGNodes()
     //
     IGNodeSpill->pushOnStack(); 
    
-    // now push NON-constrined ones, if any
+    // now push NON-constrained ones, if any
     //
     NeedMoreSpills = !pushUnconstrainedIGNodes(); 
 
@@ -154,7 +154,7 @@ bool  RegClass::pushUnconstrainedIGNodes()
 
 
 //----------------------------------------------------------------------------
-// Get the IGNode withe the minimum spill cost
+// Get the IGNode with the minimum spill cost
 //----------------------------------------------------------------------------
 IGNode * RegClass::getIGNodeWithMinSpillCost()
 {
@@ -216,8 +216,8 @@ void RegClass::colorIGNode(IGNode *const Node)
       IGNode *NeighIGNode = Node->getAdjIGNode(n);
       LiveRange *NeighLR = NeighIGNode->getParentLR();
       
-      // Don't use a color if it is in use by the neighbour,
-      // or is suggested for use by the neighbour,
+      // Don't use a color if it is in use by the neighbor,
+      // or is suggested for use by the neighbor,
       // markColorsUsed() should be given the color and the reg type for
       // LR, not for NeighLR, because it should mark registers used based on
       // the type we are looking for, not on the regType for the neighbour.