Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8

14 files changed, 10 insertions, 1582 deletions

diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td
index 19e25d4..aca868f 100644
--- a/lib/Target/ARM/ARM.td
+++ b/lib/Target/ARM/ARM.td
@@ -14,7 +14,7 @@
 // Target-independent interfaces which we are implementing
 //===----------------------------------------------------------------------===//
 
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // ARM Subtarget features.
diff --git a/lib/Target/Alpha/Alpha.td b/lib/Target/Alpha/Alpha.td
index 65a760b..e3748c6 100644
--- a/lib/Target/Alpha/Alpha.td
+++ b/lib/Target/Alpha/Alpha.td
@@ -12,7 +12,7 @@
 
 // Get the target-independent interfaces which we are implementing...
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //Alpha is little endian
 
diff --git a/lib/Target/CellSPU/SPU.td b/lib/Target/CellSPU/SPU.td
index 15809f2..a5db1d9 100644
--- a/lib/Target/CellSPU/SPU.td
+++ b/lib/Target/CellSPU/SPU.td
@@ -13,7 +13,7 @@
 
 // Get the target-independent interfaces which we are implementing.
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // Register File Description
diff --git a/lib/Target/IA64/IA64.td b/lib/Target/IA64/IA64.td
index 0cef72e..c469281 100644
--- a/lib/Target/IA64/IA64.td
+++ b/lib/Target/IA64/IA64.td
@@ -14,7 +14,7 @@
 
 // Get the target-independent interfaces which we are implementing...
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // Register File Description
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td
index 79c1890..79ae5d2 100644
--- a/lib/Target/Mips/Mips.td
+++ b/lib/Target/Mips/Mips.td
@@ -13,7 +13,7 @@
 // Target-independent interfaces
 //===----------------------------------------------------------------------===//
 
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // Register File, Calling Conv, Instruction Descriptions
diff --git a/lib/Target/PIC16/PIC16.td b/lib/Target/PIC16/PIC16.td
index d37075b..b2b9b1c 100644
--- a/lib/Target/PIC16/PIC16.td
+++ b/lib/Target/PIC16/PIC16.td
@@ -13,7 +13,7 @@
 // Target-independent interfaces
 //===----------------------------------------------------------------------===//
 
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 include "PIC16RegisterInfo.td"
 include "PIC16InstrInfo.td"
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
index cc0c8c8..08f5bb4 100644
--- a/lib/Target/PowerPC/PPC.td
+++ b/lib/Target/PowerPC/PPC.td
@@ -13,7 +13,7 @@
 
 // Get the target-independent interfaces which we are implementing.
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // PowerPC Subtarget features.
diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td
index b90fcde..53ea8f4 100644
--- a/lib/Target/Sparc/Sparc.td
+++ b/lib/Target/Sparc/Sparc.td
@@ -14,7 +14,7 @@
 // Target-independent interfaces which we are implementing
 //===----------------------------------------------------------------------===//
 
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // SPARC Subtarget features.
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
deleted file mode 100644
index e07529d..0000000
--- a/lib/Target/Target.td
+++ /dev/null
@@ -1,499 +0,0 @@
-//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-// This file defines the target-independent interfaces which should be
-// implemented by each target which is using a TableGen based code generator.
-//
-//===----------------------------------------------------------------------===//
-
-// Include all information about LLVM intrinsics.
-include "llvm/Intrinsics.td"
-
-//===----------------------------------------------------------------------===//
-// Register file description - These classes are used to fill in the target
-// description classes.
-
-class RegisterClass; // Forward def
-
-// Register - You should define one instance of this class for each register
-// in the target machine.  String n will become the "name" of the register.
-class Register<string n> {
-  string Namespace = "";
-  string AsmName = n;
-
-  // SpillSize - If this value is set to a non-zero value, it is the size in
-  // bits of the spill slot required to hold this register.  If this value is
-  // set to zero, the information is inferred from any register classes the
-  // register belongs to.
-  int SpillSize = 0;
-
-  // SpillAlignment - This value is used to specify the alignment required for
-  // spilling the register.  Like SpillSize, this should only be explicitly
-  // specified if the register is not in a register class.
-  int SpillAlignment = 0;
-
-  // Aliases - A list of registers that this register overlaps with.  A read or
-  // modification of this register can potentially read or modify the aliased
-  // registers.
-  list<Register> Aliases = [];
-  
-  // SubRegs - A list of registers that are parts of this register. Note these
-  // are "immediate" sub-registers and the registers within the list do not
-  // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
-  // not [AX, AH, AL].
-  list<Register> SubRegs = [];
-
-  // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
-  // These values can be determined by locating the <target>.h file in the
-  // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES.  The
-  // order of these names correspond to the enumeration used by gcc.  A value of
-  // -1 indicates that the gcc number is undefined and -2 that register number
-  // is invalid for this mode/flavour.
-  list<int> DwarfNumbers = [];
-}
-
-// RegisterWithSubRegs - This can be used to define instances of Register which
-// need to specify sub-registers.
-// List "subregs" specifies which registers are sub-registers to this one. This
-// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
-// This allows the code generator to be careful not to put two values with 
-// overlapping live ranges into registers which alias.
-class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
-  let SubRegs = subregs;
-}
-
-// SubRegSet - This can be used to define a specific mapping of registers to
-// indices, for use as named subregs of a particular physical register.  Each
-// register in 'subregs' becomes an addressable subregister at index 'n' of the
-// corresponding register in 'regs'.
-class SubRegSet<int n, list<Register> regs, list<Register> subregs> {
-  int index = n;
-  
-  list<Register> From = regs;
-  list<Register> To = subregs;
-}
-
-// RegisterClass - Now that all of the registers are defined, and aliases
-// between registers are defined, specify which registers belong to which
-// register classes.  This also defines the default allocation order of
-// registers by register allocators.
-//
-class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
-                    list<Register> regList> {
-  string Namespace = namespace;
-
-  // RegType - Specify the list ValueType of the registers in this register
-  // class.  Note that all registers in a register class must have the same
-  // ValueTypes.  This is a list because some targets permit storing different 
-  // types in same register, for example vector values with 128-bit total size,
-  // but different count/size of items, like SSE on x86.
-  //
-  list<ValueType> RegTypes = regTypes;
-
-  // Size - Specify the spill size in bits of the registers.  A default value of
-  // zero lets tablgen pick an appropriate size.
-  int Size = 0;
-
-  // Alignment - Specify the alignment required of the registers when they are
-  // stored or loaded to memory.
-  //
-  int Alignment = alignment;
-
-  // CopyCost - This value is used to specify the cost of copying a value
-  // between two registers in this register class. The default value is one
-  // meaning it takes a single instruction to perform the copying. A negative
-  // value means copying is extremely expensive or impossible.
-  int CopyCost = 1;
-
-  // MemberList - Specify which registers are in this class.  If the
-  // allocation_order_* method are not specified, this also defines the order of
-  // allocation used by the register allocator.
-  //
-  list<Register> MemberList = regList;
-  
-  // SubClassList - Specify which register classes correspond to subregisters
-  // of this class. The order should be by subregister set index.
-  list<RegisterClass> SubRegClassList = [];
-
-  // MethodProtos/MethodBodies - These members can be used to insert arbitrary
-  // code into a generated register class.   The normal usage of this is to 
-  // overload virtual methods.
-  code MethodProtos = [{}];
-  code MethodBodies = [{}];
-}
-
-
-//===----------------------------------------------------------------------===//
-// DwarfRegNum - This class provides a mapping of the llvm register enumeration
-// to the register numbering used by gcc and gdb.  These values are used by a
-// debug information writer (ex. DwarfWriter) to describe where values may be
-// located during execution.
-class DwarfRegNum<list<int> Numbers> {
-  // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
-  // These values can be determined by locating the <target>.h file in the
-  // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES.  The
-  // order of these names correspond to the enumeration used by gcc.  A value of
-  // -1 indicates that the gcc number is undefined and -2 that register number is 
-  // invalid for this mode/flavour.
-  list<int> DwarfNumbers = Numbers;
-}
-
-//===----------------------------------------------------------------------===//
-// Pull in the common support for scheduling
-//
-include "TargetSchedule.td"
-
-class Predicate; // Forward def
-
-//===----------------------------------------------------------------------===//
-// Instruction set description - These classes correspond to the C++ classes in
-// the Target/TargetInstrInfo.h file.
-//
-class Instruction {
-  string Namespace = "";
-
-  dag OutOperandList;       // An dag containing the MI def operand list.
-  dag InOperandList;        // An dag containing the MI use operand list.
-  string AsmString = "";    // The .s format to print the instruction with.
-
-  // Pattern - Set to the DAG pattern for this instruction, if we know of one,
-  // otherwise, uninitialized.
-  list<dag> Pattern;
-
-  // The follow state will eventually be inferred automatically from the
-  // instruction pattern.
-
-  list<Register> Uses = []; // Default to using no non-operand registers
-  list<Register> Defs = []; // Default to modifying no non-operand registers
-
-  // Predicates - List of predicates which will be turned into isel matching
-  // code.
-  list<Predicate> Predicates = [];
-
-  // Code size.
-  int CodeSize = 0;
-
-  // Added complexity passed onto matching pattern.
-  int AddedComplexity  = 0;
-
-  // These bits capture information about the high-level semantics of the
-  // instruction.
-  bit isReturn     = 0;     // Is this instruction a return instruction?
-  bit isBranch     = 0;     // Is this instruction a branch instruction?
-  bit isIndirectBranch = 0; // Is this instruction an indirect branch?
-  bit isBarrier    = 0;     // Can control flow fall through this instruction?
-  bit isCall       = 0;     // Is this instruction a call instruction?
-  bit isSimpleLoad = 0;     // Is this just a load instruction?
-  bit mayLoad      = 0;     // Is it possible for this inst to read memory?
-  bit mayStore     = 0;     // Is it possible for this inst to write memory?
-  bit isTwoAddress = 0;     // Is this a two address instruction?
-  bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
-  bit isCommutable = 0;     // Is this 3 operand instruction commutable?
-  bit isTerminator = 0;     // Is this part of the terminator for a basic block?
-  bit isReMaterializable = 0; // Is this instruction re-materializable?
-  bit isPredicable = 0;     // Is this instruction predicable?
-  bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
-  bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
-  bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
-  bit isNotDuplicable = 0;  // Is it unsafe to duplicate this instruction?
-  bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
-
-  // Side effect flags - When set, the flags have these meanings:
-  //
-  //  hasSideEffects - The instruction has side effects that are not
-  //    captured by any operands of the instruction or other flags.
-  //
-  //  mayHaveSideEffects  - Some instances of the instruction can have side
-  //    effects. The virtual method "isReallySideEffectFree" is called to
-  //    determine this. Load instructions are an example of where this is
-  //    useful. In general, loads always have side effects. However, loads from
-  //    constant pools don't. Individual back ends make this determination.
-  //
-  //  neverHasSideEffects - Set on an instruction with no pattern if it has no
-  //    side effects.
-  bit hasSideEffects = 0;
-  bit mayHaveSideEffects = 0;
-  bit neverHasSideEffects = 0;
-
-  InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
-
-  string Constraints = "";  // OperandConstraint, e.g. $src = $dst.
-  
-  /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
-  /// be encoded into the output machineinstr.
-  string DisableEncoding = "";
-}
-
-/// Predicates - These are extra conditionals which are turned into instruction
-/// selector matching code. Currently each predicate is just a string.
-class Predicate<string cond> {
-  string CondString = cond;
-}
-
-/// NoHonorSignDependentRounding - This predicate is true if support for
-/// sign-dependent-rounding is not enabled.
-def NoHonorSignDependentRounding
- : Predicate<"!HonorSignDependentRoundingFPMath()">;
-
-class Requires<list<Predicate> preds> {
-  list<Predicate> Predicates = preds;
-}
-
-/// ops definition - This is just a simple marker used to identify the operands
-/// list for an instruction. outs and ins are identical both syntatically and
-/// semantically, they are used to define def operands and use operands to
-/// improve readibility. This should be used like this:
-///     (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
-def ops;
-def outs;
-def ins;
-
-/// variable_ops definition - Mark this instruction as taking a variable number
-/// of operands.
-def variable_ops;
-
-/// ptr_rc definition - Mark this operand as being a pointer value whose
-/// register class is resolved dynamically via a callback to TargetInstrInfo.
-/// FIXME: We should probably change this to a class which contain a list of
-/// flags. But currently we have but one flag.
-def ptr_rc;
-
-/// unknown definition - Mark this operand as being of unknown type, causing
-/// it to be resolved by inference in the context it is used.
-def unknown;
-
-/// Operand Types - These provide the built-in operand types that may be used
-/// by a target.  Targets can optionally provide their own operand types as
-/// needed, though this should not be needed for RISC targets.
-class Operand<ValueType ty> {
-  ValueType Type = ty;
-  string PrintMethod = "printOperand";
-  dag MIOperandInfo = (ops);
-}
-
-def i1imm  : Operand<i1>;
-def i8imm  : Operand<i8>;
-def i16imm : Operand<i16>;
-def i32imm : Operand<i32>;
-def i64imm : Operand<i64>;
-
-def f32imm : Operand<f32>;
-def f64imm : Operand<f64>;
-
-/// zero_reg definition - Special node to stand for the zero register.
-///
-def zero_reg;
-
-/// PredicateOperand - This can be used to define a predicate operand for an
-/// instruction.  OpTypes specifies the MIOperandInfo for the operand, and
-/// AlwaysVal specifies the value of this predicate when set to "always
-/// execute".
-class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
-  : Operand<ty> {
-  let MIOperandInfo = OpTypes;
-  dag DefaultOps = AlwaysVal;
-}
-
-/// OptionalDefOperand - This is used to define a optional definition operand
-/// for an instruction. DefaultOps is the register the operand represents if none
-/// is supplied, e.g. zero_reg.
-class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
-  : Operand<ty> {
-  let MIOperandInfo = OpTypes;
-  dag DefaultOps = defaultops;
-}
-
-
-// InstrInfo - This class should only be instantiated once to provide parameters
-// which are global to the the target machine.
-//
-class InstrInfo {
-  // If the target wants to associate some target-specific information with each
-  // instruction, it should provide these two lists to indicate how to assemble
-  // the target specific information into the 32 bits available.
-  //
-  list<string> TSFlagsFields = [];
-  list<int>    TSFlagsShifts = [];
-
-  // Target can specify its instructions in either big or little-endian formats.
-  // For instance, while both Sparc and PowerPC are big-endian platforms, the
-  // Sparc manual specifies its instructions in the format [31..0] (big), while
-  // PowerPC specifies them using the format [0..31] (little).
-  bit isLittleEndianEncoding = 0;
-}
-
-// Standard Instructions.
-def PHI : Instruction {
-  let OutOperandList = (ops);
-  let InOperandList = (ops variable_ops);
-  let AsmString = "PHINODE";
-  let Namespace = "TargetInstrInfo";
-}
-def INLINEASM : Instruction {
-  let OutOperandList = (ops);
-  let InOperandList = (ops variable_ops);
-  let AsmString = "";
-  let Namespace = "TargetInstrInfo";
-}
-def DBG_LABEL : Instruction {
-  let OutOperandList = (ops);
-  let InOperandList = (ops i32imm:$id);
-  let AsmString = "";
-  let Namespace = "TargetInstrInfo";
-  let hasCtrlDep = 1;
-}
-def EH_LABEL : Instruction {
-  let OutOperandList = (ops);
-  let InOperandList = (ops i32imm:$id);
-  let AsmString = "";
-  let Namespace = "TargetInstrInfo";
-  let hasCtrlDep = 1;
-}
-def GC_LABEL : Instruction {
-  let OutOperandList = (ops);
-  let InOperandList = (ops i32imm:$id);
-  let AsmString = "";
-  let Namespace = "TargetInstrInfo";
-  let hasCtrlDep = 1;
-}
-def DECLARE : Instruction {
-  let OutOperandList = (ops);
-  let InOperandList = (ops variable_ops);
-  let AsmString = "";
-  let Namespace = "TargetInstrInfo";
-  let hasCtrlDep = 1;
-}
-def EXTRACT_SUBREG : Instruction {
-  let OutOperandList = (ops unknown:$dst);
-  let InOperandList = (ops unknown:$supersrc, i32imm:$subidx);
-  let AsmString = "";
-  let Namespace = "TargetInstrInfo";
-  let neverHasSideEffects = 1;
-}
-def INSERT_SUBREG : Instruction {
-  let OutOperandList = (ops unknown:$dst);
-  let InOperandList = (ops unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
-  let AsmString = "";
-  let Namespace = "TargetInstrInfo";
-  let neverHasSideEffects = 1;
-  let Constraints = "$supersrc = $dst";
-}
-def IMPLICIT_DEF : Instruction {
-  let OutOperandList = (ops unknown:$dst);
-  let InOperandList = (ops);
-  let AsmString = "";
-  let Namespace = "TargetInstrInfo";
-  let neverHasSideEffects = 1;
-  let isReMaterializable = 1;
-  let isAsCheapAsAMove = 1;
-}
-def SUBREG_TO_REG : Instruction {
-  let OutOperandList = (ops unknown:$dst);
-  let InOperandList = (ops unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
-  let AsmString = "";
-  let Namespace = "TargetInstrInfo";
-  let neverHasSideEffects = 1;
-}
-
-//===----------------------------------------------------------------------===//
-// AsmWriter - This class can be implemented by targets that need to customize
-// the format of the .s file writer.
-//
-// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
-// on X86 for example).
-//
-class AsmWriter {
-  // AsmWriterClassName - This specifies the suffix to use for the asmwriter
-  // class.  Generated AsmWriter classes are always prefixed with the target
-  // name.
-  string AsmWriterClassName  = "AsmPrinter";
-
-  // InstFormatName - AsmWriters can specify the name of the format string to
-  // print instructions with.
-  string InstFormatName = "AsmString";
-
-  // Variant - AsmWriters can be of multiple different variants.  Variants are
-  // used to support targets that need to emit assembly code in ways that are
-  // mostly the same for different targets, but have minor differences in
-  // syntax.  If the asmstring contains {|} characters in them, this integer
-  // will specify which alternative to use.  For example "{x|y|z}" with Variant
-  // == 1, will expand to "y".
-  int Variant = 0;
-}
-def DefaultAsmWriter : AsmWriter;
-
-
-//===----------------------------------------------------------------------===//
-// Target - This class contains the "global" target information
-//
-class Target {
-  // InstructionSet - Instruction set description for this target.
-  InstrInfo InstructionSet;
-
-  // AssemblyWriters - The AsmWriter instances available for this target.
-  list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
-}
-
-//===----------------------------------------------------------------------===//
-// SubtargetFeature - A characteristic of the chip set.
-//
-class SubtargetFeature<string n, string a,  string v, string d,
-                       list<SubtargetFeature> i = []> {
-  // Name - Feature name.  Used by command line (-mattr=) to determine the
-  // appropriate target chip.
-  //
-  string Name = n;
-  
-  // Attribute - Attribute to be set by feature.
-  //
-  string Attribute = a;
-  
-  // Value - Value the attribute to be set to by feature.
-  //
-  string Value = v;
-  
-  // Desc - Feature description.  Used by command line (-mattr=) to display help
-  // information.
-  //
-  string Desc = d;
-
-  // Implies - Features that this feature implies are present. If one of those
-  // features isn't set, then this one shouldn't be set either.
-  //
-  list<SubtargetFeature> Implies = i;
-}
-
-//===----------------------------------------------------------------------===//
-// Processor chip sets - These values represent each of the chip sets supported
-// by the scheduler.  Each Processor definition requires corresponding
-// instruction itineraries.
-//
-class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
-  // Name - Chip set name.  Used by command line (-mcpu=) to determine the
-  // appropriate target chip.
-  //
-  string Name = n;
-  
-  // ProcItin - The scheduling information for the target processor.
-  //
-  ProcessorItineraries ProcItin = pi;
-  
-  // Features - list of 
-  list<SubtargetFeature> Features = f;
-}
-
-//===----------------------------------------------------------------------===//
-// Pull in the common support for calling conventions.
-//
-include "TargetCallingConv.td"
-
-//===----------------------------------------------------------------------===//
-// Pull in the common support for DAG isel generation.
-//
-include "TargetSelectionDAG.td"
diff --git a/lib/Target/TargetCallingConv.td b/lib/Target/TargetCallingConv.td
deleted file mode 100644
index 908e16e..0000000
--- a/lib/Target/TargetCallingConv.td
+++ /dev/null
@@ -1,103 +0,0 @@
-//===- TargetCallingConv.td - Target Calling Conventions ---*- tablegen -*-===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-// This file defines the target-independent interfaces with which targets
-// describe their calling conventions.
-//
-//===----------------------------------------------------------------------===//
-
-class CCAction;
-class CallingConv;
-
-/// CCPredicateAction - Instances of this class check some predicate, then
-/// delegate to another action if the predicate is true.
-class CCPredicateAction<CCAction A> : CCAction {
-  CCAction SubAction = A;
-}
-
-/// CCIfType - If the current argument is one of the specified types, apply
-/// Action A.
-class CCIfType<list<ValueType> vts, CCAction A> : CCPredicateAction<A> {
-  list<ValueType> VTs = vts;
-}
-
-/// CCIf - If the predicate matches, apply A.
-class CCIf<string predicate, CCAction A> : CCPredicateAction<A> {
-  string Predicate = predicate;
-}
-
-/// CCIfByVal - If the current argument has ByVal parameter attribute, apply
-/// Action A.
-class CCIfByVal<CCAction A> : CCIf<"ArgFlags.isByVal()", A> {
-}
-
-/// CCIfCC - Match of the current calling convention is 'CC'.
-class CCIfCC<string CC, CCAction A>
-  : CCIf<!strconcat("State.getCallingConv() == ", CC), A> {}
-
-/// CCIfInReg - If this argument is marked with the 'inreg' attribute, apply
-/// the specified action.
-class CCIfInReg<CCAction A> : CCIf<"ArgFlags.isInReg()", A> {}
-
-/// CCIfNest - If this argument is marked with the 'nest' attribute, apply
-/// the specified action.
-class CCIfNest<CCAction A> : CCIf<"ArgFlags.isNest()", A> {}
-
-/// CCIfNotVarArg - If the current function is not vararg - apply the action
-class CCIfNotVarArg<CCAction A> : CCIf<"!State.isVarArg()", A> {}
-
-/// CCAssignToReg - This action matches if there is a register in the specified
-/// list that is still available.  If so, it assigns the value to the first
-/// available register and succeeds.
-class CCAssignToReg<list<Register> regList> : CCAction {
-  list<Register> RegList = regList;
-}
-
-/// CCAssignToRegWithShadow - Same as CCAssignToReg, but with list of registers
-/// which became shadowed, when some register is used.
-class CCAssignToRegWithShadow<list<Register> regList,
-                              list<Register> shadowList> : CCAction {
-  list<Register> RegList = regList;
-  list<Register> ShadowRegList = shadowList;
-}
-
-/// CCAssignToStack - This action always matches: it assigns the value to a
-/// stack slot of the specified size and alignment on the stack.  If size is
-/// zero then the ABI size is used; if align is zero then the ABI alignment
-/// is used - these may depend on the target or subtarget.
-class CCAssignToStack<int size, int align> : CCAction {
-  int Size = size;
-  int Align = align;
-}
-
-/// CCPassByVal - This action always matches: it assigns the value to a stack
-/// slot to implement ByVal aggregate parameter passing. Size and alignment
-/// specify the minimum size and alignment for the stack slot.
-class CCPassByVal<int size, int align> : CCAction {
-  int Size = size;
-  int Align = align;
-}
-
-/// CCPromoteToType - If applied, this promotes the specified current value to
-/// the specified type.
-class CCPromoteToType<ValueType destTy> : CCAction {
-  ValueType DestTy = destTy;
-}
-
-/// CCDelegateTo - This action invokes the specified sub-calling-convention.  It
-/// is successful if the specified CC matches.
-class CCDelegateTo<CallingConv cc> : CCAction {
-  CallingConv CC = cc;
-}
-
-/// CallingConv - An instance of this is used to define each calling convention
-/// that the target supports.
-class CallingConv<list<CCAction> actions> {
-  list<CCAction> Actions = actions;
-}
diff --git a/lib/Target/TargetSchedule.td b/lib/Target/TargetSchedule.td
deleted file mode 100644
index 38461c5..0000000
--- a/lib/Target/TargetSchedule.td
+++ /dev/null
@@ -1,72 +0,0 @@
-//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-// This file defines the target-independent scheduling interfaces which should
-// be implemented by each target which is using TableGen based scheduling.
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Processor functional unit - These values represent the function units
-// available across all chip sets for the target.  Eg., IntUnit, FPUnit, ...
-// These may be independent values for each chip set or may be shared across
-// all chip sets of the target.  Each functional unit is treated as a resource
-// during scheduling and has an affect instruction order based on availability
-// during a time interval.
-//  
-class FuncUnit;
-
-//===----------------------------------------------------------------------===//
-// Instruction stage - These values represent a step in the execution of an
-// instruction.  The latency represents the number of discrete time slots used
-// need to complete the stage.  Units represent the choice of functional units
-// that can be used to complete the stage.  Eg. IntUnit1, IntUnit2.
-//
-class InstrStage<int cycles, list<FuncUnit> units> {
-  int Cycles          = cycles;       // length of stage in machine cycles
-  list<FuncUnit> Units = units;       // choice of functional units
-}
-
-//===----------------------------------------------------------------------===//
-// Instruction itinerary - An itinerary represents a sequential series of steps
-// required to complete an instruction.  Itineraries are represented as lists of
-// instruction stages.
-//
-
-//===----------------------------------------------------------------------===//
-// Instruction itinerary classes - These values represent 'named' instruction
-// itinerary.  Using named itineraries simplifies managing groups of
-// instructions across chip sets.  An instruction uses the same itinerary class
-// across all chip sets.  Thus a new chip set can be added without modifying
-// instruction information.
-//
-class InstrItinClass;
-def NoItinerary : InstrItinClass;
-
-//===----------------------------------------------------------------------===//
-// Instruction itinerary data - These values provide a runtime map of an 
-// instruction itinerary class (name) to it's itinerary data.
-//
-class InstrItinData<InstrItinClass Class, list<InstrStage> stages> {
-  InstrItinClass TheClass = Class;
-  list<InstrStage> Stages = stages;
-}
-
-//===----------------------------------------------------------------------===//
-// Processor itineraries - These values represent the set of all itinerary
-// classes for a given chip set.
-//
-class ProcessorItineraries<list<InstrItinData> iid> {
-  list<InstrItinData> IID = iid;
-}
-
-// NoItineraries - A marker that can be used by processors without schedule
-// info.
-def NoItineraries : ProcessorItineraries<[]>;
-
diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td
deleted file mode 100644
index c936f7a..0000000
--- a/lib/Target/TargetSelectionDAG.td
+++ /dev/null
@@ -1,898 +0,0 @@
-//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-// This file defines the target-independent interfaces used by SelectionDAG
-// instruction selection generators.
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Type Constraint definitions.
-//
-// Note that the semantics of these constraints are hard coded into tblgen.  To
-// modify or add constraints, you have to hack tblgen.
-//
-
-class SDTypeConstraint<int opnum> {
-  int OperandNum = opnum;
-}
-
-// SDTCisVT - The specified operand has exactly this VT.
-class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
-  ValueType VT = vt;
-}
-
-class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
-
-// SDTCisInt - The specified operand is has integer type.
-class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
-
-// SDTCisFP - The specified operand is has floating point type.
-class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
-
-// SDTCisSameAs - The two specified operands have identical types.
-class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
-  int OtherOperandNum = OtherOp;
-}
-
-// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
-// smaller than the 'Other' operand.
-class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
-  int OtherOperandNum = OtherOp;
-}
-
-class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
-  int BigOperandNum = BigOp;
-}
-
-/// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
-/// vector types, and that ThisOp is the result of 
-/// MVT::getIntVectorWithNumElements with the number of elements
-/// that ThisOp has.
-class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
-  : SDTypeConstraint<ThisOp> {
-  int OtherOpNum = OtherOp;
-}
-
-/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
-/// type as the element type of OtherOp, which is a vector type.
-class SDTCisEltOfVec<int ThisOp, int OtherOp>
-  : SDTypeConstraint<ThisOp> {
-  int OtherOpNum = OtherOp;
-}
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Type Profile definitions.
-//
-// These use the constraints defined above to describe the type requirements of
-// the various nodes.  These are not hard coded into tblgen, allowing targets to
-// add their own if needed.
-//
-
-// SDTypeProfile - This profile describes the type requirements of a Selection
-// DAG node.
-class SDTypeProfile<int numresults, int numoperands,
-                    list<SDTypeConstraint> constraints> {
-  int NumResults = numresults;
-  int NumOperands = numoperands;
-  list<SDTypeConstraint> Constraints = constraints;
-}
-
-// Builtin profiles.
-def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>;         // for 'imm'.
-def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>;          // for 'fpimm'.
-def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;       // for '&g'.
-def SDTOther  : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
-def SDTUNDEF  : SDTypeProfile<1, 0, []>;                     // for 'undef'.
-def SDTUnaryOp  : SDTypeProfile<1, 1, []>;                   // for bitconvert.
-
-def SDTIntBinOp : SDTypeProfile<1, 2, [     // add, and, or, xor, udiv, etc.
-  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
-]>;
-def SDTIntShiftOp : SDTypeProfile<1, 2, [   // shl, sra, srl
-  SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
-]>;
-def SDTFPBinOp : SDTypeProfile<1, 2, [      // fadd, fmul, etc.
-  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
-]>;
-def SDTFPSignOp : SDTypeProfile<1, 2, [     // fcopysign.
-  SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
-]>;
-def SDTFPTernaryOp : SDTypeProfile<1, 3, [  // fmadd, fnmsub, etc.
-  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
-]>;
-def SDTIntUnaryOp : SDTypeProfile<1, 1, [   // ctlz
-  SDTCisSameAs<0, 1>, SDTCisInt<0>
-]>;
-def SDTIntExtendOp : SDTypeProfile<1, 1, [  // sext, zext, anyext
-  SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
-]>;
-def SDTIntTruncOp  : SDTypeProfile<1, 1, [  // trunc
-  SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
-]>;
-def SDTFPUnaryOp  : SDTypeProfile<1, 1, [   // fneg, fsqrt, etc
-  SDTCisSameAs<0, 1>, SDTCisFP<0>
-]>;
-def SDTFPRoundOp  : SDTypeProfile<1, 1, [   // fround
-  SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
-]>;
-def SDTFPExtendOp  : SDTypeProfile<1, 1, [  // fextend
-  SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
-]>;
-def SDTIntToFPOp : SDTypeProfile<1, 1, [    // [su]int_to_fp 
-  SDTCisFP<0>, SDTCisInt<1>
-]>;
-def SDTFPToIntOp : SDTypeProfile<1, 1, [    // fp_to_[su]int 
-  SDTCisInt<0>, SDTCisFP<1>
-]>;
-def SDTExtInreg : SDTypeProfile<1, 2, [     // sext_inreg
-  SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
-  SDTCisVTSmallerThanOp<2, 1>
-]>;
-
-def SDTSetCC : SDTypeProfile<1, 3, [        // setcc
-  SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
-]>;
-
-def SDTSelect : SDTypeProfile<1, 3, [       // select 
-  SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
-]>;
-
-def SDTSelectCC : SDTypeProfile<1, 5, [     // select_cc
-  SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
-  SDTCisVT<5, OtherVT>
-]>;
-
-def SDTBr : SDTypeProfile<0, 1, [           // br
-  SDTCisVT<0, OtherVT>
-]>;
-
-def SDTBrcond : SDTypeProfile<0, 2, [       // brcond
-  SDTCisInt<0>, SDTCisVT<1, OtherVT>
-]>;
-
-def SDTBrind : SDTypeProfile<0, 1, [        // brind
-  SDTCisPtrTy<0>
-]>;
-
-def SDTNone : SDTypeProfile<0, 0, []>;      // ret, trap
-
-def SDTLoad : SDTypeProfile<1, 1, [         // load
-  SDTCisPtrTy<1>  
-]>;
-
-def SDTStore : SDTypeProfile<0, 2, [        // store
-  SDTCisPtrTy<1>  
-]>;
-
-def SDTIStore : SDTypeProfile<1, 3, [       // indexed store
-  SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
-]>;
-
-def SDTVecShuffle : SDTypeProfile<1, 3, [
-  SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
-]>;
-def SDTVecExtract : SDTypeProfile<1, 2, [   // vector extract
-  SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
-]>;
-def SDTVecInsert : SDTypeProfile<1, 3, [    // vector insert
-  SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
-]>;
-
-def STDPrefetch : SDTypeProfile<0, 3, [     // prefetch
-  SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
-]>;
-
-def STDMemBarrier : SDTypeProfile<0, 5, [   // memory barier
-  SDTCisSameAs<0,1>,  SDTCisSameAs<0,2>,  SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
-  SDTCisInt<0>
-]>;
-def STDAtomic3 : SDTypeProfile<1, 3, [
-  SDTCisSameAs<0,2>,  SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
-]>;
-def STDAtomic2 : SDTypeProfile<1, 2, [
-  SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
-]>;
-
-def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
-  SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
-]>;
-
-class SDCallSeqStart<list<SDTypeConstraint> constraints> :
-        SDTypeProfile<0, 1, constraints>;
-class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
-        SDTypeProfile<0, 2, constraints>;
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Node Properties.
-//
-// Note: These are hard coded into tblgen.
-//
-class SDNodeProperty;
-def SDNPCommutative : SDNodeProperty;   // X op Y == Y op X
-def SDNPAssociative : SDNodeProperty;   // (X op Y) op Z == X op (Y op Z)
-def SDNPHasChain    : SDNodeProperty;   // R/W chain operand and result
-def SDNPOutFlag     : SDNodeProperty;   // Write a flag result
-def SDNPInFlag      : SDNodeProperty;   // Read a flag operand
-def SDNPOptInFlag   : SDNodeProperty;   // Optionally read a flag operand
-def SDNPMayStore    : SDNodeProperty;   // May write to memory, sets 'mayStore'.
-def SDNPMayLoad     : SDNodeProperty;   // May read memory, sets 'mayLoad'.
-def SDNPSideEffect  : SDNodeProperty;   // Sets 'HasUnmodelledSideEffects'.
-def SDNPMemOperand  : SDNodeProperty;   // Touches memory, has assoc MemOperand
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Node definitions.
-//
-class SDNode<string opcode, SDTypeProfile typeprof,
-             list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
-  string Opcode  = opcode;
-  string SDClass = sdclass;
-  list<SDNodeProperty> Properties = props;
-  SDTypeProfile TypeProfile = typeprof;
-}
-
-def set;
-def implicit;
-def parallel;
-def node;
-def srcvalue;
-
-def imm        : SDNode<"ISD::Constant"  , SDTIntLeaf , [], "ConstantSDNode">;
-def timm       : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
-def fpimm      : SDNode<"ISD::ConstantFP", SDTFPLeaf  , [], "ConstantFPSDNode">;
-def vt         : SDNode<"ISD::VALUETYPE" , SDTOther   , [], "VTSDNode">;
-def bb         : SDNode<"ISD::BasicBlock", SDTOther   , [], "BasicBlockSDNode">;
-def cond       : SDNode<"ISD::CONDCODE"  , SDTOther   , [], "CondCodeSDNode">;
-def undef      : SDNode<"ISD::UNDEF"     , SDTUNDEF   , []>;
-def globaladdr : SDNode<"ISD::GlobalAddress",         SDTPtrLeaf, [],
-                        "GlobalAddressSDNode">;
-def tglobaladdr : SDNode<"ISD::TargetGlobalAddress",  SDTPtrLeaf, [],
-                         "GlobalAddressSDNode">;
-def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress",         SDTPtrLeaf, [],
-                          "GlobalAddressSDNode">;
-def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress",  SDTPtrLeaf, [],
-                           "GlobalAddressSDNode">;
-def constpool   : SDNode<"ISD::ConstantPool",         SDTPtrLeaf, [],
-                         "ConstantPoolSDNode">;
-def tconstpool  : SDNode<"ISD::TargetConstantPool",   SDTPtrLeaf, [],
-                         "ConstantPoolSDNode">;
-def jumptable   : SDNode<"ISD::JumpTable",            SDTPtrLeaf, [],
-                         "JumpTableSDNode">;
-def tjumptable  : SDNode<"ISD::TargetJumpTable",      SDTPtrLeaf, [],
-                         "JumpTableSDNode">;
-def frameindex  : SDNode<"ISD::FrameIndex",           SDTPtrLeaf, [],
-                         "FrameIndexSDNode">;
-def tframeindex : SDNode<"ISD::TargetFrameIndex",     SDTPtrLeaf, [],
-                         "FrameIndexSDNode">;
-def externalsym : SDNode<"ISD::ExternalSymbol",       SDTPtrLeaf, [],
-                         "ExternalSymbolSDNode">;
-def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
-                         "ExternalSymbolSDNode">;
-
-def add        : SDNode<"ISD::ADD"       , SDTIntBinOp   ,
-                        [SDNPCommutative, SDNPAssociative]>;
-def sub        : SDNode<"ISD::SUB"       , SDTIntBinOp>;
-def mul        : SDNode<"ISD::MUL"       , SDTIntBinOp,
-                        [SDNPCommutative, SDNPAssociative]>;
-def mulhs      : SDNode<"ISD::MULHS"     , SDTIntBinOp, [SDNPCommutative]>;
-def mulhu      : SDNode<"ISD::MULHU"     , SDTIntBinOp, [SDNPCommutative]>;
-def sdiv       : SDNode<"ISD::SDIV"      , SDTIntBinOp>;
-def udiv       : SDNode<"ISD::UDIV"      , SDTIntBinOp>;
-def srem       : SDNode<"ISD::SREM"      , SDTIntBinOp>;
-def urem       : SDNode<"ISD::UREM"      , SDTIntBinOp>;
-def srl        : SDNode<"ISD::SRL"       , SDTIntShiftOp>;
-def sra        : SDNode<"ISD::SRA"       , SDTIntShiftOp>;
-def shl        : SDNode<"ISD::SHL"       , SDTIntShiftOp>;
-def rotl       : SDNode<"ISD::ROTL"      , SDTIntShiftOp>;
-def rotr       : SDNode<"ISD::ROTR"      , SDTIntShiftOp>;
-def and        : SDNode<"ISD::AND"       , SDTIntBinOp,
-                        [SDNPCommutative, SDNPAssociative]>;
-def or         : SDNode<"ISD::OR"        , SDTIntBinOp,
-                        [SDNPCommutative, SDNPAssociative]>;
-def xor        : SDNode<"ISD::XOR"       , SDTIntBinOp,
-                        [SDNPCommutative, SDNPAssociative]>;
-def addc       : SDNode<"ISD::ADDC"      , SDTIntBinOp,
-                        [SDNPCommutative, SDNPOutFlag]>;
-def adde       : SDNode<"ISD::ADDE"      , SDTIntBinOp,
-                        [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
-def subc       : SDNode<"ISD::SUBC"      , SDTIntBinOp,
-                        [SDNPOutFlag]>;
-def sube       : SDNode<"ISD::SUBE"      , SDTIntBinOp,
-                        [SDNPOutFlag, SDNPInFlag]>;
-                        
-def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
-def bswap      : SDNode<"ISD::BSWAP"      , SDTIntUnaryOp>;
-def ctlz       : SDNode<"ISD::CTLZ"       , SDTIntUnaryOp>;
-def cttz       : SDNode<"ISD::CTTZ"       , SDTIntUnaryOp>;
-def ctpop      : SDNode<"ISD::CTPOP"      , SDTIntUnaryOp>;
-def sext       : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
-def zext       : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
-def anyext     : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
-def trunc      : SDNode<"ISD::TRUNCATE"   , SDTIntTruncOp>;
-def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
-def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
-def insertelt  : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
-
-                        
-def fadd       : SDNode<"ISD::FADD"       , SDTFPBinOp, [SDNPCommutative]>;
-def fsub       : SDNode<"ISD::FSUB"       , SDTFPBinOp>;
-def fmul       : SDNode<"ISD::FMUL"       , SDTFPBinOp, [SDNPCommutative]>;
-def fdiv       : SDNode<"ISD::FDIV"       , SDTFPBinOp>;
-def frem       : SDNode<"ISD::FREM"       , SDTFPBinOp>;
-def fabs       : SDNode<"ISD::FABS"       , SDTFPUnaryOp>;
-def fneg       : SDNode<"ISD::FNEG"       , SDTFPUnaryOp>;
-def fsqrt      : SDNode<"ISD::FSQRT"      , SDTFPUnaryOp>;
-def fsin       : SDNode<"ISD::FSIN"       , SDTFPUnaryOp>;
-def fcos       : SDNode<"ISD::FCOS"       , SDTFPUnaryOp>;
-def frint      : SDNode<"ISD::FRINT"      , SDTFPUnaryOp>;
-def ftrunc     : SDNode<"ISD::FTRUNC"     , SDTFPUnaryOp>;
-def fceil      : SDNode<"ISD::FCEIL"      , SDTFPUnaryOp>;
-def ffloor     : SDNode<"ISD::FFLOOR"     , SDTFPUnaryOp>;
-def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
-
-def fround     : SDNode<"ISD::FP_ROUND"   , SDTFPRoundOp>;
-def fextend    : SDNode<"ISD::FP_EXTEND"  , SDTFPExtendOp>;
-def fcopysign  : SDNode<"ISD::FCOPYSIGN"  , SDTFPSignOp>;
-
-def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
-def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
-def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
-def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
-
-def setcc      : SDNode<"ISD::SETCC"      , SDTSetCC>;
-def select     : SDNode<"ISD::SELECT"     , SDTSelect>;
-def selectcc   : SDNode<"ISD::SELECT_CC"  , SDTSelectCC>;
-def vsetcc     : SDNode<"ISD::VSETCC"     , SDTSetCC>;
-
-def brcond     : SDNode<"ISD::BRCOND"     , SDTBrcond, [SDNPHasChain]>;
-def brind      : SDNode<"ISD::BRIND"      , SDTBrind,  [SDNPHasChain]>;
-def br         : SDNode<"ISD::BR"         , SDTBr,     [SDNPHasChain]>;
-def ret        : SDNode<"ISD::RET"        , SDTNone,   [SDNPHasChain]>;
-def trap       : SDNode<"ISD::TRAP"       , SDTNone,
-                        [SDNPHasChain, SDNPSideEffect]>;
-
-def prefetch   : SDNode<"ISD::PREFETCH"   , STDPrefetch,
-                        [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
-
-def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
-                        [SDNPHasChain, SDNPSideEffect]>;
-
-def atomic_cmp_swap_8 : SDNode<"ISD::ATOMIC_CMP_SWAP_8" , STDAtomic3,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_add_8 : SDNode<"ISD::ATOMIC_LOAD_ADD_8" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_swap_8     : SDNode<"ISD::ATOMIC_SWAP_8", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_sub_8 : SDNode<"ISD::ATOMIC_LOAD_SUB_8" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_and_8 : SDNode<"ISD::ATOMIC_LOAD_AND_8" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_or_8  : SDNode<"ISD::ATOMIC_LOAD_OR_8" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_xor_8 : SDNode<"ISD::ATOMIC_LOAD_XOR_8" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_nand_8: SDNode<"ISD::ATOMIC_LOAD_NAND_8", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_min_8 : SDNode<"ISD::ATOMIC_LOAD_MIN_8", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_max_8 : SDNode<"ISD::ATOMIC_LOAD_MAX_8", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_umin_8 : SDNode<"ISD::ATOMIC_LOAD_UMIN_8", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_umax_8 : SDNode<"ISD::ATOMIC_LOAD_UMAX_8", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_cmp_swap_16 : SDNode<"ISD::ATOMIC_CMP_SWAP_16" , STDAtomic3,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_add_16 : SDNode<"ISD::ATOMIC_LOAD_ADD_16" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_swap_16     : SDNode<"ISD::ATOMIC_SWAP_16", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_sub_16 : SDNode<"ISD::ATOMIC_LOAD_SUB_16" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_and_16 : SDNode<"ISD::ATOMIC_LOAD_AND_16" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_or_16  : SDNode<"ISD::ATOMIC_LOAD_OR_16" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_xor_16 : SDNode<"ISD::ATOMIC_LOAD_XOR_16" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_nand_16: SDNode<"ISD::ATOMIC_LOAD_NAND_16", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_min_16 : SDNode<"ISD::ATOMIC_LOAD_MIN_16", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_max_16 : SDNode<"ISD::ATOMIC_LOAD_MAX_16", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_umin_16 : SDNode<"ISD::ATOMIC_LOAD_UMIN_16", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_umax_16 : SDNode<"ISD::ATOMIC_LOAD_UMAX_16", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_cmp_swap_32 : SDNode<"ISD::ATOMIC_CMP_SWAP_32" , STDAtomic3,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_add_32 : SDNode<"ISD::ATOMIC_LOAD_ADD_32" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_swap_32     : SDNode<"ISD::ATOMIC_SWAP_32", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_sub_32 : SDNode<"ISD::ATOMIC_LOAD_SUB_32" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_and_32 : SDNode<"ISD::ATOMIC_LOAD_AND_32" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_or_32  : SDNode<"ISD::ATOMIC_LOAD_OR_32" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_xor_32 : SDNode<"ISD::ATOMIC_LOAD_XOR_32" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_nand_32: SDNode<"ISD::ATOMIC_LOAD_NAND_32", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_min_32 : SDNode<"ISD::ATOMIC_LOAD_MIN_32", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_max_32 : SDNode<"ISD::ATOMIC_LOAD_MAX_32", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_umin_32 : SDNode<"ISD::ATOMIC_LOAD_UMIN_32", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_umax_32 : SDNode<"ISD::ATOMIC_LOAD_UMAX_32", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_cmp_swap_64 : SDNode<"ISD::ATOMIC_CMP_SWAP_64" , STDAtomic3,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_add_64 : SDNode<"ISD::ATOMIC_LOAD_ADD_64" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_swap_64     : SDNode<"ISD::ATOMIC_SWAP_64", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_sub_64 : SDNode<"ISD::ATOMIC_LOAD_SUB_64" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_and_64 : SDNode<"ISD::ATOMIC_LOAD_AND_64" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_or_64  : SDNode<"ISD::ATOMIC_LOAD_OR_64" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_xor_64 : SDNode<"ISD::ATOMIC_LOAD_XOR_64" , STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_nand_64: SDNode<"ISD::ATOMIC_LOAD_NAND_64", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_min_64 : SDNode<"ISD::ATOMIC_LOAD_MIN_64", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_max_64 : SDNode<"ISD::ATOMIC_LOAD_MAX_64", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_umin_64 : SDNode<"ISD::ATOMIC_LOAD_UMIN_64", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def atomic_load_umax_64 : SDNode<"ISD::ATOMIC_LOAD_UMAX_64", STDAtomic2,
-                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-
-// Do not use ld, st directly. Use load, extload, sextload, zextload, store,
-// and truncst (see below).
-def ld         : SDNode<"ISD::LOAD"       , SDTLoad,
-                        [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
-def st         : SDNode<"ISD::STORE"      , SDTStore,
-                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
-def ist        : SDNode<"ISD::STORE"      , SDTIStore,
-                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
-
-def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
-def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
-def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
-                              []>;
-def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
-    SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
-def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
-    SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
-    
-def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG", 
-    SDTypeProfile<1, 2, []>>;
-def insert_subreg : SDNode<"ISD::INSERT_SUBREG", 
-    SDTypeProfile<1, 3, []>>;
-
-// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
-// these internally.  Don't reference these directly.
-def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 
-                            SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
-                            [SDNPHasChain]>;
-def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 
-                               SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
-                               [SDNPHasChain]>;
-def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 
-                                SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
-
-// Do not use cvt directly. Use cvt forms below
-def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Condition Codes
-
-class CondCode; // ISD::CondCode enums
-def SETOEQ : CondCode; def SETOGT : CondCode;
-def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
-def SETONE : CondCode; def SETO   : CondCode; def SETUO  : CondCode;
-def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
-def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
-
-def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
-def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
-
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Node Transformation Functions.
-//
-// This mechanism allows targets to manipulate nodes in the output DAG once a
-// match has been formed.  This is typically used to manipulate immediate
-// values.
-//
-class SDNodeXForm<SDNode opc, code xformFunction> {
-  SDNode Opcode = opc;
-  code XFormFunction = xformFunction;
-}
-
-def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
-
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Pattern Fragments.
-//
-// Pattern fragments are reusable chunks of dags that match specific things.
-// They can take arguments and have C++ predicates that control whether they
-// match.  They are intended to make the patterns for common instructions more
-// compact and readable.
-//
-
-/// PatFrag - Represents a pattern fragment.  This can match something on the
-/// DAG, frame a single node to multiply nested other fragments.
-///
-class PatFrag<dag ops, dag frag, code pred = [{}],
-              SDNodeXForm xform = NOOP_SDNodeXForm> {
-  dag Operands = ops;
-  dag Fragment = frag;
-  code Predicate = pred;
-  SDNodeXForm OperandTransform = xform;
-}
-
-// PatLeaf's are pattern fragments that have no operands.  This is just a helper
-// to define immediates and other common things concisely.
-class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
- : PatFrag<(ops), frag, pred, xform>;
-
-// Leaf fragments.
-
-def vtInt      : PatLeaf<(vt),  [{ return N->getVT().isInteger(); }]>;
-def vtFP       : PatLeaf<(vt),  [{ return N->getVT().isFloatingPoint(); }]>;
-
-def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
-def immAllOnesV: PatLeaf<(build_vector), [{
-  return ISD::isBuildVectorAllOnes(N);
-}]>;
-def immAllOnesV_bc: PatLeaf<(bitconvert), [{
-  return ISD::isBuildVectorAllOnes(N);
-}]>;
-def immAllZerosV: PatLeaf<(build_vector), [{
-  return ISD::isBuildVectorAllZeros(N);
-}]>;
-def immAllZerosV_bc: PatLeaf<(bitconvert), [{
-  return ISD::isBuildVectorAllZeros(N);
-}]>;
-
-
-
-// Other helper fragments.
-def not  : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
-def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
-def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
-def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
-
-// load fragments.
-def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
-  return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
-}]>;
-def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
-}]>;
-
-// extending load fragments.
-def extload   : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
-}]>;
-def sextload  : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
-}]>;
-def zextload  : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
-}]>;
-
-def extloadi1  : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
-}]>;
-def extloadi8  : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
-}]>;
-def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
-}]>;
-def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
-}]>;
-def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
-}]>;
-def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
-}]>;
-
-def sextloadi1  : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
-}]>;
-def sextloadi8  : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
-}]>;
-def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
-}]>;
-def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
-}]>;
-
-def zextloadi1  : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
-}]>;
-def zextloadi8  : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
-}]>;
-def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
-}]>;
-def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
-  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
-}]>;
-
-// store fragments.
-def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
-                             (st node:$val, node:$ptr), [{
-  return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
-}]>;
-def store : PatFrag<(ops node:$val, node:$ptr),
-                    (unindexedstore node:$val, node:$ptr), [{
-  return !cast<StoreSDNode>(N)->isTruncatingStore();
-}]>;
-
-// truncstore fragments.
-def truncstore : PatFrag<(ops node:$val, node:$ptr),
-                         (unindexedstore node:$val, node:$ptr), [{
-  return cast<StoreSDNode>(N)->isTruncatingStore();
-}]>;
-def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
-                           (truncstore node:$val, node:$ptr), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
-}]>;
-def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
-                            (truncstore node:$val, node:$ptr), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
-}]>;
-def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
-                            (truncstore node:$val, node:$ptr), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
-}]>;
-def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
-                            (truncstore node:$val, node:$ptr), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
-}]>;
-def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
-                            (truncstore node:$val, node:$ptr), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
-}]>;
-
-// indexed store fragments.
-def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
-                     (ist node:$val, node:$base, node:$offset), [{
-  return !cast<StoreSDNode>(N)->isTruncatingStore();
-}]>;
-
-def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
-                        (istore node:$val, node:$base, node:$offset), [{
-  ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
-  return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
-}]>;
-
-def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
-                          (ist node:$val, node:$base, node:$offset), [{
-  return cast<StoreSDNode>(N)->isTruncatingStore();
-}]>;
-def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
-                          (itruncstore node:$val, node:$base, node:$offset), [{
-  ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
-  return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
-}]>;
-def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
-                            (pre_truncst node:$val, node:$base, node:$offset), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
-}]>;
-def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
-                            (pre_truncst node:$val, node:$base, node:$offset), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
-}]>;
-def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
-                             (pre_truncst node:$val, node:$base, node:$offset), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
-}]>;
-def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
-                             (pre_truncst node:$val, node:$base, node:$offset), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
-}]>;
-def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
-                             (pre_truncst node:$val, node:$base, node:$offset), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
-}]>;
-
-def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
-                         (istore node:$val, node:$ptr, node:$offset), [{
-  ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
-  return AM == ISD::POST_INC || AM == ISD::POST_DEC;
-}]>;
-
-def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
-                           (itruncstore node:$val, node:$base, node:$offset), [{
-  ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
-  return AM == ISD::POST_INC || AM == ISD::POST_DEC;
-}]>;
-def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
-                             (post_truncst node:$val, node:$base, node:$offset), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
-}]>;
-def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
-                             (post_truncst node:$val, node:$base, node:$offset), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
-}]>;
-def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
-                              (post_truncst node:$val, node:$base, node:$offset), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
-}]>;
-def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
-                              (post_truncst node:$val, node:$base, node:$offset), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
-}]>;
-def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
-                              (post_truncst node:$val, node:$base, node:$offset), [{
-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
-}]>;
-
-// setcc convenience fragments.
-def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETOEQ)>;
-def setogt : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETOGT)>;
-def setoge : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETOGE)>;
-def setolt : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETOLT)>;
-def setole : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETOLE)>;
-def setone : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETONE)>;
-def seto   : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETO)>;
-def setuo  : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETUO)>;
-def setueq : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETUEQ)>;
-def setugt : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETUGT)>;
-def setuge : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETUGE)>;
-def setult : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETULT)>;
-def setule : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETULE)>;
-def setune : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETUNE)>;
-def seteq  : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETEQ)>;
-def setgt  : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETGT)>;
-def setge  : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETGE)>;
-def setlt  : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETLT)>;
-def setle  : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETLE)>;
-def setne  : PatFrag<(ops node:$lhs, node:$rhs),
-                     (setcc node:$lhs, node:$rhs, SETNE)>;
-
-//===----------------------------------------------------------------------===//
-// Selection DAG CONVERT_RNDSAT patterns
-
-def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
-    (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
-       return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
-    }]>;
-
-def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
-    (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
-       return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
-    }]>;
-
-def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
-    (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
-       return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
-    }]>;
-
-def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
-    (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
-       return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
-    }]>;
-
-def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
-    (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
-       return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
-    }]>;
-
-def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
-    (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
-       return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
-    }]>;
-
-def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
-    (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
-       return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
-    }]>;
-
-def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
-    (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
-       return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
-    }]>;
-
-def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
-    (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
-       return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
-    }]>;
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Pattern Support.
-//
-// Patterns are what are actually matched against the target-flavored
-// instruction selection DAG.  Instructions defined by the target implicitly
-// define patterns in most cases, but patterns can also be explicitly added when
-// an operation is defined by a sequence of instructions (e.g. loading a large
-// immediate value on RISC targets that do not support immediates as large as
-// their GPRs).
-//
-
-class Pattern<dag patternToMatch, list<dag> resultInstrs> {
-  dag             PatternToMatch  = patternToMatch;
-  list<dag>       ResultInstrs    = resultInstrs;
-  list<Predicate> Predicates      = [];  // See class Instruction in Target.td.
-  int             AddedComplexity = 0;  // See class Instruction in Target.td.
-}
-
-// Pat - A simple (but common) form of a pattern, which produces a simple result
-// not needing a full list.
-class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
-
-//===----------------------------------------------------------------------===//
-// Complex pattern definitions.
-//
-
-class CPAttribute;
-// Pass the parent Operand as root to CP function rather 
-// than the root of the sub-DAG
-def CPAttrParentAsRoot : CPAttribute;
-
-// Complex patterns, e.g. X86 addressing mode, requires pattern matching code
-// in C++. NumOperands is the number of operands returned by the select function;
-// SelectFunc is the name of the function used to pattern match the max. pattern;
-// RootNodes are the list of possible root nodes of the sub-dags to match.
-// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
-//
-class ComplexPattern<ValueType ty, int numops, string fn,
-                     list<SDNode> roots = [], list<SDNodeProperty> props = [],
-                     list<CPAttribute> attrs = []> {
-  ValueType Ty = ty;
-  int NumOperands = numops;
-  string SelectFunc = fn;
-  list<SDNode> RootNodes = roots;
-  list<SDNodeProperty> Properties = props;
-  list<CPAttribute> Attributes = attrs;
-}
-
-//===----------------------------------------------------------------------===//
-// Dwarf support.
-//
-def SDT_dwarf_loc : SDTypeProfile<0, 3,
-                      [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
-def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index f70c175..6d08b36 100644
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -14,7 +14,7 @@
 
 // Get the target-independent interfaces which we are implementing...
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // X86 Subtarget features.
diff --git a/lib/Target/XCore/XCore.td b/lib/Target/XCore/XCore.td
index 39c4226..7a2dcdb 100644
--- a/lib/Target/XCore/XCore.td
+++ b/lib/Target/XCore/XCore.td
@@ -14,7 +14,7 @@
 // Target-independent interfaces which we are implementing
 //===----------------------------------------------------------------------===//
 
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // Descriptions