diff options
| author | Duncan Sands <baldrick@free.fr> | 2008-06-14 17:48:34 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2008-06-14 17:48:34 +0000 |
| commit | 184a876ee61dbbd602597f35e18240a5df8f5ee4 (patch) | |
| tree | 4930c0926e61ed8ff23125a7db6ed5253216958a /lib | |
| parent | 5d2bc857ec1ae11ec2ea85e596f3712d02fd2c2b (diff) | |
| download | external_llvm-184a876ee61dbbd602597f35e18240a5df8f5ee4.zip external_llvm-184a876ee61dbbd602597f35e18240a5df8f5ee4.tar.gz external_llvm-184a876ee61dbbd602597f35e18240a5df8f5ee4.tar.bz2 | |
Remove a redundant AfterLegalize check. Turn
on some code when !AfterLegalize - but since
this whole code section is turned off by an
"if (0)" it's not really turning anything on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52276 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index ad8a227..ac433cf 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4758,8 +4758,7 @@ SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { // original load. unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> getABITypeAlignment(LVT.getTypeForMVT()); - if (NewAlign > Align || - (AfterLegalize && !TLI.isOperationLegal(ISD::LOAD, LVT))) + if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT)) return SDOperand(); Align = NewAlign; } @@ -5350,7 +5349,8 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, // otherwise, go ahead with the folds. if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { MVT XType = N0.getValueType(); - if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { + if (!AfterLegalize || + TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); if (Res.getValueType() != VT) Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); @@ -5359,7 +5359,8 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, // seteq X, 0 -> srl (ctlz X, log2(size(X))) if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && - TLI.isOperationLegal(ISD::CTLZ, XType)) { + (!AfterLegalize || + TLI.isOperationLegal(ISD::CTLZ, XType))) { SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); return DAG.getNode(ISD::SRL, XType, Ctlz, DAG.getConstant(Log2_32(XType.getSizeInBits()), |