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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-21 22:43:58 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-21 22:43:58 +0000 |
commit | 35242e27c578da3915451079b5bdd7b9a89ed77c (patch) | |
tree | 8d9ce6cfd27ec45b8d3ac95ed7a2725f0b7e4068 /lib | |
parent | 8aaed99a99fcb879be2ed9bbc25a68c2e8558960 (diff) | |
download | external_llvm-35242e27c578da3915451079b5bdd7b9a89ed77c.zip external_llvm-35242e27c578da3915451079b5bdd7b9a89ed77c.tar.gz external_llvm-35242e27c578da3915451079b5bdd7b9a89ed77c.tar.bz2 |
[mips] Refactor count leading zero or one instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170942 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 4 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrFormats.td | 16 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 29 |
3 files changed, 29 insertions, 20 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 20d4932..b2a0d07 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -196,8 +196,8 @@ def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10>; def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18>; /// Count Leading -def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>; -def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>; +def DCLZ : CountLeading0<"dclz", CPU64Regs>, CLO_FM<0x24>; +def DCLO : CountLeading1<"dclo", CPU64Regs>, CLO_FM<0x25>; /// Double Word Swap Bytes/HalfWords def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>; diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index 89bcd38..8dad6c2 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -340,6 +340,22 @@ class SEB_FM<bits<5> funct> { let Inst{5-0} = 0x20; } +class CLO_FM<bits<6> funct> { + bits<5> rd; + bits<5> rs; + bits<5> rt; + + bits<32> Inst; + + let Inst{31-26} = 0x1c; + let Inst{25-21} = rs; + let Inst{20-16} = rt; + let Inst{15-11} = rd; + let Inst{10-6} = 0; + let Inst{5-0} = funct; + let rt = rd; +} + //===----------------------------------------------------------------------===// // // FLOATING POINT INSTRUCTION FORMATS diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 38d6137..6d33bdf 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -684,23 +684,16 @@ class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand } // Count Leading Ones/Zeros in Word -class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>: - FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), - !strconcat(instr_asm, "\t$rd, $rs"), - [(set RC:$rd, (ctlz RC:$rs))], IIAlu>, - Requires<[HasBitCount, HasStdEnc]> { - let shamt = 0; - let rt = rd; -} +class CountLeading0<string opstr, RegisterClass RC>: + InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), + [(set RC:$rd, (ctlz RC:$rs))], IIAlu, FrmR>, + Requires<[HasBitCount, HasStdEnc]>; + +class CountLeading1<string opstr, RegisterClass RC>: + InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), + [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu, FrmR>, + Requires<[HasBitCount, HasStdEnc]>; -class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>: - FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), - !strconcat(instr_asm, "\t$rd, $rs"), - [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>, - Requires<[HasBitCount, HasStdEnc]> { - let shamt = 0; - let rt = rd; -} // Sign Extend in Register. class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : @@ -966,8 +959,8 @@ def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10>; def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18>; /// Count Leading -def CLZ : CountLeading0<0x20, "clz", CPURegs>; -def CLO : CountLeading1<0x21, "clo", CPURegs>; +def CLZ : CountLeading0<"clz", CPURegs>, CLO_FM<0x20>; +def CLO : CountLeading1<"clo", CPURegs>, CLO_FM<0x21>; /// Word Swap Bytes Within Halfwords def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; |