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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-01-19 16:56:52 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-01-19 16:56:52 +0000 |
| commit | 3abd75bf1dc96ee0cd7e8c1b8331e27672437b8b (patch) | |
| tree | 9374a5b6ba641f99b84aa92b4ed0987b64279ad0 /lib | |
| parent | c4440e3e307fb696146c08c127c53300a982fe82 (diff) | |
| download | external_llvm-3abd75bf1dc96ee0cd7e8c1b8331e27672437b8b.zip external_llvm-3abd75bf1dc96ee0cd7e8c1b8331e27672437b8b.tar.gz external_llvm-3abd75bf1dc96ee0cd7e8c1b8331e27672437b8b.tar.bz2 | |
Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123837 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 5161f88..8018fe7 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -3745,28 +3745,28 @@ def MRC2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1, let Inst{19-16} = CRn; } -def MCRR : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc, +def MCRR : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), - NoItinerary, "mcrr", "\t$cop, $opc, $Rt, $Rt2, $CRm", + NoItinerary, "mcrr", "\t$cop, $opc1, $Rt, $Rt2, $CRm", [/* For disassembly only; pattern left blank */]> { let Inst{23-20} = 0b0100; bits<4> Rt; bits<4> Rt2; bits<4> cop; - bits<3> opc1; + bits<4> opc1; bits<4> CRm; let Inst{15-12} = Rt; let Inst{19-16} = Rt2; let Inst{11-8} = cop; - let Inst{7-5} = opc1; + let Inst{7-4} = opc1; let Inst{3-0} = CRm; } -def MCRR2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc, +def MCRR2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), - NoItinerary, "mcrr2\t$cop, $opc, $Rt, $Rt2, $CRm", + NoItinerary, "mcrr2\t$cop, $opc1, $Rt, $Rt2, $CRm", [/* For disassembly only; pattern left blank */]> { let Inst{31-28} = 0b1111; let Inst{23-20} = 0b0100; @@ -3774,38 +3774,38 @@ def MCRR2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc, bits<4> Rt; bits<4> Rt2; bits<4> cop; - bits<3> opc1; + bits<4> opc1; bits<4> CRm; let Inst{15-12} = Rt; let Inst{19-16} = Rt2; let Inst{11-8} = cop; - let Inst{7-5} = opc1; + let Inst{7-4} = opc1; let Inst{3-0} = CRm; } -def MRRC : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc, +def MRRC : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), - NoItinerary, "mrrc", "\t$cop, $opc, $Rt, $Rt2, $CRm", + NoItinerary, "mrrc", "\t$cop, $opc1, $Rt, $Rt2, $CRm", [/* For disassembly only; pattern left blank */]> { let Inst{23-20} = 0b0101; bits<4> Rt; bits<4> Rt2; bits<4> cop; - bits<3> opc1; + bits<4> opc1; bits<4> CRm; let Inst{15-12} = Rt; let Inst{19-16} = Rt2; let Inst{11-8} = cop; - let Inst{7-5} = opc1; + let Inst{7-4} = opc1; let Inst{3-0} = CRm; } -def MRRC2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc, +def MRRC2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), - NoItinerary, "mrrc2\t$cop, $opc, $Rt, $Rt2, $CRm", + NoItinerary, "mrrc2\t$cop, $opc1, $Rt, $Rt2, $CRm", [/* For disassembly only; pattern left blank */]> { let Inst{31-28} = 0b1111; let Inst{23-20} = 0b0101; @@ -3813,13 +3813,13 @@ def MRRC2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc, bits<4> Rt; bits<4> Rt2; bits<4> cop; - bits<3> opc1; + bits<4> opc1; bits<4> CRm; let Inst{15-12} = Rt; let Inst{19-16} = Rt2; let Inst{11-8} = cop; - let Inst{7-5} = opc1; + let Inst{7-4} = opc1; let Inst{3-0} = CRm; } |