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authorChris Lattner <sabre@nondot.org>2007-04-17 22:53:02 +0000
committerChris Lattner <sabre@nondot.org>2007-04-17 22:53:02 +0000
commit8c7d2d56bf5aa2186e2d08ed1dc37c2f392b4aae (patch)
treee589c601d11eacfb2f6ad717dbf1d52a9b8143a8 /lib
parent120fba91a3d894daaa9317474b51e1fed8577a83 (diff)
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Fix a bug in my previous patch, grabbing the shift amount width from the
wrong operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36223 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 3da06f9..ff27b12 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -581,7 +581,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
}
SDOperand NewSA =
- TLO.DAG.getConstant(ShAmt-C1, Op.getOperand(0).getValueType());
+ TLO.DAG.getConstant(ShAmt-C1, Op.getOperand(1).getValueType());
MVT::ValueType VT = Op.getValueType();
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT,
InOp.getOperand(0), NewSA));
@@ -619,7 +619,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
}
SDOperand NewSA =
- TLO.DAG.getConstant(Diff, Op.getOperand(0).getValueType());
+ TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
InOp.getOperand(0), NewSA));
}