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author | Pirama Arumuga Nainar <pirama@google.com> | 2015-05-20 12:55:36 -0700 |
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committer | Pirama Arumuga Nainar <pirama@google.com> | 2015-05-26 14:28:33 -0700 |
commit | 560a17f4e3f8019a108abb7848a4735c59a43be0 (patch) | |
tree | 89b942fa3484ef229429f490a5e8219e741af0d1 /test/CodeGen/AArch64/fp16-vector-nvcast.ll | |
parent | 2c3e0051c31c3f5b2328b447eadf1cf9c4427442 (diff) | |
download | external_llvm-560a17f4e3f8019a108abb7848a4735c59a43be0.zip external_llvm-560a17f4e3f8019a108abb7848a4735c59a43be0.tar.gz external_llvm-560a17f4e3f8019a108abb7848a4735c59a43be0.tar.bz2 |
Update aosp/master LLVM with patches for fp16
Cherry-pick LLVM revisions r235191, r235215, r235220, r235341, r235363,
r235530, r235609, r235610, r237004
r235191 has a required bug-fix and the rest are all related to fp16.
Change-Id: I7fe8da5ffd8f2c06150885a54769abd18c3a04c6
(cherry picked from commit a18e6af1712fd41c4a705a19ad71f6e9ac7a4e68)
Diffstat (limited to 'test/CodeGen/AArch64/fp16-vector-nvcast.ll')
-rw-r--r-- | test/CodeGen/AArch64/fp16-vector-nvcast.ll | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/fp16-vector-nvcast.ll b/test/CodeGen/AArch64/fp16-vector-nvcast.ll new file mode 100644 index 0000000..83e0df7 --- /dev/null +++ b/test/CodeGen/AArch64/fp16-vector-nvcast.ll @@ -0,0 +1,89 @@ +; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s + +; Test pattern (v4f16 (AArch64NvCast (v2i32 FPR64:$src))) +define void @nvcast_v2i32(<4 x half>* %a) #0 { +; CHECK-LABEL: nvcast_v2i32: +; CHECK-NEXT: movi v[[REG:[0-9]+]].2s, #0xab, lsl #16 +; CHECK-NEXT: str d[[REG]], [x0] +; CHECK-NEXT: ret + store volatile <4 x half> <half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB>, <4 x half>* %a + ret void +} + + +; Test pattern (v4f16 (AArch64NvCast (v4i16 FPR64:$src))) +define void @nvcast_v4i16(<4 x half>* %a) #0 { +; CHECK-LABEL: nvcast_v4i16: +; CHECK-NEXT: movi v[[REG:[0-9]+]].4h, #0xab +; CHECK-NEXT: str d[[REG]], [x0] +; CHECK-NEXT: ret + store volatile <4 x half> <half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB>, <4 x half>* %a + ret void +} + + +; Test pattern (v4f16 (AArch64NvCast (v8i8 FPR64:$src))) +define void @nvcast_v8i8(<4 x half>* %a) #0 { +; CHECK-LABEL: nvcast_v8i8: +; CHECK-NEXT: movi v[[REG:[0-9]+]].8b, #0xab +; CHECK-NEXT: str d[[REG]], [x0] +; CHECK-NEXT: ret + store volatile <4 x half> <half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB>, <4 x half>* %a + ret void +} + + +; Test pattern (v4f16 (AArch64NvCast (f64 FPR64:$src))) +define void @nvcast_f64(<4 x half>* %a) #0 { +; CHECK-LABEL: nvcast_f64: +; CHECK-NEXT: movi d[[REG:[0-9]+]], #0000000000000000 +; CHECK-NEXT: str d[[REG]], [x0] +; CHECK-NEXT: ret + store volatile <4 x half> zeroinitializer, <4 x half>* %a + ret void +} + +; Test pattern (v8f16 (AArch64NvCast (v4i32 FPR128:$src))) +define void @nvcast_v4i32(<8 x half>* %a) #0 { +; CHECK-LABEL: nvcast_v4i32: +; CHECK-NEXT: movi v[[REG:[0-9]+]].4s, #0xab, lsl #16 +; CHECK-NEXT: str q[[REG]], [x0] +; CHECK-NEXT: ret + store volatile <8 x half> <half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB>, <8 x half>* %a + ret void +} + + +; Test pattern (v8f16 (AArch64NvCast (v8i16 FPR128:$src))) +define void @nvcast_v8i16(<8 x half>* %a) #0 { +; CHECK-LABEL: nvcast_v8i16: +; CHECK-NEXT: movi v[[REG:[0-9]+]].8h, #0xab +; CHECK-NEXT: str q[[REG]], [x0] +; CHECK-NEXT: ret + store volatile <8 x half> <half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB>, <8 x half>* %a + ret void +} + + +; Test pattern (v8f16 (AArch64NvCast (v16i8 FPR128:$src))) +define void @nvcast_v16i8(<8 x half>* %a) #0 { +; CHECK-LABEL: nvcast_v16i8: +; CHECK-NEXT: movi v[[REG:[0-9]+]].16b, #0xab +; CHECK-NEXT: str q[[REG]], [x0] +; CHECK-NEXT: ret + store volatile <8 x half> <half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB>, <8 x half>* %a + ret void +} + + +; Test pattern (v8f16 (AArch64NvCast (v2i64 FPR128:$src))) +define void @nvcast_v2i64(<8 x half>* %a) #0 { +; CHECK-LABEL: nvcast_v2i64: +; CHECK-NEXT: movi v[[REG:[0-9]+]].2d, #0000000000000000 +; CHECK-NEXT: str q[[REG]], [x0] +; CHECK-NEXT: ret + store volatile <8 x half> zeroinitializer, <8 x half>* %a + ret void +} + +attributes #0 = { nounwind } |