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| author | Stephen Hines <srhines@google.com> | 2014-12-01 14:51:49 -0800 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-12-02 16:08:10 -0800 |
| commit | 37ed9c199ca639565f6ce88105f9e39e898d82d0 (patch) | |
| tree | 8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /test/CodeGen/ARM/adv-copy-opt.ll | |
| parent | d2327b22152ced7bc46dc629fc908959e8a52d03 (diff) | |
| download | external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.zip external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.gz external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.bz2 | |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Diffstat (limited to 'test/CodeGen/ARM/adv-copy-opt.ll')
| -rw-r--r-- | test/CodeGen/ARM/adv-copy-opt.ll | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/adv-copy-opt.ll b/test/CodeGen/ARM/adv-copy-opt.ll new file mode 100644 index 0000000..f71bf78 --- /dev/null +++ b/test/CodeGen/ARM/adv-copy-opt.ll @@ -0,0 +1,38 @@ +; RUN: llc -O1 -mtriple=armv7s-apple-ios -mcpu=swift < %s -disable-adv-copy-opt=true | FileCheck -check-prefix=NOOPT --check-prefix=CHECK %s +; RUN: llc -O1 -mtriple=armv7s-apple-ios -mcpu=swift < %s -disable-adv-copy-opt=false | FileCheck -check-prefix=OPT --check-prefix=CHECK %s +; RUN: llc -O1 -mtriple=thumbv7s-apple-ios -mcpu=swift < %s -disable-adv-copy-opt=true | FileCheck -check-prefix=NOOPT --check-prefix=CHECK %s +; RUN: llc -O1 -mtriple=thumbv7s-apple-ios -mcpu=swift < %s -disable-adv-copy-opt=false | FileCheck -check-prefix=OPT --check-prefix=CHECK %s + +; CHECK-LABEL: simpleVectorDiv +; ABI: %A => r0, r1. +; %B => r2, r3 +; ret => r0, r1 +; We want to compute: +; r0 = r0 / r2 +; r1 = r1 / r3 +; +; NOOPT: vmov [[B:d[0-9]+]], r2, r3 +; NOOPT-NEXT: vmov [[A:d[0-9]+]], r0, r1 +; Move the low part of B into a register. +; Unfortunately, we cannot express that the 's' register is the low +; part of B, i.e., sIdx == BIdx x 2. E.g., B = d1, B_low = s2. +; NOOPT-NEXT: vmov [[B_LOW:r[0-9]+]], s{{[0-9]+}} +; NOOPT-NEXT: vmov [[A_LOW:r[0-9]+]], s{{[0-9]+}} +; NOOPT-NEXT: udiv [[RES_LOW:r[0-9]+]], [[A_LOW]], [[B_LOW]] +; NOOPT-NEXT: vmov [[B_HIGH:r[0-9]+]], s{{[0-9]+}} +; NOOPT-NEXT: vmov [[A_HIGH:r[0-9]+]], s{{[0-9]+}} +; NOOPT-NEXT: udiv [[RES_HIGH:r[0-9]+]], [[A_HIGH]], [[B_HIGH]] +; NOOPT-NEXT: vmov.32 [[RES:d[0-9]+]][0], [[RES_LOW]] +; NOOPT-NEXT: vmov.32 [[RES]][1], [[RES_HIGH]] +; NOOPT-NEXT: vmov r0, r1, [[RES]] +; NOOPT-NEXT: bx lr +; +; OPT-NOT: vmov +; OPT: udiv r0, r0, r2 +; OPT-NEXT: udiv r1, r1, r3 +; OPT-NEXT: bx lr +define <2 x i32> @simpleVectorDiv(<2 x i32> %A, <2 x i32> %B) nounwind { +entry: + %div = udiv <2 x i32> %A, %B + ret <2 x i32> %div +} |