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author | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
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committer | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
commit | ebe69fe11e48d322045d5949c83283927a0d790b (patch) | |
tree | c92f1907a6b8006628a4b01615f38264d29834ea /test/CodeGen/ARM/interrupt-attr.ll | |
parent | b7d2e72b02a4cb8034f32f8247a2558d2434e121 (diff) | |
download | external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.zip external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.gz external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.bz2 |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
Diffstat (limited to 'test/CodeGen/ARM/interrupt-attr.ll')
-rw-r--r-- | test/CodeGen/ARM/interrupt-attr.ll | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/test/CodeGen/ARM/interrupt-attr.ll b/test/CodeGen/ARM/interrupt-attr.ll index 96d1ee2..c6da09d 100644 --- a/test/CodeGen/ARM/interrupt-attr.ll +++ b/test/CodeGen/ARM/interrupt-attr.ll @@ -15,7 +15,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr} ; CHECK-A: add r11, sp, #20 ; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}} -; CHECK-A: bic sp, sp, #7 +; CHECK-A: bfc sp, #0, #3 ; CHECK-A: bl bar ; CHECK-A: sub sp, r11, #20 ; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr} @@ -25,7 +25,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; CHECK-A-THUMB: push.w {r0, r1, r2, r3, r4, r7, r12, lr} ; CHECK-A-THUMB: add r7, sp, #20 ; CHECK-A-THUMB: mov r4, sp -; CHECK-A-THUMB: bic r4, r4, #7 +; CHECK-A-THUMB: bfc r4, #0, #3 ; CHECK-A-THUMB: bl bar ; CHECK-A-THUMB: sub.w r4, r7, #20 ; CHECK-A-THUMB: mov sp, r4 @@ -38,7 +38,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; CHECK-M: push.w {r4, r10, r11, lr} ; CHECK-M: add.w r11, sp, #8 ; CHECK-M: mov r4, sp -; CHECK-M: bic r4, r4, #7 +; CHECK-M: bfc r4, #0, #3 ; CHECK-M: mov sp, r4 ; CHECK-M: bl _bar ; CHECK-M: sub.w r4, r11, #8 @@ -56,7 +56,7 @@ define arm_aapcscc void @fiq_fn() alignstack(8) "interrupt"="FIQ" { ; 32 to get past r0, r1, ..., r7 ; CHECK-A: add r11, sp, #32 ; CHECK-A: sub sp, sp, #{{[0-9]+}} -; CHECK-A: bic sp, sp, #7 +; CHECK-A: bfc sp, #0, #3 ; [...] ; 32 must match above ; CHECK-A: sub sp, r11, #32 @@ -75,7 +75,7 @@ define arm_aapcscc void @swi_fn() alignstack(8) "interrupt"="SWI" { ; CHECK-A: push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr} ; CHECK-A: add r11, sp, #44 ; CHECK-A: sub sp, sp, #{{[0-9]+}} -; CHECK-A: bic sp, sp, #7 +; CHECK-A: bfc sp, #0, #3 ; [...] ; CHECK-A: sub sp, r11, #44 ; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr} @@ -91,7 +91,7 @@ define arm_aapcscc void @undef_fn() alignstack(8) "interrupt"="UNDEF" { ; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr} ; CHECK-A: add r11, sp, #20 ; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}} -; CHECK-A: bic sp, sp, #7 +; CHECK-A: bfc sp, #0, #3 ; [...] ; CHECK-A: sub sp, r11, #20 ; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr} @@ -106,7 +106,7 @@ define arm_aapcscc void @abort_fn() alignstack(8) "interrupt"="ABORT" { ; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr} ; CHECK-A: add r11, sp, #20 ; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}} -; CHECK-A: bic sp, sp, #7 +; CHECK-A: bfc sp, #0, #3 ; [...] ; CHECK-A: sub sp, r11, #20 ; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr} |