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| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-11-12 10:14:03 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-11-12 10:14:03 +0000 |
| commit | 7ea1ab5f41299563eb648aed159cfaff09e774d8 (patch) | |
| tree | 9352a3ac97282d9786b31ae08a2d03057186984e /test/CodeGen/CellSPU | |
| parent | d0c82a683e965f326e36a2bcaa85c00e917f8282 (diff) | |
| download | external_llvm-7ea1ab5f41299563eb648aed159cfaff09e774d8.zip external_llvm-7ea1ab5f41299563eb648aed159cfaff09e774d8.tar.gz external_llvm-7ea1ab5f41299563eb648aed159cfaff09e774d8.tar.bz2 | |
Fix memory access lowering on SPU, adding
support for the case where alignment<value size.
These cases were silently miscompiled before this patch.
Now they are overly verbose -especially storing is- and
any front-end should still avoid misaligned memory
accesses as much as possible. The bit juggling algorithm
added here probably has some room for improvement still.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118889 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/CellSPU')
| -rw-r--r-- | test/CodeGen/CellSPU/arg_ret.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/loads.ll | 12 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/stores.ll | 13 |
3 files changed, 26 insertions, 1 deletions
diff --git a/test/CodeGen/CellSPU/arg_ret.ll b/test/CodeGen/CellSPU/arg_ret.ll index 6f07458..7410b72 100644 --- a/test/CodeGen/CellSPU/arg_ret.ll +++ b/test/CodeGen/CellSPU/arg_ret.ll @@ -26,7 +26,7 @@ define ccc i32 @test_regs_and_stack( %paramstruct %prm, i32 %stackprm ) define ccc %paramstruct @test_return( i32 %param, %paramstruct %prm ) { -;CHECK: lqd $75, 80($sp) +;CHECK: lqd {{\$[0-9]+}}, 80($sp) ;CHECK-NOT: ori {{\$[0-9]+, \$[0-9]+, 0}} ;CHECK: lr $3, $4 ret %paramstruct %prm diff --git a/test/CodeGen/CellSPU/loads.ll b/test/CodeGen/CellSPU/loads.ll index d40217d..03d7ad1 100644 --- a/test/CodeGen/CellSPU/loads.ll +++ b/test/CodeGen/CellSPU/loads.ll @@ -38,3 +38,15 @@ define <4 x float> @load_undef(){ %val = load <4 x float>* undef ret <4 x float> %val } + +;check that 'misaligned' loads that may span two memory chunks +;have two loads. Don't check for the bitmanipulation, as that +;might change with improved algorithms or scheduling +define i32 @load_misaligned( i32* %ptr ){ +;CHECK: load_misaligned +;CHECK: lqd +;CHECK: lqd +;CHECK: bi $lr + %rv = load i32* %ptr, align 2 + ret i32 %rv +} diff --git a/test/CodeGen/CellSPU/stores.ll b/test/CodeGen/CellSPU/stores.ll index 05f44f4..efc915c 100644 --- a/test/CodeGen/CellSPU/stores.ll +++ b/test/CodeGen/CellSPU/stores.ll @@ -14,6 +14,7 @@ ; RUN: grep iohl %t1.s | count 8 ; RUN: grep shufb %t1.s | count 15 ; RUN: grep frds %t1.s | count 1 +; RUN: llc < %s -march=cellspu | FileCheck %s ; ModuleID = 'stores.bc' target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" @@ -149,3 +150,15 @@ entry: store float %conv, float* %dest ret float %conv } + +;Check stores that might span two 16 byte memory blocks +define void @store_misaligned( i32 %val, i32* %ptr) { +;CHECK: store_misaligned +;CHECK: lqd +;CHECK: lqd +;CHECK: stqd +;CHECK: stqd +;CHECK: bi $lr + store i32 %val, i32*%ptr, align 2 + ret void +} |