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author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-01-14 22:09:38 +0000 |
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committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-01-14 22:09:38 +0000 |
commit | 74a265686dd3e816c0f580c77d07fbb9e8bf3ddd (patch) | |
tree | 2904e50b2c3cb92de37d2248983fc9df4afc71ed /test/CodeGen/MSP430 | |
parent | 5fcf52ccf34d6cb56e0bd6314aaa9a847f3a0939 (diff) | |
download | external_llvm-74a265686dd3e816c0f580c77d07fbb9e8bf3ddd.zip external_llvm-74a265686dd3e816c0f580c77d07fbb9e8bf3ddd.tar.gz external_llvm-74a265686dd3e816c0f580c77d07fbb9e8bf3ddd.tar.bz2 |
Add variable-width shifts for MSP430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93468 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/MSP430')
-rw-r--r-- | test/CodeGen/MSP430/shifts.ll | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/test/CodeGen/MSP430/shifts.ll b/test/CodeGen/MSP430/shifts.ll new file mode 100644 index 0000000..b5b3054 --- /dev/null +++ b/test/CodeGen/MSP430/shifts.ll @@ -0,0 +1,51 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-n8:16" +target triple = "msp430-elf" + +define zeroext i8 @lshr8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone { +entry: +; CHECK: lshr8: +; CHECK: rrc.b + %shr = lshr i8 %a, %cnt + ret i8 %shr +} + +define signext i8 @ashr8(i8 signext %a, i8 zeroext %cnt) nounwind readnone { +entry: +; CHECK: ashr8: +; CHECK: rra.b + %shr = ashr i8 %a, %cnt + ret i8 %shr +} + +define zeroext i8 @shl8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone { +entry: +; CHECK: shl8 +; CHECK: rla.b + %shl = shl i8 %a, %cnt + ret i8 %shl +} + +define zeroext i16 @lshr16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone { +entry: +; CHECK: lshr16: +; CHECK: rrc.w + %shr = lshr i16 %a, %cnt + ret i16 %shr +} + +define signext i16 @ashr16(i16 signext %a, i16 zeroext %cnt) nounwind readnone { +entry: +; CHECK: ashr16: +; CHECK: rra.w + %shr = ashr i16 %a, %cnt + ret i16 %shr +} + +define zeroext i16 @shl16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone { +entry: +; CHECK: shl16: +; CHECK: rla.w + %shl = shl i16 %a, %cnt + ret i16 %shl +} |