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author | Eric Christopher <echristo@apple.com> | 2012-05-07 03:13:32 +0000 |
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committer | Eric Christopher <echristo@apple.com> | 2012-05-07 03:13:32 +0000 |
commit | 50ab03954ec0a43708ad0a5cf3d253ce41a30db3 (patch) | |
tree | b7bf1f31906c48a53eb7c3fd1b2a29fbd17be061 /test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll | |
parent | 0ed1f764f4e0d4cc940052e8ccca260bf5c39407 (diff) | |
download | external_llvm-50ab03954ec0a43708ad0a5cf3d253ce41a30db3.zip external_llvm-50ab03954ec0a43708ad0a5cf3d253ce41a30db3.tar.gz external_llvm-50ab03954ec0a43708ad0a5cf3d253ce41a30db3.tar.bz2 |
Add support for the 'I' inline asm constraint. Also add tests
from the previous 2 patches.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156279 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll')
-rw-r--r-- | test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll new file mode 100644 index 0000000..7870666 --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll @@ -0,0 +1,20 @@ +; +; Register constraint "r" shouldn't take long long unless +; The target is 64 bit. +; +; +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s + + +define i32 @main() nounwind { +entry: + + +; r with long long +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3 +;CHECK: #NO_APP + tail call i64 asm sideeffect "addi $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind + ret i32 0 +} + |