diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-29 18:09:28 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-29 18:09:28 +0000 |
| commit | 089751535d6e9adf65842e2ca5867bf9a70e1e95 (patch) | |
| tree | 883781d177686ef496311a6d049024b5b61219ef /test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll | |
| parent | d7e473c629a5e4fb1584fb5c5c1b0c1e142fdc8f (diff) | |
| download | external_llvm-089751535d6e9adf65842e2ca5867bf9a70e1e95.zip external_llvm-089751535d6e9adf65842e2ca5867bf9a70e1e95.tar.gz external_llvm-089751535d6e9adf65842e2ca5867bf9a70e1e95.tar.bz2 | |
Avoiding overly aggressive latency scheduling. If the two nodes share an
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.
BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB
=>
BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB
This fixed the recent 256.bzip2 regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117675 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll')
| -rw-r--r-- | test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll b/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll index 0b6c92b..080341c 100644 --- a/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll +++ b/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll @@ -23,7 +23,10 @@ entry: %4 = insertelement <2 x double> %2, double %V.0.ph, i32 1 ; <<2 x double>> [#uses=2] ; Constant pool load followed by add. ; Then clobber the loaded register, not the sum. +; CHECK: vldr.64 +; CHECK: vadd.f64 ; CHECK: vldr.64 [[LDR:d.*]], +; CHECK: LPC0_0: ; CHECK: vadd.f64 [[ADD:d.*]], [[LDR]], [[LDR]] ; CHECK: vmov.f64 [[LDR]] %5 = fadd <2 x double> %3, %3 ; <<2 x double>> [#uses=2] |