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authorJim Grosbach <grosbach@apple.com>2009-11-17 00:20:26 +0000
committerJim Grosbach <grosbach@apple.com>2009-11-17 00:20:26 +0000
commit1187285e90215c28194bd1590704d56951d365ad (patch)
tree96de6ce469c2f5c1056207fc6146656ba54b5ecb /test/CodeGen/Thumb2/thumb2-uxtb.ll
parent727f0c37fbfcfd01569ddb41abab7c2585953159 (diff)
downloadexternal_llvm-1187285e90215c28194bd1590704d56951d365ad.zip
external_llvm-1187285e90215c28194bd1590704d56951d365ad.tar.gz
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Convert to FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89007 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2/thumb2-uxtb.ll')
-rw-r--r--test/CodeGen/Thumb2/thumb2-uxtb.ll28
1 files changed, 26 insertions, 2 deletions
diff --git a/test/CodeGen/Thumb2/thumb2-uxtb.ll b/test/CodeGen/Thumb2/thumb2-uxtb.ll
index 4022d95..4e23f53 100644
--- a/test/CodeGen/Thumb2/thumb2-uxtb.ll
+++ b/test/CodeGen/Thumb2/thumb2-uxtb.ll
@@ -1,36 +1,47 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
-; RUN: grep uxt | count 10
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @test1(i32 %x) {
+; CHECK: test1
+; CHECK: uxtb16.w r0, r0
%tmp1 = and i32 %x, 16711935 ; <i32> [#uses=1]
ret i32 %tmp1
}
define i32 @test2(i32 %x) {
+; CHECK: test2
+; CHECK: uxtb16.w r0, r0, ror #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp2
}
define i32 @test3(i32 %x) {
+; CHECK: test3
+; CHECK: uxtb16.w r0, r0, ror #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp2
}
define i32 @test4(i32 %x) {
+; CHECK: test4
+; CHECK: uxtb16.w r0, r0, ror #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp6 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp6
}
define i32 @test5(i32 %x) {
+; CHECK: test5
+; CHECK: uxtb16.w r0, r0, ror #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp2
}
define i32 @test6(i32 %x) {
+; CHECK: test6
+; CHECK: uxtb16.w r0, r0, ror #16
%tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1]
%tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
@@ -40,6 +51,8 @@ define i32 @test6(i32 %x) {
}
define i32 @test7(i32 %x) {
+; CHECK: test7
+; CHECK: uxtb16.w r0, r0, ror #16
%tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1]
%tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
@@ -49,6 +62,8 @@ define i32 @test7(i32 %x) {
}
define i32 @test8(i32 %x) {
+; CHECK: test8
+; CHECK: uxtb16.w r0, r0, ror #24
%tmp1 = shl i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711680 ; <i32> [#uses=1]
%tmp5 = lshr i32 %x, 24 ; <i32> [#uses=1]
@@ -57,6 +72,8 @@ define i32 @test8(i32 %x) {
}
define i32 @test9(i32 %x) {
+; CHECK: test9
+; CHECK: uxtb16.w r0, r0, ror #24
%tmp1 = lshr i32 %x, 24 ; <i32> [#uses=1]
%tmp4 = shl i32 %x, 8 ; <i32> [#uses=1]
%tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
@@ -65,6 +82,13 @@ define i32 @test9(i32 %x) {
}
define i32 @test10(i32 %p0) {
+; CHECK: test10
+; CHECK: mov.w r1, #16253176
+; CHECK: and.w r0, r1, r0, lsr #7
+; CHECK: lsrs r1, r0, #5
+; CHECK: uxtb16.w r1, r1
+; CHECK: orr.w r0, r1, r0
+
%tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2]
%tmp4 = lshr i32 %tmp2, 5 ; <i32> [#uses=1]