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author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-12 09:20:14 +0000 |
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committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-12 09:20:14 +0000 |
commit | 566fb9fe3ed767be7218fb1608ec6a284067d3b0 (patch) | |
tree | 4dd475b0d14b590c5fa4bcbb54935140e1483399 /test/CodeGen | |
parent | 9bcad42c3aadab118b6ed5f30f2ea0d87228fd3f (diff) | |
download | external_llvm-566fb9fe3ed767be7218fb1608ec6a284067d3b0.zip external_llvm-566fb9fe3ed767be7218fb1608ec6a284067d3b0.tar.gz external_llvm-566fb9fe3ed767be7218fb1608ec6a284067d3b0.tar.bz2 |
[SystemZ] Add test missing from r186148
Sigh, twice in two days sorry. One day I'll remember...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186150 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r-- | test/CodeGen/SystemZ/asm-17.ll | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/test/CodeGen/SystemZ/asm-17.ll b/test/CodeGen/SystemZ/asm-17.ll new file mode 100644 index 0000000..f2fbba6 --- /dev/null +++ b/test/CodeGen/SystemZ/asm-17.ll @@ -0,0 +1,82 @@ +; Test explicit register names. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test i32 GPRs. +define i32 @f1() { +; CHECK: f1: +; CHECK: lhi %r4, 1 +; CHECK: blah %r4 +; CHECK: lr %r2, %r4 +; CHECK: br %r14 + %ret = call i32 asm "blah $0", "={r4},0" (i32 1) + ret i32 %ret +} + +; Test i64 GPRs. +define i64 @f2() { +; CHECK: f2: +; CHECK: lghi %r4, 1 +; CHECK: blah %r4 +; CHECK: lgr %r2, %r4 +; CHECK: br %r14 + %ret = call i64 asm "blah $0", "={r4},0" (i64 1) + ret i64 %ret +} + +; Test i32 FPRs. +define float @f3() { +; CHECK: f3: +; CHECK: lzer %f4 +; CHECK: blah %f4 +; CHECK: ler %f0, %f4 +; CHECK: br %r14 + %ret = call float asm "blah $0", "={f4},0" (float 0.0) + ret float %ret +} + +; Test i64 FPRs. +define double @f4() { +; CHECK: f4: +; CHECK: lzdr %f4 +; CHECK: blah %f4 +; CHECK: ldr %f0, %f4 +; CHECK: br %r14 + %ret = call double asm "blah $0", "={f4},0" (double 0.0) + ret double %ret +} + +; Test i128 FPRs. +define void @f5(fp128 *%dest) { +; CHECK: f5: +; CHECK: lzxr %f4 +; CHECK: blah %f4 +; CHECK-DAG: std %f4, 0(%r2) +; CHECK-DAG: std %f6, 8(%r2) +; CHECK: br %r14 + %ret = call fp128 asm "blah $0", "={f4},0" (fp128 0xL00000000000000000000000000000000) + store fp128 %ret, fp128 *%dest + ret void +} + +; Test clobbers of GPRs and CC. +define i32 @f6(i32 %in) { +; CHECK: f6: +; CHECK: lr [[REG:%r[01345]]], %r2 +; CHECK: blah +; CHECK: lr %r2, [[REG]] +; CHECK: br %r14 + call void asm sideeffect "blah", "~{r2},~{cc}"() + ret i32 %in +} + +; Test clobbers of FPRs and CC. +define float @f7(float %in) { +; CHECK: f7: +; CHECK: ler [[REG:%f[1-7]]], %f0 +; CHECK: blah +; CHECK: ler %f0, [[REG]] +; CHECK: br %r14 + call void asm sideeffect "blah", "~{f0},~{cc}"() + ret float %in +} |