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| author | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
| commit | dce4a407a24b04eebc6a376f8e62b41aaa7b071f (patch) | |
| tree | dcebc53f2b182f145a2e659393bf9a0472cedf23 /test/MC/AArch64 | |
| parent | 220b921aed042f9e520c26cffd8282a94c66c3d5 (diff) | |
| download | external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.zip external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.gz external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.bz2 | |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
Diffstat (limited to 'test/MC/AArch64')
64 files changed, 13141 insertions, 3459 deletions
diff --git a/test/MC/AArch64/arm64-adr.s b/test/MC/AArch64/arm64-adr.s new file mode 100644 index 0000000..131e545 --- /dev/null +++ b/test/MC/AArch64/arm64-adr.s @@ -0,0 +1,31 @@ +// RUN: not llvm-mc -triple arm64 -show-encoding < %s 2>%t | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +adr x0, #0 +adr x0, #1 +adr x0, 1f +adr x0, foo +// CHECK: adr x0, #0 // encoding: [0x00,0x00,0x00,0x10] +// CHECK: adr x0, #1 // encoding: [0x00,0x00,0x00,0x30] +// CHECK: adr x0, .Ltmp0 // encoding: [A,A,A,0x10'A'] +// CHECK-NEXT: // fixup A - offset: 0, value: .Ltmp0, kind: fixup_aarch64_pcrel_adr_imm21 +// CHECK: adr x0, foo // encoding: [A,A,A,0x10'A'] +// CHECK-NEXT: // fixup A - offset: 0, value: foo, kind: fixup_aarch64_pcrel_adr_imm21 + +adrp x0, #0 +adrp x0, #4096 +adrp x0, 1f +adrp x0, foo +// CHECK: adrp x0, #0 // encoding: [0x00,0x00,0x00,0x90] +// CHECK: adrp x0, #4096 // encoding: [0x00,0x00,0x00,0xb0] +// CHECK: adrp x0, .Ltmp0 // encoding: [A,A,A,0x90'A'] +// CHECK-NEXT: // fixup A - offset: 0, value: .Ltmp0, kind: fixup_aarch64_pcrel_adrp_imm21 +// CHECK: adrp x0, foo // encoding: [A,A,A,0x90'A'] +// CHECK-NEXT: // fixup A - offset: 0, value: foo, kind: fixup_aarch64_pcrel_adrp_imm21 + +adr x0, #0xffffffff +adrp x0, #0xffffffff +adrp x0, #1 +// CHECK-ERRORS: error: expected label or encodable integer pc offset +// CHECK-ERRORS: error: expected label or encodable integer pc offset +// CHECK-ERRORS: error: expected label or encodable integer pc offset diff --git a/test/MC/AArch64/arm64-advsimd.s b/test/MC/AArch64/arm64-advsimd.s new file mode 100644 index 0000000..c627de7 --- /dev/null +++ b/test/MC/AArch64/arm64-advsimd.s @@ -0,0 +1,1997 @@ +; RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 -show-encoding < %s | FileCheck %s + +foo: + + abs.8b v0, v0 + abs.16b v0, v0 + abs.4h v0, v0 + abs.8h v0, v0 + abs.2s v0, v0 + abs.4s v0, v0 + +; CHECK: abs.8b v0, v0 ; encoding: [0x00,0xb8,0x20,0x0e] +; CHECK: abs.16b v0, v0 ; encoding: [0x00,0xb8,0x20,0x4e] +; CHECK: abs.4h v0, v0 ; encoding: [0x00,0xb8,0x60,0x0e] +; CHECK: abs.8h v0, v0 ; encoding: [0x00,0xb8,0x60,0x4e] +; CHECK: abs.2s v0, v0 ; encoding: [0x00,0xb8,0xa0,0x0e] +; CHECK: abs.4s v0, v0 ; encoding: [0x00,0xb8,0xa0,0x4e] + + add.8b v0, v0, v0 + add.16b v0, v0, v0 + add.4h v0, v0, v0 + add.8h v0, v0, v0 + add.2s v0, v0, v0 + add.4s v0, v0, v0 + add.2d v0, v0, v0 + +; CHECK: add.8b v0, v0, v0 ; encoding: [0x00,0x84,0x20,0x0e] +; CHECK: add.16b v0, v0, v0 ; encoding: [0x00,0x84,0x20,0x4e] +; CHECK: add.4h v0, v0, v0 ; encoding: [0x00,0x84,0x60,0x0e] +; CHECK: add.8h v0, v0, v0 ; encoding: [0x00,0x84,0x60,0x4e] +; CHECK: add.2s v0, v0, v0 ; encoding: [0x00,0x84,0xa0,0x0e] +; CHECK: add.4s v0, v0, v0 ; encoding: [0x00,0x84,0xa0,0x4e] +; CHECK: add.2d v0, v0, v0 ; encoding: [0x00,0x84,0xe0,0x4e] + + add d1, d2, d3 + +; CHECK: add d1, d2, d3 ; encoding: [0x41,0x84,0xe3,0x5e] + + addhn.8b v0, v0, v0 + addhn2.16b v0, v0, v0 + addhn.4h v0, v0, v0 + addhn2.8h v0, v0, v0 + addhn.2s v0, v0, v0 + addhn2.4s v0, v0, v0 + +; CHECK: addhn.8b v0, v0, v0 ; encoding: [0x00,0x40,0x20,0x0e] +; CHECK: addhn2.16b v0, v0, v0 ; encoding: [0x00,0x40,0x20,0x4e] +; CHECK: addhn.4h v0, v0, v0 ; encoding: [0x00,0x40,0x60,0x0e] +; CHECK: addhn2.8h v0, v0, v0 ; encoding: [0x00,0x40,0x60,0x4e] +; CHECK: addhn.2s v0, v0, v0 ; encoding: [0x00,0x40,0xa0,0x0e] +; CHECK: addhn2.4s v0, v0, v0 ; encoding: [0x00,0x40,0xa0,0x4e] + + addp.8b v0, v0, v0 + addp.16b v0, v0, v0 + addp.4h v0, v0, v0 + addp.8h v0, v0, v0 + addp.2s v0, v0, v0 + addp.4s v0, v0, v0 + addp.2d v0, v0, v0 + +; CHECK: addp.8b v0, v0, v0 ; encoding: [0x00,0xbc,0x20,0x0e] +; CHECK: addp.16b v0, v0, v0 ; encoding: [0x00,0xbc,0x20,0x4e] +; CHECK: addp.4h v0, v0, v0 ; encoding: [0x00,0xbc,0x60,0x0e] +; CHECK: addp.8h v0, v0, v0 ; encoding: [0x00,0xbc,0x60,0x4e] +; CHECK: addp.2s v0, v0, v0 ; encoding: [0x00,0xbc,0xa0,0x0e] +; CHECK: addp.4s v0, v0, v0 ; encoding: [0x00,0xbc,0xa0,0x4e] +; CHECK: addp.2d v0, v0, v0 ; encoding: [0x00,0xbc,0xe0,0x4e] + + addp.2d d0, v0 + +; CHECK: addp.2d d0, v0 ; encoding: [0x00,0xb8,0xf1,0x5e] + + addv.8b b0, v0 + addv.16b b0, v0 + addv.4h h0, v0 + addv.8h h0, v0 + addv.4s s0, v0 + +; CHECK: addv.8b b0, v0 ; encoding: [0x00,0xb8,0x31,0x0e] +; CHECK: addv.16b b0, v0 ; encoding: [0x00,0xb8,0x31,0x4e] +; CHECK: addv.4h h0, v0 ; encoding: [0x00,0xb8,0x71,0x0e] +; CHECK: addv.8h h0, v0 ; encoding: [0x00,0xb8,0x71,0x4e] +; CHECK: addv.4s s0, v0 ; encoding: [0x00,0xb8,0xb1,0x4e] + + +; INS/DUP + dup.2d v0, x3 + dup.4s v0, w3 + dup.2s v0, w3 + dup.8h v0, w3 + dup.4h v0, w3 + dup.16b v0, w3 + dup.8b v0, w3 + + dup v1.2d, x3 + dup v2.4s, w4 + dup v3.2s, w5 + dup v4.8h, w6 + dup v5.4h, w7 + dup v6.16b, w8 + dup v7.8b, w9 + +; CHECK: dup.2d v0, x3 ; encoding: [0x60,0x0c,0x08,0x4e] +; CHECK: dup.4s v0, w3 ; encoding: [0x60,0x0c,0x04,0x4e] +; CHECK: dup.2s v0, w3 ; encoding: [0x60,0x0c,0x04,0x0e] +; CHECK: dup.8h v0, w3 ; encoding: [0x60,0x0c,0x02,0x4e] +; CHECK: dup.4h v0, w3 ; encoding: [0x60,0x0c,0x02,0x0e] +; CHECK: dup.16b v0, w3 ; encoding: [0x60,0x0c,0x01,0x4e] +; CHECK: dup.8b v0, w3 ; encoding: [0x60,0x0c,0x01,0x0e] + +; CHECK: dup.2d v1, x3 ; encoding: [0x61,0x0c,0x08,0x4e] +; CHECK: dup.4s v2, w4 ; encoding: [0x82,0x0c,0x04,0x4e] +; CHECK: dup.2s v3, w5 ; encoding: [0xa3,0x0c,0x04,0x0e] +; CHECK: dup.8h v4, w6 ; encoding: [0xc4,0x0c,0x02,0x4e] +; CHECK: dup.4h v5, w7 ; encoding: [0xe5,0x0c,0x02,0x0e] +; CHECK: dup.16b v6, w8 ; encoding: [0x06,0x0d,0x01,0x4e] +; CHECK: dup.8b v7, w9 ; encoding: [0x27,0x0d,0x01,0x0e] + + dup.2d v0, v3[1] + dup.2s v0, v3[1] + dup.4s v0, v3[1] + dup.4h v0, v3[1] + dup.8h v0, v3[1] + dup.8b v0, v3[1] + dup.16b v0, v3[1] + + dup v7.2d, v9.d[1] + dup v6.2s, v8.s[1] + dup v5.4s, v7.s[2] + dup v4.4h, v6.h[3] + dup v3.8h, v5.h[4] + dup v2.8b, v4.b[5] + dup v1.16b, v3.b[6] + +; CHECK: dup.2d v0, v3[1] ; encoding: [0x60,0x04,0x18,0x4e] +; CHECK: dup.2s v0, v3[1] ; encoding: [0x60,0x04,0x0c,0x0e] +; CHECK: dup.4s v0, v3[1] ; encoding: [0x60,0x04,0x0c,0x4e] +; CHECK: dup.4h v0, v3[1] ; encoding: [0x60,0x04,0x06,0x0e] +; CHECK: dup.8h v0, v3[1] ; encoding: [0x60,0x04,0x06,0x4e] +; CHECK: dup.8b v0, v3[1] ; encoding: [0x60,0x04,0x03,0x0e] +; CHECK: dup.16b v0, v3[1] ; encoding: [0x60,0x04,0x03,0x4e] + +; CHECK: dup.2d v7, v9[1] ; encoding: [0x27,0x05,0x18,0x4e] +; CHECK: dup.2s v6, v8[1] ; encoding: [0x06,0x05,0x0c,0x0e] +; CHECK: dup.4s v5, v7[2] ; encoding: [0xe5,0x04,0x14,0x4e] +; CHECK: dup.4h v4, v6[3] ; encoding: [0xc4,0x04,0x0e,0x0e] +; CHECK: dup.8h v3, v5[4] ; encoding: [0xa3,0x04,0x12,0x4e] +; CHECK: dup.8b v2, v4[5] ; encoding: [0x82,0x04,0x0b,0x0e] +; CHECK: dup.16b v1, v3[6] ; encoding: [0x61,0x04,0x0d,0x4e] + + dup b3, v4[1] + dup h3, v4[1] + dup s3, v4[1] + dup d3, v4[1] + dup b3, v4.b[1] + dup h3, v4.h[1] + dup s3, v4.s[1] + dup d3, v4.d[1] + + mov b3, v4[1] + mov h3, v4[1] + mov s3, v4[1] + mov d3, v4[1] + mov b3, v4.b[1] + mov h3, v4.h[1] + mov s3, v4.s[1] + mov d3, v4.d[1] + +; CHECK: mov b3, v4[1] ; encoding: [0x83,0x04,0x03,0x5e] +; CHECK: mov h3, v4[1] ; encoding: [0x83,0x04,0x06,0x5e] +; CHECK: mov s3, v4[1] ; encoding: [0x83,0x04,0x0c,0x5e] +; CHECK: mov d3, v4[1] ; encoding: [0x83,0x04,0x18,0x5e] +; CHECK: mov b3, v4[1] ; encoding: [0x83,0x04,0x03,0x5e] +; CHECK: mov h3, v4[1] ; encoding: [0x83,0x04,0x06,0x5e] +; CHECK: mov s3, v4[1] ; encoding: [0x83,0x04,0x0c,0x5e] +; CHECK: mov d3, v4[1] ; encoding: [0x83,0x04,0x18,0x5e] + +; CHECK: mov b3, v4[1] ; encoding: [0x83,0x04,0x03,0x5e] +; CHECK: mov h3, v4[1] ; encoding: [0x83,0x04,0x06,0x5e] +; CHECK: mov s3, v4[1] ; encoding: [0x83,0x04,0x0c,0x5e] +; CHECK: mov d3, v4[1] ; encoding: [0x83,0x04,0x18,0x5e] +; CHECK: mov b3, v4[1] ; encoding: [0x83,0x04,0x03,0x5e] +; CHECK: mov h3, v4[1] ; encoding: [0x83,0x04,0x06,0x5e] +; CHECK: mov s3, v4[1] ; encoding: [0x83,0x04,0x0c,0x5e] +; CHECK: mov d3, v4[1] ; encoding: [0x83,0x04,0x18,0x5e] + + smov.s x3, v2[2] + smov x3, v2.s[2] + umov.s w3, v2[2] + umov w3, v2.s[2] + umov.d x3, v2[1] + umov x3, v2.d[1] + +; CHECK: smov.s x3, v2[2] ; encoding: [0x43,0x2c,0x14,0x4e] +; CHECK: smov.s x3, v2[2] ; encoding: [0x43,0x2c,0x14,0x4e] +; CHECK: mov.s w3, v2[2] ; encoding: [0x43,0x3c,0x14,0x0e] +; CHECK: mov.s w3, v2[2] ; encoding: [0x43,0x3c,0x14,0x0e] +; CHECK: mov.d x3, v2[1] ; encoding: [0x43,0x3c,0x18,0x4e] +; CHECK: mov.d x3, v2[1] ; encoding: [0x43,0x3c,0x18,0x4e] + + ; MOV aliases for UMOV instructions above + + mov.s w2, v3[3] + mov w5, v7.s[2] + mov.d x11, v13[1] + mov x17, v19.d[0] + +; CHECK: mov.s w2, v3[3] ; encoding: [0x62,0x3c,0x1c,0x0e] +; CHECK: mov.s w5, v7[2] ; encoding: [0xe5,0x3c,0x14,0x0e] +; CHECK: mov.d x11, v13[1] ; encoding: [0xab,0x3d,0x18,0x4e] +; CHECK: mov.d x17, v19[0] ; encoding: [0x71,0x3e,0x08,0x4e] + + ins.d v2[1], x5 + ins.s v2[1], w5 + ins.h v2[1], w5 + ins.b v2[1], w5 + + ins v2.d[1], x5 + ins v2.s[1], w5 + ins v2.h[1], w5 + ins v2.b[1], w5 + +; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e] +; CHECK: ins.s v2[1], w5 ; encoding: [0xa2,0x1c,0x0c,0x4e] +; CHECK: ins.h v2[1], w5 ; encoding: [0xa2,0x1c,0x06,0x4e] +; CHECK: ins.b v2[1], w5 ; encoding: [0xa2,0x1c,0x03,0x4e] + +; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e] +; CHECK: ins.s v2[1], w5 ; encoding: [0xa2,0x1c,0x0c,0x4e] +; CHECK: ins.h v2[1], w5 ; encoding: [0xa2,0x1c,0x06,0x4e] +; CHECK: ins.b v2[1], w5 ; encoding: [0xa2,0x1c,0x03,0x4e] + + ins.d v2[1], v15[1] + ins.s v2[1], v15[1] + ins.h v2[1], v15[1] + ins.b v2[1], v15[1] + + ins v2.d[1], v15.d[0] + ins v2.s[3], v15.s[2] + ins v2.h[7], v15.h[3] + ins v2.b[10], v15.b[5] + +; CHECK: ins.d v2[1], v15[1] ; encoding: [0xe2,0x45,0x18,0x6e] +; CHECK: ins.s v2[1], v15[1] ; encoding: [0xe2,0x25,0x0c,0x6e] +; CHECK: ins.h v2[1], v15[1] ; encoding: [0xe2,0x15,0x06,0x6e] +; CHECK: ins.b v2[1], v15[1] ; encoding: [0xe2,0x0d,0x03,0x6e] + +; CHECK: ins.d v2[1], v15[0] ; encoding: [0xe2,0x05,0x18,0x6e] +; CHECK: ins.s v2[3], v15[2] ; encoding: [0xe2,0x45,0x1c,0x6e] +; CHECK: ins.h v2[7], v15[3] ; encoding: [0xe2,0x35,0x1e,0x6e] +; CHECK: ins.b v2[10], v15[5] ; encoding: [0xe2,0x2d,0x15,0x6e] + +; MOV aliases for the above INS instructions. + mov.d v2[1], x5 + mov.s v3[1], w6 + mov.h v4[1], w7 + mov.b v5[1], w8 + + mov v9.d[1], x2 + mov v8.s[1], w3 + mov v7.h[1], w4 + mov v6.b[1], w5 + + mov.d v1[1], v10[1] + mov.s v2[1], v11[1] + mov.h v7[1], v12[1] + mov.b v8[1], v15[1] + + mov v2.d[1], v15.d[0] + mov v7.s[3], v16.s[2] + mov v8.h[7], v17.h[3] + mov v9.b[10], v18.b[5] + +; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e] +; CHECK: ins.s v3[1], w6 ; encoding: [0xc3,0x1c,0x0c,0x4e] +; CHECK: ins.h v4[1], w7 ; encoding: [0xe4,0x1c,0x06,0x4e] +; CHECK: ins.b v5[1], w8 ; encoding: [0x05,0x1d,0x03,0x4e] +; CHECK: ins.d v9[1], x2 ; encoding: [0x49,0x1c,0x18,0x4e] +; CHECK: ins.s v8[1], w3 ; encoding: [0x68,0x1c,0x0c,0x4e] +; CHECK: ins.h v7[1], w4 ; encoding: [0x87,0x1c,0x06,0x4e] +; CHECK: ins.b v6[1], w5 ; encoding: [0xa6,0x1c,0x03,0x4e] +; CHECK: ins.d v1[1], v10[1] ; encoding: [0x41,0x45,0x18,0x6e] +; CHECK: ins.s v2[1], v11[1] ; encoding: [0x62,0x25,0x0c,0x6e] +; CHECK: ins.h v7[1], v12[1] ; encoding: [0x87,0x15,0x06,0x6e] +; CHECK: ins.b v8[1], v15[1] ; encoding: [0xe8,0x0d,0x03,0x6e] +; CHECK: ins.d v2[1], v15[0] ; encoding: [0xe2,0x05,0x18,0x6e] +; CHECK: ins.s v7[3], v16[2] ; encoding: [0x07,0x46,0x1c,0x6e] +; CHECK: ins.h v8[7], v17[3] ; encoding: [0x28,0x36,0x1e,0x6e] +; CHECK: ins.b v9[10], v18[5] ; encoding: [0x49,0x2e,0x15,0x6e] + + + and.8b v0, v0, v0 + and.16b v0, v0, v0 + +; CHECK: and.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x20,0x0e] +; CHECK: and.16b v0, v0, v0 ; encoding: [0x00,0x1c,0x20,0x4e] + + bic.8b v0, v0, v0 + +; CHECK: bic.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x60,0x0e] + + cmeq.8b v0, v0, v0 + cmge.8b v0, v0, v0 + cmgt.8b v0, v0, v0 + cmhi.8b v0, v0, v0 + cmhs.8b v0, v0, v0 + cmtst.8b v0, v0, v0 + fabd.2s v0, v0, v0 + facge.2s v0, v0, v0 + facgt.2s v0, v0, v0 + faddp.2s v0, v0, v0 + fadd.2s v0, v0, v0 + fcmeq.2s v0, v0, v0 + fcmge.2s v0, v0, v0 + fcmgt.2s v0, v0, v0 + fdiv.2s v0, v0, v0 + fmaxnmp.2s v0, v0, v0 + fmaxnm.2s v0, v0, v0 + fmaxp.2s v0, v0, v0 + fmax.2s v0, v0, v0 + fminnmp.2s v0, v0, v0 + fminnm.2s v0, v0, v0 + fminp.2s v0, v0, v0 + fmin.2s v0, v0, v0 + fmla.2s v0, v0, v0 + fmls.2s v0, v0, v0 + fmulx.2s v0, v0, v0 + fmul.2s v0, v0, v0 + fmulx d2, d3, d1 + fmulx s2, s3, s1 + frecps.2s v0, v0, v0 + frsqrts.2s v0, v0, v0 + fsub.2s v0, v0, v0 + mla.8b v0, v0, v0 + mls.8b v0, v0, v0 + mul.8b v0, v0, v0 + pmul.8b v0, v0, v0 + saba.8b v0, v0, v0 + sabd.8b v0, v0, v0 + shadd.8b v0, v0, v0 + shsub.8b v0, v0, v0 + smaxp.8b v0, v0, v0 + smax.8b v0, v0, v0 + sminp.8b v0, v0, v0 + smin.8b v0, v0, v0 + sqadd.8b v0, v0, v0 + sqdmulh.4h v0, v0, v0 + sqrdmulh.4h v0, v0, v0 + sqrshl.8b v0, v0, v0 + sqshl.8b v0, v0, v0 + sqsub.8b v0, v0, v0 + srhadd.8b v0, v0, v0 + srshl.8b v0, v0, v0 + sshl.8b v0, v0, v0 + sub.8b v0, v0, v0 + uaba.8b v0, v0, v0 + uabd.8b v0, v0, v0 + uhadd.8b v0, v0, v0 + uhsub.8b v0, v0, v0 + umaxp.8b v0, v0, v0 + umax.8b v0, v0, v0 + uminp.8b v0, v0, v0 + umin.8b v0, v0, v0 + uqadd.8b v0, v0, v0 + uqrshl.8b v0, v0, v0 + uqshl.8b v0, v0, v0 + uqsub.8b v0, v0, v0 + urhadd.8b v0, v0, v0 + urshl.8b v0, v0, v0 + ushl.8b v0, v0, v0 + +; CHECK: cmeq.8b v0, v0, v0 ; encoding: [0x00,0x8c,0x20,0x2e] +; CHECK: cmge.8b v0, v0, v0 ; encoding: [0x00,0x3c,0x20,0x0e] +; CHECK: cmgt.8b v0, v0, v0 ; encoding: [0x00,0x34,0x20,0x0e] +; CHECK: cmhi.8b v0, v0, v0 ; encoding: [0x00,0x34,0x20,0x2e] +; CHECK: cmhs.8b v0, v0, v0 ; encoding: [0x00,0x3c,0x20,0x2e] +; CHECK: cmtst.8b v0, v0, v0 ; encoding: [0x00,0x8c,0x20,0x0e] +; CHECK: fabd.2s v0, v0, v0 ; encoding: [0x00,0xd4,0xa0,0x2e] +; CHECK: facge.2s v0, v0, v0 ; encoding: [0x00,0xec,0x20,0x2e] +; CHECK: facgt.2s v0, v0, v0 ; encoding: [0x00,0xec,0xa0,0x2e] +; CHECK: faddp.2s v0, v0, v0 ; encoding: [0x00,0xd4,0x20,0x2e] +; CHECK: fadd.2s v0, v0, v0 ; encoding: [0x00,0xd4,0x20,0x0e] +; CHECK: fcmeq.2s v0, v0, v0 ; encoding: [0x00,0xe4,0x20,0x0e] +; CHECK: fcmge.2s v0, v0, v0 ; encoding: [0x00,0xe4,0x20,0x2e] +; CHECK: fcmgt.2s v0, v0, v0 ; encoding: [0x00,0xe4,0xa0,0x2e] +; CHECK: fdiv.2s v0, v0, v0 ; encoding: [0x00,0xfc,0x20,0x2e] +; CHECK: fmaxnmp.2s v0, v0, v0 ; encoding: [0x00,0xc4,0x20,0x2e] +; CHECK: fmaxnm.2s v0, v0, v0 ; encoding: [0x00,0xc4,0x20,0x0e] +; CHECK: fmaxp.2s v0, v0, v0 ; encoding: [0x00,0xf4,0x20,0x2e] +; CHECK: fmax.2s v0, v0, v0 ; encoding: [0x00,0xf4,0x20,0x0e] +; CHECK: fminnmp.2s v0, v0, v0 ; encoding: [0x00,0xc4,0xa0,0x2e] +; CHECK: fminnm.2s v0, v0, v0 ; encoding: [0x00,0xc4,0xa0,0x0e] +; CHECK: fminp.2s v0, v0, v0 ; encoding: [0x00,0xf4,0xa0,0x2e] +; CHECK: fmin.2s v0, v0, v0 ; encoding: [0x00,0xf4,0xa0,0x0e] +; CHECK: fmla.2s v0, v0, v0 ; encoding: [0x00,0xcc,0x20,0x0e] +; CHECK: fmls.2s v0, v0, v0 ; encoding: [0x00,0xcc,0xa0,0x0e] +; CHECK: fmulx.2s v0, v0, v0 ; encoding: [0x00,0xdc,0x20,0x0e] + +; CHECK: fmul.2s v0, v0, v0 ; encoding: [0x00,0xdc,0x20,0x2e] +; CHECK: fmulx d2, d3, d1 ; encoding: [0x62,0xdc,0x61,0x5e] +; CHECK: fmulx s2, s3, s1 ; encoding: [0x62,0xdc,0x21,0x5e] +; CHECK: frecps.2s v0, v0, v0 ; encoding: [0x00,0xfc,0x20,0x0e] +; CHECK: frsqrts.2s v0, v0, v0 ; encoding: [0x00,0xfc,0xa0,0x0e] +; CHECK: fsub.2s v0, v0, v0 ; encoding: [0x00,0xd4,0xa0,0x0e] +; CHECK: mla.8b v0, v0, v0 ; encoding: [0x00,0x94,0x20,0x0e] +; CHECK: mls.8b v0, v0, v0 ; encoding: [0x00,0x94,0x20,0x2e] +; CHECK: mul.8b v0, v0, v0 ; encoding: [0x00,0x9c,0x20,0x0e] +; CHECK: pmul.8b v0, v0, v0 ; encoding: [0x00,0x9c,0x20,0x2e] +; CHECK: saba.8b v0, v0, v0 ; encoding: [0x00,0x7c,0x20,0x0e] +; CHECK: sabd.8b v0, v0, v0 ; encoding: [0x00,0x74,0x20,0x0e] +; CHECK: shadd.8b v0, v0, v0 ; encoding: [0x00,0x04,0x20,0x0e] +; CHECK: shsub.8b v0, v0, v0 ; encoding: [0x00,0x24,0x20,0x0e] +; CHECK: smaxp.8b v0, v0, v0 ; encoding: [0x00,0xa4,0x20,0x0e] +; CHECK: smax.8b v0, v0, v0 ; encoding: [0x00,0x64,0x20,0x0e] +; CHECK: sminp.8b v0, v0, v0 ; encoding: [0x00,0xac,0x20,0x0e] +; CHECK: smin.8b v0, v0, v0 ; encoding: [0x00,0x6c,0x20,0x0e] +; CHECK: sqadd.8b v0, v0, v0 ; encoding: [0x00,0x0c,0x20,0x0e] +; CHECK: sqdmulh.4h v0, v0, v0 ; encoding: [0x00,0xb4,0x60,0x0e] +; CHECK: sqrdmulh.4h v0, v0, v0 ; encoding: [0x00,0xb4,0x60,0x2e] +; CHECK: sqrshl.8b v0, v0, v0 ; encoding: [0x00,0x5c,0x20,0x0e] +; CHECK: sqshl.8b v0, v0, v0 ; encoding: [0x00,0x4c,0x20,0x0e] +; CHECK: sqsub.8b v0, v0, v0 ; encoding: [0x00,0x2c,0x20,0x0e] +; CHECK: srhadd.8b v0, v0, v0 ; encoding: [0x00,0x14,0x20,0x0e] +; CHECK: srshl.8b v0, v0, v0 ; encoding: [0x00,0x54,0x20,0x0e] +; CHECK: sshl.8b v0, v0, v0 ; encoding: [0x00,0x44,0x20,0x0e] +; CHECK: sub.8b v0, v0, v0 ; encoding: [0x00,0x84,0x20,0x2e] +; CHECK: uaba.8b v0, v0, v0 ; encoding: [0x00,0x7c,0x20,0x2e] +; CHECK: uabd.8b v0, v0, v0 ; encoding: [0x00,0x74,0x20,0x2e] +; CHECK: uhadd.8b v0, v0, v0 ; encoding: [0x00,0x04,0x20,0x2e] +; CHECK: uhsub.8b v0, v0, v0 ; encoding: [0x00,0x24,0x20,0x2e] +; CHECK: umaxp.8b v0, v0, v0 ; encoding: [0x00,0xa4,0x20,0x2e] +; CHECK: umax.8b v0, v0, v0 ; encoding: [0x00,0x64,0x20,0x2e] +; CHECK: uminp.8b v0, v0, v0 ; encoding: [0x00,0xac,0x20,0x2e] +; CHECK: umin.8b v0, v0, v0 ; encoding: [0x00,0x6c,0x20,0x2e] +; CHECK: uqadd.8b v0, v0, v0 ; encoding: [0x00,0x0c,0x20,0x2e] +; CHECK: uqrshl.8b v0, v0, v0 ; encoding: [0x00,0x5c,0x20,0x2e] +; CHECK: uqshl.8b v0, v0, v0 ; encoding: [0x00,0x4c,0x20,0x2e] +; CHECK: uqsub.8b v0, v0, v0 ; encoding: [0x00,0x2c,0x20,0x2e] +; CHECK: urhadd.8b v0, v0, v0 ; encoding: [0x00,0x14,0x20,0x2e] +; CHECK: urshl.8b v0, v0, v0 ; encoding: [0x00,0x54,0x20,0x2e] +; CHECK: ushl.8b v0, v0, v0 ; encoding: [0x00,0x44,0x20,0x2e] + + bif.8b v0, v0, v0 + bit.8b v0, v0, v0 + bsl.8b v0, v0, v0 + eor.8b v0, v0, v0 + orn.8b v0, v0, v0 + orr.8b v0, v0, v1 + +; CHECK: bif.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xe0,0x2e] +; CHECK: bit.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xa0,0x2e] +; CHECK: bsl.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x60,0x2e] +; CHECK: eor.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x20,0x2e] +; CHECK: orn.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xe0,0x0e] +; CHECK: orr.8b v0, v0, v1 ; encoding: [0x00,0x1c,0xa1,0x0e] + + sadalp.4h v0, v0 + sadalp.8h v0, v0 + sadalp.2s v0, v0 + sadalp.4s v0, v0 + sadalp.1d v0, v0 + sadalp.2d v0, v0 + +; CHECK: sadalp.4h v0, v0 ; encoding: [0x00,0x68,0x20,0x0e] +; CHECK: sadalp.8h v0, v0 ; encoding: [0x00,0x68,0x20,0x4e] +; CHECK: sadalp.2s v0, v0 ; encoding: [0x00,0x68,0x60,0x0e] +; CHECK: sadalp.4s v0, v0 ; encoding: [0x00,0x68,0x60,0x4e] +; CHECK: sadalp.1d v0, v0 ; encoding: [0x00,0x68,0xa0,0x0e] +; CHECK: sadalp.2d v0, v0 ; encoding: [0x00,0x68,0xa0,0x4e] + + cls.8b v0, v0 + clz.8b v0, v0 + cnt.8b v0, v0 + fabs.2s v0, v0 + fneg.2s v0, v0 + frecpe.2s v0, v0 + frinta.2s v0, v0 + frintx.2s v0, v0 + frinti.2s v0, v0 + frintm.2s v0, v0 + frintn.2s v0, v0 + frintp.2s v0, v0 + frintz.2s v0, v0 + frsqrte.2s v0, v0 + fsqrt.2s v0, v0 + neg.8b v0, v0 + not.8b v0, v0 + rbit.8b v0, v0 + rev16.8b v0, v0 + rev32.8b v0, v0 + rev64.8b v0, v0 + sadalp.4h v0, v0 + saddlp.4h v0, v0 + scvtf.2s v0, v0 + sqabs.8b v0, v0 + sqneg.8b v0, v0 + sqxtn.8b v0, v0 + sqxtun.8b v0, v0 + suqadd.8b v0, v0 + uadalp.4h v0, v0 + uaddlp.4h v0, v0 + ucvtf.2s v0, v0 + uqxtn.8b v0, v0 + urecpe.2s v0, v0 + ursqrte.2s v0, v0 + usqadd.8b v0, v0 + xtn.8b v0, v0 + shll.8h v1, v2, #8 + shll.4s v3, v4, #16 + shll.2d v5, v6, #32 + shll2.8h v7, v8, #8 + shll2.4s v9, v10, #16 + shll2.2d v11, v12, #32 + shll v1.8h, v2.8b, #8 + shll v1.4s, v2.4h, #16 + shll v1.2d, v2.2s, #32 + shll2 v1.8h, v2.16b, #8 + shll2 v1.4s, v2.8h, #16 + shll2 v1.2d, v2.4s, #32 + +; CHECK: cls.8b v0, v0 ; encoding: [0x00,0x48,0x20,0x0e] +; CHECK: clz.8b v0, v0 ; encoding: [0x00,0x48,0x20,0x2e] +; CHECK: cnt.8b v0, v0 ; encoding: [0x00,0x58,0x20,0x0e] +; CHECK: fabs.2s v0, v0 ; encoding: [0x00,0xf8,0xa0,0x0e] +; CHECK: fneg.2s v0, v0 ; encoding: [0x00,0xf8,0xa0,0x2e] +; CHECK: frecpe.2s v0, v0 ; encoding: [0x00,0xd8,0xa1,0x0e] +; CHECK: frinta.2s v0, v0 ; encoding: [0x00,0x88,0x21,0x2e] +; CHECK: frintx.2s v0, v0 ; encoding: [0x00,0x98,0x21,0x2e] +; CHECK: frinti.2s v0, v0 ; encoding: [0x00,0x98,0xa1,0x2e] +; CHECK: frintm.2s v0, v0 ; encoding: [0x00,0x98,0x21,0x0e] +; CHECK: frintn.2s v0, v0 ; encoding: [0x00,0x88,0x21,0x0e] +; CHECK: frintp.2s v0, v0 ; encoding: [0x00,0x88,0xa1,0x0e] +; CHECK: frintz.2s v0, v0 ; encoding: [0x00,0x98,0xa1,0x0e] +; CHECK: frsqrte.2s v0, v0 ; encoding: [0x00,0xd8,0xa1,0x2e] +; CHECK: fsqrt.2s v0, v0 ; encoding: [0x00,0xf8,0xa1,0x2e] +; CHECK: neg.8b v0, v0 ; encoding: [0x00,0xb8,0x20,0x2e] +; CHECK: mvn.8b v0, v0 ; encoding: [0x00,0x58,0x20,0x2e] +; CHECK: rbit.8b v0, v0 ; encoding: [0x00,0x58,0x60,0x2e] +; CHECK: rev16.8b v0, v0 ; encoding: [0x00,0x18,0x20,0x0e] +; CHECK: rev32.8b v0, v0 ; encoding: [0x00,0x08,0x20,0x2e] +; CHECK: rev64.8b v0, v0 ; encoding: [0x00,0x08,0x20,0x0e] +; CHECK: sadalp.4h v0, v0 ; encoding: [0x00,0x68,0x20,0x0e] +; CHECK: saddlp.4h v0, v0 ; encoding: [0x00,0x28,0x20,0x0e] +; CHECK: scvtf.2s v0, v0 ; encoding: [0x00,0xd8,0x21,0x0e] +; CHECK: sqabs.8b v0, v0 ; encoding: [0x00,0x78,0x20,0x0e] +; CHECK: sqneg.8b v0, v0 ; encoding: [0x00,0x78,0x20,0x2e] +; CHECK: sqxtn.8b v0, v0 ; encoding: [0x00,0x48,0x21,0x0e] +; CHECK: sqxtun.8b v0, v0 ; encoding: [0x00,0x28,0x21,0x2e] +; CHECK: suqadd.8b v0, v0 ; encoding: [0x00,0x38,0x20,0x0e] +; CHECK: uadalp.4h v0, v0 ; encoding: [0x00,0x68,0x20,0x2e] +; CHECK: uaddlp.4h v0, v0 ; encoding: [0x00,0x28,0x20,0x2e] +; CHECK: ucvtf.2s v0, v0 ; encoding: [0x00,0xd8,0x21,0x2e] +; CHECK: uqxtn.8b v0, v0 ; encoding: [0x00,0x48,0x21,0x2e] +; CHECK: urecpe.2s v0, v0 ; encoding: [0x00,0xc8,0xa1,0x0e] +; CHECK: ursqrte.2s v0, v0 ; encoding: [0x00,0xc8,0xa1,0x2e] +; CHECK: usqadd.8b v0, v0 ; encoding: [0x00,0x38,0x20,0x2e] +; CHECK: xtn.8b v0, v0 ; encoding: [0x00,0x28,0x21,0x0e] +; CHECK: shll.8h v1, v2, #8 ; encoding: [0x41,0x38,0x21,0x2e] +; CHECK: shll.4s v3, v4, #16 ; encoding: [0x83,0x38,0x61,0x2e] +; CHECK: shll.2d v5, v6, #32 ; encoding: [0xc5,0x38,0xa1,0x2e] +; CHECK: shll2.8h v7, v8, #8 ; encoding: [0x07,0x39,0x21,0x6e] +; CHECK: shll2.4s v9, v10, #16 ; encoding: [0x49,0x39,0x61,0x6e] +; CHECK: shll2.2d v11, v12, #32 ; encoding: [0x8b,0x39,0xa1,0x6e] +; CHECK: shll.8h v1, v2, #8 ; encoding: [0x41,0x38,0x21,0x2e] +; CHECK: shll.4s v1, v2, #16 ; encoding: [0x41,0x38,0x61,0x2e] +; CHECK: shll.2d v1, v2, #32 ; encoding: [0x41,0x38,0xa1,0x2e] +; CHECK: shll2.8h v1, v2, #8 ; encoding: [0x41,0x38,0x21,0x6e] +; CHECK: shll2.4s v1, v2, #16 ; encoding: [0x41,0x38,0x61,0x6e] +; CHECK: shll2.2d v1, v2, #32 ; encoding: [0x41,0x38,0xa1,0x6e] + + + cmeq.8b v0, v0, #0 + cmeq.16b v0, v0, #0 + cmeq.4h v0, v0, #0 + cmeq.8h v0, v0, #0 + cmeq.2s v0, v0, #0 + cmeq.4s v0, v0, #0 + cmeq.2d v0, v0, #0 + +; CHECK: cmeq.8b v0, v0, #0 ; encoding: [0x00,0x98,0x20,0x0e] +; CHECK: cmeq.16b v0, v0, #0 ; encoding: [0x00,0x98,0x20,0x4e] +; CHECK: cmeq.4h v0, v0, #0 ; encoding: [0x00,0x98,0x60,0x0e] +; CHECK: cmeq.8h v0, v0, #0 ; encoding: [0x00,0x98,0x60,0x4e] +; CHECK: cmeq.2s v0, v0, #0 ; encoding: [0x00,0x98,0xa0,0x0e] +; CHECK: cmeq.4s v0, v0, #0 ; encoding: [0x00,0x98,0xa0,0x4e] +; CHECK: cmeq.2d v0, v0, #0 ; encoding: [0x00,0x98,0xe0,0x4e] + + cmge.8b v0, v0, #0 + cmgt.8b v0, v0, #0 + cmle.8b v0, v0, #0 + cmlt.8b v0, v0, #0 + fcmeq.2s v0, v0, #0 + fcmge.2s v0, v0, #0 + fcmgt.2s v0, v0, #0 + fcmle.2s v0, v0, #0 + fcmlt.2s v0, v0, #0 + +; ARM verbose mode aliases + cmlt v8.8b, v14.8b, #0 + cmlt v8.16b, v14.16b, #0 + cmlt v8.4h, v14.4h, #0 + cmlt v8.8h, v14.8h, #0 + cmlt v8.2s, v14.2s, #0 + cmlt v8.4s, v14.4s, #0 + cmlt v8.2d, v14.2d, #0 + +; CHECK: cmge.8b v0, v0, #0 ; encoding: [0x00,0x88,0x20,0x2e] +; CHECK: cmgt.8b v0, v0, #0 ; encoding: [0x00,0x88,0x20,0x0e] +; CHECK: cmle.8b v0, v0, #0 ; encoding: [0x00,0x98,0x20,0x2e] +; CHECK: cmlt.8b v0, v0, #0 ; encoding: [0x00,0xa8,0x20,0x0e] +; CHECK: fcmeq.2s v0, v0, #0.0 ; encoding: [0x00,0xd8,0xa0,0x0e] +; CHECK: fcmge.2s v0, v0, #0.0 ; encoding: [0x00,0xc8,0xa0,0x2e] +; CHECK: fcmgt.2s v0, v0, #0.0 ; encoding: [0x00,0xc8,0xa0,0x0e] +; CHECK: fcmle.2s v0, v0, #0.0 ; encoding: [0x00,0xd8,0xa0,0x2e] +; CHECK: fcmlt.2s v0, v0, #0.0 ; encoding: [0x00,0xe8,0xa0,0x0e] +; CHECK: cmlt.8b v8, v14, #0 ; encoding: [0xc8,0xa9,0x20,0x0e] +; CHECK: cmlt.16b v8, v14, #0 ; encoding: [0xc8,0xa9,0x20,0x4e] +; CHECK: cmlt.4h v8, v14, #0 ; encoding: [0xc8,0xa9,0x60,0x0e] +; CHECK: cmlt.8h v8, v14, #0 ; encoding: [0xc8,0xa9,0x60,0x4e] +; CHECK: cmlt.2s v8, v14, #0 ; encoding: [0xc8,0xa9,0xa0,0x0e] +; CHECK: cmlt.4s v8, v14, #0 ; encoding: [0xc8,0xa9,0xa0,0x4e] +; CHECK: cmlt.2d v8, v14, #0 ; encoding: [0xc8,0xa9,0xe0,0x4e] + + +;===-------------------------------------------------------------------------=== +; AdvSIMD Floating-point <-> Integer Conversions +;===-------------------------------------------------------------------------=== + + fcvtas.2s v0, v0 + fcvtas.4s v0, v0 + fcvtas.2d v0, v0 + fcvtas s0, s0 + fcvtas d0, d0 + +; CHECK: fcvtas.2s v0, v0 ; encoding: [0x00,0xc8,0x21,0x0e] +; CHECK: fcvtas.4s v0, v0 ; encoding: [0x00,0xc8,0x21,0x4e] +; CHECK: fcvtas.2d v0, v0 ; encoding: [0x00,0xc8,0x61,0x4e] +; CHECK: fcvtas s0, s0 ; encoding: [0x00,0xc8,0x21,0x5e] +; CHECK: fcvtas d0, d0 ; encoding: [0x00,0xc8,0x61,0x5e] + + fcvtau.2s v0, v0 + fcvtau.4s v0, v0 + fcvtau.2d v0, v0 + fcvtau s0, s0 + fcvtau d0, d0 + +; CHECK: fcvtau.2s v0, v0 ; encoding: [0x00,0xc8,0x21,0x2e] +; CHECK: fcvtau.4s v0, v0 ; encoding: [0x00,0xc8,0x21,0x6e] +; CHECK: fcvtau.2d v0, v0 ; encoding: [0x00,0xc8,0x61,0x6e] +; CHECK: fcvtau s0, s0 ; encoding: [0x00,0xc8,0x21,0x7e] +; CHECK: fcvtau d0, d0 ; encoding: [0x00,0xc8,0x61,0x7e] + + fcvtl v1.4s, v5.4h + fcvtl v2.2d, v6.2s + fcvtl2 v3.4s, v7.8h + fcvtl2 v4.2d, v8.4s + +; CHECK: fcvtl v1.4s, v5.4h ; encoding: [0xa1,0x78,0x21,0x0e] +; CHECK: fcvtl v2.2d, v6.2s ; encoding: [0xc2,0x78,0x61,0x0e] +; CHECK: fcvtl2 v3.4s, v7.8h ; encoding: [0xe3,0x78,0x21,0x4e] +; CHECK: fcvtl2 v4.2d, v8.4s ; encoding: [0x04,0x79,0x61,0x4e] + + fcvtms.2s v0, v0 + fcvtms.4s v0, v0 + fcvtms.2d v0, v0 + fcvtms s0, s0 + fcvtms d0, d0 + +; CHECK: fcvtms.2s v0, v0 ; encoding: [0x00,0xb8,0x21,0x0e] +; CHECK: fcvtms.4s v0, v0 ; encoding: [0x00,0xb8,0x21,0x4e] +; CHECK: fcvtms.2d v0, v0 ; encoding: [0x00,0xb8,0x61,0x4e] +; CHECK: fcvtms s0, s0 ; encoding: [0x00,0xb8,0x21,0x5e] +; CHECK: fcvtms d0, d0 ; encoding: [0x00,0xb8,0x61,0x5e] + + fcvtmu.2s v0, v0 + fcvtmu.4s v0, v0 + fcvtmu.2d v0, v0 + fcvtmu s0, s0 + fcvtmu d0, d0 + +; CHECK: fcvtmu.2s v0, v0 ; encoding: [0x00,0xb8,0x21,0x2e] +; CHECK: fcvtmu.4s v0, v0 ; encoding: [0x00,0xb8,0x21,0x6e] +; CHECK: fcvtmu.2d v0, v0 ; encoding: [0x00,0xb8,0x61,0x6e] +; CHECK: fcvtmu s0, s0 ; encoding: [0x00,0xb8,0x21,0x7e] +; CHECK: fcvtmu d0, d0 ; encoding: [0x00,0xb8,0x61,0x7e] + + fcvtns.2s v0, v0 + fcvtns.4s v0, v0 + fcvtns.2d v0, v0 + fcvtns s0, s0 + fcvtns d0, d0 + +; CHECK: fcvtns.2s v0, v0 ; encoding: [0x00,0xa8,0x21,0x0e] +; CHECK: fcvtns.4s v0, v0 ; encoding: [0x00,0xa8,0x21,0x4e] +; CHECK: fcvtns.2d v0, v0 ; encoding: [0x00,0xa8,0x61,0x4e] +; CHECK: fcvtns s0, s0 ; encoding: [0x00,0xa8,0x21,0x5e] +; CHECK: fcvtns d0, d0 ; encoding: [0x00,0xa8,0x61,0x5e] + + fcvtnu.2s v0, v0 + fcvtnu.4s v0, v0 + fcvtnu.2d v0, v0 + fcvtnu s0, s0 + fcvtnu d0, d0 + +; CHECK: fcvtnu.2s v0, v0 ; encoding: [0x00,0xa8,0x21,0x2e] +; CHECK: fcvtnu.4s v0, v0 ; encoding: [0x00,0xa8,0x21,0x6e] +; CHECK: fcvtnu.2d v0, v0 ; encoding: [0x00,0xa8,0x61,0x6e] +; CHECK: fcvtnu s0, s0 ; encoding: [0x00,0xa8,0x21,0x7e] +; CHECK: fcvtnu d0, d0 ; encoding: [0x00,0xa8,0x61,0x7e] + + fcvtn v2.4h, v4.4s + fcvtn v3.2s, v5.2d + fcvtn2 v4.8h, v6.4s + fcvtn2 v5.4s, v7.2d + fcvtxn v6.2s, v9.2d + fcvtxn2 v7.4s, v8.2d + +; CHECK: fcvtn v2.4h, v4.4s ; encoding: [0x82,0x68,0x21,0x0e] +; CHECK: fcvtn v3.2s, v5.2d ; encoding: [0xa3,0x68,0x61,0x0e] +; CHECK: fcvtn2 v4.8h, v6.4s ; encoding: [0xc4,0x68,0x21,0x4e] +; CHECK: fcvtn2 v5.4s, v7.2d ; encoding: [0xe5,0x68,0x61,0x4e] +; CHECK: fcvtxn v6.2s, v9.2d ; encoding: [0x26,0x69,0x61,0x2e] +; CHECK: fcvtxn2 v7.4s, v8.2d ; encoding: [0x07,0x69,0x61,0x6e] + + fcvtps.2s v0, v0 + fcvtps.4s v0, v0 + fcvtps.2d v0, v0 + fcvtps s0, s0 + fcvtps d0, d0 + +; CHECK: fcvtps.2s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x0e] +; CHECK: fcvtps.4s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x4e] +; CHECK: fcvtps.2d v0, v0 ; encoding: [0x00,0xa8,0xe1,0x4e] +; CHECK: fcvtps s0, s0 ; encoding: [0x00,0xa8,0xa1,0x5e] +; CHECK: fcvtps d0, d0 ; encoding: [0x00,0xa8,0xe1,0x5e] + + fcvtpu.2s v0, v0 + fcvtpu.4s v0, v0 + fcvtpu.2d v0, v0 + fcvtpu s0, s0 + fcvtpu d0, d0 + +; CHECK: fcvtpu.2s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x2e] +; CHECK: fcvtpu.4s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x6e] +; CHECK: fcvtpu.2d v0, v0 ; encoding: [0x00,0xa8,0xe1,0x6e] +; CHECK: fcvtpu s0, s0 ; encoding: [0x00,0xa8,0xa1,0x7e] +; CHECK: fcvtpu d0, d0 ; encoding: [0x00,0xa8,0xe1,0x7e] + + fcvtzs.2s v0, v0 + fcvtzs.4s v0, v0 + fcvtzs.2d v0, v0 + fcvtzs s0, s0 + fcvtzs d0, d0 + +; CHECK: fcvtzs.2s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x0e] +; CHECK: fcvtzs.4s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x4e] +; CHECK: fcvtzs.2d v0, v0 ; encoding: [0x00,0xb8,0xe1,0x4e] +; CHECK: fcvtzs s0, s0 ; encoding: [0x00,0xb8,0xa1,0x5e] +; CHECK: fcvtzs d0, d0 ; encoding: [0x00,0xb8,0xe1,0x5e] + + fcvtzu.2s v0, v0 + fcvtzu.4s v0, v0 + fcvtzu.2d v0, v0 + fcvtzu s0, s0 + fcvtzu d0, d0 + +; CHECK: fcvtzu.2s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x2e] +; CHECK: fcvtzu.4s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x6e] +; CHECK: fcvtzu.2d v0, v0 ; encoding: [0x00,0xb8,0xe1,0x6e] +; CHECK: fcvtzu s0, s0 ; encoding: [0x00,0xb8,0xa1,0x7e] +; CHECK: fcvtzu d0, d0 ; encoding: [0x00,0xb8,0xe1,0x7e] + +;===-------------------------------------------------------------------------=== +; AdvSIMD modified immediate instructions +;===-------------------------------------------------------------------------=== + + bic.2s v0, #1 + bic.2s v0, #1, lsl #0 + bic.2s v0, #1, lsl #8 + bic.2s v0, #1, lsl #16 + bic.2s v0, #1, lsl #24 + +; CHECK: bic.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x2f] +; CHECK: bic.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x2f] +; CHECK: bic.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x2f] +; CHECK: bic.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x2f] +; CHECK: bic.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x2f] + + bic.4h v0, #1 + bic.4h v0, #1, lsl #0 + bic.4h v0, #1, lsl #8 + +; CHECK: bic.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x2f] +; CHECK: bic.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x2f] +; CHECK: bic.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x2f] + + bic.4s v0, #1 + bic.4s v0, #1, lsl #0 + bic.4s v0, #1, lsl #8 + bic.4s v0, #1, lsl #16 + bic.4s v0, #1, lsl #24 + +; CHECK: bic.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x6f] +; CHECK: bic.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x6f] +; CHECK: bic.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x6f] +; CHECK: bic.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x6f] +; CHECK: bic.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x6f] + + bic.8h v0, #1 + bic.8h v0, #1, lsl #0 + bic.8h v0, #1, lsl #8 + +; CHECK: bic.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x6f] +; CHECK: bic.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x6f] +; CHECK: bic.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x6f] + + fmov.2d v0, #1.250000e-01 + +; CHECK: fmov.2d v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x6f] + + fmov.2s v0, #1.250000e-01 + fmov.4s v0, #1.250000e-01 + +; CHECK: fmov.2s v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x0f] +; CHECK: fmov.4s v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x4f] + + orr.2s v0, #1 + orr.2s v0, #1, lsl #0 + orr.2s v0, #1, lsl #8 + orr.2s v0, #1, lsl #16 + orr.2s v0, #1, lsl #24 + +; CHECK: orr.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x0f] +; CHECK: orr.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x0f] +; CHECK: orr.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x0f] +; CHECK: orr.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x0f] +; CHECK: orr.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x0f] + + orr.4h v0, #1 + orr.4h v0, #1, lsl #0 + orr.4h v0, #1, lsl #8 + +; CHECK: orr.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x0f] +; CHECK: orr.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x0f] +; CHECK: orr.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x0f] + + orr.4s v0, #1 + orr.4s v0, #1, lsl #0 + orr.4s v0, #1, lsl #8 + orr.4s v0, #1, lsl #16 + orr.4s v0, #1, lsl #24 + +; CHECK: orr.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x4f] +; CHECK: orr.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x4f] +; CHECK: orr.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x4f] +; CHECK: orr.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x4f] +; CHECK: orr.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x4f] + + orr.8h v0, #1 + orr.8h v0, #1, lsl #0 + orr.8h v0, #1, lsl #8 + +; CHECK: orr.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x4f] +; CHECK: orr.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x4f] +; CHECK: orr.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x4f] + + movi d0, #0x000000000000ff + movi.2d v0, #0x000000000000ff + +; CHECK: movi d0, #0x000000000000ff ; encoding: [0x20,0xe4,0x00,0x2f] +; CHECK: movi.2d v0, #0x000000000000ff ; encoding: [0x20,0xe4,0x00,0x6f] + + movi.2s v0, #1 + movi.2s v0, #1, lsl #0 + movi.2s v0, #1, lsl #8 + movi.2s v0, #1, lsl #16 + movi.2s v0, #1, lsl #24 + +; CHECK: movi.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x0f] +; CHECK: movi.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x0f] +; CHECK: movi.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x0f] +; CHECK: movi.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x0f] +; CHECK: movi.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x0f] + + movi.4s v0, #1 + movi.4s v0, #1, lsl #0 + movi.4s v0, #1, lsl #8 + movi.4s v0, #1, lsl #16 + movi.4s v0, #1, lsl #24 + +; CHECK: movi.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x4f] +; CHECK: movi.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x4f] +; CHECK: movi.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x4f] +; CHECK: movi.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x4f] +; CHECK: movi.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x4f] + + movi.4h v0, #1 + movi.4h v0, #1, lsl #0 + movi.4h v0, #1, lsl #8 + +; CHECK: movi.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x0f] +; CHECK: movi.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x0f] +; CHECK: movi.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x0f] + + movi.8h v0, #1 + movi.8h v0, #1, lsl #0 + movi.8h v0, #1, lsl #8 + +; CHECK: movi.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x4f] +; CHECK: movi.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x4f] +; CHECK: movi.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x4f] + + movi.2s v0, #1, msl #8 + movi.2s v0, #1, msl #16 + movi.4s v0, #1, msl #8 + movi.4s v0, #1, msl #16 + +; CHECK: movi.2s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x0f] +; CHECK: movi.2s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x0f] +; CHECK: movi.4s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x4f] +; CHECK: movi.4s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x4f] + + movi.8b v0, #1 + movi.16b v0, #1 + +; CHECK: movi.8b v0, #0x1 ; encoding: [0x20,0xe4,0x00,0x0f] +; CHECK: movi.16b v0, #0x1 ; encoding: [0x20,0xe4,0x00,0x4f] + + mvni.2s v0, #1 + mvni.2s v0, #1, lsl #0 + mvni.2s v0, #1, lsl #8 + mvni.2s v0, #1, lsl #16 + mvni.2s v0, #1, lsl #24 + +; CHECK: mvni.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x2f] + + mvni.4s v0, #1 + mvni.4s v0, #1, lsl #0 + mvni.4s v0, #1, lsl #8 + mvni.4s v0, #1, lsl #16 + mvni.4s v0, #1, lsl #24 + +; CHECK: mvni.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x6f] + + mvni.4h v0, #1 + mvni.4h v0, #1, lsl #0 + mvni.4h v0, #1, lsl #8 + +; CHECK: mvni.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x2f] +; CHECK: mvni.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x2f] +; CHECK: mvni.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x2f] + + mvni.8h v0, #1 + mvni.8h v0, #1, lsl #0 + mvni.8h v0, #1, lsl #8 + +; CHECK: mvni.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x6f] +; CHECK: mvni.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x6f] +; CHECK: mvni.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x6f] + + mvni.2s v0, #1, msl #8 + mvni.2s v0, #1, msl #16 + mvni.4s v0, #1, msl #8 + mvni.4s v0, #1, msl #16 + +; CHECK: mvni.2s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x2f] +; CHECK: mvni.4s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x6f] + +;===-------------------------------------------------------------------------=== +; AdvSIMD scalar x index +;===-------------------------------------------------------------------------=== + + fmla.s s0, s0, v0[3] + fmla.d d0, d0, v0[1] + fmls.s s0, s0, v0[3] + fmls.d d0, d0, v0[1] + fmulx.s s0, s0, v0[3] + fmulx.d d0, d0, v0[1] + fmul.s s0, s0, v0[3] + fmul.d d0, d0, v0[1] + sqdmlal.h s0, h0, v0[7] + sqdmlal.s d0, s0, v0[3] + sqdmlsl.h s0, h0, v0[7] + sqdmulh.h h0, h0, v0[7] + sqdmulh.s s0, s0, v0[3] + sqdmull.h s0, h0, v0[7] + sqdmull.s d0, s0, v0[3] + sqrdmulh.h h0, h0, v0[7] + sqrdmulh.s s0, s0, v0[3] + +; CHECK: fmla.s s0, s0, v0[3] ; encoding: [0x00,0x18,0xa0,0x5f] +; CHECK: fmla.d d0, d0, v0[1] ; encoding: [0x00,0x18,0xc0,0x5f] +; CHECK: fmls.s s0, s0, v0[3] ; encoding: [0x00,0x58,0xa0,0x5f] +; CHECK: fmls.d d0, d0, v0[1] ; encoding: [0x00,0x58,0xc0,0x5f] +; CHECK: fmulx.s s0, s0, v0[3] ; encoding: [0x00,0x98,0xa0,0x7f] +; CHECK: fmulx.d d0, d0, v0[1] ; encoding: [0x00,0x98,0xc0,0x7f] +; CHECK: fmul.s s0, s0, v0[3] ; encoding: [0x00,0x98,0xa0,0x5f] +; CHECK: fmul.d d0, d0, v0[1] ; encoding: [0x00,0x98,0xc0,0x5f] +; CHECK: sqdmlal.h s0, h0, v0[7] ; encoding: [0x00,0x38,0x70,0x5f] +; CHECK: sqdmlal.s d0, s0, v0[3] ; encoding: [0x00,0x38,0xa0,0x5f] +; CHECK: sqdmlsl.h s0, h0, v0[7] ; encoding: [0x00,0x78,0x70,0x5f] +; CHECK: sqdmulh.h h0, h0, v0[7] ; encoding: [0x00,0xc8,0x70,0x5f] +; CHECK: sqdmulh.s s0, s0, v0[3] ; encoding: [0x00,0xc8,0xa0,0x5f] +; CHECK: sqdmull.h s0, h0, v0[7] ; encoding: [0x00,0xb8,0x70,0x5f] +; CHECK: sqdmull.s d0, s0, v0[3] ; encoding: [0x00,0xb8,0xa0,0x5f] +; CHECK: sqrdmulh.h h0, h0, v0[7] ; encoding: [0x00,0xd8,0x70,0x5f] +; CHECK: sqrdmulh.s s0, s0, v0[3] ; encoding: [0x00,0xd8,0xa0,0x5f] + +;===-------------------------------------------------------------------------=== +; AdvSIMD SMLAL +;===-------------------------------------------------------------------------=== + smlal.8h v1, v2, v3 + smlal.4s v1, v2, v3 + smlal.2d v1, v2, v3 + smlal2.8h v1, v2, v3 + smlal2.4s v1, v2, v3 + smlal2.2d v1, v2, v3 + + smlal v13.8h, v8.8b, v0.8b + smlal v13.4s, v8.4h, v0.4h + smlal v13.2d, v8.2s, v0.2s + smlal2 v13.8h, v8.16b, v0.16b + smlal2 v13.4s, v8.8h, v0.8h + smlal2 v13.2d, v8.4s, v0.4s + +; CHECK: smlal.8h v1, v2, v3 ; encoding: [0x41,0x80,0x23,0x0e] +; CHECK: smlal.4s v1, v2, v3 ; encoding: [0x41,0x80,0x63,0x0e] +; CHECK: smlal.2d v1, v2, v3 ; encoding: [0x41,0x80,0xa3,0x0e] +; CHECK: smlal2.8h v1, v2, v3 ; encoding: [0x41,0x80,0x23,0x4e] +; CHECK: smlal2.4s v1, v2, v3 ; encoding: [0x41,0x80,0x63,0x4e] +; CHECK: smlal2.2d v1, v2, v3 ; encoding: [0x41,0x80,0xa3,0x4e] +; CHECK: smlal.8h v13, v8, v0 ; encoding: [0x0d,0x81,0x20,0x0e] +; CHECK: smlal.4s v13, v8, v0 ; encoding: [0x0d,0x81,0x60,0x0e] +; CHECK: smlal.2d v13, v8, v0 ; encoding: [0x0d,0x81,0xa0,0x0e] +; CHECK: smlal2.8h v13, v8, v0 ; encoding: [0x0d,0x81,0x20,0x4e] +; CHECK: smlal2.4s v13, v8, v0 ; encoding: [0x0d,0x81,0x60,0x4e] +; CHECK: smlal2.2d v13, v8, v0 ; encoding: [0x0d,0x81,0xa0,0x4e] + + +;===-------------------------------------------------------------------------=== +; AdvSIMD scalar x index +;===-------------------------------------------------------------------------=== + + fmla.2s v0, v0, v0[0] + fmla.4s v0, v0, v0[1] + fmla.2d v0, v0, v0[1] + fmls.2s v0, v0, v0[0] + fmls.4s v0, v0, v0[1] + fmls.2d v0, v0, v0[1] + fmulx.2s v0, v0, v0[0] + fmulx.4s v0, v0, v0[1] + fmulx.2d v0, v0, v0[1] + fmul.2s v0, v0, v0[0] + fmul.4s v0, v0, v0[1] + fmul.2d v0, v0, v0[1] + mla.4h v0, v0, v0[0] + mla.8h v0, v0, v0[1] + mla.2s v0, v0, v0[2] + mla.4s v0, v0, v0[3] + mls.4h v0, v0, v0[0] + mls.8h v0, v0, v0[1] + mls.2s v0, v0, v0[2] + mls.4s v0, v0, v0[3] + mul.4h v0, v0, v0[0] + mul.8h v0, v0, v0[1] + mul.2s v0, v0, v0[2] + mul.4s v0, v0, v0[3] + smlal.4s v0, v0, v0[0] + smlal2.4s v0, v0, v0[1] + smlal.2d v0, v0, v0[2] + smlal2.2d v0, v0, v0[3] + smlsl.4s v0, v0, v0[0] + smlsl2.4s v0, v0, v0[1] + smlsl.2d v0, v0, v0[2] + smlsl2.2d v0, v0, v0[3] + smull.4s v0, v0, v0[0] + smull2.4s v0, v0, v0[1] + smull.2d v0, v0, v0[2] + smull2.2d v0, v0, v0[3] + sqdmlal.4s v0, v0, v0[0] + sqdmlal2.4s v0, v0, v0[1] + sqdmlal.2d v0, v0, v0[2] + sqdmlal2.2d v0, v0, v0[3] + sqdmlsl.4s v0, v0, v0[0] + sqdmlsl2.4s v0, v0, v0[1] + sqdmlsl.2d v0, v0, v0[2] + sqdmlsl2.2d v0, v0, v0[3] + sqdmulh.4h v0, v0, v0[0] + sqdmulh.8h v0, v0, v0[1] + sqdmulh.2s v0, v0, v0[2] + sqdmulh.4s v0, v0, v0[3] + sqdmull.4s v0, v0, v0[0] + sqdmull2.4s v0, v0, v0[1] + sqdmull.2d v0, v0, v0[2] + sqdmull2.2d v0, v0, v0[3] + sqrdmulh.4h v0, v0, v0[0] + sqrdmulh.8h v0, v0, v0[1] + sqrdmulh.2s v0, v0, v0[2] + sqrdmulh.4s v0, v0, v0[3] + umlal.4s v0, v0, v0[0] + umlal2.4s v0, v0, v0[1] + umlal.2d v0, v0, v0[2] + umlal2.2d v0, v0, v0[3] + umlsl.4s v0, v0, v0[0] + umlsl2.4s v0, v0, v0[1] + umlsl.2d v0, v0, v0[2] + umlsl2.2d v0, v0, v0[3] + umull.4s v0, v0, v0[0] + umull2.4s v0, v0, v0[1] + umull.2d v0, v0, v0[2] + umull2.2d v0, v0, v0[3] + +; CHECK: fmla.2s v0, v0, v0[0] ; encoding: [0x00,0x10,0x80,0x0f] +; CHECK: fmla.4s v0, v0, v0[1] ; encoding: [0x00,0x10,0xa0,0x4f] +; CHECK: fmla.2d v0, v0, v0[1] ; encoding: [0x00,0x18,0xc0,0x4f] +; CHECK: fmls.2s v0, v0, v0[0] ; encoding: [0x00,0x50,0x80,0x0f] +; CHECK: fmls.4s v0, v0, v0[1] ; encoding: [0x00,0x50,0xa0,0x4f] +; CHECK: fmls.2d v0, v0, v0[1] ; encoding: [0x00,0x58,0xc0,0x4f] +; CHECK: fmulx.2s v0, v0, v0[0] ; encoding: [0x00,0x90,0x80,0x2f] +; CHECK: fmulx.4s v0, v0, v0[1] ; encoding: [0x00,0x90,0xa0,0x6f] +; CHECK: fmulx.2d v0, v0, v0[1] ; encoding: [0x00,0x98,0xc0,0x6f] +; CHECK: fmul.2s v0, v0, v0[0] ; encoding: [0x00,0x90,0x80,0x0f] +; CHECK: fmul.4s v0, v0, v0[1] ; encoding: [0x00,0x90,0xa0,0x4f] +; CHECK: fmul.2d v0, v0, v0[1] ; encoding: [0x00,0x98,0xc0,0x4f] +; CHECK: mla.4h v0, v0, v0[0] ; encoding: [0x00,0x00,0x40,0x2f] +; CHECK: mla.8h v0, v0, v0[1] ; encoding: [0x00,0x00,0x50,0x6f] +; CHECK: mla.2s v0, v0, v0[2] ; encoding: [0x00,0x08,0x80,0x2f] +; CHECK: mla.4s v0, v0, v0[3] ; encoding: [0x00,0x08,0xa0,0x6f] +; CHECK: mls.4h v0, v0, v0[0] ; encoding: [0x00,0x40,0x40,0x2f] +; CHECK: mls.8h v0, v0, v0[1] ; encoding: [0x00,0x40,0x50,0x6f] +; CHECK: mls.2s v0, v0, v0[2] ; encoding: [0x00,0x48,0x80,0x2f] +; CHECK: mls.4s v0, v0, v0[3] ; encoding: [0x00,0x48,0xa0,0x6f] +; CHECK: mul.4h v0, v0, v0[0] ; encoding: [0x00,0x80,0x40,0x0f] +; CHECK: mul.8h v0, v0, v0[1] ; encoding: [0x00,0x80,0x50,0x4f] +; CHECK: mul.2s v0, v0, v0[2] ; encoding: [0x00,0x88,0x80,0x0f] +; CHECK: mul.4s v0, v0, v0[3] ; encoding: [0x00,0x88,0xa0,0x4f] +; CHECK: smlal.4s v0, v0, v0[0] ; encoding: [0x00,0x20,0x40,0x0f] +; CHECK: smlal2.4s v0, v0, v0[1] ; encoding: [0x00,0x20,0x50,0x4f] +; CHECK: smlal.2d v0, v0, v0[2] ; encoding: [0x00,0x28,0x80,0x0f] +; CHECK: smlal2.2d v0, v0, v0[3] ; encoding: [0x00,0x28,0xa0,0x4f] +; CHECK: smlsl.4s v0, v0, v0[0] ; encoding: [0x00,0x60,0x40,0x0f] +; CHECK: smlsl2.4s v0, v0, v0[1] ; encoding: [0x00,0x60,0x50,0x4f] +; CHECK: smlsl.2d v0, v0, v0[2] ; encoding: [0x00,0x68,0x80,0x0f] +; CHECK: smlsl2.2d v0, v0, v0[3] ; encoding: [0x00,0x68,0xa0,0x4f] +; CHECK: smull.4s v0, v0, v0[0] ; encoding: [0x00,0xa0,0x40,0x0f] +; CHECK: smull2.4s v0, v0, v0[1] ; encoding: [0x00,0xa0,0x50,0x4f] +; CHECK: smull.2d v0, v0, v0[2] ; encoding: [0x00,0xa8,0x80,0x0f] +; CHECK: smull2.2d v0, v0, v0[3] ; encoding: [0x00,0xa8,0xa0,0x4f] +; CHECK: sqdmlal.4s v0, v0, v0[0] ; encoding: [0x00,0x30,0x40,0x0f] +; CHECK: sqdmlal2.4s v0, v0, v0[1] ; encoding: [0x00,0x30,0x50,0x4f] +; CHECK: sqdmlal.2d v0, v0, v0[2] ; encoding: [0x00,0x38,0x80,0x0f] +; CHECK: sqdmlal2.2d v0, v0, v0[3] ; encoding: [0x00,0x38,0xa0,0x4f] +; CHECK: sqdmlsl.4s v0, v0, v0[0] ; encoding: [0x00,0x70,0x40,0x0f] +; CHECK: sqdmlsl2.4s v0, v0, v0[1] ; encoding: [0x00,0x70,0x50,0x4f] +; CHECK: sqdmlsl.2d v0, v0, v0[2] ; encoding: [0x00,0x78,0x80,0x0f] +; CHECK: sqdmlsl2.2d v0, v0, v0[3] ; encoding: [0x00,0x78,0xa0,0x4f] +; CHECK: sqdmulh.4h v0, v0, v0[0] ; encoding: [0x00,0xc0,0x40,0x0f] +; CHECK: sqdmulh.8h v0, v0, v0[1] ; encoding: [0x00,0xc0,0x50,0x4f] +; CHECK: sqdmulh.2s v0, v0, v0[2] ; encoding: [0x00,0xc8,0x80,0x0f] +; CHECK: sqdmulh.4s v0, v0, v0[3] ; encoding: [0x00,0xc8,0xa0,0x4f] +; CHECK: sqdmull.4s v0, v0, v0[0] ; encoding: [0x00,0xb0,0x40,0x0f] +; CHECK: sqdmull2.4s v0, v0, v0[1] ; encoding: [0x00,0xb0,0x50,0x4f] +; CHECK: sqdmull.2d v0, v0, v0[2] ; encoding: [0x00,0xb8,0x80,0x0f] +; CHECK: sqdmull2.2d v0, v0, v0[3] ; encoding: [0x00,0xb8,0xa0,0x4f] +; CHECK: sqrdmulh.4h v0, v0, v0[0] ; encoding: [0x00,0xd0,0x40,0x0f] +; CHECK: sqrdmulh.8h v0, v0, v0[1] ; encoding: [0x00,0xd0,0x50,0x4f] +; CHECK: sqrdmulh.2s v0, v0, v0[2] ; encoding: [0x00,0xd8,0x80,0x0f] +; CHECK: sqrdmulh.4s v0, v0, v0[3] ; encoding: [0x00,0xd8,0xa0,0x4f] +; CHECK: umlal.4s v0, v0, v0[0] ; encoding: [0x00,0x20,0x40,0x2f] +; CHECK: umlal2.4s v0, v0, v0[1] ; encoding: [0x00,0x20,0x50,0x6f] +; CHECK: umlal.2d v0, v0, v0[2] ; encoding: [0x00,0x28,0x80,0x2f] +; CHECK: umlal2.2d v0, v0, v0[3] ; encoding: [0x00,0x28,0xa0,0x6f] +; CHECK: umlsl.4s v0, v0, v0[0] ; encoding: [0x00,0x60,0x40,0x2f] +; CHECK: umlsl2.4s v0, v0, v0[1] ; encoding: [0x00,0x60,0x50,0x6f] +; CHECK: umlsl.2d v0, v0, v0[2] ; encoding: [0x00,0x68,0x80,0x2f] +; CHECK: umlsl2.2d v0, v0, v0[3] ; encoding: [0x00,0x68,0xa0,0x6f] +; CHECK: umull.4s v0, v0, v0[0] ; encoding: [0x00,0xa0,0x40,0x2f] +; CHECK: umull2.4s v0, v0, v0[1] ; encoding: [0x00,0xa0,0x50,0x6f] +; CHECK: umull.2d v0, v0, v0[2] ; encoding: [0x00,0xa8,0x80,0x2f] +; CHECK: umull2.2d v0, v0, v0[3] ; encoding: [0x00,0xa8,0xa0,0x6f] + + +;===-------------------------------------------------------------------------=== +; AdvSIMD scalar with shift +;===-------------------------------------------------------------------------=== + + fcvtzs s0, s0, #1 + fcvtzs d0, d0, #2 + fcvtzu s0, s0, #1 + fcvtzu d0, d0, #2 + shl d0, d0, #1 + sli d0, d0, #1 + sqrshrn b0, h0, #1 + sqrshrn h0, s0, #2 + sqrshrn s0, d0, #3 + sqrshrun b0, h0, #1 + sqrshrun h0, s0, #2 + sqrshrun s0, d0, #3 + sqshlu b0, b0, #1 + sqshlu h0, h0, #2 + sqshlu s0, s0, #3 + sqshlu d0, d0, #4 + sqshl b0, b0, #1 + sqshl h0, h0, #2 + sqshl s0, s0, #3 + sqshl d0, d0, #4 + sqshrn b0, h0, #1 + sqshrn h0, s0, #2 + sqshrn s0, d0, #3 + sqshrun b0, h0, #1 + sqshrun h0, s0, #2 + sqshrun s0, d0, #3 + sri d0, d0, #1 + srshr d0, d0, #1 + srsra d0, d0, #1 + sshr d0, d0, #1 + ucvtf s0, s0, #1 + ucvtf d0, d0, #2 + scvtf s0, s0, #1 + scvtf d0, d0, #2 + uqrshrn b0, h0, #1 + uqrshrn h0, s0, #2 + uqrshrn s0, d0, #3 + uqshl b0, b0, #1 + uqshl h0, h0, #2 + uqshl s0, s0, #3 + uqshl d0, d0, #4 + uqshrn b0, h0, #1 + uqshrn h0, s0, #2 + uqshrn s0, d0, #3 + urshr d0, d0, #1 + ursra d0, d0, #1 + ushr d0, d0, #1 + usra d0, d0, #1 + +; CHECK: fcvtzs s0, s0, #1 ; encoding: [0x00,0xfc,0x3f,0x5f] +; CHECK: fcvtzs d0, d0, #2 ; encoding: [0x00,0xfc,0x7e,0x5f] +; CHECK: fcvtzu s0, s0, #1 ; encoding: [0x00,0xfc,0x3f,0x7f] +; CHECK: fcvtzu d0, d0, #2 ; encoding: [0x00,0xfc,0x7e,0x7f] +; CHECK: shl d0, d0, #1 ; encoding: [0x00,0x54,0x41,0x5f] +; CHECK: sli d0, d0, #1 ; encoding: [0x00,0x54,0x41,0x7f] +; CHECK: sqrshrn b0, h0, #1 ; encoding: [0x00,0x9c,0x0f,0x5f] +; CHECK: sqrshrn h0, s0, #2 ; encoding: [0x00,0x9c,0x1e,0x5f] +; CHECK: sqrshrn s0, d0, #3 ; encoding: [0x00,0x9c,0x3d,0x5f] +; CHECK: sqrshrun b0, h0, #1 ; encoding: [0x00,0x8c,0x0f,0x7f] +; CHECK: sqrshrun h0, s0, #2 ; encoding: [0x00,0x8c,0x1e,0x7f] +; CHECK: sqrshrun s0, d0, #3 ; encoding: [0x00,0x8c,0x3d,0x7f] +; CHECK: sqshlu b0, b0, #1 ; encoding: [0x00,0x64,0x09,0x7f] +; CHECK: sqshlu h0, h0, #2 ; encoding: [0x00,0x64,0x12,0x7f] +; CHECK: sqshlu s0, s0, #3 ; encoding: [0x00,0x64,0x23,0x7f] +; CHECK: sqshlu d0, d0, #4 ; encoding: [0x00,0x64,0x44,0x7f] +; CHECK: sqshl b0, b0, #1 ; encoding: [0x00,0x74,0x09,0x5f] +; CHECK: sqshl h0, h0, #2 ; encoding: [0x00,0x74,0x12,0x5f] +; CHECK: sqshl s0, s0, #3 ; encoding: [0x00,0x74,0x23,0x5f] +; CHECK: sqshl d0, d0, #4 ; encoding: [0x00,0x74,0x44,0x5f] +; CHECK: sqshrn b0, h0, #1 ; encoding: [0x00,0x94,0x0f,0x5f] +; CHECK: sqshrn h0, s0, #2 ; encoding: [0x00,0x94,0x1e,0x5f] +; CHECK: sqshrn s0, d0, #3 ; encoding: [0x00,0x94,0x3d,0x5f] +; CHECK: sqshrun b0, h0, #1 ; encoding: [0x00,0x84,0x0f,0x7f] +; CHECK: sqshrun h0, s0, #2 ; encoding: [0x00,0x84,0x1e,0x7f] +; CHECK: sqshrun s0, d0, #3 ; encoding: [0x00,0x84,0x3d,0x7f] +; CHECK: sri d0, d0, #1 ; encoding: [0x00,0x44,0x7f,0x7f] +; CHECK: srshr d0, d0, #1 ; encoding: [0x00,0x24,0x7f,0x5f] +; CHECK: srsra d0, d0, #1 ; encoding: [0x00,0x34,0x7f,0x5f] +; CHECK: sshr d0, d0, #1 ; encoding: [0x00,0x04,0x7f,0x5f] +; CHECK: ucvtf s0, s0, #1 ; encoding: [0x00,0xe4,0x3f,0x7f] +; CHECK: ucvtf d0, d0, #2 ; encoding: [0x00,0xe4,0x7e,0x7f] +; check: scvtf s0, s0, #1 ; encoding: [0x00,0xe4,0x3f,0x5f] +; check: scvtf d0, d0, #2 ; encoding: [0x00,0xe4,0x7e,0x5f] +; CHECK: uqrshrn b0, h0, #1 ; encoding: [0x00,0x9c,0x0f,0x7f] +; CHECK: uqrshrn h0, s0, #2 ; encoding: [0x00,0x9c,0x1e,0x7f] +; CHECK: uqrshrn s0, d0, #3 ; encoding: [0x00,0x9c,0x3d,0x7f] +; CHECK: uqshl b0, b0, #1 ; encoding: [0x00,0x74,0x09,0x7f] +; CHECK: uqshl h0, h0, #2 ; encoding: [0x00,0x74,0x12,0x7f] +; CHECK: uqshl s0, s0, #3 ; encoding: [0x00,0x74,0x23,0x7f] +; CHECK: uqshl d0, d0, #4 ; encoding: [0x00,0x74,0x44,0x7f] +; CHECK: uqshrn b0, h0, #1 ; encoding: [0x00,0x94,0x0f,0x7f] +; CHECK: uqshrn h0, s0, #2 ; encoding: [0x00,0x94,0x1e,0x7f] +; CHECK: uqshrn s0, d0, #3 ; encoding: [0x00,0x94,0x3d,0x7f] +; CHECK: urshr d0, d0, #1 ; encoding: [0x00,0x24,0x7f,0x7f] +; CHECK: ursra d0, d0, #1 ; encoding: [0x00,0x34,0x7f,0x7f] +; CHECK: ushr d0, d0, #1 ; encoding: [0x00,0x04,0x7f,0x7f] +; CHECK: usra d0, d0, #1 ; encoding: [0x00,0x14,0x7f,0x7f] + + +;===-------------------------------------------------------------------------=== +; AdvSIMD vector with shift +;===-------------------------------------------------------------------------=== + + fcvtzs.2s v0, v0, #1 + fcvtzs.4s v0, v0, #2 + fcvtzs.2d v0, v0, #3 + fcvtzu.2s v0, v0, #1 + fcvtzu.4s v0, v0, #2 + fcvtzu.2d v0, v0, #3 + rshrn.8b v0, v0, #1 + rshrn2.16b v0, v0, #2 + rshrn.4h v0, v0, #3 + rshrn2.8h v0, v0, #4 + rshrn.2s v0, v0, #5 + rshrn2.4s v0, v0, #6 + scvtf.2s v0, v0, #1 + scvtf.4s v0, v0, #2 + scvtf.2d v0, v0, #3 + shl.8b v0, v0, #1 + shl.16b v0, v0, #2 + shl.4h v0, v0, #3 + shl.8h v0, v0, #4 + shl.2s v0, v0, #5 + shl.4s v0, v0, #6 + shl.2d v0, v0, #7 + shrn.8b v0, v0, #1 + shrn2.16b v0, v0, #2 + shrn.4h v0, v0, #3 + shrn2.8h v0, v0, #4 + shrn.2s v0, v0, #5 + shrn2.4s v0, v0, #6 + sli.8b v0, v0, #1 + sli.16b v0, v0, #2 + sli.4h v0, v0, #3 + sli.8h v0, v0, #4 + sli.2s v0, v0, #5 + sli.4s v0, v0, #6 + sli.2d v0, v0, #7 + sqrshrn.8b v0, v0, #1 + sqrshrn2.16b v0, v0, #2 + sqrshrn.4h v0, v0, #3 + sqrshrn2.8h v0, v0, #4 + sqrshrn.2s v0, v0, #5 + sqrshrn2.4s v0, v0, #6 + sqrshrun.8b v0, v0, #1 + sqrshrun2.16b v0, v0, #2 + sqrshrun.4h v0, v0, #3 + sqrshrun2.8h v0, v0, #4 + sqrshrun.2s v0, v0, #5 + sqrshrun2.4s v0, v0, #6 + sqshlu.8b v0, v0, #1 + sqshlu.16b v0, v0, #2 + sqshlu.4h v0, v0, #3 + sqshlu.8h v0, v0, #4 + sqshlu.2s v0, v0, #5 + sqshlu.4s v0, v0, #6 + sqshlu.2d v0, v0, #7 + sqshl.8b v0, v0, #1 + sqshl.16b v0, v0, #2 + sqshl.4h v0, v0, #3 + sqshl.8h v0, v0, #4 + sqshl.2s v0, v0, #5 + sqshl.4s v0, v0, #6 + sqshl.2d v0, v0, #7 + sqshrn.8b v0, v0, #1 + sqshrn2.16b v0, v0, #2 + sqshrn.4h v0, v0, #3 + sqshrn2.8h v0, v0, #4 + sqshrn.2s v0, v0, #5 + sqshrn2.4s v0, v0, #6 + sqshrun.8b v0, v0, #1 + sqshrun2.16b v0, v0, #2 + sqshrun.4h v0, v0, #3 + sqshrun2.8h v0, v0, #4 + sqshrun.2s v0, v0, #5 + sqshrun2.4s v0, v0, #6 + sri.8b v0, v0, #1 + sri.16b v0, v0, #2 + sri.4h v0, v0, #3 + sri.8h v0, v0, #4 + sri.2s v0, v0, #5 + sri.4s v0, v0, #6 + sri.2d v0, v0, #7 + srshr.8b v0, v0, #1 + srshr.16b v0, v0, #2 + srshr.4h v0, v0, #3 + srshr.8h v0, v0, #4 + srshr.2s v0, v0, #5 + srshr.4s v0, v0, #6 + srshr.2d v0, v0, #7 + srsra.8b v0, v0, #1 + srsra.16b v0, v0, #2 + srsra.4h v0, v0, #3 + srsra.8h v0, v0, #4 + srsra.2s v0, v0, #5 + srsra.4s v0, v0, #6 + srsra.2d v0, v0, #7 + sshll.8h v0, v0, #1 + sshll2.8h v0, v0, #2 + sshll.4s v0, v0, #3 + sshll2.4s v0, v0, #4 + sshll.2d v0, v0, #5 + sshll2.2d v0, v0, #6 + sshr.8b v0, v0, #1 + sshr.16b v0, v0, #2 + sshr.4h v0, v0, #3 + sshr.8h v0, v0, #4 + sshr.2s v0, v0, #5 + sshr.4s v0, v0, #6 + sshr.2d v0, v0, #7 + sshr.8b v0, v0, #1 + ssra.16b v0, v0, #2 + ssra.4h v0, v0, #3 + ssra.8h v0, v0, #4 + ssra.2s v0, v0, #5 + ssra.4s v0, v0, #6 + ssra.2d v0, v0, #7 + ssra d0, d0, #64 + ucvtf.2s v0, v0, #1 + ucvtf.4s v0, v0, #2 + ucvtf.2d v0, v0, #3 + uqrshrn.8b v0, v0, #1 + uqrshrn2.16b v0, v0, #2 + uqrshrn.4h v0, v0, #3 + uqrshrn2.8h v0, v0, #4 + uqrshrn.2s v0, v0, #5 + uqrshrn2.4s v0, v0, #6 + uqshl.8b v0, v0, #1 + uqshl.16b v0, v0, #2 + uqshl.4h v0, v0, #3 + uqshl.8h v0, v0, #4 + uqshl.2s v0, v0, #5 + uqshl.4s v0, v0, #6 + uqshl.2d v0, v0, #7 + uqshrn.8b v0, v0, #1 + uqshrn2.16b v0, v0, #2 + uqshrn.4h v0, v0, #3 + uqshrn2.8h v0, v0, #4 + uqshrn.2s v0, v0, #5 + uqshrn2.4s v0, v0, #6 + urshr.8b v0, v0, #1 + urshr.16b v0, v0, #2 + urshr.4h v0, v0, #3 + urshr.8h v0, v0, #4 + urshr.2s v0, v0, #5 + urshr.4s v0, v0, #6 + urshr.2d v0, v0, #7 + ursra.8b v0, v0, #1 + ursra.16b v0, v0, #2 + ursra.4h v0, v0, #3 + ursra.8h v0, v0, #4 + ursra.2s v0, v0, #5 + ursra.4s v0, v0, #6 + ursra.2d v0, v0, #7 + ushll.8h v0, v0, #1 + ushll2.8h v0, v0, #2 + ushll.4s v0, v0, #3 + ushll2.4s v0, v0, #4 + ushll.2d v0, v0, #5 + ushll2.2d v0, v0, #6 + ushr.8b v0, v0, #1 + ushr.16b v0, v0, #2 + ushr.4h v0, v0, #3 + ushr.8h v0, v0, #4 + ushr.2s v0, v0, #5 + ushr.4s v0, v0, #6 + ushr.2d v0, v0, #7 + usra.8b v0, v0, #1 + usra.16b v0, v0, #2 + usra.4h v0, v0, #3 + usra.8h v0, v0, #4 + usra.2s v0, v0, #5 + usra.4s v0, v0, #6 + usra.2d v0, v0, #7 + +; CHECK: fcvtzs.2s v0, v0, #1 ; encoding: [0x00,0xfc,0x3f,0x0f] +; CHECK: fcvtzs.4s v0, v0, #2 ; encoding: [0x00,0xfc,0x3e,0x4f] +; CHECK: fcvtzs.2d v0, v0, #3 ; encoding: [0x00,0xfc,0x7d,0x4f] +; CHECK: fcvtzu.2s v0, v0, #1 ; encoding: [0x00,0xfc,0x3f,0x2f] +; CHECK: fcvtzu.4s v0, v0, #2 ; encoding: [0x00,0xfc,0x3e,0x6f] +; CHECK: fcvtzu.2d v0, v0, #3 ; encoding: [0x00,0xfc,0x7d,0x6f] +; CHECK: rshrn.8b v0, v0, #1 ; encoding: [0x00,0x8c,0x0f,0x0f] +; CHECK: rshrn2.16b v0, v0, #2 ; encoding: [0x00,0x8c,0x0e,0x4f] +; CHECK: rshrn.4h v0, v0, #3 ; encoding: [0x00,0x8c,0x1d,0x0f] +; CHECK: rshrn2.8h v0, v0, #4 ; encoding: [0x00,0x8c,0x1c,0x4f] +; CHECK: rshrn.2s v0, v0, #5 ; encoding: [0x00,0x8c,0x3b,0x0f] +; CHECK: rshrn2.4s v0, v0, #6 ; encoding: [0x00,0x8c,0x3a,0x4f] +; CHECK: scvtf.2s v0, v0, #1 ; encoding: [0x00,0xe4,0x3f,0x0f] +; CHECK: scvtf.4s v0, v0, #2 ; encoding: [0x00,0xe4,0x3e,0x4f] +; CHECK: scvtf.2d v0, v0, #3 ; encoding: [0x00,0xe4,0x7d,0x4f] +; CHECK: shl.8b v0, v0, #1 ; encoding: [0x00,0x54,0x09,0x0f] +; CHECK: shl.16b v0, v0, #2 ; encoding: [0x00,0x54,0x0a,0x4f] +; CHECK: shl.4h v0, v0, #3 ; encoding: [0x00,0x54,0x13,0x0f] +; CHECK: shl.8h v0, v0, #4 ; encoding: [0x00,0x54,0x14,0x4f] +; CHECK: shl.2s v0, v0, #5 ; encoding: [0x00,0x54,0x25,0x0f] +; CHECK: shl.4s v0, v0, #6 ; encoding: [0x00,0x54,0x26,0x4f] +; CHECK: shl.2d v0, v0, #7 ; encoding: [0x00,0x54,0x47,0x4f] +; CHECK: shrn.8b v0, v0, #1 ; encoding: [0x00,0x84,0x0f,0x0f] +; CHECK: shrn2.16b v0, v0, #2 ; encoding: [0x00,0x84,0x0e,0x4f] +; CHECK: shrn.4h v0, v0, #3 ; encoding: [0x00,0x84,0x1d,0x0f] +; CHECK: shrn2.8h v0, v0, #4 ; encoding: [0x00,0x84,0x1c,0x4f] +; CHECK: shrn.2s v0, v0, #5 ; encoding: [0x00,0x84,0x3b,0x0f] +; CHECK: shrn2.4s v0, v0, #6 ; encoding: [0x00,0x84,0x3a,0x4f] +; CHECK: sli.8b v0, v0, #1 ; encoding: [0x00,0x54,0x09,0x2f] +; CHECK: sli.16b v0, v0, #2 ; encoding: [0x00,0x54,0x0a,0x6f] +; CHECK: sli.4h v0, v0, #3 ; encoding: [0x00,0x54,0x13,0x2f] +; CHECK: sli.8h v0, v0, #4 ; encoding: [0x00,0x54,0x14,0x6f] +; CHECK: sli.2s v0, v0, #5 ; encoding: [0x00,0x54,0x25,0x2f] +; CHECK: sli.4s v0, v0, #6 ; encoding: [0x00,0x54,0x26,0x6f] +; CHECK: sli.2d v0, v0, #7 ; encoding: [0x00,0x54,0x47,0x6f] +; CHECK: sqrshrn.8b v0, v0, #1 ; encoding: [0x00,0x9c,0x0f,0x0f] +; CHECK: sqrshrn2.16b v0, v0, #2 ; encoding: [0x00,0x9c,0x0e,0x4f] +; CHECK: sqrshrn.4h v0, v0, #3 ; encoding: [0x00,0x9c,0x1d,0x0f] +; CHECK: sqrshrn2.8h v0, v0, #4 ; encoding: [0x00,0x9c,0x1c,0x4f] +; CHECK: sqrshrn.2s v0, v0, #5 ; encoding: [0x00,0x9c,0x3b,0x0f] +; CHECK: sqrshrn2.4s v0, v0, #6 ; encoding: [0x00,0x9c,0x3a,0x4f] +; CHECK: sqrshrun.8b v0, v0, #1 ; encoding: [0x00,0x8c,0x0f,0x2f] +; CHECK: sqrshrun2.16b v0, v0, #2 ; encoding: [0x00,0x8c,0x0e,0x6f] +; CHECK: sqrshrun.4h v0, v0, #3 ; encoding: [0x00,0x8c,0x1d,0x2f] +; CHECK: sqrshrun2.8h v0, v0, #4 ; encoding: [0x00,0x8c,0x1c,0x6f] +; CHECK: sqrshrun.2s v0, v0, #5 ; encoding: [0x00,0x8c,0x3b,0x2f] +; CHECK: sqrshrun2.4s v0, v0, #6 ; encoding: [0x00,0x8c,0x3a,0x6f] +; CHECK: sqshlu.8b v0, v0, #1 ; encoding: [0x00,0x64,0x09,0x2f] +; CHECK: sqshlu.16b v0, v0, #2 ; encoding: [0x00,0x64,0x0a,0x6f] +; CHECK: sqshlu.4h v0, v0, #3 ; encoding: [0x00,0x64,0x13,0x2f] +; CHECK: sqshlu.8h v0, v0, #4 ; encoding: [0x00,0x64,0x14,0x6f] +; CHECK: sqshlu.2s v0, v0, #5 ; encoding: [0x00,0x64,0x25,0x2f] +; CHECK: sqshlu.4s v0, v0, #6 ; encoding: [0x00,0x64,0x26,0x6f] +; CHECK: sqshlu.2d v0, v0, #7 ; encoding: [0x00,0x64,0x47,0x6f] +; CHECK: sqshl.8b v0, v0, #1 ; encoding: [0x00,0x74,0x09,0x0f] +; CHECK: sqshl.16b v0, v0, #2 ; encoding: [0x00,0x74,0x0a,0x4f] +; CHECK: sqshl.4h v0, v0, #3 ; encoding: [0x00,0x74,0x13,0x0f] +; CHECK: sqshl.8h v0, v0, #4 ; encoding: [0x00,0x74,0x14,0x4f] +; CHECK: sqshl.2s v0, v0, #5 ; encoding: [0x00,0x74,0x25,0x0f] +; CHECK: sqshl.4s v0, v0, #6 ; encoding: [0x00,0x74,0x26,0x4f] +; CHECK: sqshl.2d v0, v0, #7 ; encoding: [0x00,0x74,0x47,0x4f] +; CHECK: sqshrn.8b v0, v0, #1 ; encoding: [0x00,0x94,0x0f,0x0f] +; CHECK: sqshrn2.16b v0, v0, #2 ; encoding: [0x00,0x94,0x0e,0x4f] +; CHECK: sqshrn.4h v0, v0, #3 ; encoding: [0x00,0x94,0x1d,0x0f] +; CHECK: sqshrn2.8h v0, v0, #4 ; encoding: [0x00,0x94,0x1c,0x4f] +; CHECK: sqshrn.2s v0, v0, #5 ; encoding: [0x00,0x94,0x3b,0x0f] +; CHECK: sqshrn2.4s v0, v0, #6 ; encoding: [0x00,0x94,0x3a,0x4f] +; CHECK: sqshrun.8b v0, v0, #1 ; encoding: [0x00,0x84,0x0f,0x2f] +; CHECK: sqshrun2.16b v0, v0, #2 ; encoding: [0x00,0x84,0x0e,0x6f] +; CHECK: sqshrun.4h v0, v0, #3 ; encoding: [0x00,0x84,0x1d,0x2f] +; CHECK: sqshrun2.8h v0, v0, #4 ; encoding: [0x00,0x84,0x1c,0x6f] +; CHECK: sqshrun.2s v0, v0, #5 ; encoding: [0x00,0x84,0x3b,0x2f] +; CHECK: sqshrun2.4s v0, v0, #6 ; encoding: [0x00,0x84,0x3a,0x6f] +; CHECK: sri.8b v0, v0, #1 ; encoding: [0x00,0x44,0x0f,0x2f] +; CHECK: sri.16b v0, v0, #2 ; encoding: [0x00,0x44,0x0e,0x6f] +; CHECK: sri.4h v0, v0, #3 ; encoding: [0x00,0x44,0x1d,0x2f] +; CHECK: sri.8h v0, v0, #4 ; encoding: [0x00,0x44,0x1c,0x6f] +; CHECK: sri.2s v0, v0, #5 ; encoding: [0x00,0x44,0x3b,0x2f] +; CHECK: sri.4s v0, v0, #6 ; encoding: [0x00,0x44,0x3a,0x6f] +; CHECK: sri.2d v0, v0, #7 ; encoding: [0x00,0x44,0x79,0x6f] +; CHECK: srshr.8b v0, v0, #1 ; encoding: [0x00,0x24,0x0f,0x0f] +; CHECK: srshr.16b v0, v0, #2 ; encoding: [0x00,0x24,0x0e,0x4f] +; CHECK: srshr.4h v0, v0, #3 ; encoding: [0x00,0x24,0x1d,0x0f] +; CHECK: srshr.8h v0, v0, #4 ; encoding: [0x00,0x24,0x1c,0x4f] +; CHECK: srshr.2s v0, v0, #5 ; encoding: [0x00,0x24,0x3b,0x0f] +; CHECK: srshr.4s v0, v0, #6 ; encoding: [0x00,0x24,0x3a,0x4f] +; CHECK: srshr.2d v0, v0, #7 ; encoding: [0x00,0x24,0x79,0x4f] +; CHECK: srsra.8b v0, v0, #1 ; encoding: [0x00,0x34,0x0f,0x0f] +; CHECK: srsra.16b v0, v0, #2 ; encoding: [0x00,0x34,0x0e,0x4f] +; CHECK: srsra.4h v0, v0, #3 ; encoding: [0x00,0x34,0x1d,0x0f] +; CHECK: srsra.8h v0, v0, #4 ; encoding: [0x00,0x34,0x1c,0x4f] +; CHECK: srsra.2s v0, v0, #5 ; encoding: [0x00,0x34,0x3b,0x0f] +; CHECK: srsra.4s v0, v0, #6 ; encoding: [0x00,0x34,0x3a,0x4f] +; CHECK: srsra.2d v0, v0, #7 ; encoding: [0x00,0x34,0x79,0x4f] +; CHECK: sshll.8h v0, v0, #1 ; encoding: [0x00,0xa4,0x09,0x0f] +; CHECK: sshll2.8h v0, v0, #2 ; encoding: [0x00,0xa4,0x0a,0x4f] +; CHECK: sshll.4s v0, v0, #3 ; encoding: [0x00,0xa4,0x13,0x0f] +; CHECK: sshll2.4s v0, v0, #4 ; encoding: [0x00,0xa4,0x14,0x4f] +; CHECK: sshll.2d v0, v0, #5 ; encoding: [0x00,0xa4,0x25,0x0f] +; CHECK: sshll2.2d v0, v0, #6 ; encoding: [0x00,0xa4,0x26,0x4f] +; CHECK: sshr.8b v0, v0, #1 ; encoding: [0x00,0x04,0x0f,0x0f] +; CHECK: sshr.16b v0, v0, #2 ; encoding: [0x00,0x04,0x0e,0x4f] +; CHECK: sshr.4h v0, v0, #3 ; encoding: [0x00,0x04,0x1d,0x0f] +; CHECK: sshr.8h v0, v0, #4 ; encoding: [0x00,0x04,0x1c,0x4f] +; CHECK: sshr.2s v0, v0, #5 ; encoding: [0x00,0x04,0x3b,0x0f] +; CHECK: sshr.4s v0, v0, #6 ; encoding: [0x00,0x04,0x3a,0x4f] +; CHECK: sshr.2d v0, v0, #7 ; encoding: [0x00,0x04,0x79,0x4f] +; CHECK: sshr.8b v0, v0, #1 ; encoding: [0x00,0x04,0x0f,0x0f] +; CHECK: ssra.16b v0, v0, #2 ; encoding: [0x00,0x14,0x0e,0x4f] +; CHECK: ssra.4h v0, v0, #3 ; encoding: [0x00,0x14,0x1d,0x0f] +; CHECK: ssra.8h v0, v0, #4 ; encoding: [0x00,0x14,0x1c,0x4f] +; CHECK: ssra.2s v0, v0, #5 ; encoding: [0x00,0x14,0x3b,0x0f] +; CHECK: ssra.4s v0, v0, #6 ; encoding: [0x00,0x14,0x3a,0x4f] +; CHECK: ssra.2d v0, v0, #7 ; encoding: [0x00,0x14,0x79,0x4f] +; CHECK: ssra d0, d0, #64 ; encoding: [0x00,0x14,0x40,0x5f] +; CHECK: ucvtf.2s v0, v0, #1 ; encoding: [0x00,0xe4,0x3f,0x2f] +; CHECK: ucvtf.4s v0, v0, #2 ; encoding: [0x00,0xe4,0x3e,0x6f] +; CHECK: ucvtf.2d v0, v0, #3 ; encoding: [0x00,0xe4,0x7d,0x6f] +; CHECK: uqrshrn.8b v0, v0, #1 ; encoding: [0x00,0x9c,0x0f,0x2f] +; CHECK: uqrshrn2.16b v0, v0, #2 ; encoding: [0x00,0x9c,0x0e,0x6f] +; CHECK: uqrshrn.4h v0, v0, #3 ; encoding: [0x00,0x9c,0x1d,0x2f] +; CHECK: uqrshrn2.8h v0, v0, #4 ; encoding: [0x00,0x9c,0x1c,0x6f] +; CHECK: uqrshrn.2s v0, v0, #5 ; encoding: [0x00,0x9c,0x3b,0x2f] +; CHECK: uqrshrn2.4s v0, v0, #6 ; encoding: [0x00,0x9c,0x3a,0x6f] +; CHECK: uqshl.8b v0, v0, #1 ; encoding: [0x00,0x74,0x09,0x2f] +; CHECK: uqshl.16b v0, v0, #2 ; encoding: [0x00,0x74,0x0a,0x6f] +; CHECK: uqshl.4h v0, v0, #3 ; encoding: [0x00,0x74,0x13,0x2f] +; CHECK: uqshl.8h v0, v0, #4 ; encoding: [0x00,0x74,0x14,0x6f] +; CHECK: uqshl.2s v0, v0, #5 ; encoding: [0x00,0x74,0x25,0x2f] +; CHECK: uqshl.4s v0, v0, #6 ; encoding: [0x00,0x74,0x26,0x6f] +; CHECK: uqshl.2d v0, v0, #7 ; encoding: [0x00,0x74,0x47,0x6f] +; CHECK: uqshrn.8b v0, v0, #1 ; encoding: [0x00,0x94,0x0f,0x2f] +; CHECK: uqshrn2.16b v0, v0, #2 ; encoding: [0x00,0x94,0x0e,0x6f] +; CHECK: uqshrn.4h v0, v0, #3 ; encoding: [0x00,0x94,0x1d,0x2f] +; CHECK: uqshrn2.8h v0, v0, #4 ; encoding: [0x00,0x94,0x1c,0x6f] +; CHECK: uqshrn.2s v0, v0, #5 ; encoding: [0x00,0x94,0x3b,0x2f] +; CHECK: uqshrn2.4s v0, v0, #6 ; encoding: [0x00,0x94,0x3a,0x6f] +; CHECK: urshr.8b v0, v0, #1 ; encoding: [0x00,0x24,0x0f,0x2f] +; CHECK: urshr.16b v0, v0, #2 ; encoding: [0x00,0x24,0x0e,0x6f] +; CHECK: urshr.4h v0, v0, #3 ; encoding: [0x00,0x24,0x1d,0x2f] +; CHECK: urshr.8h v0, v0, #4 ; encoding: [0x00,0x24,0x1c,0x6f] +; CHECK: urshr.2s v0, v0, #5 ; encoding: [0x00,0x24,0x3b,0x2f] +; CHECK: urshr.4s v0, v0, #6 ; encoding: [0x00,0x24,0x3a,0x6f] +; CHECK: urshr.2d v0, v0, #7 ; encoding: [0x00,0x24,0x79,0x6f] +; CHECK: ursra.8b v0, v0, #1 ; encoding: [0x00,0x34,0x0f,0x2f] +; CHECK: ursra.16b v0, v0, #2 ; encoding: [0x00,0x34,0x0e,0x6f] +; CHECK: ursra.4h v0, v0, #3 ; encoding: [0x00,0x34,0x1d,0x2f] +; CHECK: ursra.8h v0, v0, #4 ; encoding: [0x00,0x34,0x1c,0x6f] +; CHECK: ursra.2s v0, v0, #5 ; encoding: [0x00,0x34,0x3b,0x2f] +; CHECK: ursra.4s v0, v0, #6 ; encoding: [0x00,0x34,0x3a,0x6f] +; CHECK: ursra.2d v0, v0, #7 ; encoding: [0x00,0x34,0x79,0x6f] +; CHECK: ushll.8h v0, v0, #1 ; encoding: [0x00,0xa4,0x09,0x2f] +; CHECK: ushll2.8h v0, v0, #2 ; encoding: [0x00,0xa4,0x0a,0x6f] +; CHECK: ushll.4s v0, v0, #3 ; encoding: [0x00,0xa4,0x13,0x2f] +; CHECK: ushll2.4s v0, v0, #4 ; encoding: [0x00,0xa4,0x14,0x6f] +; CHECK: ushll.2d v0, v0, #5 ; encoding: [0x00,0xa4,0x25,0x2f] +; CHECK: ushll2.2d v0, v0, #6 ; encoding: [0x00,0xa4,0x26,0x6f] +; CHECK: ushr.8b v0, v0, #1 ; encoding: [0x00,0x04,0x0f,0x2f] +; CHECK: ushr.16b v0, v0, #2 ; encoding: [0x00,0x04,0x0e,0x6f] +; CHECK: ushr.4h v0, v0, #3 ; encoding: [0x00,0x04,0x1d,0x2f] +; CHECK: ushr.8h v0, v0, #4 ; encoding: [0x00,0x04,0x1c,0x6f] +; CHECK: ushr.2s v0, v0, #5 ; encoding: [0x00,0x04,0x3b,0x2f] +; CHECK: ushr.4s v0, v0, #6 ; encoding: [0x00,0x04,0x3a,0x6f] +; CHECK: ushr.2d v0, v0, #7 ; encoding: [0x00,0x04,0x79,0x6f] +; CHECK: usra.8b v0, v0, #1 ; encoding: [0x00,0x14,0x0f,0x2f] +; CHECK: usra.16b v0, v0, #2 ; encoding: [0x00,0x14,0x0e,0x6f] +; CHECK: usra.4h v0, v0, #3 ; encoding: [0x00,0x14,0x1d,0x2f] +; CHECK: usra.8h v0, v0, #4 ; encoding: [0x00,0x14,0x1c,0x6f] +; CHECK: usra.2s v0, v0, #5 ; encoding: [0x00,0x14,0x3b,0x2f] +; CHECK: usra.4s v0, v0, #6 ; encoding: [0x00,0x14,0x3a,0x6f] +; CHECK: usra.2d v0, v0, #7 ; encoding: [0x00,0x14,0x79,0x6f] + + +; ARM Verbose syntax variants. + + rshrn v9.8b, v11.8h, #1 + rshrn2 v8.16b, v9.8h, #2 + rshrn v7.4h, v8.4s, #3 + rshrn2 v6.8h, v7.4s, #4 + rshrn v5.2s, v6.2d, #5 + rshrn2 v4.4s, v5.2d, #6 + + shrn v9.8b, v11.8h, #1 + shrn2 v8.16b, v9.8h, #2 + shrn v7.4h, v8.4s, #3 + shrn2 v6.8h, v7.4s, #4 + shrn v5.2s, v6.2d, #5 + shrn2 v4.4s, v5.2d, #6 + + sqrshrn v9.8b, v11.8h, #1 + sqrshrn2 v8.16b, v9.8h, #2 + sqrshrn v7.4h, v8.4s, #3 + sqrshrn2 v6.8h, v7.4s, #4 + sqrshrn v5.2s, v6.2d, #5 + sqrshrn2 v4.4s, v5.2d, #6 + + sqshrn v9.8b, v11.8h, #1 + sqshrn2 v8.16b, v9.8h, #2 + sqshrn v7.4h, v8.4s, #3 + sqshrn2 v6.8h, v7.4s, #4 + sqshrn v5.2s, v6.2d, #5 + sqshrn2 v4.4s, v5.2d, #6 + + sqrshrun v9.8b, v11.8h, #1 + sqrshrun2 v8.16b, v9.8h, #2 + sqrshrun v7.4h, v8.4s, #3 + sqrshrun2 v6.8h, v7.4s, #4 + sqrshrun v5.2s, v6.2d, #5 + sqrshrun2 v4.4s, v5.2d, #6 + + sqshrun v9.8b, v11.8h, #1 + sqshrun2 v8.16b, v9.8h, #2 + sqshrun v7.4h, v8.4s, #3 + sqshrun2 v6.8h, v7.4s, #4 + sqshrun v5.2s, v6.2d, #5 + sqshrun2 v4.4s, v5.2d, #6 + + uqrshrn v9.8b, v11.8h, #1 + uqrshrn2 v8.16b, v9.8h, #2 + uqrshrn v7.4h, v8.4s, #3 + uqrshrn2 v6.8h, v7.4s, #4 + uqrshrn v5.2s, v6.2d, #5 + uqrshrn2 v4.4s, v5.2d, #6 + + uqshrn v9.8b, v11.8h, #1 + uqshrn2 v8.16b, v9.8h, #2 + uqshrn v7.4h, v8.4s, #3 + uqshrn2 v6.8h, v7.4s, #4 + uqshrn v5.2s, v6.2d, #5 + uqshrn2 v4.4s, v5.2d, #6 + + sshll2 v10.8h, v3.16b, #6 + sshll2 v11.4s, v4.8h, #5 + sshll2 v12.2d, v5.4s, #4 + sshll v13.8h, v6.8b, #3 + sshll v14.4s, v7.4h, #2 + sshll v15.2d, v8.2s, #7 + + ushll2 v10.8h, v3.16b, #6 + ushll2 v11.4s, v4.8h, #5 + ushll2 v12.2d, v5.4s, #4 + ushll v13.8h, v6.8b, #3 + ushll v14.4s, v7.4h, #2 + ushll v15.2d, v8.2s, #7 + + +; CHECK: rshrn.8b v9, v11, #1 ; encoding: [0x69,0x8d,0x0f,0x0f] +; CHECK: rshrn2.16b v8, v9, #2 ; encoding: [0x28,0x8d,0x0e,0x4f] +; CHECK: rshrn.4h v7, v8, #3 ; encoding: [0x07,0x8d,0x1d,0x0f] +; CHECK: rshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x8c,0x1c,0x4f] +; CHECK: rshrn.2s v5, v6, #5 ; encoding: [0xc5,0x8c,0x3b,0x0f] +; CHECK: rshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x8c,0x3a,0x4f] +; CHECK: shrn.8b v9, v11, #1 ; encoding: [0x69,0x85,0x0f,0x0f] +; CHECK: shrn2.16b v8, v9, #2 ; encoding: [0x28,0x85,0x0e,0x4f] +; CHECK: shrn.4h v7, v8, #3 ; encoding: [0x07,0x85,0x1d,0x0f] +; CHECK: shrn2.8h v6, v7, #4 ; encoding: [0xe6,0x84,0x1c,0x4f] +; CHECK: shrn.2s v5, v6, #5 ; encoding: [0xc5,0x84,0x3b,0x0f] +; CHECK: shrn2.4s v4, v5, #6 ; encoding: [0xa4,0x84,0x3a,0x4f] +; CHECK: sqrshrn.8b v9, v11, #1 ; encoding: [0x69,0x9d,0x0f,0x0f] +; CHECK: sqrshrn2.16b v8, v9, #2 ; encoding: [0x28,0x9d,0x0e,0x4f] +; CHECK: sqrshrn.4h v7, v8, #3 ; encoding: [0x07,0x9d,0x1d,0x0f] +; CHECK: sqrshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x9c,0x1c,0x4f] +; CHECK: sqrshrn.2s v5, v6, #5 ; encoding: [0xc5,0x9c,0x3b,0x0f] +; CHECK: sqrshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x9c,0x3a,0x4f] +; CHECK: sqshrn.8b v9, v11, #1 ; encoding: [0x69,0x95,0x0f,0x0f] +; CHECK: sqshrn2.16b v8, v9, #2 ; encoding: [0x28,0x95,0x0e,0x4f] +; CHECK: sqshrn.4h v7, v8, #3 ; encoding: [0x07,0x95,0x1d,0x0f] +; CHECK: sqshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x94,0x1c,0x4f] +; CHECK: sqshrn.2s v5, v6, #5 ; encoding: [0xc5,0x94,0x3b,0x0f] +; CHECK: sqshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x94,0x3a,0x4f] +; CHECK: sqrshrun.8b v9, v11, #1 ; encoding: [0x69,0x8d,0x0f,0x2f] +; CHECK: sqrshrun2.16b v8, v9, #2 ; encoding: [0x28,0x8d,0x0e,0x6f] +; CHECK: sqrshrun.4h v7, v8, #3 ; encoding: [0x07,0x8d,0x1d,0x2f] +; CHECK: sqrshrun2.8h v6, v7, #4 ; encoding: [0xe6,0x8c,0x1c,0x6f] +; CHECK: sqrshrun.2s v5, v6, #5 ; encoding: [0xc5,0x8c,0x3b,0x2f] +; CHECK: sqrshrun2.4s v4, v5, #6 ; encoding: [0xa4,0x8c,0x3a,0x6f] +; CHECK: sqshrun.8b v9, v11, #1 ; encoding: [0x69,0x85,0x0f,0x2f] +; CHECK: sqshrun2.16b v8, v9, #2 ; encoding: [0x28,0x85,0x0e,0x6f] +; CHECK: sqshrun.4h v7, v8, #3 ; encoding: [0x07,0x85,0x1d,0x2f] +; CHECK: sqshrun2.8h v6, v7, #4 ; encoding: [0xe6,0x84,0x1c,0x6f] +; CHECK: sqshrun.2s v5, v6, #5 ; encoding: [0xc5,0x84,0x3b,0x2f] +; CHECK: sqshrun2.4s v4, v5, #6 ; encoding: [0xa4,0x84,0x3a,0x6f] +; CHECK: uqrshrn.8b v9, v11, #1 ; encoding: [0x69,0x9d,0x0f,0x2f] +; CHECK: uqrshrn2.16b v8, v9, #2 ; encoding: [0x28,0x9d,0x0e,0x6f] +; CHECK: uqrshrn.4h v7, v8, #3 ; encoding: [0x07,0x9d,0x1d,0x2f] +; CHECK: uqrshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x9c,0x1c,0x6f] +; CHECK: uqrshrn.2s v5, v6, #5 ; encoding: [0xc5,0x9c,0x3b,0x2f] +; CHECK: uqrshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x9c,0x3a,0x6f] +; CHECK: uqshrn.8b v9, v11, #1 ; encoding: [0x69,0x95,0x0f,0x2f] +; CHECK: uqshrn2.16b v8, v9, #2 ; encoding: [0x28,0x95,0x0e,0x6f] +; CHECK: uqshrn.4h v7, v8, #3 ; encoding: [0x07,0x95,0x1d,0x2f] +; CHECK: uqshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x94,0x1c,0x6f] +; CHECK: uqshrn.2s v5, v6, #5 ; encoding: [0xc5,0x94,0x3b,0x2f] +; CHECK: uqshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x94,0x3a,0x6f] +; CHECK: sshll2.8h v10, v3, #6 ; encoding: [0x6a,0xa4,0x0e,0x4f] +; CHECK: sshll2.4s v11, v4, #5 ; encoding: [0x8b,0xa4,0x15,0x4f] +; CHECK: sshll2.2d v12, v5, #4 ; encoding: [0xac,0xa4,0x24,0x4f] +; CHECK: sshll.8h v13, v6, #3 ; encoding: [0xcd,0xa4,0x0b,0x0f] +; CHECK: sshll.4s v14, v7, #2 ; encoding: [0xee,0xa4,0x12,0x0f] +; CHECK: sshll.2d v15, v8, #7 ; encoding: [0x0f,0xa5,0x27,0x0f] +; CHECK: ushll2.8h v10, v3, #6 ; encoding: [0x6a,0xa4,0x0e,0x6f] +; CHECK: ushll2.4s v11, v4, #5 ; encoding: [0x8b,0xa4,0x15,0x6f] +; CHECK: ushll2.2d v12, v5, #4 ; encoding: [0xac,0xa4,0x24,0x6f] +; CHECK: ushll.8h v13, v6, #3 ; encoding: [0xcd,0xa4,0x0b,0x2f] +; CHECK: ushll.4s v14, v7, #2 ; encoding: [0xee,0xa4,0x12,0x2f] +; CHECK: ushll.2d v15, v8, #7 ; encoding: [0x0f,0xa5,0x27,0x2f] + + + pmull.8h v0, v0, v0 + pmull2.8h v0, v0, v0 + pmull.1q v2, v3, v4 + pmull2.1q v2, v3, v4 + pmull v2.1q, v3.1d, v4.1d + pmull2 v2.1q, v3.2d, v4.2d + +; CHECK: pmull.8h v0, v0, v0 ; encoding: [0x00,0xe0,0x20,0x0e] +; CHECK: pmull2.8h v0, v0, v0 ; encoding: [0x00,0xe0,0x20,0x4e] +; CHECK: pmull.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x0e] +; CHECK: pmull2.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x4e] +; CHECK: pmull.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x0e] +; CHECK: pmull2.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x4e] + + + faddp.2d d1, v2 + faddp.2s s3, v4 +; CHECK: faddp.2d d1, v2 ; encoding: [0x41,0xd8,0x70,0x7e] +; CHECK: faddp.2s s3, v4 ; encoding: [0x83,0xd8,0x30,0x7e] + + tbl.16b v2, {v4,v5,v6,v7}, v1 + tbl.8b v0, {v4,v5,v6,v7}, v1 + tbl.16b v2, {v5}, v1 + tbl.8b v0, {v5}, v1 + tbl.16b v2, {v5,v6,v7}, v1 + tbl.8b v0, {v5,v6,v7}, v1 + tbl.16b v2, {v6,v7}, v1 + tbl.8b v0, {v6,v7}, v1 +; CHECK: tbl.16b v2, { v4, v5, v6, v7 }, v1 ; encoding: [0x82,0x60,0x01,0x4e] +; CHECK: tbl.8b v0, { v4, v5, v6, v7 }, v1 ; encoding: [0x80,0x60,0x01,0x0e] +; CHECK: tbl.16b v2, { v5 }, v1 ; encoding: [0xa2,0x00,0x01,0x4e] +; CHECK: tbl.8b v0, { v5 }, v1 ; encoding: [0xa0,0x00,0x01,0x0e] +; CHECK: tbl.16b v2, { v5, v6, v7 }, v1 ; encoding: [0xa2,0x40,0x01,0x4e] +; CHECK: tbl.8b v0, { v5, v6, v7 }, v1 ; encoding: [0xa0,0x40,0x01,0x0e] +; CHECK: tbl.16b v2, { v6, v7 }, v1 ; encoding: [0xc2,0x20,0x01,0x4e] +; CHECK: tbl.8b v0, { v6, v7 }, v1 ; encoding: [0xc0,0x20,0x01,0x0e] + + tbl v2.16b, {v4.16b,v5.16b,v6.16b,v7.16b}, v1.16b + tbl v0.8b, {v4.16b,v5.16b,v6.16b,v7.16b}, v1.8b + tbl v2.16b, {v5.16b}, v1.16b + tbl v0.8b, {v5.16b}, v1.8b + tbl v2.16b, {v5.16b,v6.16b,v7.16b}, v1.16b + tbl v0.8b, {v5.16b,v6.16b,v7.16b}, v1.8b + tbl v2.16b, {v6.16b,v7.16b}, v1.16b + tbl v0.8b, {v6.16b,v7.16b}, v1.8b +; CHECK: tbl.16b v2, { v4, v5, v6, v7 }, v1 ; encoding: [0x82,0x60,0x01,0x4e] +; CHECK: tbl.8b v0, { v4, v5, v6, v7 }, v1 ; encoding: [0x80,0x60,0x01,0x0e] +; CHECK: tbl.16b v2, { v5 }, v1 ; encoding: [0xa2,0x00,0x01,0x4e] +; CHECK: tbl.8b v0, { v5 }, v1 ; encoding: [0xa0,0x00,0x01,0x0e] +; CHECK: tbl.16b v2, { v5, v6, v7 }, v1 ; encoding: [0xa2,0x40,0x01,0x4e] +; CHECK: tbl.8b v0, { v5, v6, v7 }, v1 ; encoding: [0xa0,0x40,0x01,0x0e] +; CHECK: tbl.16b v2, { v6, v7 }, v1 ; encoding: [0xc2,0x20,0x01,0x4e] +; CHECK: tbl.8b v0, { v6, v7 }, v1 ; encoding: [0xc0,0x20,0x01,0x0e] + + sqdmull s0, h0, h0 + sqdmull d0, s0, s0 +; CHECK: sqdmull s0, h0, h0 ; encoding: [0x00,0xd0,0x60,0x5e] +; CHECK: sqdmull d0, s0, s0 ; encoding: [0x00,0xd0,0xa0,0x5e] + + frsqrte s0, s0 + frsqrte d0, d0 +; CHECK: frsqrte s0, s0 ; encoding: [0x00,0xd8,0xa1,0x7e] +; CHECK: frsqrte d0, d0 ; encoding: [0x00,0xd8,0xe1,0x7e] + + mov.16b v0, v0 + mov.2s v0, v0 +; CHECK: mov.16b v0, v0 ; encoding: [0x00,0x1c,0xa0,0x4e] +; CHECK: mov.8b v0, v0 ; encoding: [0x00,0x1c,0xa0,0x0e] + + +; uadalp/sadalp verbose mode aliases. + uadalp v14.4h, v25.8b + uadalp v15.8h, v24.16b + uadalp v16.2s, v23.4h + uadalp v17.4s, v22.8h + uadalp v18.1d, v21.2s + uadalp v19.2d, v20.4s + + sadalp v1.4h, v11.8b + sadalp v2.8h, v12.16b + sadalp v3.2s, v13.4h + sadalp v4.4s, v14.8h + sadalp v5.1d, v15.2s + sadalp v6.2d, v16.4s + +; CHECK: uadalp.4h v14, v25 ; encoding: [0x2e,0x6b,0x20,0x2e] +; CHECK: uadalp.8h v15, v24 ; encoding: [0x0f,0x6b,0x20,0x6e] +; CHECK: uadalp.2s v16, v23 ; encoding: [0xf0,0x6a,0x60,0x2e] +; CHECK: uadalp.4s v17, v22 ; encoding: [0xd1,0x6a,0x60,0x6e] +; CHECK: uadalp.1d v18, v21 ; encoding: [0xb2,0x6a,0xa0,0x2e] +; CHECK: uadalp.2d v19, v20 ; encoding: [0x93,0x6a,0xa0,0x6e] +; CHECK: sadalp.4h v1, v11 ; encoding: [0x61,0x69,0x20,0x0e] +; CHECK: sadalp.8h v2, v12 ; encoding: [0x82,0x69,0x20,0x4e] +; CHECK: sadalp.2s v3, v13 ; encoding: [0xa3,0x69,0x60,0x0e] +; CHECK: sadalp.4s v4, v14 ; encoding: [0xc4,0x69,0x60,0x4e] +; CHECK: sadalp.1d v5, v15 ; encoding: [0xe5,0x69,0xa0,0x0e] +; CHECK: sadalp.2d v6, v16 ; encoding: [0x06,0x6a,0xa0,0x4e] + +; MVN is an alias for 'not'. + mvn v1.8b, v4.8b + mvn v19.16b, v17.16b + mvn.8b v10, v6 + mvn.16b v11, v7 + +; CHECK: mvn.8b v1, v4 ; encoding: [0x81,0x58,0x20,0x2e] +; CHECK: mvn.16b v19, v17 ; encoding: [0x33,0x5a,0x20,0x6e] +; CHECK: mvn.8b v10, v6 ; encoding: [0xca,0x58,0x20,0x2e] +; CHECK: mvn.16b v11, v7 ; encoding: [0xeb,0x58,0x20,0x6e] + +; sqdmull verbose mode aliases + sqdmull v10.4s, v12.4h, v12.4h + sqdmull2 v10.4s, v13.8h, v13.8h + sqdmull v10.2d, v13.2s, v13.2s + sqdmull2 v10.2d, v13.4s, v13.4s +; CHECK: sqdmull.4s v10, v12, v12 ; encoding: [0x8a,0xd1,0x6c,0x0e] +; CHECK: sqdmull2.4s v10, v13, v13 ; encoding: [0xaa,0xd1,0x6d,0x4e] +; CHECK: sqdmull.2d v10, v13, v13 ; encoding: [0xaa,0xd1,0xad,0x0e] +; CHECK: sqdmull2.2d v10, v13, v13 ; encoding: [0xaa,0xd1,0xad,0x4e] + +; xtn verbose mode aliases + xtn v14.8b, v14.8h + xtn2 v14.16b, v14.8h + xtn v14.4h, v14.4s + xtn2 v14.8h, v14.4s + xtn v14.2s, v14.2d + xtn2 v14.4s, v14.2d +; CHECK: xtn.8b v14, v14 ; encoding: [0xce,0x29,0x21,0x0e] +; CHECK: xtn2.16b v14, v14 ; encoding: [0xce,0x29,0x21,0x4e] +; CHECK: xtn.4h v14, v14 ; encoding: [0xce,0x29,0x61,0x0e] +; CHECK: xtn2.8h v14, v14 ; encoding: [0xce,0x29,0x61,0x4e] +; CHECK: xtn.2s v14, v14 ; encoding: [0xce,0x29,0xa1,0x0e] +; CHECK: xtn2.4s v14, v14 ; encoding: [0xce,0x29,0xa1,0x4e] + +; uaddl verbose mode aliases + uaddl v9.8h, v13.8b, v14.8b + uaddl2 v9.8h, v13.16b, v14.16b + uaddl v9.4s, v13.4h, v14.4h + uaddl2 v9.4s, v13.8h, v14.8h + uaddl v9.2d, v13.2s, v14.2s + uaddl2 v9.2d, v13.4s, v14.4s +; CHECK: uaddl.8h v9, v13, v14 ; encoding: [0xa9,0x01,0x2e,0x2e] +; CHECK: uaddl2.8h v9, v13, v14 ; encoding: [0xa9,0x01,0x2e,0x6e] +; CHECK: uaddl.4s v9, v13, v14 ; encoding: [0xa9,0x01,0x6e,0x2e] +; CHECK: uaddl2.4s v9, v13, v14 ; encoding: [0xa9,0x01,0x6e,0x6e] +; CHECK: uaddl.2d v9, v13, v14 ; encoding: [0xa9,0x01,0xae,0x2e] +; CHECK: uaddl2.2d v9, v13, v14 ; encoding: [0xa9,0x01,0xae,0x6e] + +; bit verbose mode aliases + bit v9.16b, v10.16b, v10.16b + bit v9.8b, v10.8b, v10.8b +; CHECK: bit.16b v9, v10, v10 ; encoding: [0x49,0x1d,0xaa,0x6e] +; CHECK: bit.8b v9, v10, v10 ; encoding: [0x49,0x1d,0xaa,0x2e] + +; pmull verbose mode aliases + pmull v8.8h, v8.8b, v8.8b + pmull2 v8.8h, v8.16b, v8.16b + pmull v8.1q, v8.1d, v8.1d + pmull2 v8.1q, v8.2d, v8.2d +; CHECK: pmull.8h v8, v8, v8 ; encoding: [0x08,0xe1,0x28,0x0e] +; CHECK: pmull2.8h v8, v8, v8 ; encoding: [0x08,0xe1,0x28,0x4e] +; CHECK: pmull.1q v8, v8, v8 ; encoding: [0x08,0xe1,0xe8,0x0e] +; CHECK: pmull2.1q v8, v8, v8 ; encoding: [0x08,0xe1,0xe8,0x4e] + +; usubl verbose mode aliases + usubl v9.8h, v13.8b, v14.8b + usubl2 v9.8h, v13.16b, v14.16b + usubl v9.4s, v13.4h, v14.4h + usubl2 v9.4s, v13.8h, v14.8h + usubl v9.2d, v13.2s, v14.2s + usubl2 v9.2d, v13.4s, v14.4s +; CHECK: usubl.8h v9, v13, v14 ; encoding: [0xa9,0x21,0x2e,0x2e] +; CHECK: usubl2.8h v9, v13, v14 ; encoding: [0xa9,0x21,0x2e,0x6e] +; CHECK: usubl.4s v9, v13, v14 ; encoding: [0xa9,0x21,0x6e,0x2e] +; CHECK: usubl2.4s v9, v13, v14 ; encoding: [0xa9,0x21,0x6e,0x6e] +; CHECK: usubl.2d v9, v13, v14 ; encoding: [0xa9,0x21,0xae,0x2e] +; CHECK: usubl2.2d v9, v13, v14 ; encoding: [0xa9,0x21,0xae,0x6e] + +; uabdl verbose mode aliases + uabdl v9.8h, v13.8b, v14.8b + uabdl2 v9.8h, v13.16b, v14.16b + uabdl v9.4s, v13.4h, v14.4h + uabdl2 v9.4s, v13.8h, v14.8h + uabdl v9.2d, v13.2s, v14.2s + uabdl2 v9.2d, v13.4s, v14.4s +; CHECK: uabdl.8h v9, v13, v14 ; encoding: [0xa9,0x71,0x2e,0x2e] +; CHECK: uabdl2.8h v9, v13, v14 ; encoding: [0xa9,0x71,0x2e,0x6e] +; CHECK: uabdl.4s v9, v13, v14 ; encoding: [0xa9,0x71,0x6e,0x2e] +; CHECK: uabdl2.4s v9, v13, v14 ; encoding: [0xa9,0x71,0x6e,0x6e] +; CHECK: uabdl.2d v9, v13, v14 ; encoding: [0xa9,0x71,0xae,0x2e] +; CHECK: uabdl2.2d v9, v13, v14 ; encoding: [0xa9,0x71,0xae,0x6e] + +; umull verbose mode aliases + umull v9.8h, v13.8b, v14.8b + umull2 v9.8h, v13.16b, v14.16b + umull v9.4s, v13.4h, v14.4h + umull2 v9.4s, v13.8h, v14.8h + umull v9.2d, v13.2s, v14.2s + umull2 v9.2d, v13.4s, v14.4s +; CHECK: umull.8h v9, v13, v14 ; encoding: [0xa9,0xc1,0x2e,0x2e] +; CHECK: umull2.8h v9, v13, v14 ; encoding: [0xa9,0xc1,0x2e,0x6e] +; CHECK: umull.4s v9, v13, v14 ; encoding: [0xa9,0xc1,0x6e,0x2e] +; CHECK: umull2.4s v9, v13, v14 ; encoding: [0xa9,0xc1,0x6e,0x6e] +; CHECK: umull.2d v9, v13, v14 ; encoding: [0xa9,0xc1,0xae,0x2e] +; CHECK: umull2.2d v9, v13, v14 ; encoding: [0xa9,0xc1,0xae,0x6e] + +; smull verbose mode aliases + smull v9.8h, v13.8b, v14.8b + smull2 v9.8h, v13.16b, v14.16b + smull v9.4s, v13.4h, v14.4h + smull2 v9.4s, v13.8h, v14.8h + smull v9.2d, v13.2s, v14.2s + smull2 v9.2d, v13.4s, v14.4s +; CHECK: smull.8h v9, v13, v14 ; encoding: [0xa9,0xc1,0x2e,0x0e] +; CHECK: smull2.8h v9, v13, v14 ; encoding: [0xa9,0xc1,0x2e,0x4e] +; CHECK: smull.4s v9, v13, v14 ; encoding: [0xa9,0xc1,0x6e,0x0e] +; CHECK: smull2.4s v9, v13, v14 ; encoding: [0xa9,0xc1,0x6e,0x4e] +; CHECK: smull.2d v9, v13, v14 ; encoding: [0xa9,0xc1,0xae,0x0e] +; CHECK: smull2.2d v9, v13, v14 ; encoding: [0xa9,0xc1,0xae,0x4e] diff --git a/test/MC/AArch64/arm64-aliases.s b/test/MC/AArch64/arm64-aliases.s new file mode 100644 index 0000000..c3affe3 --- /dev/null +++ b/test/MC/AArch64/arm64-aliases.s @@ -0,0 +1,753 @@ +; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -output-asm-variant=1 -show-encoding < %s | FileCheck %s + +foo: +;----------------------------------------------------------------------------- +; ADD #0 to/from SP/WSP is a MOV +;----------------------------------------------------------------------------- + add x1, sp, #0 +; CHECK: mov x1, sp + add sp, x2, #0 +; CHECK: mov sp, x2 + add w3, wsp, #0 +; CHECK: mov w3, wsp + add wsp, w4, #0 +; CHECK: mov wsp, w4 + mov x5, sp +; CHECK: mov x5, sp + mov sp, x6 +; CHECK: mov sp, x6 + mov w7, wsp +; CHECK: mov w7, wsp + mov wsp, w8 +; CHECK: mov wsp, w8 + +;----------------------------------------------------------------------------- +; ORR Rd, Rn, Rn is a MOV +;----------------------------------------------------------------------------- + orr x2, xzr, x9 +; CHECK: mov x2, x9 + orr w2, wzr, w9 +; CHECK: mov w2, w9 + mov x3, x4 +; CHECK: mov x3, x4 + mov w5, w6 +; CHECK: mov w5, w6 + +;----------------------------------------------------------------------------- +; TST Xn, #<imm> +;----------------------------------------------------------------------------- + tst w1, #3 + tst x1, #3 + tst w1, w2 + tst x1, x2 + ands wzr, w1, w2, lsl #2 + ands xzr, x1, x2, lsl #3 + tst w3, w7, lsl #31 + tst x2, x20, asr #0 + +; CHECK: tst w1, #0x3 ; encoding: [0x3f,0x04,0x00,0x72] +; CHECK: tst x1, #0x3 ; encoding: [0x3f,0x04,0x40,0xf2] +; CHECK: tst w1, w2 ; encoding: [0x3f,0x00,0x02,0x6a] +; CHECK: tst x1, x2 ; encoding: [0x3f,0x00,0x02,0xea] +; CHECK: tst w1, w2, lsl #2 ; encoding: [0x3f,0x08,0x02,0x6a] +; CHECK: tst x1, x2, lsl #3 ; encoding: [0x3f,0x0c,0x02,0xea] +; CHECK: tst w3, w7, lsl #31 ; encoding: [0x7f,0x7c,0x07,0x6a] +; CHECK: tst x2, x20, asr #0 ; encoding: [0x5f,0x00,0x94,0xea] + +;----------------------------------------------------------------------------- +; ADDS to WZR/XZR is a CMN +;----------------------------------------------------------------------------- + cmn w1, #3, lsl #0 + cmn x2, #4194304 + cmn w4, w5 + cmn x6, x7 + cmn w8, w9, asr #3 + cmn x2, x3, lsr #4 + cmn x2, w3, uxtb #1 + cmn x4, x5, uxtx #1 + +; CHECK: cmn w1, #3 ; encoding: [0x3f,0x0c,0x00,0x31] +; CHECK: cmn x2, #1024, lsl #12 ; encoding: [0x5f,0x00,0x50,0xb1] +; CHECK: cmn w4, w5 ; encoding: [0x9f,0x00,0x05,0x2b] +; CHECK: cmn x6, x7 ; encoding: [0xdf,0x00,0x07,0xab] +; CHECK: cmn w8, w9, asr #3 ; encoding: [0x1f,0x0d,0x89,0x2b] +; CHECK: cmn x2, x3, lsr #4 ; encoding: [0x5f,0x10,0x43,0xab] +; CHECK: cmn x2, w3, uxtb #1 ; encoding: [0x5f,0x04,0x23,0xab] +; CHECK: cmn x4, x5, uxtx #1 ; encoding: [0x9f,0x64,0x25,0xab] + + +;----------------------------------------------------------------------------- +; SUBS to WZR/XZR is a CMP +;----------------------------------------------------------------------------- + cmp w1, #1024, lsl #12 + cmp x2, #1024 + cmp w4, w5 + cmp x6, x7 + cmp w8, w9, asr #3 + cmp x2, x3, lsr #4 + cmp x2, w3, uxth #2 + cmp x4, x5, uxtx + cmp wzr, w1 + cmp x8, w8, uxtw + cmp w9, w8, uxtw + cmp wsp, w9, lsl #0 + +; CHECK: cmp w1, #1024, lsl #12 ; encoding: [0x3f,0x00,0x50,0x71] +; CHECK: cmp x2, #1024 ; encoding: [0x5f,0x00,0x10,0xf1] +; CHECK: cmp w4, w5 ; encoding: [0x9f,0x00,0x05,0x6b] +; CHECK: cmp x6, x7 ; encoding: [0xdf,0x00,0x07,0xeb] +; CHECK: cmp w8, w9, asr #3 ; encoding: [0x1f,0x0d,0x89,0x6b] +; CHECK: cmp x2, x3, lsr #4 ; encoding: [0x5f,0x10,0x43,0xeb] +; CHECK: cmp x2, w3, uxth #2 ; encoding: [0x5f,0x28,0x23,0xeb] +; CHECK: cmp x4, x5, uxtx ; encoding: [0x9f,0x60,0x25,0xeb] +; CHECK: cmp wzr, w1 ; encoding: [0xff,0x03,0x01,0x6b] +; CHECK: cmp x8, w8, uxtw ; encoding: [0x1f,0x41,0x28,0xeb] +; CHECK: cmp w9, w8, uxtw ; encoding: [0x3f,0x41,0x28,0x6b] +; CHECK: cmp wsp, w9 ; encoding: [0xff,0x43,0x29,0x6b] + + +;----------------------------------------------------------------------------- +; SUB/SUBS from WZR/XZR is a NEG +;----------------------------------------------------------------------------- + + neg w0, w1 +; CHECK: neg w0, w1 + neg w0, w1, lsl #1 +; CHECK: neg w0, w1, lsl #1 + neg x0, x1 +; CHECK: neg x0, x1 + neg x0, x1, asr #1 +; CHECK: neg x0, x1, asr #1 + negs w0, w1 +; CHECK: negs w0, w1 + negs w0, w1, lsl #1 +; CHECK: negs w0, w1, lsl #1 + negs x0, x1 +; CHECK: negs x0, x1 + negs x0, x1, asr #1 +; CHECK: negs x0, x1, asr #1 + +;----------------------------------------------------------------------------- +; MOV aliases +;----------------------------------------------------------------------------- + + mov x0, #281470681743360 + mov x0, #18446744073709486080 + +; CHECK: movz x0, #0xffff, lsl #32 +; CHECK: movn x0, #0xffff + + mov w0, #0xffffffff + mov w0, #0xffffff00 + mov wzr, #0xffffffff + mov wzr, #0xffffff00 + +; CHECK: movn w0, #0 +; CHECK: movn w0, #0xff +; CHECK: movn wzr, #0 +; CHECK: movn wzr, #0xff + +;----------------------------------------------------------------------------- +; MVN aliases +;----------------------------------------------------------------------------- + + mvn w4, w9 + mvn x2, x3 + orn w4, wzr, w9 + +; CHECK: mvn w4, w9 ; encoding: [0xe4,0x03,0x29,0x2a] +; CHECK: mvn x2, x3 ; encoding: [0xe2,0x03,0x23,0xaa] +; CHECK: mvn w4, w9 ; encoding: [0xe4,0x03,0x29,0x2a] + + mvn w4, w9, lsl #1 + mvn x2, x3, lsl #1 + orn w4, wzr, w9, lsl #1 + +; CHECK: mvn w4, w9, lsl #1 ; encoding: [0xe4,0x07,0x29,0x2a] +; CHECK: mvn x2, x3, lsl #1 ; encoding: [0xe2,0x07,0x23,0xaa] +; CHECK: mvn w4, w9, lsl #1 ; encoding: [0xe4,0x07,0x29,0x2a] + +;----------------------------------------------------------------------------- +; Bitfield aliases +;----------------------------------------------------------------------------- + + bfi w0, w0, #1, #4 + bfi x0, x0, #1, #4 + bfi w0, w0, #0, #2 + bfi x0, x0, #0, #2 + bfxil w0, w0, #2, #3 + bfxil x0, x0, #2, #3 + sbfiz w0, w0, #1, #4 + sbfiz x0, x0, #1, #4 + sbfx w0, w0, #2, #3 + sbfx x0, x0, #2, #3 + ubfiz w0, w0, #1, #4 + ubfiz x0, x0, #1, #4 + ubfx w0, w0, #2, #3 + ubfx x0, x0, #2, #3 + +; CHECK: bfi w0, w0, #1, #4 +; CHECK: bfi x0, x0, #1, #4 +; CHECK: bfxil w0, w0, #0, #2 +; CHECK: bfxil x0, x0, #0, #2 +; CHECK: bfxil w0, w0, #2, #3 +; CHECK: bfxil x0, x0, #2, #3 +; CHECK: sbfiz w0, w0, #1, #4 +; CHECK: sbfiz x0, x0, #1, #4 +; CHECK: sbfx w0, w0, #2, #3 +; CHECK: sbfx x0, x0, #2, #3 +; CHECK: ubfiz w0, w0, #1, #4 +; CHECK: ubfiz x0, x0, #1, #4 +; CHECK: ubfx w0, w0, #2, #3 +; CHECK: ubfx x0, x0, #2, #3 + +;----------------------------------------------------------------------------- +; Shift (immediate) aliases +;----------------------------------------------------------------------------- + +; CHECK: asr w1, w3, #13 +; CHECK: asr x1, x3, #13 +; CHECK: lsl w0, w0, #1 +; CHECK: lsl x0, x0, #1 +; CHECK: lsr w0, w0, #4 +; CHECK: lsr x0, x0, #4 + + sbfm w1, w3, #13, #31 + sbfm x1, x3, #13, #63 + ubfm w0, w0, #31, #30 + ubfm x0, x0, #63, #62 + ubfm w0, w0, #4, #31 + ubfm x0, x0, #4, #63 +; CHECK: ror w1, w3, #5 +; CHECK: ror x1, x3, #5 + ror w1, w3, #5 + ror x1, x3, #5 +; CHECK: lsl w1, wzr, #3 + lsl w1, wzr, #3 + +;----------------------------------------------------------------------------- +; Sign/Zero extend aliases +;----------------------------------------------------------------------------- + + sxtb w1, w2 + sxth w1, w2 + uxtb w1, w2 + uxth w1, w2 + +; CHECK: sxtb w1, w2 +; CHECK: sxth w1, w2 +; CHECK: uxtb w1, w2 +; CHECK: uxth w1, w2 + + sxtb x1, w2 + sxth x1, w2 + sxtw x1, w2 + uxtb x1, w2 + uxth x1, w2 + uxtw x1, w2 + +; CHECK: sxtb x1, w2 +; CHECK: sxth x1, w2 +; CHECK: sxtw x1, w2 +; CHECK: uxtb w1, w2 +; CHECK: uxth w1, w2 +; CHECK: ubfx x1, x2, #0, #32 + +;----------------------------------------------------------------------------- +; Negate with carry +;----------------------------------------------------------------------------- + + ngc w1, w2 + ngc x1, x2 + ngcs w1, w2 + ngcs x1, x2 + +; CHECK: ngc w1, w2 +; CHECK: ngc x1, x2 +; CHECK: ngcs w1, w2 +; CHECK: ngcs x1, x2 + +;----------------------------------------------------------------------------- +; 6.6.1 Multiply aliases +;----------------------------------------------------------------------------- + + mneg w1, w2, w3 + mneg x1, x2, x3 + mul w1, w2, w3 + mul x1, x2, x3 + smnegl x1, w2, w3 + umnegl x1, w2, w3 + smull x1, w2, w3 + umull x1, w2, w3 + +; CHECK: mneg w1, w2, w3 +; CHECK: mneg x1, x2, x3 +; CHECK: mul w1, w2, w3 +; CHECK: mul x1, x2, x3 +; CHECK: smnegl x1, w2, w3 +; CHECK: umnegl x1, w2, w3 +; CHECK: smull x1, w2, w3 +; CHECK: umull x1, w2, w3 + +;----------------------------------------------------------------------------- +; Conditional select aliases +;----------------------------------------------------------------------------- + + cset w1, eq + cset x1, eq + csetm w1, ne + csetm x1, ne + cinc w1, w2, lt + cinc x1, x2, lt + cinv w1, w2, mi + cinv x1, x2, mi + +; CHECK: cset w1, eq +; CHECK: cset x1, eq +; CHECK: csetm w1, ne +; CHECK: csetm x1, ne +; CHECK: cinc w1, w2, lt +; CHECK: cinc x1, x2, lt +; CHECK: cinv w1, w2, mi +; CHECK: cinv x1, x2, mi + +;----------------------------------------------------------------------------- +; SYS aliases +;----------------------------------------------------------------------------- + + sys #0, c7, c1, #0 +; CHECK: ic ialluis + sys #0, c7, c5, #0 +; CHECK: ic iallu + sys #3, c7, c5, #1 +; CHECK: ic ivau + + sys #3, c7, c4, #1 +; CHECK: dc zva + sys #0, c7, c6, #1 +; CHECK: dc ivac + sys #0, c7, c6, #2 +; CHECK: dc isw + sys #3, c7, c10, #1 +; CHECK: dc cvac + sys #0, c7, c10, #2 +; CHECK: dc csw + sys #3, c7, c11, #1 +; CHECK: dc cvau + sys #3, c7, c14, #1 +; CHECK: dc civac + sys #0, c7, c14, #2 +; CHECK: dc cisw + + sys #0, c7, c8, #0 +; CHECK: at s1e1r + sys #4, c7, c8, #0 +; CHECK: at s1e2r + sys #6, c7, c8, #0 +; CHECK: at s1e3r + sys #0, c7, c8, #1 +; CHECK: at s1e1w + sys #4, c7, c8, #1 +; CHECK: at s1e2w + sys #6, c7, c8, #1 +; CHECK: at s1e3w + sys #0, c7, c8, #2 +; CHECK: at s1e0r + sys #0, c7, c8, #3 +; CHECK: at s1e0w + sys #4, c7, c8, #4 +; CHECK: at s12e1r + sys #4, c7, c8, #5 +; CHECK: at s12e1w + sys #4, c7, c8, #6 +; CHECK: at s12e0r + sys #4, c7, c8, #7 +; CHECK: at s12e0w + + sys #0, c8, c3, #0 +; CHECK: tlbi vmalle1is + sys #4, c8, c3, #0 +; CHECK: tlbi alle2is + sys #6, c8, c3, #0 +; CHECK: tlbi alle3is + sys #0, c8, c3, #1 +; CHECK: tlbi vae1is + sys #4, c8, c3, #1 +; CHECK: tlbi vae2is + sys #6, c8, c3, #1 +; CHECK: tlbi vae3is + sys #0, c8, c3, #2 +; CHECK: tlbi aside1is + sys #0, c8, c3, #3 +; CHECK: tlbi vaae1is + sys #4, c8, c3, #4 +; CHECK: tlbi alle1is + sys #0, c8, c3, #5 +; CHECK: tlbi vale1is + sys #0, c8, c3, #7 +; CHECK: tlbi vaale1is + sys #0, c8, c7, #0 +; CHECK: tlbi vmalle1 + sys #4, c8, c7, #0 +; CHECK: tlbi alle2 + sys #4, c8, c3, #5 +; CHECK: tlbi vale2is + sys #6, c8, c3, #5 +; CHECK: tlbi vale3is + sys #6, c8, c7, #0 +; CHECK: tlbi alle3 + sys #0, c8, c7, #1 +; CHECK: tlbi vae1 + sys #4, c8, c7, #1 +; CHECK: tlbi vae2 + sys #6, c8, c7, #1 +; CHECK: tlbi vae3 + sys #0, c8, c7, #2 +; CHECK: tlbi aside1 + sys #0, c8, c7, #3 +; CHECK: tlbi vaae1 + sys #4, c8, c7, #4 +; CHECK: tlbi alle1 + sys #0, c8, c7, #5 +; CHECK: tlbi vale1 + sys #4, c8, c7, #5 +; CHECK: tlbi vale2 + sys #6, c8, c7, #5 +; CHECK: tlbi vale3 + sys #0, c8, c7, #7 +; CHECK: tlbi vaale1 + sys #4, c8, c4, #1 +; CHECK: tlbi ipas2e1 + sys #4, c8, c4, #5 +; CHECK: tlbi ipas2le1 + sys #4, c8, c0, #1 +; CHECK: tlbi ipas2e1is + sys #4, c8, c0, #5 +; CHECK: tlbi ipas2le1is + sys #4, c8, c7, #6 +; CHECK: tlbi vmalls12e1 + sys #4, c8, c3, #6 +; CHECK: tlbi vmalls12e1is + + ic ialluis +; CHECK: ic ialluis ; encoding: [0x1f,0x71,0x08,0xd5] + ic iallu +; CHECK: ic iallu ; encoding: [0x1f,0x75,0x08,0xd5] + ic ivau, x0 +; CHECK: ic ivau, x0 ; encoding: [0x20,0x75,0x0b,0xd5] + + dc zva, x0 +; CHECK: dc zva, x0 ; encoding: [0x20,0x74,0x0b,0xd5] + dc ivac, x0 +; CHECK: dc ivac, x0 ; encoding: [0x20,0x76,0x08,0xd5] + dc isw, x0 +; CHECK: dc isw, x0 ; encoding: [0x40,0x76,0x08,0xd5] + dc cvac, x0 +; CHECK: dc cvac, x0 ; encoding: [0x20,0x7a,0x0b,0xd5] + dc csw, x0 +; CHECK: dc csw, x0 ; encoding: [0x40,0x7a,0x08,0xd5] + dc cvau, x0 +; CHECK: dc cvau, x0 ; encoding: [0x20,0x7b,0x0b,0xd5] + dc civac, x0 +; CHECK: dc civac, x0 ; encoding: [0x20,0x7e,0x0b,0xd5] + dc cisw, x0 +; CHECK: dc cisw, x0 ; encoding: [0x40,0x7e,0x08,0xd5] + + at s1e1r, x0 +; CHECK: at s1e1r, x0 ; encoding: [0x00,0x78,0x08,0xd5] + at s1e2r, x0 +; CHECK: at s1e2r, x0 ; encoding: [0x00,0x78,0x0c,0xd5] + at s1e3r, x0 +; CHECK: at s1e3r, x0 ; encoding: [0x00,0x78,0x0e,0xd5] + at s1e1w, x0 +; CHECK: at s1e1w, x0 ; encoding: [0x20,0x78,0x08,0xd5] + at s1e2w, x0 +; CHECK: at s1e2w, x0 ; encoding: [0x20,0x78,0x0c,0xd5] + at s1e3w, x0 +; CHECK: at s1e3w, x0 ; encoding: [0x20,0x78,0x0e,0xd5] + at s1e0r, x0 +; CHECK: at s1e0r, x0 ; encoding: [0x40,0x78,0x08,0xd5] + at s1e0w, x0 +; CHECK: at s1e0w, x0 ; encoding: [0x60,0x78,0x08,0xd5] + at s12e1r, x0 +; CHECK: at s12e1r, x0 ; encoding: [0x80,0x78,0x0c,0xd5] + at s12e1w, x0 +; CHECK: at s12e1w, x0 ; encoding: [0xa0,0x78,0x0c,0xd5] + at s12e0r, x0 +; CHECK: at s12e0r, x0 ; encoding: [0xc0,0x78,0x0c,0xd5] + at s12e0w, x0 +; CHECK: at s12e0w, x0 ; encoding: [0xe0,0x78,0x0c,0xd5] + + tlbi vmalle1is +; CHECK: tlbi vmalle1is ; encoding: [0x1f,0x83,0x08,0xd5] + tlbi alle2is +; CHECK: tlbi alle2is ; encoding: [0x1f,0x83,0x0c,0xd5] + tlbi alle3is +; CHECK: tlbi alle3is ; encoding: [0x1f,0x83,0x0e,0xd5] + tlbi vae1is, x0 +; CHECK: tlbi vae1is, x0 ; encoding: [0x20,0x83,0x08,0xd5] + tlbi vae2is, x0 +; CHECK: tlbi vae2is, x0 ; encoding: [0x20,0x83,0x0c,0xd5] + tlbi vae3is, x0 +; CHECK: tlbi vae3is, x0 ; encoding: [0x20,0x83,0x0e,0xd5] + tlbi aside1is, x0 +; CHECK: tlbi aside1is, x0 ; encoding: [0x40,0x83,0x08,0xd5] + tlbi vaae1is, x0 +; CHECK: tlbi vaae1is, x0 ; encoding: [0x60,0x83,0x08,0xd5] + tlbi alle1is +; CHECK: tlbi alle1is ; encoding: [0x9f,0x83,0x0c,0xd5] + tlbi vale1is, x0 +; CHECK: tlbi vale1is, x0 ; encoding: [0xa0,0x83,0x08,0xd5] + tlbi vaale1is, x0 +; CHECK: tlbi vaale1is, x0 ; encoding: [0xe0,0x83,0x08,0xd5] + tlbi vmalle1 +; CHECK: tlbi vmalle1 ; encoding: [0x1f,0x87,0x08,0xd5] + tlbi alle2 +; CHECK: tlbi alle2 ; encoding: [0x1f,0x87,0x0c,0xd5] + tlbi vale2is, x0 +; CHECK: tlbi vale2is, x0 ; encoding: [0xa0,0x83,0x0c,0xd5] + tlbi vale3is, x0 +; CHECK: tlbi vale3is, x0 ; encoding: [0xa0,0x83,0x0e,0xd5] + tlbi alle3 +; CHECK: tlbi alle3 ; encoding: [0x1f,0x87,0x0e,0xd5] + tlbi vae1, x0 +; CHECK: tlbi vae1, x0 ; encoding: [0x20,0x87,0x08,0xd5] + tlbi vae2, x0 +; CHECK: tlbi vae2, x0 ; encoding: [0x20,0x87,0x0c,0xd5] + tlbi vae3, x0 +; CHECK: tlbi vae3, x0 ; encoding: [0x20,0x87,0x0e,0xd5] + tlbi aside1, x0 +; CHECK: tlbi aside1, x0 ; encoding: [0x40,0x87,0x08,0xd5] + tlbi vaae1, x0 +; CHECK: tlbi vaae1, x0 ; encoding: [0x60,0x87,0x08,0xd5] + tlbi alle1 +; CHECK: tlbi alle1 ; encoding: [0x9f,0x87,0x0c,0xd5 + tlbi vale1, x0 +; CHECK: tlbi vale1, x0 ; encoding: [0xa0,0x87,0x08,0xd5] + tlbi vale2, x0 +; CHECK: tlbi vale2, x0 ; encoding: [0xa0,0x87,0x0c,0xd5] + tlbi vale3, x0 +; CHECK: tlbi vale3, x0 ; encoding: [0xa0,0x87,0x0e,0xd5] + tlbi vaale1, x0 +; CHECK: tlbi vaale1, x0 ; encoding: [0xe0,0x87,0x08,0xd5] + tlbi ipas2e1, x0 +; CHECK: tlbi ipas2e1, x0 ; encoding: [0x20,0x84,0x0c,0xd5] + tlbi ipas2le1, x0 +; CHECK: tlbi ipas2le1, x0 ; encoding: [0xa0,0x84,0x0c,0xd5] + tlbi ipas2e1is, x0 +; CHECK: tlbi ipas2e1is, x0 ; encoding: [0x20,0x80,0x0c,0xd5] + tlbi ipas2le1is, x0 +; CHECK: tlbi ipas2le1is, x0 ; encoding: [0xa0,0x80,0x0c,0xd5] + tlbi vmalls12e1 +; CHECK: tlbi vmalls12e1 ; encoding: [0xdf,0x87,0x0c,0xd5] + tlbi vmalls12e1is +; CHECK: tlbi vmalls12e1is ; encoding: [0xdf,0x83,0x0c,0xd5] + +;----------------------------------------------------------------------------- +; 5.8.5 Vector Arithmetic aliases +;----------------------------------------------------------------------------- + + cmls.8b v0, v2, v1 + cmls.16b v0, v2, v1 + cmls.4h v0, v2, v1 + cmls.8h v0, v2, v1 + cmls.2s v0, v2, v1 + cmls.4s v0, v2, v1 + cmls.2d v0, v2, v1 +; CHECK: cmhs.8b v0, v1, v2 +; CHECK: cmhs.16b v0, v1, v2 +; CHECK: cmhs.4h v0, v1, v2 +; CHECK: cmhs.8h v0, v1, v2 +; CHECK: cmhs.2s v0, v1, v2 +; CHECK: cmhs.4s v0, v1, v2 +; CHECK: cmhs.2d v0, v1, v2 + + cmlo.8b v0, v2, v1 + cmlo.16b v0, v2, v1 + cmlo.4h v0, v2, v1 + cmlo.8h v0, v2, v1 + cmlo.2s v0, v2, v1 + cmlo.4s v0, v2, v1 + cmlo.2d v0, v2, v1 +; CHECK: cmhi.8b v0, v1, v2 +; CHECK: cmhi.16b v0, v1, v2 +; CHECK: cmhi.4h v0, v1, v2 +; CHECK: cmhi.8h v0, v1, v2 +; CHECK: cmhi.2s v0, v1, v2 +; CHECK: cmhi.4s v0, v1, v2 +; CHECK: cmhi.2d v0, v1, v2 + + cmle.8b v0, v2, v1 + cmle.16b v0, v2, v1 + cmle.4h v0, v2, v1 + cmle.8h v0, v2, v1 + cmle.2s v0, v2, v1 + cmle.4s v0, v2, v1 + cmle.2d v0, v2, v1 +; CHECK: cmge.8b v0, v1, v2 +; CHECK: cmge.16b v0, v1, v2 +; CHECK: cmge.4h v0, v1, v2 +; CHECK: cmge.8h v0, v1, v2 +; CHECK: cmge.2s v0, v1, v2 +; CHECK: cmge.4s v0, v1, v2 +; CHECK: cmge.2d v0, v1, v2 + + cmlt.8b v0, v2, v1 + cmlt.16b v0, v2, v1 + cmlt.4h v0, v2, v1 + cmlt.8h v0, v2, v1 + cmlt.2s v0, v2, v1 + cmlt.4s v0, v2, v1 + cmlt.2d v0, v2, v1 +; CHECK: cmgt.8b v0, v1, v2 +; CHECK: cmgt.16b v0, v1, v2 +; CHECK: cmgt.4h v0, v1, v2 +; CHECK: cmgt.8h v0, v1, v2 +; CHECK: cmgt.2s v0, v1, v2 +; CHECK: cmgt.4s v0, v1, v2 +; CHECK: cmgt.2d v0, v1, v2 + + fcmle.2s v0, v2, v1 + fcmle.4s v0, v2, v1 + fcmle.2d v0, v2, v1 +; CHECK: fcmge.2s v0, v1, v2 +; CHECK: fcmge.4s v0, v1, v2 +; CHECK: fcmge.2d v0, v1, v2 + + fcmlt.2s v0, v2, v1 + fcmlt.4s v0, v2, v1 + fcmlt.2d v0, v2, v1 +; CHECK: fcmgt.2s v0, v1, v2 +; CHECK: fcmgt.4s v0, v1, v2 +; CHECK: fcmgt.2d v0, v1, v2 + + facle.2s v0, v2, v1 + facle.4s v0, v2, v1 + facle.2d v0, v2, v1 +; CHECK: facge.2s v0, v1, v2 +; CHECK: facge.4s v0, v1, v2 +; CHECK: facge.2d v0, v1, v2 + + faclt.2s v0, v2, v1 + faclt.4s v0, v2, v1 + faclt.2d v0, v2, v1 +; CHECK: facgt.2s v0, v1, v2 +; CHECK: facgt.4s v0, v1, v2 +; CHECK: facgt.2d v0, v1, v2 + +;----------------------------------------------------------------------------- +; 5.8.6 Scalar Arithmetic aliases +;----------------------------------------------------------------------------- + + cmls d0, d2, d1 +; CHECK: cmhs d0, d1, d2 + + cmle d0, d2, d1 +; CHECK: cmge d0, d1, d2 + + cmlo d0, d2, d1 +; CHECK: cmhi d0, d1, d2 + + cmlt d0, d2, d1 +; CHECK: cmgt d0, d1, d2 + + fcmle s0, s2, s1 + fcmle d0, d2, d1 +; CHECK: fcmge s0, s1, s2 +; CHECK: fcmge d0, d1, d2 + + fcmlt s0, s2, s1 + fcmlt d0, d2, d1 +; CHECK: fcmgt s0, s1, s2 +; CHECK: fcmgt d0, d1, d2 + + facle s0, s2, s1 + facle d0, d2, d1 +; CHECK: facge s0, s1, s2 +; CHECK: facge d0, d1, d2 + + faclt s0, s2, s1 + faclt d0, d2, d1 +; CHECK: facgt s0, s1, s2 +; CHECK: facgt d0, d1, d2 + +;----------------------------------------------------------------------------- +; 5.8.14 Vector Shift (immediate) +;----------------------------------------------------------------------------- + sxtl v1.8h, v2.8b +; CHECK: sshll.8h v1, v2, #0 + sxtl.8h v1, v2 +; CHECK: sshll.8h v1, v2, #0 + + sxtl v1.4s, v2.4h +; CHECK: sshll.4s v1, v2, #0 + sxtl.4s v1, v2 +; CHECK: sshll.4s v1, v2, #0 + + sxtl v1.2d, v2.2s +; CHECK: sshll.2d v1, v2, #0 + sxtl.2d v1, v2 +; CHECK: sshll.2d v1, v2, #0 + + sxtl2 v1.8h, v2.16b +; CHECK: sshll2.8h v1, v2, #0 + sxtl2.8h v1, v2 +; CHECK: sshll2.8h v1, v2, #0 + + sxtl2 v1.4s, v2.8h +; CHECK: sshll2.4s v1, v2, #0 + sxtl2.4s v1, v2 +; CHECK: sshll2.4s v1, v2, #0 + + sxtl2 v1.2d, v2.4s +; CHECK: sshll2.2d v1, v2, #0 + sxtl2.2d v1, v2 +; CHECK: sshll2.2d v1, v2, #0 + + uxtl v1.8h, v2.8b +; CHECK: ushll.8h v1, v2, #0 + uxtl.8h v1, v2 +; CHECK: ushll.8h v1, v2, #0 + + uxtl v1.4s, v2.4h +; CHECK: ushll.4s v1, v2, #0 + uxtl.4s v1, v2 +; CHECK: ushll.4s v1, v2, #0 + + uxtl v1.2d, v2.2s +; CHECK: ushll.2d v1, v2, #0 + uxtl.2d v1, v2 +; CHECK: ushll.2d v1, v2, #0 + + uxtl2 v1.8h, v2.16b +; CHECK: ushll2.8h v1, v2, #0 + uxtl2.8h v1, v2 +; CHECK: ushll2.8h v1, v2, #0 + + uxtl2 v1.4s, v2.8h +; CHECK: ushll2.4s v1, v2, #0 + uxtl2.4s v1, v2 +; CHECK: ushll2.4s v1, v2, #0 + + uxtl2 v1.2d, v2.4s +; CHECK: ushll2.2d v1, v2, #0 + uxtl2.2d v1, v2 +; CHECK: ushll2.2d v1, v2, #0 + + +;----------------------------------------------------------------------------- +; MOVI verbose syntax with shift operand omitted. +;----------------------------------------------------------------------------- + movi v4.16b, #0x00 + movi v4.16B, #0x01 + movi v4.8b, #0x02 + movi v4.8B, #0x03 + movi v1.2d, #0x000000000000ff + movi v2.2D, #0x000000000000ff + +; CHECK: movi.16b v4, #0 ; encoding: [0x04,0xe4,0x00,0x4f] +; CHECK: movi.16b v4, #0x1 ; encoding: [0x24,0xe4,0x00,0x4f] +; CHECK: movi.8b v4, #0x2 ; encoding: [0x44,0xe4,0x00,0x0f] +; CHECK: movi.8b v4, #0x3 ; encoding: [0x64,0xe4,0x00,0x0f] +; CHECK: movi.2d v1, #0x000000000000ff ; encoding: [0x21,0xe4,0x00,0x6f] +; CHECK: movi.2d v2, #0x000000000000ff ; encoding: [0x22,0xe4,0x00,0x6f] diff --git a/test/MC/AArch64/arm64-arithmetic-encoding.s b/test/MC/AArch64/arm64-arithmetic-encoding.s new file mode 100644 index 0000000..5fd5912 --- /dev/null +++ b/test/MC/AArch64/arm64-arithmetic-encoding.s @@ -0,0 +1,615 @@ +; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -show-encoding < %s | FileCheck %s + +foo: +;==---------------------------------------------------------------------------== +; Add/Subtract with carry/borrow +;==---------------------------------------------------------------------------== + + adc w1, w2, w3 + adc x1, x2, x3 + adcs w5, w4, w3 + adcs x5, x4, x3 + +; CHECK: adc w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x1a] +; CHECK: adc x1, x2, x3 ; encoding: [0x41,0x00,0x03,0x9a] +; CHECK: adcs w5, w4, w3 ; encoding: [0x85,0x00,0x03,0x3a] +; CHECK: adcs x5, x4, x3 ; encoding: [0x85,0x00,0x03,0xba] + + sbc w1, w2, w3 + sbc x1, x2, x3 + sbcs w1, w2, w3 + sbcs x1, x2, x3 + +; CHECK: sbc w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x5a] +; CHECK: sbc x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xda] +; CHECK: sbcs w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x7a] +; CHECK: sbcs x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xfa] + +;==---------------------------------------------------------------------------== +; Add/Subtract with (optionally shifted) immediate +;==---------------------------------------------------------------------------== + + add w3, w4, #1024 + add w3, w4, #1024, lsl #0 + add x3, x4, #1024 + add x3, x4, #1024, lsl #0 + +; CHECK: add w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x11] +; CHECK: add w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x11] +; CHECK: add x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0x91] +; CHECK: add x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0x91] + + add w3, w4, #1024, lsl #12 + add w3, w4, #4194304 + add w3, w4, #0, lsl #12 + add x3, x4, #1024, lsl #12 + add x3, x4, #4194304 + add x3, x4, #0, lsl #12 + add sp, sp, #32 + +; CHECK: add w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x11] +; CHECK: add w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x11] +; CHECK: add w3, w4, #0, lsl #12 ; encoding: [0x83,0x00,0x40,0x11] +; CHECK: add x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x91] +; CHECK: add x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x91] +; CHECK: add x3, x4, #0, lsl #12 ; encoding: [0x83,0x00,0x40,0x91] +; CHECK: add sp, sp, #32 ; encoding: [0xff,0x83,0x00,0x91] + + adds w3, w4, #1024 + adds w3, w4, #1024, lsl #0 + adds w3, w4, #1024, lsl #12 + adds x3, x4, #1024 + adds x3, x4, #1024, lsl #0 + adds x3, x4, #1024, lsl #12 + +; CHECK: adds w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x31] +; CHECK: adds w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x31] +; CHECK: adds w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x31] +; CHECK: adds x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xb1] +; CHECK: adds x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xb1] +; CHECK: adds x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xb1] + + sub w3, w4, #1024 + sub w3, w4, #1024, lsl #0 + sub w3, w4, #1024, lsl #12 + sub x3, x4, #1024 + sub x3, x4, #1024, lsl #0 + sub x3, x4, #1024, lsl #12 + sub sp, sp, #32 + +; CHECK: sub w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x51] +; CHECK: sub w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x51] +; CHECK: sub w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x51] +; CHECK: sub x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xd1] +; CHECK: sub x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xd1] +; CHECK: sub x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xd1] +; CHECK: sub sp, sp, #32 ; encoding: [0xff,0x83,0x00,0xd1] + + subs w3, w4, #1024 + subs w3, w4, #1024, lsl #0 + subs w3, w4, #1024, lsl #12 + subs x3, x4, #1024 + subs x3, x4, #1024, lsl #0 + subs x3, x4, #1024, lsl #12 + +; CHECK: subs w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x71] +; CHECK: subs w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x71] +; CHECK: subs w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x71] +; CHECK: subs x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xf1] +; CHECK: subs x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xf1] +; CHECK: subs x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xf1] + +;==---------------------------------------------------------------------------== +; Add/Subtract register with (optional) shift +;==---------------------------------------------------------------------------== + + add w12, w13, w14 + add x12, x13, x14 + add w12, w13, w14, lsl #12 + add x12, x13, x14, lsl #12 + add x12, x13, x14, lsr #42 + add x12, x13, x14, asr #39 + +; CHECK: add w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x0b] +; CHECK: add x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0x8b] +; CHECK: add w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x0b] +; CHECK: add x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x8b] +; CHECK: add x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0x8b] +; CHECK: add x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0x8b] + + sub w12, w13, w14 + sub x12, x13, x14 + sub w12, w13, w14, lsl #12 + sub x12, x13, x14, lsl #12 + sub x12, x13, x14, lsr #42 + sub x12, x13, x14, asr #39 + +; CHECK: sub w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x4b] +; CHECK: sub x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0xcb] +; CHECK: sub w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x4b] +; CHECK: sub x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0xcb] +; CHECK: sub x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0xcb] +; CHECK: sub x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xcb] + + adds w12, w13, w14 + adds x12, x13, x14 + adds w12, w13, w14, lsl #12 + adds x12, x13, x14, lsl #12 + adds x12, x13, x14, lsr #42 + adds x12, x13, x14, asr #39 + +; CHECK: adds w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x2b] +; CHECK: adds x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0xab] +; CHECK: adds w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x2b] +; CHECK: adds x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0xab] +; CHECK: adds x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0xab] +; CHECK: adds x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xab] + + subs w12, w13, w14 + subs x12, x13, x14 + subs w12, w13, w14, lsl #12 + subs x12, x13, x14, lsl #12 + subs x12, x13, x14, lsr #42 + subs x12, x13, x14, asr #39 + +; CHECK: subs w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x6b] +; CHECK: subs x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0xeb] +; CHECK: subs w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x6b] +; CHECK: subs x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0xeb] +; CHECK: subs x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0xeb] +; CHECK: subs x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xeb] + +; Check use of upper case register names rdar://14354073 + add X2, X2, X2 +; CHECK: add x2, x2, x2 ; encoding: [0x42,0x00,0x02,0x8b] + +;==---------------------------------------------------------------------------== +; Add/Subtract with (optional) extend +;==---------------------------------------------------------------------------== + + add w1, w2, w3, uxtb + add w1, w2, w3, uxth + add w1, w2, w3, uxtw + add w1, w2, w3, uxtx + add w1, w2, w3, sxtb + add w1, w2, w3, sxth + add w1, w2, w3, sxtw + add w1, w2, w3, sxtx + +; CHECK: add w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x0b] +; CHECK: add w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x0b] +; CHECK: add w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x0b] +; CHECK: add w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x0b] +; CHECK: add w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x0b] +; CHECK: add w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x0b] +; CHECK: add w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x0b] +; CHECK: add w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x0b] + + add x1, x2, w3, uxtb + add x1, x2, w3, uxth + add x1, x2, w3, uxtw + add x1, x2, w3, sxtb + add x1, x2, w3, sxth + add x1, x2, w3, sxtw + +; CHECK: add x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x8b] +; CHECK: add x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0x8b] +; CHECK: add x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x8b] +; CHECK: add x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x8b] +; CHECK: add x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x8b] +; CHECK: add x1, x2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x8b] + + add w1, wsp, w3 + add w1, wsp, w3, uxtw #0 + add w2, wsp, w3, lsl #1 + add sp, x2, x3 + add sp, x2, x3, uxtx #0 + +; CHECK: add w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x0b] +; CHECK: add w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x0b] +; CHECK: add w2, wsp, w3, lsl #1 ; encoding: [0xe2,0x47,0x23,0x0b] +; CHECK: add sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0x8b] +; CHECK: add sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0x8b] + + sub w1, w2, w3, uxtb + sub w1, w2, w3, uxth + sub w1, w2, w3, uxtw + sub w1, w2, w3, uxtx + sub w1, w2, w3, sxtb + sub w1, w2, w3, sxth + sub w1, w2, w3, sxtw + sub w1, w2, w3, sxtx + +; CHECK: sub w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x4b] +; CHECK: sub w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x4b] +; CHECK: sub w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x4b] +; CHECK: sub w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x4b] +; CHECK: sub w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x4b] +; CHECK: sub w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x4b] +; CHECK: sub w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x4b] +; CHECK: sub w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x4b] + + sub x1, x2, w3, uxtb + sub x1, x2, w3, uxth + sub x1, x2, w3, uxtw + sub x1, x2, w3, sxtb + sub x1, x2, w3, sxth + sub x1, x2, w3, sxtw + +; CHECK: sub x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0xcb] +; CHECK: sub x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0xcb] +; CHECK: sub x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0xcb] +; CHECK: sub x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0xcb] +; CHECK: sub x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0xcb] +; CHECK: sub x1, x2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0xcb] + + sub w1, wsp, w3 + sub w1, wsp, w3, uxtw #0 + sub sp, x2, x3 + sub sp, x2, x3, uxtx #0 + sub sp, x3, x7, lsl #4 + +; CHECK: sub w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x4b] +; CHECK: sub w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x4b] +; CHECK: sub sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0xcb] +; CHECK: sub sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0xcb] +; CHECK: sp, x3, x7, lsl #4 ; encoding: [0x7f,0x70,0x27,0xcb] + + adds w1, w2, w3, uxtb + adds w1, w2, w3, uxth + adds w1, w2, w3, uxtw + adds w1, w2, w3, uxtx + adds w1, w2, w3, sxtb + adds w1, w2, w3, sxth + adds w1, w2, w3, sxtw + adds w1, w2, w3, sxtx + +; CHECK: adds w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x2b] +; CHECK: adds w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x2b] +; CHECK: adds w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x2b] +; CHECK: adds w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x2b] +; CHECK: adds w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x2b] +; CHECK: adds w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x2b] +; CHECK: adds w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x2b] +; CHECK: adds w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x2b] + + adds x1, x2, w3, uxtb + adds x1, x2, w3, uxth + adds x1, x2, w3, uxtw + adds x1, x2, w3, uxtx + adds x1, x2, w3, sxtb + adds x1, x2, w3, sxth + adds x1, x2, w3, sxtw + adds x1, x2, w3, sxtx + +; CHECK: adds x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0xab] +; CHECK: adds x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0xab] +; CHECK: adds x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0xab] +; CHECK: adds x1, x2, w3, uxtx ; encoding: [0x41,0x60,0x23,0xab] +; CHECK: adds x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0xab] +; CHECK: adds x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0xab] +; CHECK: adds x1, x2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0xab] +; CHECK: adds x1, x2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0xab] + + adds w1, wsp, w3 + adds w1, wsp, w3, uxtw #0 + adds wzr, wsp, w3, lsl #4 + +; CHECK: adds w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x2b] +; CHECK: adds w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x2b] +; CHECK: cmn wsp, w3, lsl #4 ; encoding: [0xff,0x53,0x23,0x2b] + + subs w1, w2, w3, uxtb + subs w1, w2, w3, uxth + subs w1, w2, w3, uxtw + subs w1, w2, w3, uxtx + subs w1, w2, w3, sxtb + subs w1, w2, w3, sxth + subs w1, w2, w3, sxtw + subs w1, w2, w3, sxtx + +; CHECK: subs w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x6b] +; CHECK: subs w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x6b] +; CHECK: subs w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x6b] +; CHECK: subs w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x6b] +; CHECK: subs w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x6b] +; CHECK: subs w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x6b] +; CHECK: subs w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x6b] +; CHECK: subs w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x6b] + + subs x1, x2, w3, uxtb + subs x1, x2, w3, uxth + subs x1, x2, w3, uxtw + subs x1, x2, w3, uxtx + subs x1, x2, w3, sxtb + subs x1, x2, w3, sxth + subs x1, x2, w3, sxtw + subs x1, x2, w3, sxtx + +; CHECK: subs x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0xeb] +; CHECK: subs x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0xeb] +; CHECK: subs x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0xeb] +; CHECK: subs x1, x2, w3, uxtx ; encoding: [0x41,0x60,0x23,0xeb] +; CHECK: subs x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0xeb] +; CHECK: subs x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0xeb] +; CHECK: subs x1, x2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0xeb] +; CHECK: subs x1, x2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0xeb] + + subs w1, wsp, w3 + subs w1, wsp, w3, uxtw #0 + +; CHECK: subs w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x6b] +; CHECK: subs w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x6b] + + cmp wsp, w9, lsl #0 + subs x3, sp, x9, lsl #2 + cmp wsp, w8, uxtw + subs wzr, wsp, w8, uxtw + cmp sp, w8, uxtw + subs xzr, sp, w8, uxtw + +; CHECK: cmp wsp, w9 ; encoding: [0xff,0x43,0x29,0x6b] +; CHECK: subs x3, sp, x9, lsl #2 ; encoding: [0xe3,0x6b,0x29,0xeb] +; CHECK: cmp wsp, w8 ; encoding: [0xff,0x43,0x28,0x6b] +; CHECK: cmp wsp, w8 ; encoding: [0xff,0x43,0x28,0x6b] +; CHECK: cmp sp, w8, uxtw ; encoding: [0xff,0x43,0x28,0xeb] +; CHECK: cmp sp, w8, uxtw ; encoding: [0xff,0x43,0x28,0xeb] + + sub wsp, w9, w8, uxtw + sub w1, wsp, w8, uxtw + sub wsp, wsp, w8, uxtw + sub sp, x9, w8, uxtw + sub x1, sp, w8, uxtw + sub sp, sp, w8, uxtw + subs w1, wsp, w8, uxtw + subs x1, sp, w8, uxtw + +; CHECK: sub wsp, w9, w8 ; encoding: [0x3f,0x41,0x28,0x4b] +; CHECK: sub w1, wsp, w8 ; encoding: [0xe1,0x43,0x28,0x4b] +; CHECK: sub wsp, wsp, w8 ; encoding: [0xff,0x43,0x28,0x4b] +; CHECK: sub sp, x9, w8, uxtw ; encoding: [0x3f,0x41,0x28,0xcb] +; CHECK: sub x1, sp, w8, uxtw ; encoding: [0xe1,0x43,0x28,0xcb] +; CHECK: sub sp, sp, w8, uxtw ; encoding: [0xff,0x43,0x28,0xcb] +; CHECK: subs w1, wsp, w8 ; encoding: [0xe1,0x43,0x28,0x6b] +; CHECK: subs x1, sp, w8, uxtw ; encoding: [0xe1,0x43,0x28,0xeb] + +;==---------------------------------------------------------------------------== +; Signed/Unsigned divide +;==---------------------------------------------------------------------------== + + sdiv w1, w2, w3 + sdiv x1, x2, x3 + udiv w1, w2, w3 + udiv x1, x2, x3 + +; CHECK: sdiv w1, w2, w3 ; encoding: [0x41,0x0c,0xc3,0x1a] +; CHECK: sdiv x1, x2, x3 ; encoding: [0x41,0x0c,0xc3,0x9a] +; CHECK: udiv w1, w2, w3 ; encoding: [0x41,0x08,0xc3,0x1a] +; CHECK: udiv x1, x2, x3 ; encoding: [0x41,0x08,0xc3,0x9a] + +;==---------------------------------------------------------------------------== +; Variable shifts +;==---------------------------------------------------------------------------== + + asrv w1, w2, w3 + asrv x1, x2, x3 + asr w1, w2, w3 + asr x1, x2, x3 + lslv w1, w2, w3 + lslv x1, x2, x3 + lsl w1, w2, w3 + lsl x1, x2, x3 + lsrv w1, w2, w3 + lsrv x1, x2, x3 + lsr w1, w2, w3 + lsr x1, x2, x3 + rorv w1, w2, w3 + rorv x1, x2, x3 + ror w1, w2, w3 + ror x1, x2, x3 + +; CHECK: encoding: [0x41,0x28,0xc3,0x1a] +; CHECK: encoding: [0x41,0x28,0xc3,0x9a] +; CHECK: encoding: [0x41,0x28,0xc3,0x1a] +; CHECK: encoding: [0x41,0x28,0xc3,0x9a] +; CHECK: encoding: [0x41,0x20,0xc3,0x1a] +; CHECK: encoding: [0x41,0x20,0xc3,0x9a] +; CHECK: encoding: [0x41,0x20,0xc3,0x1a] +; CHECK: encoding: [0x41,0x20,0xc3,0x9a] +; CHECK: encoding: [0x41,0x24,0xc3,0x1a] +; CHECK: encoding: [0x41,0x24,0xc3,0x9a] +; CHECK: encoding: [0x41,0x24,0xc3,0x1a] +; CHECK: encoding: [0x41,0x24,0xc3,0x9a] +; CHECK: encoding: [0x41,0x2c,0xc3,0x1a] +; CHECK: encoding: [0x41,0x2c,0xc3,0x9a] +; CHECK: encoding: [0x41,0x2c,0xc3,0x1a] +; CHECK: encoding: [0x41,0x2c,0xc3,0x9a] + +;==---------------------------------------------------------------------------== +; One operand instructions +;==---------------------------------------------------------------------------== + + cls w1, w2 + cls x1, x2 + clz w1, w2 + clz x1, x2 + rbit w1, w2 + rbit x1, x2 + rev w1, w2 + rev x1, x2 + rev16 w1, w2 + rev16 x1, x2 + rev32 x1, x2 + +; CHECK: encoding: [0x41,0x14,0xc0,0x5a] +; CHECK: encoding: [0x41,0x14,0xc0,0xda] +; CHECK: encoding: [0x41,0x10,0xc0,0x5a] +; CHECK: encoding: [0x41,0x10,0xc0,0xda] +; CHECK: encoding: [0x41,0x00,0xc0,0x5a] +; CHECK: encoding: [0x41,0x00,0xc0,0xda] +; CHECK: encoding: [0x41,0x08,0xc0,0x5a] +; CHECK: encoding: [0x41,0x0c,0xc0,0xda] +; CHECK: encoding: [0x41,0x04,0xc0,0x5a] +; CHECK: encoding: [0x41,0x04,0xc0,0xda] +; CHECK: encoding: [0x41,0x08,0xc0,0xda] + +;==---------------------------------------------------------------------------== +; 6.6.1 Multiply-add instructions +;==---------------------------------------------------------------------------== + + madd w1, w2, w3, w4 + madd x1, x2, x3, x4 + msub w1, w2, w3, w4 + msub x1, x2, x3, x4 + smaddl x1, w2, w3, x4 + smsubl x1, w2, w3, x4 + umaddl x1, w2, w3, x4 + umsubl x1, w2, w3, x4 + +; CHECK: madd w1, w2, w3, w4 ; encoding: [0x41,0x10,0x03,0x1b] +; CHECK: madd x1, x2, x3, x4 ; encoding: [0x41,0x10,0x03,0x9b] +; CHECK: msub w1, w2, w3, w4 ; encoding: [0x41,0x90,0x03,0x1b] +; CHECK: msub x1, x2, x3, x4 ; encoding: [0x41,0x90,0x03,0x9b] +; CHECK: smaddl x1, w2, w3, x4 ; encoding: [0x41,0x10,0x23,0x9b] +; CHECK: smsubl x1, w2, w3, x4 ; encoding: [0x41,0x90,0x23,0x9b] +; CHECK: umaddl x1, w2, w3, x4 ; encoding: [0x41,0x10,0xa3,0x9b] +; CHECK: umsubl x1, w2, w3, x4 ; encoding: [0x41,0x90,0xa3,0x9b] + +;==---------------------------------------------------------------------------== +; Multiply-high instructions +;==---------------------------------------------------------------------------== + + smulh x1, x2, x3 + umulh x1, x2, x3 + +; CHECK: smulh x1, x2, x3 ; encoding: [0x41,0x7c,0x43,0x9b] +; CHECK: umulh x1, x2, x3 ; encoding: [0x41,0x7c,0xc3,0x9b] + +;==---------------------------------------------------------------------------== +; Move immediate instructions +;==---------------------------------------------------------------------------== + + movz w0, #1 + movz x0, #1 + movz w0, #1, lsl #16 + movz x0, #1, lsl #16 + +; CHECK: movz w0, #0x1 ; encoding: [0x20,0x00,0x80,0x52] +; CHECK: movz x0, #0x1 ; encoding: [0x20,0x00,0x80,0xd2] +; CHECK: movz w0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x52] +; CHECK: movz x0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xd2] + + movn w0, #2 + movn x0, #2 + movn w0, #2, lsl #16 + movn x0, #2, lsl #16 + +; CHECK: movn w0, #0x2 ; encoding: [0x40,0x00,0x80,0x12] +; CHECK: movn x0, #0x2 ; encoding: [0x40,0x00,0x80,0x92] +; CHECK: movn w0, #0x2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x12] +; CHECK: movn x0, #0x2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x92] + + movk w0, #1 + movk x0, #1 + movk w0, #1, lsl #16 + movk x0, #1, lsl #16 + +; CHECK: movk w0, #0x1 ; encoding: [0x20,0x00,0x80,0x72] +; CHECK: movk x0, #0x1 ; encoding: [0x20,0x00,0x80,0xf2] +; CHECK: movk w0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x72] +; CHECK: movk x0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xf2] + +;==---------------------------------------------------------------------------== +; Conditionally set flags instructions +;==---------------------------------------------------------------------------== + + ccmn w1, #2, #3, eq + ccmn x1, #2, #3, eq + ccmp w1, #2, #3, eq + ccmp x1, #2, #3, eq + +; CHECK: encoding: [0x23,0x08,0x42,0x3a] +; CHECK: encoding: [0x23,0x08,0x42,0xba] +; CHECK: encoding: [0x23,0x08,0x42,0x7a] +; CHECK: encoding: [0x23,0x08,0x42,0xfa] + + ccmn w1, w2, #3, eq + ccmn x1, x2, #3, eq + ccmp w1, w2, #3, eq + ccmp x1, x2, #3, eq + +; CHECK: encoding: [0x23,0x00,0x42,0x3a] +; CHECK: encoding: [0x23,0x00,0x42,0xba] +; CHECK: encoding: [0x23,0x00,0x42,0x7a] +; CHECK: encoding: [0x23,0x00,0x42,0xfa] + +;==---------------------------------------------------------------------------== +; Conditional select instructions +;==---------------------------------------------------------------------------== + + csel w1, w2, w3, eq + csel x1, x2, x3, eq + csinc w1, w2, w3, eq + csinc x1, x2, x3, eq + csinv w1, w2, w3, eq + csinv x1, x2, x3, eq + csneg w1, w2, w3, eq + csneg x1, x2, x3, eq + +; CHECK: encoding: [0x41,0x00,0x83,0x1a] +; CHECK: encoding: [0x41,0x00,0x83,0x9a] +; CHECK: encoding: [0x41,0x04,0x83,0x1a] +; CHECK: encoding: [0x41,0x04,0x83,0x9a] +; CHECK: encoding: [0x41,0x00,0x83,0x5a] +; CHECK: encoding: [0x41,0x00,0x83,0xda] +; CHECK: encoding: [0x41,0x04,0x83,0x5a] +; CHECK: encoding: [0x41,0x04,0x83,0xda] + +; Make sure we handle upper case, too. In particular, condition codes. + CSEL W16, W7, W27, EQ + CSEL W15, W6, W26, NE + CSEL W14, W5, W25, CS + CSEL W13, W4, W24, HS + csel w12, w3, w23, CC + csel w11, w2, w22, LO + csel w10, w1, w21, MI + csel x9, x9, x1, PL + csel x8, x8, x2, VS + CSEL X7, X7, X3, VC + CSEL X6, X7, X4, HI + CSEL X5, X6, X5, LS + CSEL X4, X5, X6, GE + csel x3, x4, x7, LT + csel x2, x3, x8, GT + csel x1, x2, x9, LE + csel x10, x1, x20, AL + +; CHECK: csel w16, w7, w27, eq ; encoding: [0xf0,0x00,0x9b,0x1a] +; CHECK: csel w15, w6, w26, ne ; encoding: [0xcf,0x10,0x9a,0x1a] +; CHECK: csel w14, w5, w25, hs ; encoding: [0xae,0x20,0x99,0x1a] +; CHECK: csel w13, w4, w24, hs ; encoding: [0x8d,0x20,0x98,0x1a] +; CHECK: csel w12, w3, w23, lo ; encoding: [0x6c,0x30,0x97,0x1a] +; CHECK: csel w11, w2, w22, lo ; encoding: [0x4b,0x30,0x96,0x1a] +; CHECK: csel w10, w1, w21, mi ; encoding: [0x2a,0x40,0x95,0x1a] +; CHECK: csel x9, x9, x1, pl ; encoding: [0x29,0x51,0x81,0x9a] +; CHECK: csel x8, x8, x2, vs ; encoding: [0x08,0x61,0x82,0x9a] +; CHECK: csel x7, x7, x3, vc ; encoding: [0xe7,0x70,0x83,0x9a] +; CHECK: csel x6, x7, x4, hi ; encoding: [0xe6,0x80,0x84,0x9a] +; CHECK: csel x5, x6, x5, ls ; encoding: [0xc5,0x90,0x85,0x9a] +; CHECK: csel x4, x5, x6, ge ; encoding: [0xa4,0xa0,0x86,0x9a] +; CHECK: csel x3, x4, x7, lt ; encoding: [0x83,0xb0,0x87,0x9a] +; CHECK: csel x2, x3, x8, gt ; encoding: [0x62,0xc0,0x88,0x9a] +; CHECK: csel x1, x2, x9, le ; encoding: [0x41,0xd0,0x89,0x9a] +; CHECK: csel x10, x1, x20, al ; encoding: [0x2a,0xe0,0x94,0x9a] + + +;==---------------------------------------------------------------------------== +; Scalar saturating arithmetic +;==---------------------------------------------------------------------------== + uqxtn b4, h2 + uqxtn h2, s3 + uqxtn s9, d2 + +; CHECK: uqxtn b4, h2 ; encoding: [0x44,0x48,0x21,0x7e] +; CHECK: uqxtn h2, s3 ; encoding: [0x62,0x48,0x61,0x7e] +; CHECK: uqxtn s9, d2 ; encoding: [0x49,0x48,0xa1,0x7e] diff --git a/test/MC/AArch64/arm64-arm64-fixup.s b/test/MC/AArch64/arm64-arm64-fixup.s new file mode 100644 index 0000000..81306fb --- /dev/null +++ b/test/MC/AArch64/arm64-arm64-fixup.s @@ -0,0 +1,10 @@ +; RUN: llvm-mc < %s -triple arm64-apple-darwin --show-encoding | FileCheck %s + +foo: + adr x3, Lbar +; CHECK: adr x3, Lbar ; encoding: [0x03'A',A,A,0x10'A'] +; CHECK: fixup A - offset: 0, value: Lbar, kind: fixup_aarch64_pcrel_adr_imm21 +Lbar: + adrp x3, _printf@page +; CHECK: adrp x3, _printf@PAGE ; encoding: [0x03'A',A,A,0x90'A'] +; CHECK: fixup A - offset: 0, value: _printf@PAGE, kind: fixup_aarch64_pcrel_adrp_imm21 diff --git a/test/MC/AArch64/arm64-basic-a64-instructions.s b/test/MC/AArch64/arm64-basic-a64-instructions.s new file mode 100644 index 0000000..2f58ead --- /dev/null +++ b/test/MC/AArch64/arm64-basic-a64-instructions.s @@ -0,0 +1,18 @@ +// RUN: llvm-mc -triple arm64 -mattr=+crc -show-encoding < %s | FileCheck %s + + crc32b w5, w7, w20 + crc32h w28, wzr, w30 + crc32w w0, w1, w2 + crc32x w7, w9, x20 + crc32cb w9, w5, w4 + crc32ch w13, w17, w25 + crc32cw wzr, w3, w5 + crc32cx w18, w16, xzr +// CHECK: crc32b w5, w7, w20 // encoding: [0xe5,0x40,0xd4,0x1a] +// CHECK: crc32h w28, wzr, w30 // encoding: [0xfc,0x47,0xde,0x1a] +// CHECK: crc32w w0, w1, w2 // encoding: [0x20,0x48,0xc2,0x1a] +// CHECK: crc32x w7, w9, x20 // encoding: [0x27,0x4d,0xd4,0x9a] +// CHECK: crc32cb w9, w5, w4 // encoding: [0xa9,0x50,0xc4,0x1a] +// CHECK: crc32ch w13, w17, w25 // encoding: [0x2d,0x56,0xd9,0x1a] +// CHECK: crc32cw wzr, w3, w5 // encoding: [0x7f,0x58,0xc5,0x1a] +// CHECK: crc32cx w18, w16, xzr // encoding: [0x12,0x5e,0xdf,0x9a] diff --git a/test/MC/AArch64/arm64-be-datalayout.s b/test/MC/AArch64/arm64-be-datalayout.s new file mode 100644 index 0000000..f448a4b --- /dev/null +++ b/test/MC/AArch64/arm64-be-datalayout.s @@ -0,0 +1,4 @@ +// RUN: llvm-mc -filetype=obj -triple arm64_be %s | llvm-readobj -section-data -sections | FileCheck %s + +// CHECK: 0000: 00123456 789ABCDE +foo: .xword 0x123456789abcde diff --git a/test/MC/AArch64/arm64-bitfield-encoding.s b/test/MC/AArch64/arm64-bitfield-encoding.s new file mode 100644 index 0000000..1589aa7 --- /dev/null +++ b/test/MC/AArch64/arm64-bitfield-encoding.s @@ -0,0 +1,38 @@ +; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s + +foo: +;==---------------------------------------------------------------------------== +; 5.4.4 Bitfield Operations +;==---------------------------------------------------------------------------== + + bfm w1, w2, #1, #15 + bfm x1, x2, #1, #15 + sbfm w1, w2, #1, #15 + sbfm x1, x2, #1, #15 + ubfm w1, w2, #1, #15 + ubfm x1, x2, #1, #15 + sbfiz wzr, w0, #31, #1 + sbfiz xzr, x0, #31, #1 + ubfiz wzr, w0, #31, #1 + ubfiz xzr, x0, #31, #1 + +; CHECK: bfxil w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x33] +; CHECK: bfxil x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0xb3] +; CHECK: sbfx w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x13] +; CHECK: sbfx x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0x93] +; CHECK: ubfx w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x53] +; CHECK: ubfx x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0xd3] +; CHECK: sbfiz wzr, w0, #31, #1 ; encoding: [0x1f,0x00,0x01,0x13] +; CHECK: sbfiz xzr, x0, #31, #1 ; encoding: [0x1f,0x00,0x61,0x93] +; CHECK: lsl wzr, w0, #31 ; encoding: [0x1f,0x00,0x01,0x53] +; CHECK: ubfiz xzr, x0, #31, #1 ; encoding: [0x1f,0x00,0x61,0xd3] + +;==---------------------------------------------------------------------------== +; 5.4.5 Extract (immediate) +;==---------------------------------------------------------------------------== + + extr w1, w2, w3, #15 + extr x2, x3, x4, #1 + +; CHECK: extr w1, w2, w3, #15 ; encoding: [0x41,0x3c,0x83,0x13] +; CHECK: extr x2, x3, x4, #1 ; encoding: [0x62,0x04,0xc4,0x93] diff --git a/test/MC/AArch64/arm64-branch-encoding.s b/test/MC/AArch64/arm64-branch-encoding.s new file mode 100644 index 0000000..48c2099 --- /dev/null +++ b/test/MC/AArch64/arm64-branch-encoding.s @@ -0,0 +1,159 @@ +; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s + +foo: + +;----------------------------------------------------------------------------- +; Unconditional branch (register) instructions. +;----------------------------------------------------------------------------- + + ret +; CHECK: encoding: [0xc0,0x03,0x5f,0xd6] + ret x1 +; CHECK: encoding: [0x20,0x00,0x5f,0xd6] + drps +; CHECK: encoding: [0xe0,0x03,0xbf,0xd6] + eret +; CHECK: encoding: [0xe0,0x03,0x9f,0xd6] + br x5 +; CHECK: encoding: [0xa0,0x00,0x1f,0xd6] + blr x9 +; CHECK: encoding: [0x20,0x01,0x3f,0xd6] + bl L1 +; CHECK: bl L1 ; encoding: [A,A,A,0b100101AA] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_call26 + +;----------------------------------------------------------------------------- +; Contitional branch instructions. +;----------------------------------------------------------------------------- + + b L1 +; CHECK: b L1 ; encoding: [A,A,A,0b000101AA] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch26 + b.eq L1 +; CHECK: b.eq L1 ; encoding: [0bAAA00000,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 + b.ne L1 +; CHECK: b.ne L1 ; encoding: [0bAAA00001,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 + b.cs L1 +; CHECK: b.hs L1 ; encoding: [0bAAA00010,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 + b.cc L1 +; CHECK: b.lo L1 ; encoding: [0bAAA00011,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 + b.mi L1 +; CHECK: b.mi L1 ; encoding: [0bAAA00100,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 + b.pl L1 +; CHECK: b.pl L1 ; encoding: [0bAAA00101,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 + b.vs L1 +; CHECK: b.vs L1 ; encoding: [0bAAA00110,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 + b.vc L1 +; CHECK: b.vc L1 ; encoding: [0bAAA00111,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 + b.hi L1 +; CHECK: b.hi L1 ; encoding: [0bAAA01000,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 + b.ls L1 +; CHECK: b.ls L1 ; encoding: [0bAAA01001,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 + b.ge L1 +; CHECK: b.ge L1 ; encoding: [0bAAA01010,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 + b.lt L1 +; CHECK: b.lt L1 ; encoding: [0bAAA01011,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 + b.gt L1 +; CHECK: b.gt L1 ; encoding: [0bAAA01100,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 + b.le L1 +; CHECK: b.le L1 ; encoding: [0bAAA01101,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 + b.al L1 +; CHECK: b.al L1 ; encoding: [0bAAA01110,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 +L1: + b #28 +; CHECK: b #28 + b.lt #28 +; CHECK: b.lt #28 + b.cc #1048572 +; CHECK: b.lo #1048572 ; encoding: [0xe3,0xff,0x7f,0x54] + b #134217724 +; CHECK: b #134217724 ; encoding: [0xff,0xff,0xff,0x15] + b #-134217728 +; CHECK: b #-134217728 ; encoding: [0x00,0x00,0x00,0x16] + +;----------------------------------------------------------------------------- +; Compare-and-branch instructions. +;----------------------------------------------------------------------------- + + cbz w1, foo +; CHECK: encoding: [0bAAA00001,A,A,0x34] + cbz x1, foo +; CHECK: encoding: [0bAAA00001,A,A,0xb4] + cbnz w2, foo +; CHECK: encoding: [0bAAA00010,A,A,0x35] + cbnz x2, foo +; CHECK: encoding: [0bAAA00010,A,A,0xb5] + cbz w1, #28 +; CHECK: cbz w1, #28 + cbz w20, #1048572 +; CHECK: cbz w20, #1048572 ; encoding: [0xf4,0xff,0x7f,0x34] + cbnz x2, #-1048576 +; CHECK: cbnz x2, #-1048576 ; encoding: [0x02,0x00,0x80,0xb5] + + +;----------------------------------------------------------------------------- +; Bit-test-and-branch instructions. +;----------------------------------------------------------------------------- + + tbz x1, #3, foo +; CHECK: encoding: [0bAAA00001,A,0b00011AAA,0x36] + tbnz x1, #63, foo +; CHECK: encoding: [0bAAA00001,A,0b11111AAA,0xb7] + + tbz w1, #3, foo +; CHECK: encoding: [0bAAA00001,A,0b00011AAA,0x36] + tbnz w1, #31, foo +; CHECK: encoding: [0bAAA00001,A,0b11111AAA,0x37] + + tbz w1, #3, #28 +; CHECK: tbz w1, #3, #28 + tbz w3, #5, #32764 +; CHECK: tbz w3, #5, #32764 ; encoding: [0xe3,0xff,0x2b,0x36] + tbnz x3, #8, #-32768 +; CHECK: tbnz w3, #8, #-32768 ; encoding: [0x03,0x00,0x44,0x37] + +;----------------------------------------------------------------------------- +; Exception generation instructions. +;----------------------------------------------------------------------------- + + brk #1 +; CHECK: encoding: [0x20,0x00,0x20,0xd4] + dcps1 #2 +; CHECK: encoding: [0x41,0x00,0xa0,0xd4] + dcps2 #3 +; CHECK: encoding: [0x62,0x00,0xa0,0xd4] + dcps3 #4 +; CHECK: encoding: [0x83,0x00,0xa0,0xd4] + hlt #5 +; CHECK: encoding: [0xa0,0x00,0x40,0xd4] + hvc #6 +; CHECK: encoding: [0xc2,0x00,0x00,0xd4] + smc #7 +; CHECK: encoding: [0xe3,0x00,0x00,0xd4] + svc #8 +; CHECK: encoding: [0x01,0x01,0x00,0xd4] + +; The immediate defaults to zero for DCPSn + dcps1 + dcps2 + dcps3 + +; CHECK: dcps1 ; encoding: [0x01,0x00,0xa0,0xd4] +; CHECK: dcps2 ; encoding: [0x02,0x00,0xa0,0xd4] +; CHECK: dcps3 ; encoding: [0x03,0x00,0xa0,0xd4] + diff --git a/test/MC/AArch64/arm64-condbr-without-dots.s b/test/MC/AArch64/arm64-condbr-without-dots.s new file mode 100644 index 0000000..2a9f7a7 --- /dev/null +++ b/test/MC/AArch64/arm64-condbr-without-dots.s @@ -0,0 +1,37 @@ +// RUN: llvm-mc -triple arm64-apple-ios -o - %s | FileCheck %s + + beq lbl + bne lbl + bcs lbl + bhs lbl + blo lbl + bcc lbl + bmi lbl + bpl lbl + bvs lbl + bvc lbl + bhi lbl + bls lbl + bge lbl + blt lbl + bgt lbl + ble lbl + bal lbl + +// CHECK: b.eq lbl +// CHECK: b.ne lbl +// CHECK: b.hs lbl +// CHECK: b.hs lbl +// CHECK: b.lo lbl +// CHECK: b.lo lbl +// CHECK: b.mi lbl +// CHECK: b.pl lbl +// CHECK: b.vs lbl +// CHECK: b.vc lbl +// CHECK: b.hi lbl +// CHECK: b.ls lbl +// CHECK: b.ge lbl +// CHECK: b.lt lbl +// CHECK: b.gt lbl +// CHECK: b.le lbl +// CHECK: b.al lbl diff --git a/test/MC/AArch64/arm64-crypto.s b/test/MC/AArch64/arm64-crypto.s new file mode 100644 index 0000000..51efd21 --- /dev/null +++ b/test/MC/AArch64/arm64-crypto.s @@ -0,0 +1,66 @@ +; RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -show-encoding -output-asm-variant=1 < %s | FileCheck %s + +foo: + aese.16b v0, v1 + aesd.16b v0, v1 + aesmc.16b v0, v1 + aesimc.16b v0, v1 + + sha1c.4s q0, s1, v2 + sha1p.4s q0, s1, v2 + sha1m.4s q0, s1, v2 + sha1su0.4s v0, v1, v2 + sha256h.4s q0, q1, v2 + sha256h2.4s q0, q1, v2 + sha256su1.4s v0, v1, v2 + sha1h s0, s1 + sha1su1.4s v0, v1 + sha256su0.4s v0, v1 + +; CHECK: aese.16b v0, v1 ; encoding: [0x20,0x48,0x28,0x4e] +; CHECK: aesd.16b v0, v1 ; encoding: [0x20,0x58,0x28,0x4e] +; CHECK: aesmc.16b v0, v1 ; encoding: [0x20,0x68,0x28,0x4e] +; CHECK: aesimc.16b v0, v1 ; encoding: [0x20,0x78,0x28,0x4e] + +; CHECK: sha1c.4s q0, s1, v2 ; encoding: [0x20,0x00,0x02,0x5e] +; CHECK: sha1p.4s q0, s1, v2 ; encoding: [0x20,0x10,0x02,0x5e] +; CHECK: sha1m.4s q0, s1, v2 ; encoding: [0x20,0x20,0x02,0x5e] +; CHECK: sha1su0.4s v0, v1, v2 ; encoding: [0x20,0x30,0x02,0x5e] +; CHECK: sha256h.4s q0, q1, v2 ; encoding: [0x20,0x40,0x02,0x5e] +; CHECK: sha256h2.4s q0, q1, v2 ; encoding: [0x20,0x50,0x02,0x5e] +; CHECK: sha256su1.4s v0, v1, v2 ; encoding: [0x20,0x60,0x02,0x5e] +; CHECK: sha1h s0, s1 ; encoding: [0x20,0x08,0x28,0x5e] +; CHECK: sha1su1.4s v0, v1 ; encoding: [0x20,0x18,0x28,0x5e] +; CHECK: sha256su0.4s v0, v1 ; encoding: [0x20,0x28,0x28,0x5e] + + aese v2.16b, v3.16b + aesd v5.16b, v7.16b + aesmc v11.16b, v13.16b + aesimc v17.16b, v19.16b + +; CHECK: aese.16b v2, v3 ; encoding: [0x62,0x48,0x28,0x4e] +; CHECK: aesd.16b v5, v7 ; encoding: [0xe5,0x58,0x28,0x4e] +; CHECK: aesmc.16b v11, v13 ; encoding: [0xab,0x69,0x28,0x4e] +; CHECK: aesimc.16b v17, v19 ; encoding: [0x71,0x7a,0x28,0x4e] + + sha1c q23, s29, v3.4s + sha1p q14, s15, v9.4s + sha1m q2, s6, v5.4s + sha1su0 v3.4s, v5.4s, v9.4s + sha256h q2, q7, v18.4s + sha256h2 q28, q18, v28.4s + sha256su1 v4.4s, v5.4s, v9.4s + sha1h s30, s0 + sha1su1 v10.4s, v21.4s + sha256su0 v2.4s, v31.4s + +; CHECK: sha1c.4s q23, s29, v3 ; encoding: [0xb7,0x03,0x03,0x5e] +; CHECK: sha1p.4s q14, s15, v9 ; encoding: [0xee,0x11,0x09,0x5e] +; CHECK: sha1m.4s q2, s6, v5 ; encoding: [0xc2,0x20,0x05,0x5e] +; CHECK: sha1su0.4s v3, v5, v9 ; encoding: [0xa3,0x30,0x09,0x5e] +; CHECK: sha256h.4s q2, q7, v18 ; encoding: [0xe2,0x40,0x12,0x5e] +; CHECK: sha256h2.4s q28, q18, v28 ; encoding: [0x5c,0x52,0x1c,0x5e] +; CHECK: sha256su1.4s v4, v5, v9 ; encoding: [0xa4,0x60,0x09,0x5e] +; CHECK: sha1h s30, s0 ; encoding: [0x1e,0x08,0x28,0x5e] +; CHECK: sha1su1.4s v10, v21 ; encoding: [0xaa,0x1a,0x28,0x5e] +; CHECK: sha256su0.4s v2, v31 ; encoding: [0xe2,0x2b,0x28,0x5e] diff --git a/test/MC/AArch64/arm64-diagno-predicate.s b/test/MC/AArch64/arm64-diagno-predicate.s new file mode 100644 index 0000000..3b757e8 --- /dev/null +++ b/test/MC/AArch64/arm64-diagno-predicate.s @@ -0,0 +1,24 @@ +// RUN: not llvm-mc -triple arm64-linux-gnu -mattr=-fp-armv8,-crc < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s + + + fcvt d0, s0 +// CHECK-ERROR: error: instruction requires: fp-armv8 +// CHECK-ERROR-NEXT: fcvt d0, s0 +// CHECK-ERROR-NEXT: ^ + + fmla v9.2s, v9.2s, v0.2s +// CHECK-ERROR: error: instruction requires: neon +// CHECK-ERROR-NEXT: fmla v9.2s, v9.2s, v0.2s +// CHECK-ERROR-NEXT: ^ + + pmull v0.1q, v1.1d, v2.1d +// CHECK-ERROR: error: instruction requires: crypto +// CHECK-ERROR-NEXT: pmull v0.1q, v1.1d, v2.1d +// CHECK-ERROR-NEXT: ^ + + crc32b w5, w7, w20 +// CHECK-ERROR: error: instruction requires: crc +// CHECK-ERROR-NEXT: crc32b w5, w7, w20 +// CHECK-ERROR-NEXT: ^ + diff --git a/test/MC/AArch64/arm64-diags.s b/test/MC/AArch64/arm64-diags.s new file mode 100644 index 0000000..cf00e98 --- /dev/null +++ b/test/MC/AArch64/arm64-diags.s @@ -0,0 +1,392 @@ +; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s +; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +foo: + +; The first should encode as an expression. The second should error expecting +; a register. + ldr x3, (foo + 4) + ldr x3, [foo + 4] +; CHECK: ldr x3, foo+4 ; encoding: [0bAAA00011,A,A,0x58] +; CHECK: ; fixup A - offset: 0, value: foo+4, kind: fixup_aarch64_ldr_pcrel_imm19 +; CHECK-ERRORS: error: invalid operand for instruction + +; The last argument should be flagged as an error. rdar://9576009 + ld4.8b {v0, v1, v2, v3}, [x0], #33 +; CHECK-ERRORS: error: invalid operand for instruction +; CHECK-ERRORS: ld4.8b {v0, v1, v2, v3}, [x0], #33 + + + ldr x0, [x0, #804] + ldr w0, [x0, #802] + ldr x0, [x0, #804]! + ldr w0, [w0, #301]! + ldr x0, [x0], #804 + ldr w0, [w0], #301 + + ldp w3, w4, [x5, #11]! + ldp x3, x4, [x5, #12]! + ldp q3, q4, [x5, #12]! + ldp w3, w4, [x5], #11 + ldp x3, x4, [x5], #12 + ldp q3, q4, [x5], #12 + + ldur x0, [x1, #-257] + +; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. +; CHECK-ERRORS: ldr x0, [x0, #804] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. +; CHECK-ERRORS: ldr w0, [x0, #802] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. +; CHECK-ERRORS: ldr x0, [x0, #804]! +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: invalid operand for instruction +; CHECK-ERRORS: ldr w0, [w0, #301]! +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. +; CHECK-ERRORS: ldr x0, [x0], #804 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: invalid operand for instruction +; CHECK-ERRORS: ldr w0, [w0], #301 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252]. +; CHECK-ERRORS: ldp w3, w4, [x5, #11]! +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504]. +; CHECK-ERRORS: ldp x3, x4, [x5, #12]! +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008]. +; CHECK-ERRORS: ldp q3, q4, [x5, #12]! +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252]. +; CHECK-ERRORS: ldp w3, w4, [x5], #11 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504]. +; CHECK-ERRORS: ldp x3, x4, [x5], #12 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008]. +; CHECK-ERRORS: ldp q3, q4, [x5], #12 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. +; CHECK-ERRORS: ldur x0, [x1, #-257] +; CHECK-ERRORS: ^ + + +ldrb w1, [x3, w3, sxtw #4] +ldrh w1, [x3, w3, sxtw #4] +ldr w1, [x3, w3, sxtw #4] +ldr x1, [x3, w3, sxtw #4] +ldr b1, [x3, w3, sxtw #4] +ldr h1, [x3, w3, sxtw #4] +ldr s1, [x3, w3, sxtw #4] +ldr d1, [x3, w3, sxtw #4] +ldr q1, [x3, w3, sxtw #1] + +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 +; CHECK-ERRORS:ldrb w1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1 +; CHECK-ERRORS:ldrh w1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2 +; CHECK-ERRORS:ldr w1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3 +; CHECK-ERRORS:ldr x1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 +; CHECK-ERRORS:ldr b1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1 +; CHECK-ERRORS:ldr h1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2 +; CHECK-ERRORS:ldr s1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3 +; CHECK-ERRORS:ldr d1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4 +; CHECK-ERRORS:ldr q1, [x3, w3, sxtw #1] +; CHECK-ERRORS: ^ + +; Check that register offset addressing modes only accept 32-bit offset +; registers when using uxtw/sxtw extends. Everything else requires a 64-bit +; register. + str d1, [x3, w3, sxtx #3] + ldr s1, [x3, d3, sxtx #2] + +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3 +; CHECK-ERRORS: str d1, [x3, w3, sxtx #3] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. +; CHECK-ERRORS: ldr s1, [x3, d3, sxtx #2] +; CHECK-ERRORS: ^ + +; Shift immediates range checking. + sqrshrn b4, h9, #10 + rshrn v9.8b, v11.8h, #17 + sqrshrn v7.4h, v8.4s, #39 + uqshrn2 v4.4s, v5.2d, #67 + +; CHECK-ERRORS: error: immediate must be an integer in range [1, 8]. +; CHECK-ERRORS: sqrshrn b4, h9, #10 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: immediate must be an integer in range [1, 8]. +; CHECK-ERRORS: rshrn v9.8b, v11.8h, #17 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: immediate must be an integer in range [1, 16]. +; CHECK-ERRORS: sqrshrn v7.4h, v8.4s, #39 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: immediate must be an integer in range [1, 32]. +; CHECK-ERRORS: uqshrn2 v4.4s, v5.2d, #67 +; CHECK-ERRORS: ^ + + + st1.s4 {v14, v15}, [x2], #32 +; CHECK-ERRORS: error: invalid type suffix for instruction +; CHECK-ERRORS: st1.s4 {v14, v15}, [x2], #32 +; CHECK-ERRORS: ^ + + + +; Load pair instructions where Rt==Rt2 and writeback load/store instructions +; where Rt==Rn or Rt2==Rn are unpredicatable. + ldp x1, x2, [x2], #16 + ldp x2, x2, [x2], #16 + ldp w1, w2, [x2], #16 + ldp w2, w2, [x2], #16 + ldp x1, x1, [x2] + + ldr x2, [x2], #8 + ldr x2, [x2, #8]! + ldr w2, [x2], #8 + ldr w2, [x2, #8]! + + str x2, [x2], #8 + str x2, [x2, #8]! + str w2, [x2], #8 + str w2, [x2, #8]! + +; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination +; CHECK-ERRORS: ldp x1, x2, [x2], #16 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination +; CHECK-ERRORS: ldp x2, x2, [x2], #16 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination +; CHECK-ERRORS: ldp w1, w2, [x2], #16 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination +; CHECK-ERRORS: ldp w2, w2, [x2], #16 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt +; CHECK-ERRORS: ldp x1, x1, [x2] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source +; CHECK-ERRORS: ldr x2, [x2], #8 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source +; CHECK-ERRORS: ldr x2, [x2, #8]! +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source +; CHECK-ERRORS: ldr w2, [x2], #8 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source +; CHECK-ERRORS: ldr w2, [x2, #8]! +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source +; CHECK-ERRORS: str x2, [x2], #8 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source +; CHECK-ERRORS: str x2, [x2, #8]! +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source +; CHECK-ERRORS: str w2, [x2], #8 +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source +; CHECK-ERRORS: str w2, [x2, #8]! +; CHECK-ERRORS: ^ + +; The validity checking for shifted-immediate operands. rdar://13174476 +; Where the immediate is out of range. + add w1, w2, w3, lsr #75 + +; CHECK-ERRORS: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4] +; CHECK-ERRORS: add w1, w2, w3, lsr #75 +; CHECK-ERRORS: ^ + +; logical instructions on 32-bit regs with shift > 31 is not legal +orr w0, w0, w0, lsl #32 +; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31] +; CHECK-ERRORS: orr w0, w0, w0, lsl #32 +; CHECK-ERRORS: ^ +eor w0, w0, w0, lsl #32 +; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31] +; CHECK-ERRORS: eor w0, w0, w0, lsl #32 +; CHECK-ERRORS: ^ +and w0, w0, w0, lsl #32 +; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31] +; CHECK-ERRORS: and w0, w0, w0, lsl #32 +; CHECK-ERRORS: ^ +ands w0, w0, w0, lsl #32 +; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31] +; CHECK-ERRORS: ands w0, w0, w0, lsl #32 +; CHECK-ERRORS: ^ + +; Relocated expressions should not be accepted for 32-bit adds or sub (imm) +add w3, w5, sym@PAGEOFF +; CHECK-ERRORS: error: invalid immediate expression +; CHECK-ERRORS: add w3, w5, sym@PAGEOFF +; CHECK-ERRORS: ^ + +adds w3, w5, sym@PAGEOFF +adds x9, x12, sym@PAGEOFF +; CHECK-ERRORS: error: invalid immediate expression +; CHECK-ERRORS: adds w3, w5, sym@PAGEOFF +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: invalid immediate expression +; CHECK-ERRORS: adds x9, x12, sym@PAGEOFF +; CHECK-ERRORS: ^ + +sub x3, x5, sym@PAGEOFF +sub w20, w30, sym@PAGEOFF +; CHECK-ERRORS: error: invalid immediate expression +; CHECK-ERRORS: sub x3, x5, sym@PAGEOFF +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: invalid immediate expression +; CHECK-ERRORS: sub w20, w30, sym@PAGEOFF +; CHECK-ERRORS: ^ + +subs w9, w10, sym@PAGEOFF +subs x20, x30, sym@PAGEOFF +; CHECK-ERRORS: error: invalid immediate expression +; CHECK-ERRORS: subs w9, w10, sym@PAGEOFF +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: invalid immediate expression +; CHECK-ERRORS: subs x20, x30, sym@PAGEOFF +; CHECK-ERRORS: ^ + +tbl v0.8b, { v1 }, v0.8b +tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b +tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b +tbx v2.8b, { v0 }, v6.8b +; CHECK-ERRORS: error: invalid operand for instruction +; CHECK-ERRORS: tbl v0.8b, { v1 }, v0.8b +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: invalid operand for instruction +; CHECK-ERRORS: tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: invalid operand for instruction +; CHECK-ERRORS: tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: invalid operand for instruction +; CHECK-ERRORS: tbx v2.8b, { v0 }, v6.8b +; CHECK-ERRORS: ^ + +b.c #0x4 +; CHECK-ERRORS: error: invalid condition code +; CHECK-ERRORS: b.c #0x4 +; CHECK-ERRORS: ^ + +ic ialluis, x0 +; CHECK-ERRORS: error: specified ic op does not use a register +ic iallu, x0 +; CHECK-ERRORS: error: specified ic op does not use a register +ic ivau +; CHECK-ERRORS: error: specified ic op requires a register + +dc zva +; CHECK-ERRORS: error: specified dc op requires a register +dc ivac +; CHECK-ERRORS: error: specified dc op requires a register +dc isw +; CHECK-ERRORS: error: specified dc op requires a register +dc cvac +; CHECK-ERRORS: error: specified dc op requires a register +dc csw +; CHECK-ERRORS: error: specified dc op requires a register +dc cvau +; CHECK-ERRORS: error: specified dc op requires a register +dc civac +; CHECK-ERRORS: error: specified dc op requires a register +dc cisw +; CHECK-ERRORS: error: specified dc op requires a register + +at s1e1r +; CHECK-ERRORS: error: specified at op requires a register +at s1e2r +; CHECK-ERRORS: error: specified at op requires a register +at s1e3r +; CHECK-ERRORS: error: specified at op requires a register +at s1e1w +; CHECK-ERRORS: error: specified at op requires a register +at s1e2w +; CHECK-ERRORS: error: specified at op requires a register +at s1e3w +; CHECK-ERRORS: error: specified at op requires a register +at s1e0r +; CHECK-ERRORS: error: specified at op requires a register +at s1e0w +; CHECK-ERRORS: error: specified at op requires a register +at s12e1r +; CHECK-ERRORS: error: specified at op requires a register +at s12e1w +; CHECK-ERRORS: error: specified at op requires a register +at s12e0r +; CHECK-ERRORS: error: specified at op requires a register +at s12e0w +; CHECK-ERRORS: error: specified at op requires a register + +tlbi vmalle1is, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi vmalle1, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi alle1is, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi alle2is, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi alle3is, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi alle1, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi alle2, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi alle3, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi vae1is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vae2is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vae3is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi aside1is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vaae1is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vale1is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vaale1is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vale2is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vale3is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vae1 +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vae2 +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vae3 +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi aside1 +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vaae1 +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vale1 +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vale2 +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vale3 +; CHECK-ERRORS: error: specified tlbi op requires a register diff --git a/test/MC/AArch64/arm64-directive_loh.s b/test/MC/AArch64/arm64-directive_loh.s new file mode 100644 index 0000000..76d2d7f --- /dev/null +++ b/test/MC/AArch64/arm64-directive_loh.s @@ -0,0 +1,93 @@ +# RUN: not llvm-mc -triple arm64-apple-darwin < %s 2> %t | FileCheck %s +# RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +.globl _fct1 +_fct1: + L1: + L2: + L3: + L4: + ret lr; + +# Known LOHs with: +# - Regular syntax. +# - Alternative syntax. + +# CHECK: .loh AdrpAdrp L1, L2 +# CHECK: .loh AdrpAdrp L1, L2 +.loh AdrpAdrp L1, L2 +.loh 1 L1, L2 + +# CHECK: .loh AdrpLdr L1, L2 +# CHECK: .loh AdrpLdr L1, L2 +.loh AdrpLdr L1, L2 +.loh 2 L1, L2 + +# CHECK: .loh AdrpAddLdr L1, L2, L3 +# CHECK: .loh AdrpAddLdr L1, L2, L3 +.loh AdrpAddLdr L1, L2, L3 +.loh 3 L1, L2, L3 + +# CHECK: .loh AdrpLdrGotLdr L1, L2, L3 +# CHECK: .loh AdrpLdrGotLdr L1, L2, L3 +.loh AdrpLdrGotLdr L1, L2, L3 +.loh 4 L1, L2, L3 + +# CHECK: .loh AdrpAddStr L1, L2, L3 +# CHECK: .loh AdrpAddStr L1, L2, L3 +.loh AdrpAddStr L1, L2, L3 +.loh 5 L1, L2, L3 + +# CHECK: .loh AdrpLdrGotStr L1, L2, L3 +# CHECK: .loh AdrpLdrGotStr L1, L2, L3 +.loh AdrpLdrGotStr L1, L2, L3 +.loh 6 L1, L2, L3 + +# CHECK: .loh AdrpAdd L1, L2 +# CHECK: .loh AdrpAdd L1, L2 +.loh AdrpAdd L1, L2 +.loh 7 L1, L2 + +# CHECK: .loh AdrpLdrGot L1, L2 +# CHECK: .loh AdrpLdrGot L1, L2 +.loh AdrpLdrGot L1, L2 +.loh 8 L1, L2 + +# End Known LOHs. + +### Errors Check #### + +# Unknown textual identifier. +# CHECK-ERRORS: error: invalid identifier in directive +# CHECK-ERRORS-NEXT: .loh Unknown +# CHECK-ERRORS-NEXT: ^ +.loh Unknown +# Unknown numeric identifier. +# CHECK-ERRORS: error: invalid numeric identifier in directive +# CHECK-ERRORS-NEXT: .loh 153, L1 +# CHECK-ERRORS-NEXT: ^ +.loh 153, L1 + +# Too much arguments. +# CHECK-ERRORS: error: unexpected token in '.loh' directive +# CHECK-ERRORS-NEXT: .loh AdrpAdrp L1, L2, L3 +# CHECK-ERRORS-NEXT: ^ +.loh AdrpAdrp L1, L2, L3 + +# Too much arguments with alternative syntax. +# CHECK-ERRORS: error: unexpected token in '.loh' directive +# CHECK-ERRORS-NEXT: .loh 1 L1, L2, L3 +# CHECK-ERRORS-NEXT: ^ +.loh 1 L1, L2, L3 + +# Too few argumets. +# CHECK-ERRORS: error: unexpected token in '.loh' directive +# CHECK-ERRORS-NEXT: .loh AdrpAdrp L1 +# CHECK-ERRORS-NEXT: ^ +.loh AdrpAdrp L1 + +# Too few argumets with alternative syntax. +# CHECK-ERRORS: error: unexpected token in '.loh' directive +# CHECK-ERRORS-NEXT: .loh 1 L1 +# CHECK-ERRORS-NEXT: ^ +.loh 1 L1 diff --git a/test/MC/AArch64/elf-reloc-condbr.s b/test/MC/AArch64/arm64-elf-reloc-condbr.s index b70dfa7..9b70a20 100644 --- a/test/MC/AArch64/elf-reloc-condbr.s +++ b/test/MC/AArch64/arm64-elf-reloc-condbr.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ +// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \ // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s b.eq somewhere diff --git a/test/MC/AArch64/arm64-elf-relocs.s b/test/MC/AArch64/arm64-elf-relocs.s new file mode 100644 index 0000000..eb22cc2 --- /dev/null +++ b/test/MC/AArch64/arm64-elf-relocs.s @@ -0,0 +1,249 @@ +// RUN: llvm-mc -triple=arm64-linux-gnu -o - < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj < %s | llvm-objdump -triple=arm64-linux-gnu - -r | FileCheck %s --check-prefix=CHECK-OBJ + + add x0, x2, #:lo12:sym +// CHECK: add x0, x2, :lo12:sym +// CHECK-OBJ: 0 R_AARCH64_ADD_ABS_LO12_NC sym + + add x5, x7, #:dtprel_lo12:sym +// CHECK: add x5, x7, :dtprel_lo12:sym +// CHECK-OBJ: 4 R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym + + add x9, x12, #:dtprel_lo12_nc:sym +// CHECK: add x9, x12, :dtprel_lo12_nc:sym +// CHECK-OBJ: 8 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym + + add x20, x30, #:tprel_lo12:sym +// CHECK: add x20, x30, :tprel_lo12:sym +// CHECK-OBJ: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym + + add x9, x12, #:tprel_lo12_nc:sym +// CHECK: add x9, x12, :tprel_lo12_nc:sym +// CHECK-OBJ: 10 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym + + add x5, x0, #:tlsdesc_lo12:sym +// CHECK: add x5, x0, :tlsdesc_lo12:sym +// CHECK-OBJ: 14 R_AARCH64_TLSDESC_ADD_LO12_NC sym + + add x0, x2, #:lo12:sym+8 +// CHECK: add x0, x2, :lo12:sym +// CHECK-OBJ: 18 R_AARCH64_ADD_ABS_LO12_NC sym+8 + + add x5, x7, #:dtprel_lo12:sym+1 +// CHECK: add x5, x7, :dtprel_lo12:sym+1 +// CHECK-OBJ: 1c R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym+1 + + add x9, x12, #:dtprel_lo12_nc:sym+2 +// CHECK: add x9, x12, :dtprel_lo12_nc:sym+2 +// CHECK-OBJ:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2 + + add x20, x30, #:tprel_lo12:sym+12 +// CHECK: add x20, x30, :tprel_lo12:sym+12 +// CHECK-OBJ: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12 + + add x9, x12, #:tprel_lo12_nc:sym+54 +// CHECK: add x9, x12, :tprel_lo12_nc:sym+54 +// CHECK-OBJ: 28 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym+54 + + add x5, x0, #:tlsdesc_lo12:sym+70 +// CHECK: add x5, x0, :tlsdesc_lo12:sym+70 +// CHECK-OBJ: 2c R_AARCH64_TLSDESC_ADD_LO12_NC sym+70 + + .hword sym + 4 - . +// CHECK-OBJ: 30 R_AARCH64_PREL16 sym+4 + .word sym - . + 8 +// CHECK-OBJ: 32 R_AARCH64_PREL32 sym+8 + .xword sym-. +// CHECK-OBJ: 36 R_AARCH64_PREL64 sym{{$}} + + .hword sym +// CHECK-OBJ: 3e R_AARCH64_ABS16 sym + .word sym+1 +// CHECK-OBJ: 40 R_AARCH64_ABS32 sym+1 + .xword sym+16 +// CHECK-OBJ: 44 R_AARCH64_ABS64 sym+16 + + adrp x0, sym +// CHECK: adrp x0, sym +// CHECK-OBJ: 4c R_AARCH64_ADR_PREL_PG_HI21 sym + + adrp x15, :got:sym +// CHECK: adrp x15, :got:sym +// CHECK-OBJ: 50 R_AARCH64_ADR_GOT_PAGE sym + + adrp x29, :gottprel:sym +// CHECK: adrp x29, :gottprel:sym +// CHECK-OBJ: 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym + + adrp x2, :tlsdesc:sym +// CHECK: adrp x2, :tlsdesc:sym +// CHECK-OBJ: 58 R_AARCH64_TLSDESC_ADR_PAGE sym + + // LLVM is not competent enough to do this relocation because the + // page boundary could occur anywhere after linking. A relocation + // is needed. + adrp x3, trickQuestion + .global trickQuestion +trickQuestion: +// CHECK: adrp x3, trickQuestion +// CHECK-OBJ: 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion + + ldrb w2, [x3, :lo12:sym] + ldrsb w5, [x7, #:lo12:sym] + ldrsb x11, [x13, :lo12:sym] + ldr b17, [x19, #:lo12:sym] +// CHECK: ldrb w2, [x3, :lo12:sym] +// CHECK: ldrsb w5, [x7, :lo12:sym] +// CHECK: ldrsb x11, [x13, :lo12:sym] +// CHECK: ldr b17, [x19, :lo12:sym] +// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym +// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym +// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym +// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym + + ldrb w23, [x29, #:dtprel_lo12_nc:sym] + ldrsb w23, [x19, #:dtprel_lo12:sym] + ldrsb x17, [x13, :dtprel_lo12_nc:sym] + ldr b11, [x7, #:dtprel_lo12:sym] +// CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym] +// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym] +// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym] +// CHECK: ldr b11, [x7, :dtprel_lo12:sym] +// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym +// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym +// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym +// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym + + ldrb w1, [x2, :tprel_lo12:sym] + ldrsb w3, [x4, #:tprel_lo12_nc:sym] + ldrsb x5, [x6, :tprel_lo12:sym] + ldr b7, [x8, #:tprel_lo12_nc:sym] +// CHECK: ldrb w1, [x2, :tprel_lo12:sym] +// CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym] +// CHECK: ldrsb x5, [x6, :tprel_lo12:sym] +// CHECK: ldr b7, [x8, :tprel_lo12_nc:sym] +// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym +// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym +// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym +// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym + + ldrh w2, [x3, #:lo12:sym] + ldrsh w5, [x7, :lo12:sym] + ldrsh x11, [x13, #:lo12:sym] + ldr h17, [x19, :lo12:sym] +// CHECK: ldrh w2, [x3, :lo12:sym] +// CHECK: ldrsh w5, [x7, :lo12:sym] +// CHECK: ldrsh x11, [x13, :lo12:sym] +// CHECK: ldr h17, [x19, :lo12:sym] +// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym +// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym +// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym +// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym + + ldrh w23, [x29, #:dtprel_lo12_nc:sym] + ldrsh w23, [x19, :dtprel_lo12:sym] + ldrsh x17, [x13, :dtprel_lo12_nc:sym] + ldr h11, [x7, #:dtprel_lo12:sym] +// CHECK: ldrh w23, [x29, :dtprel_lo12_nc:sym] +// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym] +// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym] +// CHECK: ldr h11, [x7, :dtprel_lo12:sym] +// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym +// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym +// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym +// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym + + ldrh w1, [x2, :tprel_lo12:sym] + ldrsh w3, [x4, #:tprel_lo12_nc:sym] + ldrsh x5, [x6, :tprel_lo12:sym] + ldr h7, [x8, #:tprel_lo12_nc:sym] +// CHECK: ldrh w1, [x2, :tprel_lo12:sym] +// CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym] +// CHECK: ldrsh x5, [x6, :tprel_lo12:sym] +// CHECK: ldr h7, [x8, :tprel_lo12_nc:sym] +// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym +// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym +// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym +// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym + + ldr w1, [x2, #:lo12:sym] + ldrsw x3, [x4, #:lo12:sym] + ldr s4, [x5, :lo12:sym] +// CHECK: ldr w1, [x2, :lo12:sym] +// CHECK: ldrsw x3, [x4, :lo12:sym] +// CHECK: ldr s4, [x5, :lo12:sym] +// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym +// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym +// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym + + ldr w1, [x2, :dtprel_lo12:sym] + ldrsw x3, [x4, #:dtprel_lo12_nc:sym] + ldr s4, [x5, #:dtprel_lo12_nc:sym] +// CHECK: ldr w1, [x2, :dtprel_lo12:sym] +// CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym] +// CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym] +// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12 sym +// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym +// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym + + + ldr w1, [x2, #:tprel_lo12:sym] + ldrsw x3, [x4, :tprel_lo12_nc:sym] + ldr s4, [x5, :tprel_lo12_nc:sym] +// CHECK: ldr w1, [x2, :tprel_lo12:sym] +// CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym] +// CHECK: ldr s4, [x5, :tprel_lo12_nc:sym] +// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12 sym +// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym +// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym + + ldr x28, [x27, :lo12:sym] + ldr d26, [x25, #:lo12:sym] +// CHECK: ldr x28, [x27, :lo12:sym] +// CHECK: ldr d26, [x25, :lo12:sym] +// CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym +// CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym + + ldr x24, [x23, #:got_lo12:sym] + ldr d22, [x21, :got_lo12:sym] +// CHECK: ldr x24, [x23, :got_lo12:sym] +// CHECK: ldr d22, [x21, :got_lo12:sym] +// CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym +// CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym + + ldr x24, [x23, :dtprel_lo12_nc:sym] + ldr d22, [x21, #:dtprel_lo12:sym] +// CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym] +// CHECK: ldr d22, [x21, :dtprel_lo12:sym] +// CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC sym +// CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12 sym + + ldr x24, [x23, #:tprel_lo12:sym] + ldr d22, [x21, :tprel_lo12_nc:sym] +// CHECK: ldr x24, [x23, :tprel_lo12:sym] +// CHECK: ldr d22, [x21, :tprel_lo12_nc:sym] +// CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12 sym +// CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC sym + + ldr x24, [x23, :gottprel_lo12:sym] + ldr d22, [x21, #:gottprel_lo12:sym] +// CHECK: ldr x24, [x23, :gottprel_lo12:sym] +// CHECK: ldr d22, [x21, :gottprel_lo12:sym] +// CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym +// CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym + + ldr x24, [x23, #:tlsdesc_lo12:sym] + ldr d22, [x21, :tlsdesc_lo12:sym] +// CHECK: ldr x24, [x23, :tlsdesc_lo12:sym] +// CHECK: ldr d22, [x21, :tlsdesc_lo12:sym] +// CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym +// CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym + + ldr q20, [x19, #:lo12:sym] +// CHECK: ldr q20, [x19, :lo12:sym] +// CHECK-OBJ: R_AARCH64_LDST128_ABS_LO12_NC sym + +// Since relocated instructions print without a '#', that syntax should +// certainly be accepted when assembling. + add x3, x5, :lo12:imm +// CHECK: add x3, x5, :lo12:imm diff --git a/test/MC/AArch64/arm64-fp-encoding.s b/test/MC/AArch64/arm64-fp-encoding.s new file mode 100644 index 0000000..684d988 --- /dev/null +++ b/test/MC/AArch64/arm64-fp-encoding.s @@ -0,0 +1,443 @@ +; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -show-encoding -output-asm-variant=1 < %s | FileCheck %s + +foo: +;----------------------------------------------------------------------------- +; Floating-point arithmetic +;----------------------------------------------------------------------------- + + fabs s1, s2 + fabs d1, d2 + +; CHECK: fabs s1, s2 ; encoding: [0x41,0xc0,0x20,0x1e] +; CHECK: fabs d1, d2 ; encoding: [0x41,0xc0,0x60,0x1e] + + fadd s1, s2, s3 + fadd d1, d2, d3 + +; CHECK: fadd s1, s2, s3 ; encoding: [0x41,0x28,0x23,0x1e] +; CHECK: fadd d1, d2, d3 ; encoding: [0x41,0x28,0x63,0x1e] + + fdiv s1, s2, s3 + fdiv d1, d2, d3 + +; CHECK: fdiv s1, s2, s3 ; encoding: [0x41,0x18,0x23,0x1e] +; CHECK: fdiv d1, d2, d3 ; encoding: [0x41,0x18,0x63,0x1e] + + fmadd s1, s2, s3, s4 + fmadd d1, d2, d3, d4 + +; CHECK: fmadd s1, s2, s3, s4 ; encoding: [0x41,0x10,0x03,0x1f] +; CHECK: fmadd d1, d2, d3, d4 ; encoding: [0x41,0x10,0x43,0x1f] + + fmax s1, s2, s3 + fmax d1, d2, d3 + fmaxnm s1, s2, s3 + fmaxnm d1, d2, d3 + +; CHECK: fmax s1, s2, s3 ; encoding: [0x41,0x48,0x23,0x1e] +; CHECK: fmax d1, d2, d3 ; encoding: [0x41,0x48,0x63,0x1e] +; CHECK: fmaxnm s1, s2, s3 ; encoding: [0x41,0x68,0x23,0x1e] +; CHECK: fmaxnm d1, d2, d3 ; encoding: [0x41,0x68,0x63,0x1e] + + fmin s1, s2, s3 + fmin d1, d2, d3 + fminnm s1, s2, s3 + fminnm d1, d2, d3 + +; CHECK: fmin s1, s2, s3 ; encoding: [0x41,0x58,0x23,0x1e] +; CHECK: fmin d1, d2, d3 ; encoding: [0x41,0x58,0x63,0x1e] +; CHECK: fminnm s1, s2, s3 ; encoding: [0x41,0x78,0x23,0x1e] +; CHECK: fminnm d1, d2, d3 ; encoding: [0x41,0x78,0x63,0x1e] + + fmsub s1, s2, s3, s4 + fmsub d1, d2, d3, d4 + +; CHECK: fmsub s1, s2, s3, s4 ; encoding: [0x41,0x90,0x03,0x1f] +; CHECK: fmsub d1, d2, d3, d4 ; encoding: [0x41,0x90,0x43,0x1f] + + fmul s1, s2, s3 + fmul d1, d2, d3 + +; CHECK: fmul s1, s2, s3 ; encoding: [0x41,0x08,0x23,0x1e] +; CHECK: fmul d1, d2, d3 ; encoding: [0x41,0x08,0x63,0x1e] + + fneg s1, s2 + fneg d1, d2 + +; CHECK: fneg s1, s2 ; encoding: [0x41,0x40,0x21,0x1e] +; CHECK: fneg d1, d2 ; encoding: [0x41,0x40,0x61,0x1e] + + fnmadd s1, s2, s3, s4 + fnmadd d1, d2, d3, d4 + +; CHECK: fnmadd s1, s2, s3, s4 ; encoding: [0x41,0x10,0x23,0x1f] +; CHECK: fnmadd d1, d2, d3, d4 ; encoding: [0x41,0x10,0x63,0x1f] + + fnmsub s1, s2, s3, s4 + fnmsub d1, d2, d3, d4 + +; CHECK: fnmsub s1, s2, s3, s4 ; encoding: [0x41,0x90,0x23,0x1f] +; CHECK: fnmsub d1, d2, d3, d4 ; encoding: [0x41,0x90,0x63,0x1f] + + fnmul s1, s2, s3 + fnmul d1, d2, d3 + +; CHECK: fnmul s1, s2, s3 ; encoding: [0x41,0x88,0x23,0x1e] +; CHECK: fnmul d1, d2, d3 ; encoding: [0x41,0x88,0x63,0x1e] + + fsqrt s1, s2 + fsqrt d1, d2 + +; CHECK: fsqrt s1, s2 ; encoding: [0x41,0xc0,0x21,0x1e] +; CHECK: fsqrt d1, d2 ; encoding: [0x41,0xc0,0x61,0x1e] + + fsub s1, s2, s3 + fsub d1, d2, d3 + +; CHECK: fsub s1, s2, s3 ; encoding: [0x41,0x38,0x23,0x1e] +; CHECK: fsub d1, d2, d3 ; encoding: [0x41,0x38,0x63,0x1e] + +;----------------------------------------------------------------------------- +; Floating-point comparison +;----------------------------------------------------------------------------- + + fccmp s1, s2, #0, eq + fccmp d1, d2, #0, eq + fccmpe s1, s2, #0, eq + fccmpe d1, d2, #0, eq + +; CHECK: fccmp s1, s2, #0, eq ; encoding: [0x20,0x04,0x22,0x1e] +; CHECK: fccmp d1, d2, #0, eq ; encoding: [0x20,0x04,0x62,0x1e] +; CHECK: fccmpe s1, s2, #0, eq ; encoding: [0x30,0x04,0x22,0x1e] +; CHECK: fccmpe d1, d2, #0, eq ; encoding: [0x30,0x04,0x62,0x1e] + + fcmp s1, s2 + fcmp d1, d2 + fcmp s1, #0.0 + fcmp d1, #0.0 + fcmpe s1, s2 + fcmpe d1, d2 + fcmpe s1, #0.0 + fcmpe d1, #0.0 + +; CHECK: fcmp s1, s2 ; encoding: [0x20,0x20,0x22,0x1e] +; CHECK: fcmp d1, d2 ; encoding: [0x20,0x20,0x62,0x1e] +; CHECK: fcmp s1, #0.0 ; encoding: [0x28,0x20,0x20,0x1e] +; CHECK: fcmp d1, #0.0 ; encoding: [0x28,0x20,0x60,0x1e] +; CHECK: fcmpe s1, s2 ; encoding: [0x30,0x20,0x22,0x1e] +; CHECK: fcmpe d1, d2 ; encoding: [0x30,0x20,0x62,0x1e] +; CHECK: fcmpe s1, #0.0 ; encoding: [0x38,0x20,0x20,0x1e] +; CHECK: fcmpe d1, #0.0 ; encoding: [0x38,0x20,0x60,0x1e] + +;----------------------------------------------------------------------------- +; Floating-point conditional select +;----------------------------------------------------------------------------- + + fcsel s1, s2, s3, eq + fcsel d1, d2, d3, eq + +; CHECK: fcsel s1, s2, s3, eq ; encoding: [0x41,0x0c,0x23,0x1e] +; CHECK: fcsel d1, d2, d3, eq ; encoding: [0x41,0x0c,0x63,0x1e] + +;----------------------------------------------------------------------------- +; Floating-point convert +;----------------------------------------------------------------------------- + + fcvt h1, d2 + fcvt s1, d2 + fcvt d1, h2 + fcvt s1, h2 + fcvt d1, s2 + fcvt h1, s2 + +; CHECK: fcvt h1, d2 ; encoding: [0x41,0xc0,0x63,0x1e] +; CHECK: fcvt s1, d2 ; encoding: [0x41,0x40,0x62,0x1e] +; CHECK: fcvt d1, h2 ; encoding: [0x41,0xc0,0xe2,0x1e] +; CHECK: fcvt s1, h2 ; encoding: [0x41,0x40,0xe2,0x1e] +; CHECK: fcvt d1, s2 ; encoding: [0x41,0xc0,0x22,0x1e] +; CHECK: fcvt h1, s2 ; encoding: [0x41,0xc0,0x23,0x1e] + + fcvtas w1, d2 + fcvtas x1, d2 + fcvtas w1, s2 + fcvtas x1, s2 + +; CHECK: fcvtas w1, d2 ; encoding: [0x41,0x00,0x64,0x1e] +; CHECK: fcvtas x1, d2 ; encoding: [0x41,0x00,0x64,0x9e] +; CHECK: fcvtas w1, s2 ; encoding: [0x41,0x00,0x24,0x1e] +; CHECK: fcvtas x1, s2 ; encoding: [0x41,0x00,0x24,0x9e] + + fcvtau w1, s2 + fcvtau w1, d2 + fcvtau x1, s2 + fcvtau x1, d2 + +; CHECK: fcvtau w1, s2 ; encoding: [0x41,0x00,0x25,0x1e] +; CHECK: fcvtau w1, d2 ; encoding: [0x41,0x00,0x65,0x1e] +; CHECK: fcvtau x1, s2 ; encoding: [0x41,0x00,0x25,0x9e] +; CHECK: fcvtau x1, d2 ; encoding: [0x41,0x00,0x65,0x9e] + + fcvtms w1, s2 + fcvtms w1, d2 + fcvtms x1, s2 + fcvtms x1, d2 + +; CHECK: fcvtms w1, s2 ; encoding: [0x41,0x00,0x30,0x1e] +; CHECK: fcvtms w1, d2 ; encoding: [0x41,0x00,0x70,0x1e] +; CHECK: fcvtms x1, s2 ; encoding: [0x41,0x00,0x30,0x9e] +; CHECK: fcvtms x1, d2 ; encoding: [0x41,0x00,0x70,0x9e] + + fcvtmu w1, s2 + fcvtmu w1, d2 + fcvtmu x1, s2 + fcvtmu x1, d2 + +; CHECK: fcvtmu w1, s2 ; encoding: [0x41,0x00,0x31,0x1e] +; CHECK: fcvtmu w1, d2 ; encoding: [0x41,0x00,0x71,0x1e] +; CHECK: fcvtmu x1, s2 ; encoding: [0x41,0x00,0x31,0x9e] +; CHECK: fcvtmu x1, d2 ; encoding: [0x41,0x00,0x71,0x9e] + + fcvtns w1, s2 + fcvtns w1, d2 + fcvtns x1, s2 + fcvtns x1, d2 + +; CHECK: fcvtns w1, s2 ; encoding: [0x41,0x00,0x20,0x1e] +; CHECK: fcvtns w1, d2 ; encoding: [0x41,0x00,0x60,0x1e] +; CHECK: fcvtns x1, s2 ; encoding: [0x41,0x00,0x20,0x9e] +; CHECK: fcvtns x1, d2 ; encoding: [0x41,0x00,0x60,0x9e] + + fcvtnu w1, s2 + fcvtnu w1, d2 + fcvtnu x1, s2 + fcvtnu x1, d2 + +; CHECK: fcvtnu w1, s2 ; encoding: [0x41,0x00,0x21,0x1e] +; CHECK: fcvtnu w1, d2 ; encoding: [0x41,0x00,0x61,0x1e] +; CHECK: fcvtnu x1, s2 ; encoding: [0x41,0x00,0x21,0x9e] +; CHECK: fcvtnu x1, d2 ; encoding: [0x41,0x00,0x61,0x9e] + + fcvtps w1, s2 + fcvtps w1, d2 + fcvtps x1, s2 + fcvtps x1, d2 + +; CHECK: fcvtps w1, s2 ; encoding: [0x41,0x00,0x28,0x1e] +; CHECK: fcvtps w1, d2 ; encoding: [0x41,0x00,0x68,0x1e] +; CHECK: fcvtps x1, s2 ; encoding: [0x41,0x00,0x28,0x9e] +; CHECK: fcvtps x1, d2 ; encoding: [0x41,0x00,0x68,0x9e] + + fcvtpu w1, s2 + fcvtpu w1, d2 + fcvtpu x1, s2 + fcvtpu x1, d2 + +; CHECK: fcvtpu w1, s2 ; encoding: [0x41,0x00,0x29,0x1e] +; CHECK: fcvtpu w1, d2 ; encoding: [0x41,0x00,0x69,0x1e] +; CHECK: fcvtpu x1, s2 ; encoding: [0x41,0x00,0x29,0x9e] +; CHECK: fcvtpu x1, d2 ; encoding: [0x41,0x00,0x69,0x9e] + + fcvtzs w1, s2 + fcvtzs w1, s2, #1 + fcvtzs w1, d2 + fcvtzs w1, d2, #1 + fcvtzs x1, s2 + fcvtzs x1, s2, #1 + fcvtzs x1, d2 + fcvtzs x1, d2, #1 + +; CHECK: fcvtzs w1, s2 ; encoding: [0x41,0x00,0x38,0x1e] +; CHECK: fcvtzs w1, s2, #1 ; encoding: [0x41,0xfc,0x18,0x1e] +; CHECK: fcvtzs w1, d2 ; encoding: [0x41,0x00,0x78,0x1e] +; CHECK: fcvtzs w1, d2, #1 ; encoding: [0x41,0xfc,0x58,0x1e] +; CHECK: fcvtzs x1, s2 ; encoding: [0x41,0x00,0x38,0x9e] +; CHECK: fcvtzs x1, s2, #1 ; encoding: [0x41,0xfc,0x18,0x9e] +; CHECK: fcvtzs x1, d2 ; encoding: [0x41,0x00,0x78,0x9e] +; CHECK: fcvtzs x1, d2, #1 ; encoding: [0x41,0xfc,0x58,0x9e] + + fcvtzu w1, s2 + fcvtzu w1, s2, #1 + fcvtzu w1, d2 + fcvtzu w1, d2, #1 + fcvtzu x1, s2 + fcvtzu x1, s2, #1 + fcvtzu x1, d2 + fcvtzu x1, d2, #1 + +; CHECK: fcvtzu w1, s2 ; encoding: [0x41,0x00,0x39,0x1e] +; CHECK: fcvtzu w1, s2, #1 ; encoding: [0x41,0xfc,0x19,0x1e] +; CHECK: fcvtzu w1, d2 ; encoding: [0x41,0x00,0x79,0x1e] +; CHECK: fcvtzu w1, d2, #1 ; encoding: [0x41,0xfc,0x59,0x1e] +; CHECK: fcvtzu x1, s2 ; encoding: [0x41,0x00,0x39,0x9e] +; CHECK: fcvtzu x1, s2, #1 ; encoding: [0x41,0xfc,0x19,0x9e] +; CHECK: fcvtzu x1, d2 ; encoding: [0x41,0x00,0x79,0x9e] +; CHECK: fcvtzu x1, d2, #1 ; encoding: [0x41,0xfc,0x59,0x9e] + + scvtf s1, w2 + scvtf s1, w2, #1 + scvtf d1, w2 + scvtf d1, w2, #1 + scvtf s1, x2 + scvtf s1, x2, #1 + scvtf d1, x2 + scvtf d1, x2, #1 + +; CHECK: scvtf s1, w2 ; encoding: [0x41,0x00,0x22,0x1e] +; CHECK: scvtf s1, w2, #1 ; encoding: [0x41,0xfc,0x02,0x1e] +; CHECK: scvtf d1, w2 ; encoding: [0x41,0x00,0x62,0x1e] +; CHECK: scvtf d1, w2, #1 ; encoding: [0x41,0xfc,0x42,0x1e] +; CHECK: scvtf s1, x2 ; encoding: [0x41,0x00,0x22,0x9e] +; CHECK: scvtf s1, x2, #1 ; encoding: [0x41,0xfc,0x02,0x9e] +; CHECK: scvtf d1, x2 ; encoding: [0x41,0x00,0x62,0x9e] +; CHECK: scvtf d1, x2, #1 ; encoding: [0x41,0xfc,0x42,0x9e] + + ucvtf s1, w2 + ucvtf s1, w2, #1 + ucvtf d1, w2 + ucvtf d1, w2, #1 + ucvtf s1, x2 + ucvtf s1, x2, #1 + ucvtf d1, x2 + ucvtf d1, x2, #1 + +; CHECK: ucvtf s1, w2 ; encoding: [0x41,0x00,0x23,0x1e] +; CHECK: ucvtf s1, w2, #1 ; encoding: [0x41,0xfc,0x03,0x1e] +; CHECK: ucvtf d1, w2 ; encoding: [0x41,0x00,0x63,0x1e] +; CHECK: ucvtf d1, w2, #1 ; encoding: [0x41,0xfc,0x43,0x1e] +; CHECK: ucvtf s1, x2 ; encoding: [0x41,0x00,0x23,0x9e] +; CHECK: ucvtf s1, x2, #1 ; encoding: [0x41,0xfc,0x03,0x9e] +; CHECK: ucvtf d1, x2 ; encoding: [0x41,0x00,0x63,0x9e] +; CHECK: ucvtf d1, x2, #1 ; encoding: [0x41,0xfc,0x43,0x9e] + +;----------------------------------------------------------------------------- +; Floating-point move +;----------------------------------------------------------------------------- + + fmov s1, w2 + fmov w1, s2 + fmov d1, x2 + fmov x1, d2 + +; CHECK: fmov s1, w2 ; encoding: [0x41,0x00,0x27,0x1e] +; CHECK: fmov w1, s2 ; encoding: [0x41,0x00,0x26,0x1e] +; CHECK: fmov d1, x2 ; encoding: [0x41,0x00,0x67,0x9e] +; CHECK: fmov x1, d2 ; encoding: [0x41,0x00,0x66,0x9e] + + fmov s1, #0.125 + fmov s1, #0x40 + fmov d1, #0.125 + fmov d1, #0x40 + fmov d1, #-4.843750e-01 + fmov d1, #4.843750e-01 + fmov d3, #3 + fmov s2, #0.0 + fmov d2, #0.0 + +; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e] +; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e] +; CHECK: fmov d1, #0.12500000 ; encoding: [0x01,0x10,0x68,0x1e] +; CHECK: fmov d1, #0.12500000 ; encoding: [0x01,0x10,0x68,0x1e] +; CHECK: fmov d1, #-0.48437500 ; encoding: [0x01,0xf0,0x7b,0x1e] +; CHECK: fmov d1, #0.48437500 ; encoding: [0x01,0xf0,0x6b,0x1e] +; CHECK: fmov d3, #3.00000000 ; encoding: [0x03,0x10,0x61,0x1e] +; CHECK: fmov s2, wzr ; encoding: [0xe2,0x03,0x27,0x1e] +; CHECK: fmov d2, xzr ; encoding: [0xe2,0x03,0x67,0x9e] + + fmov s1, s2 + fmov d1, d2 + +; CHECK: fmov s1, s2 ; encoding: [0x41,0x40,0x20,0x1e] +; CHECK: fmov d1, d2 ; encoding: [0x41,0x40,0x60,0x1e] + + + fmov x2, v5.d[1] + fmov.d x9, v7[1] + fmov v1.d[1], x1 + fmov.d v8[1], x6 + +; CHECK: fmov.d x2, v5[1] ; encoding: [0xa2,0x00,0xae,0x9e] +; CHECK: fmov.d x9, v7[1] ; encoding: [0xe9,0x00,0xae,0x9e] +; CHECK: fmov.d v1[1], x1 ; encoding: [0x21,0x00,0xaf,0x9e] +; CHECK: fmov.d v8[1], x6 ; encoding: [0xc8,0x00,0xaf,0x9e] + + +;----------------------------------------------------------------------------- +; Floating-point round to integral +;----------------------------------------------------------------------------- + + frinta s1, s2 + frinta d1, d2 + +; CHECK: frinta s1, s2 ; encoding: [0x41,0x40,0x26,0x1e] +; CHECK: frinta d1, d2 ; encoding: [0x41,0x40,0x66,0x1e] + + frinti s1, s2 + frinti d1, d2 + +; CHECK: frinti s1, s2 ; encoding: [0x41,0xc0,0x27,0x1e] +; CHECK: frinti d1, d2 ; encoding: [0x41,0xc0,0x67,0x1e] + + frintm s1, s2 + frintm d1, d2 + +; CHECK: frintm s1, s2 ; encoding: [0x41,0x40,0x25,0x1e] +; CHECK: frintm d1, d2 ; encoding: [0x41,0x40,0x65,0x1e] + + frintn s1, s2 + frintn d1, d2 + +; CHECK: frintn s1, s2 ; encoding: [0x41,0x40,0x24,0x1e] +; CHECK: frintn d1, d2 ; encoding: [0x41,0x40,0x64,0x1e] + + frintp s1, s2 + frintp d1, d2 + +; CHECK: frintp s1, s2 ; encoding: [0x41,0xc0,0x24,0x1e] +; CHECK: frintp d1, d2 ; encoding: [0x41,0xc0,0x64,0x1e] + + frintx s1, s2 + frintx d1, d2 + +; CHECK: frintx s1, s2 ; encoding: [0x41,0x40,0x27,0x1e] +; CHECK: frintx d1, d2 ; encoding: [0x41,0x40,0x67,0x1e] + + frintz s1, s2 + frintz d1, d2 + +; CHECK: frintz s1, s2 ; encoding: [0x41,0xc0,0x25,0x1e] +; CHECK: frintz d1, d2 ; encoding: [0x41,0xc0,0x65,0x1e] + + cmhs d0, d0, d0 + cmtst d0, d0, d0 + +; CHECK: cmhs d0, d0, d0 ; encoding: [0x00,0x3c,0xe0,0x7e] +; CHECK: cmtst d0, d0, d0 ; encoding: [0x00,0x8c,0xe0,0x5e] + + + +;----------------------------------------------------------------------------- +; Floating-point extract and narrow +;----------------------------------------------------------------------------- + sqxtn b4, h2 + sqxtn h2, s3 + sqxtn s9, d2 + +; CHECK: sqxtn b4, h2 ; encoding: [0x44,0x48,0x21,0x5e] +; CHECK: sqxtn h2, s3 ; encoding: [0x62,0x48,0x61,0x5e] +; CHECK: sqxtn s9, d2 ; encoding: [0x49,0x48,0xa1,0x5e] + + sqxtun b4, h2 + sqxtun h2, s3 + sqxtun s9, d2 + +; CHECK: sqxtun b4, h2 ; encoding: [0x44,0x28,0x21,0x7e] +; CHECK: sqxtun h2, s3 ; encoding: [0x62,0x28,0x61,0x7e] +; CHECK: sqxtun s9, d2 ; encoding: [0x49,0x28,0xa1,0x7e] + + uqxtn b4, h2 + uqxtn h2, s3 + uqxtn s9, d2 + +; CHECK: uqxtn b4, h2 ; encoding: [0x44,0x48,0x21,0x7e] +; CHECK: uqxtn h2, s3 ; encoding: [0x62,0x48,0x61,0x7e] +; CHECK: uqxtn s9, d2 ; encoding: [0x49,0x48,0xa1,0x7e] diff --git a/test/MC/AArch64/arm64-large-relocs.s b/test/MC/AArch64/arm64-large-relocs.s new file mode 100644 index 0000000..2a0cfa2 --- /dev/null +++ b/test/MC/AArch64/arm64-large-relocs.s @@ -0,0 +1,38 @@ +// RUN: llvm-mc -triple=arm64-linux-gnu -show-encoding -o - %s | FileCheck %s +// RUN: llvm-mc -triple=arm64-linux-gnu -show-encoding -filetype=obj -o - %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-OBJ %s + + movz x2, #:abs_g0:sym + movk w3, #:abs_g0_nc:sym +// CHECK: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_aarch64_movw +// CHECK: movk w3, #:abs_g0_nc:sym // encoding: [0bAAA00011,A,0b100AAAAA,0x72] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_aarch64_movw + +// CHECK-OBJ: 0 R_AARCH64_MOVW_UABS_G0 sym +// CHECK-OBJ: 4 R_AARCH64_MOVW_UABS_G0_NC sym + + movz x4, #:abs_g1:sym + movk w5, #:abs_g1_nc:sym +// CHECK: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_aarch64_movw +// CHECK: movk w5, #:abs_g1_nc:sym // encoding: [0bAAA00101,A,0b101AAAAA,0x72] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_aarch64_movw + +// CHECK-OBJ: 8 R_AARCH64_MOVW_UABS_G1 sym +// CHECK-OBJ: c R_AARCH64_MOVW_UABS_G1_NC sym + + movz x6, #:abs_g2:sym + movk x7, #:abs_g2_nc:sym +// CHECK: movz x6, #:abs_g2:sym // encoding: [0bAAA00110,A,0b110AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_aarch64_movw +// CHECK: movk x7, #:abs_g2_nc:sym // encoding: [0bAAA00111,A,0b110AAAAA,0xf2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_aarch64_movw + +// CHECK-OBJ: 10 R_AARCH64_MOVW_UABS_G2 sym +// CHECK-OBJ: 14 R_AARCH64_MOVW_UABS_G2_NC sym + + movz x8, #:abs_g3:sym +// CHECK: movz x8, #:abs_g3:sym // encoding: [0bAAA01000,A,0b111AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_aarch64_movw + +// CHECK-OBJ: 18 R_AARCH64_MOVW_UABS_G3 sym diff --git a/test/MC/AArch64/arm64-leaf-compact-unwind.s b/test/MC/AArch64/arm64-leaf-compact-unwind.s new file mode 100644 index 0000000..d699813 --- /dev/null +++ b/test/MC/AArch64/arm64-leaf-compact-unwind.s @@ -0,0 +1,208 @@ +// RUN: llvm-mc -triple=arm64-apple-ios -filetype=obj < %s | \ +// RUN: llvm-readobj -sections -section-relocations -section-data | \ +// RUN: FileCheck %s +// +// rdar://13070556 + +// FIXME: we should add compact unwind support to llvm-objdump -unwind-info + +// CHECK: Section { +// CHECK: Index: 1 +// CHECK-NEXT: Name: __compact_unwind +// CHECK-NEXT: Segment: __LD +// CHECK-NEXT: Address: +// CHECK-NEXT: Size: +// CHECK-NEXT: Offset: +// CHECK-NEXT: Alignment: +// CHECK-NEXT: RelocationOffset: +// CHECK-NEXT: RelocationCount: +// CHECK-NEXT: Type: +// CHECK-NEXT: Attributes [ +// CHECK-NEXT: Debug +// CHECK-NEXT: ] +// CHECK-NEXT: Reserved1: +// CHECK-NEXT: Reserved2: +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x60 0 3 0 ARM64_RELOC_UNSIGNED 0 - +// CHECK-NEXT: 0x40 0 3 0 ARM64_RELOC_UNSIGNED 0 - +// CHECK-NEXT: 0x20 0 3 0 ARM64_RELOC_UNSIGNED 0 - +// CHECK-NEXT: 0x0 0 3 0 ARM64_RELOC_UNSIGNED 0 - +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 00000000 00000000 08000000 00000002 +// CHECK-NEXT: 0010: 00000000 00000000 00000000 00000000 +// CHECK-NEXT: 0020: 08000000 00000000 40000000 00900002 +// CHECK-NEXT: 0030: 00000000 00000000 00000000 00000000 +// CHECK-NEXT: 0040: 48000000 00000000 D4000000 0F400002 +// CHECK-NEXT: 0050: 00000000 00000000 00000000 00000000 +// CHECK-NEXT: 0060: 1C010000 00000000 54000000 10100202 +// CHECK-NEXT: 0070: 00000000 00000000 00000000 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } + + .section __TEXT,__text,regular,pure_instructions + .globl _foo1 + .align 2 +_foo1: ; @foo1 + .cfi_startproc +; BB#0: ; %entry + add w0, w0, #42 ; =#42 + ret + .cfi_endproc + + .globl _foo2 + .align 2 +_foo2: ; @foo2 + .cfi_startproc +; BB#0: ; %entry + sub sp, sp, #144 ; =#144 +Ltmp2: + .cfi_def_cfa_offset 144 + mov x9, xzr + mov x8, sp +LBB1_1: ; %for.body + ; =>This Inner Loop Header: Depth=1 + str w9, [x8, x9, lsl #2] + add x9, x9, #1 ; =#1 + cmp w9, #36 ; =#36 + b.ne LBB1_1 +; BB#2: + mov x9, xzr + mov w0, wzr +LBB1_3: ; %for.body4 + ; =>This Inner Loop Header: Depth=1 + ldr w10, [x8, x9] + add x9, x9, #4 ; =#4 + cmp w9, #144 ; =#144 + add w0, w10, w0 + b.ne LBB1_3 +; BB#4: ; %for.end9 + add sp, sp, #144 ; =#144 + ret + .cfi_endproc + + .globl _foo3 + .align 2 +_foo3: ; @foo3 + .cfi_startproc +; BB#0: ; %entry + stp x26, x25, [sp, #-64]! + stp x24, x23, [sp, #16] + stp x22, x21, [sp, #32] + stp x20, x19, [sp, #48] +Ltmp3: + .cfi_def_cfa_offset 64 +Ltmp4: + .cfi_offset w19, -16 +Ltmp5: + .cfi_offset w20, -24 +Ltmp6: + .cfi_offset w21, -32 +Ltmp7: + .cfi_offset w22, -40 +Ltmp8: + .cfi_offset w23, -48 +Ltmp9: + .cfi_offset w24, -56 +Ltmp10: + .cfi_offset w25, -64 +Ltmp11: + .cfi_offset w26, -72 +Lloh0: + adrp x8, _bar@GOTPAGE +Lloh1: + ldr x8, [x8, _bar@GOTPAGEOFF] + ldr w9, [x8] + ldr w10, [x8] + ldr w11, [x8] + ldr w12, [x8] + ldr w13, [x8] + ldr w14, [x8] + ldr w15, [x8] + ldr w16, [x8] + ldr w17, [x8] + ldr w0, [x8] + ldr w19, [x8] + ldr w20, [x8] + ldr w21, [x8] + ldr w22, [x8] + ldr w23, [x8] + ldr w24, [x8] + ldr w25, [x8] + ldr w8, [x8] + add w9, w10, w9 + add w9, w9, w11 + add w9, w9, w12 + add w9, w9, w13 + add w9, w9, w14 + add w9, w9, w15 + add w9, w9, w16 + add w9, w9, w17 + add w9, w9, w0 + add w9, w9, w19 + add w9, w9, w20 + add w9, w9, w21 + add w9, w9, w22 + add w9, w9, w23 + add w9, w9, w24 + add w9, w9, w25 + sub w8, w8, w9 + sub w8, w8, w7, lsl #1 + sub w8, w8, w6, lsl #1 + sub w8, w8, w5, lsl #1 + sub w8, w8, w4, lsl #1 + sub w8, w8, w3, lsl #1 + sub w8, w8, w2, lsl #1 + sub w0, w8, w1, lsl #1 + ldp x20, x19, [sp, #48] + ldp x22, x21, [sp, #32] + ldp x24, x23, [sp, #16] + ldp x26, x25, [sp], #64 + ret + .loh AdrpLdrGot Lloh0, Lloh1 + .cfi_endproc + + .globl _foo4 + .align 2 +_foo4: ; @foo4 + .cfi_startproc +; BB#0: ; %entry + stp x28, x27, [sp, #-16]! + sub sp, sp, #512 ; =#512 +Ltmp12: + .cfi_def_cfa_offset 528 +Ltmp13: + .cfi_offset w27, -16 +Ltmp14: + .cfi_offset w28, -24 + ; kill: W0<def> W0<kill> X0<def> + mov x9, xzr + ubfx x10, x0, #0, #32 + mov x8, sp +LBB3_1: ; %for.body + ; =>This Inner Loop Header: Depth=1 + add w11, w10, w9 + str w11, [x8, x9, lsl #2] + add x9, x9, #1 ; =#1 + cmp w9, #128 ; =#128 + b.ne LBB3_1 +; BB#2: ; %for.cond2.preheader + mov x9, xzr + mov w0, wzr + add x8, x8, w5, sxtw #2 +LBB3_3: ; %for.body4 + ; =>This Inner Loop Header: Depth=1 + ldr w10, [x8, x9] + add x9, x9, #4 ; =#4 + cmp w9, #512 ; =#512 + add w0, w10, w0 + b.ne LBB3_3 +; BB#4: ; %for.end11 + add sp, sp, #512 ; =#512 + ldp x28, x27, [sp], #16 + ret + .cfi_endproc + + .comm _bar,4,2 ; @bar + +.subsections_via_symbols diff --git a/test/MC/AArch64/arm64-logical-encoding.s b/test/MC/AArch64/arm64-logical-encoding.s new file mode 100644 index 0000000..e5f1436 --- /dev/null +++ b/test/MC/AArch64/arm64-logical-encoding.s @@ -0,0 +1,224 @@ +; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s + +foo: +;==---------------------------------------------------------------------------== +; 5.4.2 Logical (immediate) +;==---------------------------------------------------------------------------== + + and w0, w0, #1 + and x0, x0, #1 + and w1, w2, #15 + and x1, x2, #15 + and sp, x5, #~15 + ands w0, w0, #1 + ands x0, x0, #1 + ands w1, w2, #15 + ands x1, x2, #15 + +; CHECK: and w0, w0, #0x1 ; encoding: [0x00,0x00,0x00,0x12] +; CHECK: and x0, x0, #0x1 ; encoding: [0x00,0x00,0x40,0x92] +; CHECK: and w1, w2, #0xf ; encoding: [0x41,0x0c,0x00,0x12] +; CHECK: and x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0x92] +; CHECK: and sp, x5, #0xfffffffffffffff0 ; encoding: [0xbf,0xec,0x7c,0x92] +; CHECK: ands w0, w0, #0x1 ; encoding: [0x00,0x00,0x00,0x72] +; CHECK: ands x0, x0, #0x1 ; encoding: [0x00,0x00,0x40,0xf2] +; CHECK: ands w1, w2, #0xf ; encoding: [0x41,0x0c,0x00,0x72] +; CHECK: ands x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0xf2] + + eor w1, w2, #0x4000 + eor x1, x2, #0x8000 + +; CHECK: eor w1, w2, #0x4000 ; encoding: [0x41,0x00,0x12,0x52] +; CHECK: eor x1, x2, #0x8000 ; encoding: [0x41,0x00,0x71,0xd2] + + orr w1, w2, #0x4000 + orr x1, x2, #0x8000 + +; CHECK: orr w1, w2, #0x4000 ; encoding: [0x41,0x00,0x12,0x32] +; CHECK: orr x1, x2, #0x8000 ; encoding: [0x41,0x00,0x71,0xb2] + + orr w8, wzr, #0x1 + orr x8, xzr, #0x1 + +; CHECK: orr w8, wzr, #0x1 ; encoding: [0xe8,0x03,0x00,0x32] +; CHECK: orr x8, xzr, #0x1 ; encoding: [0xe8,0x03,0x40,0xb2] + +;==---------------------------------------------------------------------------== +; 5.5.3 Logical (shifted register) +;==---------------------------------------------------------------------------== + + and w1, w2, w3 + and x1, x2, x3 + and w1, w2, w3, lsl #2 + and x1, x2, x3, lsl #2 + and w1, w2, w3, lsr #2 + and x1, x2, x3, lsr #2 + and w1, w2, w3, asr #2 + and x1, x2, x3, asr #2 + and w1, w2, w3, ror #2 + and x1, x2, x3, ror #2 + +; CHECK: and w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x0a] +; CHECK: and x1, x2, x3 ; encoding: [0x41,0x00,0x03,0x8a] +; CHECK: and w1, w2, w3, lsl #2 ; encoding: [0x41,0x08,0x03,0x0a] +; CHECK: and x1, x2, x3, lsl #2 ; encoding: [0x41,0x08,0x03,0x8a] +; CHECK: and w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x0a] +; CHECK: and x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0x8a] +; CHECK: and w1, w2, w3, asr #2 ; encoding: [0x41,0x08,0x83,0x0a] +; CHECK: and x1, x2, x3, asr #2 ; encoding: [0x41,0x08,0x83,0x8a] +; CHECK: and w1, w2, w3, ror #2 ; encoding: [0x41,0x08,0xc3,0x0a] +; CHECK: and x1, x2, x3, ror #2 ; encoding: [0x41,0x08,0xc3,0x8a] + + ands w1, w2, w3 + ands x1, x2, x3 + ands w1, w2, w3, lsl #2 + ands x1, x2, x3, lsl #2 + ands w1, w2, w3, lsr #2 + ands x1, x2, x3, lsr #2 + ands w1, w2, w3, asr #2 + ands x1, x2, x3, asr #2 + ands w1, w2, w3, ror #2 + ands x1, x2, x3, ror #2 + +; CHECK: ands w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x6a] +; CHECK: ands x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xea] +; CHECK: ands w1, w2, w3, lsl #2 ; encoding: [0x41,0x08,0x03,0x6a] +; CHECK: ands x1, x2, x3, lsl #2 ; encoding: [0x41,0x08,0x03,0xea] +; CHECK: ands w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x6a] +; CHECK: ands x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0xea] +; CHECK: ands w1, w2, w3, asr #2 ; encoding: [0x41,0x08,0x83,0x6a] +; CHECK: ands x1, x2, x3, asr #2 ; encoding: [0x41,0x08,0x83,0xea] +; CHECK: ands w1, w2, w3, ror #2 ; encoding: [0x41,0x08,0xc3,0x6a] +; CHECK: ands x1, x2, x3, ror #2 ; encoding: [0x41,0x08,0xc3,0xea] + + bic w1, w2, w3 + bic x1, x2, x3 + bic w1, w2, w3, lsl #3 + bic x1, x2, x3, lsl #3 + bic w1, w2, w3, lsr #3 + bic x1, x2, x3, lsr #3 + bic w1, w2, w3, asr #3 + bic x1, x2, x3, asr #3 + bic w1, w2, w3, ror #3 + bic x1, x2, x3, ror #3 + +; CHECK: bic w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x0a] +; CHECK: bic x1, x2, x3 ; encoding: [0x41,0x00,0x23,0x8a] +; CHECK: bic w1, w2, w3, lsl #3 ; encoding: [0x41,0x0c,0x23,0x0a] +; CHECK: bic x1, x2, x3, lsl #3 ; encoding: [0x41,0x0c,0x23,0x8a] +; CHECK: bic w1, w2, w3, lsr #3 ; encoding: [0x41,0x0c,0x63,0x0a] +; CHECK: bic x1, x2, x3, lsr #3 ; encoding: [0x41,0x0c,0x63,0x8a] +; CHECK: bic w1, w2, w3, asr #3 ; encoding: [0x41,0x0c,0xa3,0x0a] +; CHECK: bic x1, x2, x3, asr #3 ; encoding: [0x41,0x0c,0xa3,0x8a] +; CHECK: bic w1, w2, w3, ror #3 ; encoding: [0x41,0x0c,0xe3,0x0a] +; CHECK: bic x1, x2, x3, ror #3 ; encoding: [0x41,0x0c,0xe3,0x8a] + + bics w1, w2, w3 + bics x1, x2, x3 + bics w1, w2, w3, lsl #3 + bics x1, x2, x3, lsl #3 + bics w1, w2, w3, lsr #3 + bics x1, x2, x3, lsr #3 + bics w1, w2, w3, asr #3 + bics x1, x2, x3, asr #3 + bics w1, w2, w3, ror #3 + bics x1, x2, x3, ror #3 + +; CHECK: bics w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x6a] +; CHECK: bics x1, x2, x3 ; encoding: [0x41,0x00,0x23,0xea] +; CHECK: bics w1, w2, w3, lsl #3 ; encoding: [0x41,0x0c,0x23,0x6a] +; CHECK: bics x1, x2, x3, lsl #3 ; encoding: [0x41,0x0c,0x23,0xea] +; CHECK: bics w1, w2, w3, lsr #3 ; encoding: [0x41,0x0c,0x63,0x6a] +; CHECK: bics x1, x2, x3, lsr #3 ; encoding: [0x41,0x0c,0x63,0xea] +; CHECK: bics w1, w2, w3, asr #3 ; encoding: [0x41,0x0c,0xa3,0x6a] +; CHECK: bics x1, x2, x3, asr #3 ; encoding: [0x41,0x0c,0xa3,0xea] +; CHECK: bics w1, w2, w3, ror #3 ; encoding: [0x41,0x0c,0xe3,0x6a] +; CHECK: bics x1, x2, x3, ror #3 ; encoding: [0x41,0x0c,0xe3,0xea] + + eon w1, w2, w3 + eon x1, x2, x3 + eon w1, w2, w3, lsl #4 + eon x1, x2, x3, lsl #4 + eon w1, w2, w3, lsr #4 + eon x1, x2, x3, lsr #4 + eon w1, w2, w3, asr #4 + eon x1, x2, x3, asr #4 + eon w1, w2, w3, ror #4 + eon x1, x2, x3, ror #4 + +; CHECK: eon w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x4a] +; CHECK: eon x1, x2, x3 ; encoding: [0x41,0x00,0x23,0xca] +; CHECK: eon w1, w2, w3, lsl #4 ; encoding: [0x41,0x10,0x23,0x4a] +; CHECK: eon x1, x2, x3, lsl #4 ; encoding: [0x41,0x10,0x23,0xca] +; CHECK: eon w1, w2, w3, lsr #4 ; encoding: [0x41,0x10,0x63,0x4a] +; CHECK: eon x1, x2, x3, lsr #4 ; encoding: [0x41,0x10,0x63,0xca] +; CHECK: eon w1, w2, w3, asr #4 ; encoding: [0x41,0x10,0xa3,0x4a] +; CHECK: eon x1, x2, x3, asr #4 ; encoding: [0x41,0x10,0xa3,0xca] +; CHECK: eon w1, w2, w3, ror #4 ; encoding: [0x41,0x10,0xe3,0x4a] +; CHECK: eon x1, x2, x3, ror #4 ; encoding: [0x41,0x10,0xe3,0xca] + + eor w1, w2, w3 + eor x1, x2, x3 + eor w1, w2, w3, lsl #5 + eor x1, x2, x3, lsl #5 + eor w1, w2, w3, lsr #5 + eor x1, x2, x3, lsr #5 + eor w1, w2, w3, asr #5 + eor x1, x2, x3, asr #5 + eor w1, w2, w3, ror #5 + eor x1, x2, x3, ror #5 + +; CHECK: eor w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x4a] +; CHECK: eor x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xca] +; CHECK: eor w1, w2, w3, lsl #5 ; encoding: [0x41,0x14,0x03,0x4a] +; CHECK: eor x1, x2, x3, lsl #5 ; encoding: [0x41,0x14,0x03,0xca] +; CHECK: eor w1, w2, w3, lsr #5 ; encoding: [0x41,0x14,0x43,0x4a] +; CHECK: eor x1, x2, x3, lsr #5 ; encoding: [0x41,0x14,0x43,0xca] +; CHECK: eor w1, w2, w3, asr #5 ; encoding: [0x41,0x14,0x83,0x4a] +; CHECK: eor x1, x2, x3, asr #5 ; encoding: [0x41,0x14,0x83,0xca] +; CHECK: eor w1, w2, w3, ror #5 ; encoding: [0x41,0x14,0xc3,0x4a] +; CHECK: eor x1, x2, x3, ror #5 ; encoding: [0x41,0x14,0xc3,0xca] + + orr w1, w2, w3 + orr x1, x2, x3 + orr w1, w2, w3, lsl #6 + orr x1, x2, x3, lsl #6 + orr w1, w2, w3, lsr #6 + orr x1, x2, x3, lsr #6 + orr w1, w2, w3, asr #6 + orr x1, x2, x3, asr #6 + orr w1, w2, w3, ror #6 + orr x1, x2, x3, ror #6 + +; CHECK: orr w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x2a] +; CHECK: orr x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xaa] +; CHECK: orr w1, w2, w3, lsl #6 ; encoding: [0x41,0x18,0x03,0x2a] +; CHECK: orr x1, x2, x3, lsl #6 ; encoding: [0x41,0x18,0x03,0xaa] +; CHECK: orr w1, w2, w3, lsr #6 ; encoding: [0x41,0x18,0x43,0x2a] +; CHECK: orr x1, x2, x3, lsr #6 ; encoding: [0x41,0x18,0x43,0xaa] +; CHECK: orr w1, w2, w3, asr #6 ; encoding: [0x41,0x18,0x83,0x2a] +; CHECK: orr x1, x2, x3, asr #6 ; encoding: [0x41,0x18,0x83,0xaa] +; CHECK: orr w1, w2, w3, ror #6 ; encoding: [0x41,0x18,0xc3,0x2a] +; CHECK: orr x1, x2, x3, ror #6 ; encoding: [0x41,0x18,0xc3,0xaa] + + orn w1, w2, w3 + orn x1, x2, x3 + orn w1, w2, w3, lsl #7 + orn x1, x2, x3, lsl #7 + orn w1, w2, w3, lsr #7 + orn x1, x2, x3, lsr #7 + orn w1, w2, w3, asr #7 + orn x1, x2, x3, asr #7 + orn w1, w2, w3, ror #7 + orn x1, x2, x3, ror #7 + +; CHECK: orn w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x2a] +; CHECK: orn x1, x2, x3 ; encoding: [0x41,0x00,0x23,0xaa] +; CHECK: orn w1, w2, w3, lsl #7 ; encoding: [0x41,0x1c,0x23,0x2a] +; CHECK: orn x1, x2, x3, lsl #7 ; encoding: [0x41,0x1c,0x23,0xaa] +; CHECK: orn w1, w2, w3, lsr #7 ; encoding: [0x41,0x1c,0x63,0x2a] +; CHECK: orn x1, x2, x3, lsr #7 ; encoding: [0x41,0x1c,0x63,0xaa] +; CHECK: orn w1, w2, w3, asr #7 ; encoding: [0x41,0x1c,0xa3,0x2a] +; CHECK: orn x1, x2, x3, asr #7 ; encoding: [0x41,0x1c,0xa3,0xaa] +; CHECK: orn w1, w2, w3, ror #7 ; encoding: [0x41,0x1c,0xe3,0x2a] +; CHECK: orn x1, x2, x3, ror #7 ; encoding: [0x41,0x1c,0xe3,0xaa] diff --git a/test/MC/AArch64/arm64-mapping-across-sections.s b/test/MC/AArch64/arm64-mapping-across-sections.s new file mode 100644 index 0000000..00b324c --- /dev/null +++ b/test/MC/AArch64/arm64-mapping-across-sections.s @@ -0,0 +1,28 @@ +// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s | llvm-objdump -t - | FileCheck %s + + .text + add w0, w0, w0 + +// .wibble should *not* inherit .text's mapping symbol. It's a completely different section. + .section .wibble + add w0, w0, w0 + +// A setion should be able to start with a $d + .section .starts_data + .word 42 + +// Changing back to .text should not emit a redundant $x + .text + add w0, w0, w0 + +// With all those constraints, we want: +// + .text to have $x at 0 and no others +// + .wibble to have $x at 0 +// + .starts_data to have $d at 0 + + +// CHECK: 00000000 .starts_data 00000000 $d +// CHECK-NEXT: 00000000 .text 00000000 $x +// CHECK-NEXT: 00000000 .wibble 00000000 $x +// CHECK-NOT: ${{[adtx]}} + diff --git a/test/MC/AArch64/arm64-mapping-within-section.s b/test/MC/AArch64/arm64-mapping-within-section.s new file mode 100644 index 0000000..f515cb9 --- /dev/null +++ b/test/MC/AArch64/arm64-mapping-within-section.s @@ -0,0 +1,23 @@ +// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s | llvm-objdump -t - | FileCheck %s + + .text +// $x at 0x0000 + add w0, w0, w0 +// $d at 0x0004 + .ascii "012" + .byte 1 + .hword 2 + .word 4 + .xword 8 + .single 4.0 + .double 8.0 + .space 10 + .zero 3 + .fill 10, 2, 42 + .org 100, 12 +// $x at 0x0018 + add x0, x0, x0 + +// CHECK: 00000004 .text 00000000 $d +// CHECK-NEXT: 00000000 .text 00000000 $x +// CHECK-NEXT: 00000064 .text 00000000 $x diff --git a/test/MC/AArch64/arm64-memory.s b/test/MC/AArch64/arm64-memory.s new file mode 100644 index 0000000..5798596 --- /dev/null +++ b/test/MC/AArch64/arm64-memory.s @@ -0,0 +1,634 @@ +; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s + +foo: +;----------------------------------------------------------------------------- +; Indexed loads +;----------------------------------------------------------------------------- + + ldr w5, [x4, #20] + ldr x4, [x3] + ldr x2, [sp, #32] + ldr b5, [sp, #1] + ldr h6, [sp, #2] + ldr s7, [sp, #4] + ldr d8, [sp, #8] + ldr q9, [sp, #16] + ldrb w4, [x3] + ldrb w5, [x4, #20] + ldrb w2, [x3, _foo@pageoff] + ldrb w3, [x2, "+[Test method].var"@PAGEOFF] + ldrsb w9, [x3] + ldrsb x2, [sp, #128] + ldrh w2, [sp, #32] + ldrsh w3, [sp, #32] + ldrsh x5, [x9, #24] + ldrsw x9, [sp, #512] + + prfm #5, [sp, #32] + prfm #31, [sp, #32] + prfm pldl1keep, [x2] + prfm pldl1strm, [x2] + prfm pldl2keep, [x2] + prfm pldl2strm, [x2] + prfm pldl3keep, [x2] + prfm pldl3strm, [x2] + prfm pstl1keep, [x2] + prfm pstl1strm, [x2] + prfm pstl2keep, [x2] + prfm pstl2strm, [x2] + prfm pstl3keep, [x2] + prfm pstl3strm, [x2] + prfm pstl3strm, [x4, x5, lsl #3] + +; CHECK: ldr w5, [x4, #20] ; encoding: [0x85,0x14,0x40,0xb9] +; CHECK: ldr x4, [x3] ; encoding: [0x64,0x00,0x40,0xf9] +; CHECK: ldr x2, [sp, #32] ; encoding: [0xe2,0x13,0x40,0xf9] +; CHECK: ldr b5, [sp, #1] ; encoding: [0xe5,0x07,0x40,0x3d] +; CHECK: ldr h6, [sp, #2] ; encoding: [0xe6,0x07,0x40,0x7d] +; CHECK: ldr s7, [sp, #4] ; encoding: [0xe7,0x07,0x40,0xbd] +; CHECK: ldr d8, [sp, #8] ; encoding: [0xe8,0x07,0x40,0xfd] +; CHECK: ldr q9, [sp, #16] ; encoding: [0xe9,0x07,0xc0,0x3d] +; CHECK: ldrb w4, [x3] ; encoding: [0x64,0x00,0x40,0x39] +; CHECK: ldrb w5, [x4, #20] ; encoding: [0x85,0x50,0x40,0x39] +; CHECK: ldrb w2, [x3, _foo@PAGEOFF] ; encoding: [0x62,0bAAAAAA00,0b01AAAAAA,0x39] +; CHECK: ldrb w3, [x2, "+[Test method].var"@PAGEOFF] ; encoding: [0x43,0bAAAAAA00,0b01AAAAAA,0x39] +; CHECK: ldrsb w9, [x3] ; encoding: [0x69,0x00,0xc0,0x39] +; CHECK: ldrsb x2, [sp, #128] ; encoding: [0xe2,0x03,0x82,0x39] +; CHECK: ldrh w2, [sp, #32] ; encoding: [0xe2,0x43,0x40,0x79] +; CHECK: ldrsh w3, [sp, #32] ; encoding: [0xe3,0x43,0xc0,0x79] +; CHECK: ldrsh x5, [x9, #24] ; encoding: [0x25,0x31,0x80,0x79] +; CHECK: ldrsw x9, [sp, #512] ; encoding: [0xe9,0x03,0x82,0xb9] +; CHECK: prfm pldl3strm, [sp, #32] ; encoding: [0xe5,0x13,0x80,0xf9] +; CHECK: prfm #31, [sp, #32] ; encoding: [0xff,0x13,0x80,0xf9] +; CHECK: prfm pldl1keep, [x2] ; encoding: [0x40,0x00,0x80,0xf9] +; CHECK: prfm pldl1strm, [x2] ; encoding: [0x41,0x00,0x80,0xf9] +; CHECK: prfm pldl2keep, [x2] ; encoding: [0x42,0x00,0x80,0xf9] +; CHECK: prfm pldl2strm, [x2] ; encoding: [0x43,0x00,0x80,0xf9] +; CHECK: prfm pldl3keep, [x2] ; encoding: [0x44,0x00,0x80,0xf9] +; CHECK: prfm pldl3strm, [x2] ; encoding: [0x45,0x00,0x80,0xf9] +; CHECK: prfm pstl1keep, [x2] ; encoding: [0x50,0x00,0x80,0xf9] +; CHECK: prfm pstl1strm, [x2] ; encoding: [0x51,0x00,0x80,0xf9] +; CHECK: prfm pstl2keep, [x2] ; encoding: [0x52,0x00,0x80,0xf9] +; CHECK: prfm pstl2strm, [x2] ; encoding: [0x53,0x00,0x80,0xf9] +; CHECK: prfm pstl3keep, [x2] ; encoding: [0x54,0x00,0x80,0xf9] +; CHECK: prfm pstl3strm, [x2] ; encoding: [0x55,0x00,0x80,0xf9] +; CHECK: prfm pstl3strm, [x4, x5, lsl #3] ; encoding: [0x95,0x78,0xa5,0xf8] + +;----------------------------------------------------------------------------- +; Indexed stores +;----------------------------------------------------------------------------- + + str x4, [x3] + str x2, [sp, #32] + str w5, [x4, #20] + str b5, [sp, #1] + str h6, [sp, #2] + str s7, [sp, #4] + str d8, [sp, #8] + str q9, [sp, #16] + strb w4, [x3] + strb w5, [x4, #20] + strh w2, [sp, #32] + +; CHECK: str x4, [x3] ; encoding: [0x64,0x00,0x00,0xf9] +; CHECK: str x2, [sp, #32] ; encoding: [0xe2,0x13,0x00,0xf9] +; CHECK: str w5, [x4, #20] ; encoding: [0x85,0x14,0x00,0xb9] +; CHECK: str b5, [sp, #1] ; encoding: [0xe5,0x07,0x00,0x3d] +; CHECK: str h6, [sp, #2] ; encoding: [0xe6,0x07,0x00,0x7d] +; CHECK: str s7, [sp, #4] ; encoding: [0xe7,0x07,0x00,0xbd] +; CHECK: str d8, [sp, #8] ; encoding: [0xe8,0x07,0x00,0xfd] +; CHECK: str q9, [sp, #16] ; encoding: [0xe9,0x07,0x80,0x3d] +; CHECK: strb w4, [x3] ; encoding: [0x64,0x00,0x00,0x39] +; CHECK: strb w5, [x4, #20] ; encoding: [0x85,0x50,0x00,0x39] +; CHECK: strh w2, [sp, #32] ; encoding: [0xe2,0x43,0x00,0x79] + +;----------------------------------------------------------------------------- +; Unscaled immediate loads and stores +;----------------------------------------------------------------------------- + + ldur w2, [x3] + ldur w2, [sp, #24] + ldur x2, [x3] + ldur x2, [sp, #24] + ldur b5, [sp, #1] + ldur h6, [sp, #2] + ldur s7, [sp, #4] + ldur d8, [sp, #8] + ldur q9, [sp, #16] + ldursb w9, [x3] + ldursb x2, [sp, #128] + ldursh w3, [sp, #32] + ldursh x5, [x9, #24] + ldursw x9, [sp, #-128] + +; CHECK: ldur w2, [x3] ; encoding: [0x62,0x00,0x40,0xb8] +; CHECK: ldur w2, [sp, #24] ; encoding: [0xe2,0x83,0x41,0xb8] +; CHECK: ldur x2, [x3] ; encoding: [0x62,0x00,0x40,0xf8] +; CHECK: ldur x2, [sp, #24] ; encoding: [0xe2,0x83,0x41,0xf8] +; CHECK: ldur b5, [sp, #1] ; encoding: [0xe5,0x13,0x40,0x3c] +; CHECK: ldur h6, [sp, #2] ; encoding: [0xe6,0x23,0x40,0x7c] +; CHECK: ldur s7, [sp, #4] ; encoding: [0xe7,0x43,0x40,0xbc] +; CHECK: ldur d8, [sp, #8] ; encoding: [0xe8,0x83,0x40,0xfc] +; CHECK: ldur q9, [sp, #16] ; encoding: [0xe9,0x03,0xc1,0x3c] +; CHECK: ldursb w9, [x3] ; encoding: [0x69,0x00,0xc0,0x38] +; CHECK: ldursb x2, [sp, #128] ; encoding: [0xe2,0x03,0x88,0x38] +; CHECK: ldursh w3, [sp, #32] ; encoding: [0xe3,0x03,0xc2,0x78] +; CHECK: ldursh x5, [x9, #24] ; encoding: [0x25,0x81,0x81,0x78] +; CHECK: ldursw x9, [sp, #-128] ; encoding: [0xe9,0x03,0x98,0xb8] + + stur w4, [x3] + stur w2, [sp, #32] + stur x4, [x3] + stur x2, [sp, #32] + stur w5, [x4, #20] + stur b5, [sp, #1] + stur h6, [sp, #2] + stur s7, [sp, #4] + stur d8, [sp, #8] + stur q9, [sp, #16] + sturb w4, [x3] + sturb w5, [x4, #20] + sturh w2, [sp, #32] + prfum #5, [sp, #32] + +; CHECK: stur w4, [x3] ; encoding: [0x64,0x00,0x00,0xb8] +; CHECK: stur w2, [sp, #32] ; encoding: [0xe2,0x03,0x02,0xb8] +; CHECK: stur x4, [x3] ; encoding: [0x64,0x00,0x00,0xf8] +; CHECK: stur x2, [sp, #32] ; encoding: [0xe2,0x03,0x02,0xf8] +; CHECK: stur w5, [x4, #20] ; encoding: [0x85,0x40,0x01,0xb8] +; CHECK: stur b5, [sp, #1] ; encoding: [0xe5,0x13,0x00,0x3c] +; CHECK: stur h6, [sp, #2] ; encoding: [0xe6,0x23,0x00,0x7c] +; CHECK: stur s7, [sp, #4] ; encoding: [0xe7,0x43,0x00,0xbc] +; CHECK: stur d8, [sp, #8] ; encoding: [0xe8,0x83,0x00,0xfc] +; CHECK: stur q9, [sp, #16] ; encoding: [0xe9,0x03,0x81,0x3c] +; CHECK: sturb w4, [x3] ; encoding: [0x64,0x00,0x00,0x38] +; CHECK: sturb w5, [x4, #20] ; encoding: [0x85,0x40,0x01,0x38] +; CHECK: sturh w2, [sp, #32] ; encoding: [0xe2,0x03,0x02,0x78] +; CHECK: prfum pldl3strm, [sp, #32] ; encoding: [0xe5,0x03,0x82,0xf8] + +;----------------------------------------------------------------------------- +; Unprivileged loads and stores +;----------------------------------------------------------------------------- + + ldtr w3, [x4, #16] + ldtr x3, [x4, #16] + ldtrb w3, [x4, #16] + ldtrsb w9, [x3] + ldtrsb x2, [sp, #128] + ldtrh w3, [x4, #16] + ldtrsh w3, [sp, #32] + ldtrsh x5, [x9, #24] + ldtrsw x9, [sp, #-128] + +; CHECK: ldtr w3, [x4, #16] ; encoding: [0x83,0x08,0x41,0xb8] +; CHECK: ldtr x3, [x4, #16] ; encoding: [0x83,0x08,0x41,0xf8] +; CHECK: ldtrb w3, [x4, #16] ; encoding: [0x83,0x08,0x41,0x38] +; CHECK: ldtrsb w9, [x3] ; encoding: [0x69,0x08,0xc0,0x38] +; CHECK: ldtrsb x2, [sp, #128] ; encoding: [0xe2,0x0b,0x88,0x38] +; CHECK: ldtrh w3, [x4, #16] ; encoding: [0x83,0x08,0x41,0x78] +; CHECK: ldtrsh w3, [sp, #32] ; encoding: [0xe3,0x0b,0xc2,0x78] +; CHECK: ldtrsh x5, [x9, #24] ; encoding: [0x25,0x89,0x81,0x78] +; CHECK: ldtrsw x9, [sp, #-128] ; encoding: [0xe9,0x0b,0x98,0xb8] + + sttr w5, [x4, #20] + sttr x4, [x3] + sttr x2, [sp, #32] + sttrb w4, [x3] + sttrb w5, [x4, #20] + sttrh w2, [sp, #32] + +; CHECK: sttr w5, [x4, #20] ; encoding: [0x85,0x48,0x01,0xb8] +; CHECK: sttr x4, [x3] ; encoding: [0x64,0x08,0x00,0xf8] +; CHECK: sttr x2, [sp, #32] ; encoding: [0xe2,0x0b,0x02,0xf8] +; CHECK: sttrb w4, [x3] ; encoding: [0x64,0x08,0x00,0x38] +; CHECK: sttrb w5, [x4, #20] ; encoding: [0x85,0x48,0x01,0x38] +; CHECK: sttrh w2, [sp, #32] ; encoding: [0xe2,0x0b,0x02,0x78] + +;----------------------------------------------------------------------------- +; Pre-indexed loads and stores +;----------------------------------------------------------------------------- + + ldr x29, [x7, #8]! + ldr x30, [x7, #8]! + ldr b5, [x0, #1]! + ldr h6, [x0, #2]! + ldr s7, [x0, #4]! + ldr d8, [x0, #8]! + ldr q9, [x0, #16]! + + str x30, [x7, #-8]! + str x29, [x7, #-8]! + str b5, [x0, #-1]! + str h6, [x0, #-2]! + str s7, [x0, #-4]! + str d8, [x0, #-8]! + str q9, [x0, #-16]! + +; CHECK: ldr x29, [x7, #8]! ; encoding: [0xfd,0x8c,0x40,0xf8] +; CHECK: ldr x30, [x7, #8]! ; encoding: [0xfe,0x8c,0x40,0xf8] +; CHECK: ldr b5, [x0, #1]! ; encoding: [0x05,0x1c,0x40,0x3c] +; CHECK: ldr h6, [x0, #2]! ; encoding: [0x06,0x2c,0x40,0x7c] +; CHECK: ldr s7, [x0, #4]! ; encoding: [0x07,0x4c,0x40,0xbc] +; CHECK: ldr d8, [x0, #8]! ; encoding: [0x08,0x8c,0x40,0xfc] +; CHECK: ldr q9, [x0, #16]! ; encoding: [0x09,0x0c,0xc1,0x3c] + +; CHECK: str x30, [x7, #-8]! ; encoding: [0xfe,0x8c,0x1f,0xf8] +; CHECK: str x29, [x7, #-8]! ; encoding: [0xfd,0x8c,0x1f,0xf8] +; CHECK: str b5, [x0, #-1]! ; encoding: [0x05,0xfc,0x1f,0x3c] +; CHECK: str h6, [x0, #-2]! ; encoding: [0x06,0xec,0x1f,0x7c] +; CHECK: str s7, [x0, #-4]! ; encoding: [0x07,0xcc,0x1f,0xbc] +; CHECK: str d8, [x0, #-8]! ; encoding: [0x08,0x8c,0x1f,0xfc] +; CHECK: str q9, [x0, #-16]! ; encoding: [0x09,0x0c,0x9f,0x3c] + +;----------------------------------------------------------------------------- +; post-indexed loads and stores +;----------------------------------------------------------------------------- + str x30, [x7], #-8 + str x29, [x7], #-8 + str b5, [x0], #-1 + str h6, [x0], #-2 + str s7, [x0], #-4 + str d8, [x0], #-8 + str q9, [x0], #-16 + + ldr x29, [x7], #8 + ldr x30, [x7], #8 + ldr b5, [x0], #1 + ldr h6, [x0], #2 + ldr s7, [x0], #4 + ldr d8, [x0], #8 + ldr q9, [x0], #16 + +; CHECK: str x30, [x7], #-8 ; encoding: [0xfe,0x84,0x1f,0xf8] +; CHECK: str x29, [x7], #-8 ; encoding: [0xfd,0x84,0x1f,0xf8] +; CHECK: str b5, [x0], #-1 ; encoding: [0x05,0xf4,0x1f,0x3c] +; CHECK: str h6, [x0], #-2 ; encoding: [0x06,0xe4,0x1f,0x7c] +; CHECK: str s7, [x0], #-4 ; encoding: [0x07,0xc4,0x1f,0xbc] +; CHECK: str d8, [x0], #-8 ; encoding: [0x08,0x84,0x1f,0xfc] +; CHECK: str q9, [x0], #-16 ; encoding: [0x09,0x04,0x9f,0x3c] + +; CHECK: ldr x29, [x7], #8 ; encoding: [0xfd,0x84,0x40,0xf8] +; CHECK: ldr x30, [x7], #8 ; encoding: [0xfe,0x84,0x40,0xf8] +; CHECK: ldr b5, [x0], #1 ; encoding: [0x05,0x14,0x40,0x3c] +; CHECK: ldr h6, [x0], #2 ; encoding: [0x06,0x24,0x40,0x7c] +; CHECK: ldr s7, [x0], #4 ; encoding: [0x07,0x44,0x40,0xbc] +; CHECK: ldr d8, [x0], #8 ; encoding: [0x08,0x84,0x40,0xfc] +; CHECK: ldr q9, [x0], #16 ; encoding: [0x09,0x04,0xc1,0x3c] + +;----------------------------------------------------------------------------- +; Load/Store pair (indexed, offset) +;----------------------------------------------------------------------------- + + ldp w3, w2, [x15, #16] + ldp x4, x9, [sp, #-16] + ldpsw x2, x3, [x14, #16] + ldpsw x2, x3, [sp, #-16] + ldp s10, s1, [x2, #64] + ldp d10, d1, [x2] + ldp q2, q3, [x0, #32] + +; CHECK: ldp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x42,0x29] +; CHECK: ldp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x7f,0xa9] +; CHECK: ldpsw x2, x3, [x14, #16] ; encoding: [0xc2,0x0d,0x42,0x69] +; CHECK: ldpsw x2, x3, [sp, #-16] ; encoding: [0xe2,0x0f,0x7e,0x69] +; CHECK: ldp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x48,0x2d] +; CHECK: ldp d10, d1, [x2] ; encoding: [0x4a,0x04,0x40,0x6d] +; CHECK: ldp q2, q3, [x0, #32] ; encoding: [0x02,0x0c,0x41,0xad] + + stp w3, w2, [x15, #16] + stp x4, x9, [sp, #-16] + stp s10, s1, [x2, #64] + stp d10, d1, [x2] + stp q2, q3, [x0, #32] + +; CHECK: stp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x02,0x29] +; CHECK: stp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x3f,0xa9] +; CHECK: stp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x08,0x2d] +; CHECK: stp d10, d1, [x2] ; encoding: [0x4a,0x04,0x00,0x6d] +; CHECK: stp q2, q3, [x0, #32] ; encoding: [0x02,0x0c,0x01,0xad] + +;----------------------------------------------------------------------------- +; Load/Store pair (pre-indexed) +;----------------------------------------------------------------------------- + + ldp w3, w2, [x15, #16]! + ldp x4, x9, [sp, #-16]! + ldpsw x2, x3, [x14, #16]! + ldpsw x2, x3, [sp, #-16]! + ldp s10, s1, [x2, #64]! + ldp d10, d1, [x2, #16]! + +; CHECK: ldp w3, w2, [x15, #16]! ; encoding: [0xe3,0x09,0xc2,0x29] +; CHECK: ldp x4, x9, [sp, #-16]! ; encoding: [0xe4,0x27,0xff,0xa9] +; CHECK: ldpsw x2, x3, [x14, #16]! ; encoding: [0xc2,0x0d,0xc2,0x69] +; CHECK: ldpsw x2, x3, [sp, #-16]! ; encoding: [0xe2,0x0f,0xfe,0x69] +; CHECK: ldp s10, s1, [x2, #64]! ; encoding: [0x4a,0x04,0xc8,0x2d] +; CHECK: ldp d10, d1, [x2, #16]! ; encoding: [0x4a,0x04,0xc1,0x6d] + + stp w3, w2, [x15, #16]! + stp x4, x9, [sp, #-16]! + stp s10, s1, [x2, #64]! + stp d10, d1, [x2, #16]! + +; CHECK: stp w3, w2, [x15, #16]! ; encoding: [0xe3,0x09,0x82,0x29] +; CHECK: stp x4, x9, [sp, #-16]! ; encoding: [0xe4,0x27,0xbf,0xa9] +; CHECK: stp s10, s1, [x2, #64]! ; encoding: [0x4a,0x04,0x88,0x2d] +; CHECK: stp d10, d1, [x2, #16]! ; encoding: [0x4a,0x04,0x81,0x6d] + +;----------------------------------------------------------------------------- +; Load/Store pair (post-indexed) +;----------------------------------------------------------------------------- + + ldp w3, w2, [x15], #16 + ldp x4, x9, [sp], #-16 + ldpsw x2, x3, [x14], #16 + ldpsw x2, x3, [sp], #-16 + ldp s10, s1, [x2], #64 + ldp d10, d1, [x2], #16 + +; CHECK: ldp w3, w2, [x15], #16 ; encoding: [0xe3,0x09,0xc2,0x28] +; CHECK: ldp x4, x9, [sp], #-16 ; encoding: [0xe4,0x27,0xff,0xa8] +; CHECK: ldpsw x2, x3, [x14], #16 ; encoding: [0xc2,0x0d,0xc2,0x68] +; CHECK: ldpsw x2, x3, [sp], #-16 ; encoding: [0xe2,0x0f,0xfe,0x68] +; CHECK: ldp s10, s1, [x2], #64 ; encoding: [0x4a,0x04,0xc8,0x2c] +; CHECK: ldp d10, d1, [x2], #16 ; encoding: [0x4a,0x04,0xc1,0x6c] + + stp w3, w2, [x15], #16 + stp x4, x9, [sp], #-16 + stp s10, s1, [x2], #64 + stp d10, d1, [x2], #16 + +; CHECK: stp w3, w2, [x15], #16 ; encoding: [0xe3,0x09,0x82,0x28] +; CHECK: stp x4, x9, [sp], #-16 ; encoding: [0xe4,0x27,0xbf,0xa8] +; CHECK: stp s10, s1, [x2], #64 ; encoding: [0x4a,0x04,0x88,0x2c] +; CHECK: stp d10, d1, [x2], #16 ; encoding: [0x4a,0x04,0x81,0x6c] + +;----------------------------------------------------------------------------- +; Load/Store pair (no-allocate) +;----------------------------------------------------------------------------- + + ldnp w3, w2, [x15, #16] + ldnp x4, x9, [sp, #-16] + ldnp s10, s1, [x2, #64] + ldnp d10, d1, [x2] + +; CHECK: ldnp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x42,0x28] +; CHECK: ldnp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x7f,0xa8] +; CHECK: ldnp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x48,0x2c] +; CHECK: ldnp d10, d1, [x2] ; encoding: [0x4a,0x04,0x40,0x6c] + + stnp w3, w2, [x15, #16] + stnp x4, x9, [sp, #-16] + stnp s10, s1, [x2, #64] + stnp d10, d1, [x2] + +; CHECK: stnp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x02,0x28] +; CHECK: stnp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x3f,0xa8] +; CHECK: stnp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x08,0x2c] +; CHECK: stnp d10, d1, [x2] ; encoding: [0x4a,0x04,0x00,0x6c] + +;----------------------------------------------------------------------------- +; Load/Store register offset +;----------------------------------------------------------------------------- + + ldr w0, [x0, x0] + ldr w0, [x0, x0, lsl #2] + ldr x0, [x0, x0] + ldr x0, [x0, x0, lsl #3] + ldr x0, [x0, x0, sxtx] + +; CHECK: ldr w0, [x0, x0] ; encoding: [0x00,0x68,0x60,0xb8] +; CHECK: ldr w0, [x0, x0, lsl #2] ; encoding: [0x00,0x78,0x60,0xb8] +; CHECK: ldr x0, [x0, x0] ; encoding: [0x00,0x68,0x60,0xf8] +; CHECK: ldr x0, [x0, x0, lsl #3] ; encoding: [0x00,0x78,0x60,0xf8] +; CHECK: ldr x0, [x0, x0, sxtx] ; encoding: [0x00,0xe8,0x60,0xf8] + + ldr b1, [x1, x2] + ldr b1, [x1, x2, lsl #0] + ldr h1, [x1, x2] + ldr h1, [x1, x2, lsl #1] + ldr s1, [x1, x2] + ldr s1, [x1, x2, lsl #2] + ldr d1, [x1, x2] + ldr d1, [x1, x2, lsl #3] + ldr q1, [x1, x2] + ldr q1, [x1, x2, lsl #4] + +; CHECK: ldr b1, [x1, x2] ; encoding: [0x21,0x68,0x62,0x3c] +; CHECK: ldr b1, [x1, x2, lsl #0] ; encoding: [0x21,0x78,0x62,0x3c] +; CHECK: ldr h1, [x1, x2] ; encoding: [0x21,0x68,0x62,0x7c] +; CHECK: ldr h1, [x1, x2, lsl #1] ; encoding: [0x21,0x78,0x62,0x7c] +; CHECK: ldr s1, [x1, x2] ; encoding: [0x21,0x68,0x62,0xbc] +; CHECK: ldr s1, [x1, x2, lsl #2] ; encoding: [0x21,0x78,0x62,0xbc] +; CHECK: ldr d1, [x1, x2] ; encoding: [0x21,0x68,0x62,0xfc] +; CHECK: ldr d1, [x1, x2, lsl #3] ; encoding: [0x21,0x78,0x62,0xfc] +; CHECK: ldr q1, [x1, x2] ; encoding: [0x21,0x68,0xe2,0x3c] +; CHECK: ldr q1, [x1, x2, lsl #4] ; encoding: [0x21,0x78,0xe2,0x3c] + + str d1, [sp, x3] + str d1, [sp, w3, uxtw #3] + str q1, [sp, x3] + str q1, [sp, w3, uxtw #4] + +; CHECK: str d1, [sp, x3] ; encoding: [0xe1,0x6b,0x23,0xfc] +; CHECK: str d1, [sp, w3, uxtw #3] ; encoding: [0xe1,0x5b,0x23,0xfc] +; CHECK: str q1, [sp, x3] ; encoding: [0xe1,0x6b,0xa3,0x3c] +; CHECK: str q1, [sp, w3, uxtw #4] ; encoding: [0xe1,0x5b,0xa3,0x3c] + +;----------------------------------------------------------------------------- +; Load literal +;----------------------------------------------------------------------------- + + ldr w5, foo + ldr x4, foo + ldrsw x9, foo + prfm #5, foo + +; CHECK: ldr w5, foo ; encoding: [0bAAA00101,A,A,0x18] +; CHECK: ldr x4, foo ; encoding: [0bAAA00100,A,A,0x58] +; CHECK: ldrsw x9, foo ; encoding: [0bAAA01001,A,A,0x98] +; CHECK: prfm pldl3strm, foo ; encoding: [0bAAA00101,A,A,0xd8] + +;----------------------------------------------------------------------------- +; Load/Store exclusive +;----------------------------------------------------------------------------- + + ldxr w6, [x1] + ldxr x6, [x1] + ldxrb w6, [x1] + ldxrh w6, [x1] + ldxp w7, w3, [x9] + ldxp x7, x3, [x9] + +; CHECK: ldxrb w6, [x1] ; encoding: [0x26,0x7c,0x5f,0x08] +; CHECK: ldxrh w6, [x1] ; encoding: [0x26,0x7c,0x5f,0x48] +; CHECK: ldxp w7, w3, [x9] ; encoding: [0x27,0x0d,0x7f,0x88] +; CHECK: ldxp x7, x3, [x9] ; encoding: [0x27,0x0d,0x7f,0xc8] + + stxr w1, x4, [x3] + stxr w1, w4, [x3] + stxrb w1, w4, [x3] + stxrh w1, w4, [x3] + stxp w1, x2, x6, [x1] + stxp w1, w2, w6, [x1] + +; CHECK: stxr w1, x4, [x3] ; encoding: [0x64,0x7c,0x01,0xc8] +; CHECK: stxr w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x88] +; CHECK: stxrb w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x08] +; CHECK: stxrh w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x48] +; CHECK: stxp w1, x2, x6, [x1] ; encoding: [0x22,0x18,0x21,0xc8] +; CHECK: stxp w1, w2, w6, [x1] ; encoding: [0x22,0x18,0x21,0x88] + +;----------------------------------------------------------------------------- +; Load-acquire/Store-release non-exclusive +;----------------------------------------------------------------------------- + + ldar w4, [sp] + ldar x4, [sp, #0] + ldarb w4, [sp] + ldarh w4, [sp] + +; CHECK: ldar w4, [sp] ; encoding: [0xe4,0xff,0xdf,0x88] +; CHECK: ldar x4, [sp] ; encoding: [0xe4,0xff,0xdf,0xc8] +; CHECK: ldarb w4, [sp] ; encoding: [0xe4,0xff,0xdf,0x08] +; CHECK: ldarh w4, [sp] ; encoding: [0xe4,0xff,0xdf,0x48] + + stlr w3, [x6] + stlr x3, [x6] + stlrb w3, [x6] + stlrh w3, [x6] + +; CHECK: stlr w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x88] +; CHECK: stlr x3, [x6] ; encoding: [0xc3,0xfc,0x9f,0xc8] +; CHECK: stlrb w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x08] +; CHECK: stlrh w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x48] + +;----------------------------------------------------------------------------- +; Load-acquire/Store-release exclusive +;----------------------------------------------------------------------------- + + ldaxr w2, [x4] + ldaxr x2, [x4] + ldaxrb w2, [x4, #0] + ldaxrh w2, [x4] + ldaxp w2, w6, [x1] + ldaxp x2, x6, [x1] + +; CHECK: ldaxr w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x88] +; CHECK: ldaxr x2, [x4] ; encoding: [0x82,0xfc,0x5f,0xc8] +; CHECK: ldaxrb w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x08] +; CHECK: ldaxrh w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x48] +; CHECK: ldaxp w2, w6, [x1] ; encoding: [0x22,0x98,0x7f,0x88] +; CHECK: ldaxp x2, x6, [x1] ; encoding: [0x22,0x98,0x7f,0xc8] + + stlxr w8, x7, [x1] + stlxr w8, w7, [x1] + stlxrb w8, w7, [x1] + stlxrh w8, w7, [x1] + stlxp w1, x2, x6, [x1] + stlxp w1, w2, w6, [x1] + +; CHECK: stlxr w8, x7, [x1] ; encoding: [0x27,0xfc,0x08,0xc8] +; CHECK: stlxr w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x88] +; CHECK: stlxrb w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x08] +; CHECK: stlxrh w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x48] +; CHECK: stlxp w1, x2, x6, [x1] ; encoding: [0x22,0x98,0x21,0xc8] +; CHECK: stlxp w1, w2, w6, [x1] ; encoding: [0x22,0x98,0x21,0x88] + + +;----------------------------------------------------------------------------- +; LDUR/STUR aliases for negative and unaligned LDR/STR instructions. +; +; According to the ARM ISA documentation: +; "A programmer-friendly assembler should also generate these instructions +; in response to the standard LDR/STR mnemonics when the immediate offset is +; unambiguous, i.e. negative or unaligned." +;----------------------------------------------------------------------------- + + ldr x11, [x29, #-8] + ldr x11, [x29, #7] + ldr w0, [x0, #2] + ldr w0, [x0, #-256] + ldr b2, [x1, #-2] + ldr h3, [x2, #3] + ldr h3, [x3, #-4] + ldr s3, [x4, #3] + ldr s3, [x5, #-4] + ldr d4, [x6, #4] + ldr d4, [x7, #-8] + ldr q5, [x8, #8] + ldr q5, [x9, #-16] + +; CHECK: ldur x11, [x29, #-8] ; encoding: [0xab,0x83,0x5f,0xf8] +; CHECK: ldur x11, [x29, #7] ; encoding: [0xab,0x73,0x40,0xf8] +; CHECK: ldur w0, [x0, #2] ; encoding: [0x00,0x20,0x40,0xb8] +; CHECK: ldur w0, [x0, #-256] ; encoding: [0x00,0x00,0x50,0xb8] +; CHECK: ldur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x5f,0x3c] +; CHECK: ldur h3, [x2, #3] ; encoding: [0x43,0x30,0x40,0x7c] +; CHECK: ldur h3, [x3, #-4] ; encoding: [0x63,0xc0,0x5f,0x7c] +; CHECK: ldur s3, [x4, #3] ; encoding: [0x83,0x30,0x40,0xbc] +; CHECK: ldur s3, [x5, #-4] ; encoding: [0xa3,0xc0,0x5f,0xbc] +; CHECK: ldur d4, [x6, #4] ; encoding: [0xc4,0x40,0x40,0xfc] +; CHECK: ldur d4, [x7, #-8] ; encoding: [0xe4,0x80,0x5f,0xfc] +; CHECK: ldur q5, [x8, #8] ; encoding: [0x05,0x81,0xc0,0x3c] +; CHECK: ldur q5, [x9, #-16] ; encoding: [0x25,0x01,0xdf,0x3c] + + str x11, [x29, #-8] + str x11, [x29, #7] + str w0, [x0, #2] + str w0, [x0, #-256] + str b2, [x1, #-2] + str h3, [x2, #3] + str h3, [x3, #-4] + str s3, [x4, #3] + str s3, [x5, #-4] + str d4, [x6, #4] + str d4, [x7, #-8] + str q5, [x8, #8] + str q5, [x9, #-16] + +; CHECK: stur x11, [x29, #-8] ; encoding: [0xab,0x83,0x1f,0xf8] +; CHECK: stur x11, [x29, #7] ; encoding: [0xab,0x73,0x00,0xf8] +; CHECK: stur w0, [x0, #2] ; encoding: [0x00,0x20,0x00,0xb8] +; CHECK: stur w0, [x0, #-256] ; encoding: [0x00,0x00,0x10,0xb8] +; CHECK: stur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x1f,0x3c] +; CHECK: stur h3, [x2, #3] ; encoding: [0x43,0x30,0x00,0x7c] +; CHECK: stur h3, [x3, #-4] ; encoding: [0x63,0xc0,0x1f,0x7c] +; CHECK: stur s3, [x4, #3] ; encoding: [0x83,0x30,0x00,0xbc] +; CHECK: stur s3, [x5, #-4] ; encoding: [0xa3,0xc0,0x1f,0xbc] +; CHECK: stur d4, [x6, #4] ; encoding: [0xc4,0x40,0x00,0xfc] +; CHECK: stur d4, [x7, #-8] ; encoding: [0xe4,0x80,0x1f,0xfc] +; CHECK: stur q5, [x8, #8] ; encoding: [0x05,0x81,0x80,0x3c] +; CHECK: stur q5, [x9, #-16] ; encoding: [0x25,0x01,0x9f,0x3c] + + ldrb w3, [x1, #-1] + ldrh w4, [x2, #1] + ldrh w5, [x3, #-1] + ldrsb w6, [x4, #-1] + ldrsb x7, [x5, #-1] + ldrsh w8, [x6, #1] + ldrsh w9, [x7, #-1] + ldrsh x1, [x8, #1] + ldrsh x2, [x9, #-1] + ldrsw x3, [x10, #10] + ldrsw x4, [x11, #-1] + +; CHECK: ldurb w3, [x1, #-1] ; encoding: [0x23,0xf0,0x5f,0x38] +; CHECK: ldurh w4, [x2, #1] ; encoding: [0x44,0x10,0x40,0x78] +; CHECK: ldurh w5, [x3, #-1] ; encoding: [0x65,0xf0,0x5f,0x78] +; CHECK: ldursb w6, [x4, #-1] ; encoding: [0x86,0xf0,0xdf,0x38] +; CHECK: ldursb x7, [x5, #-1] ; encoding: [0xa7,0xf0,0x9f,0x38] +; CHECK: ldursh w8, [x6, #1] ; encoding: [0xc8,0x10,0xc0,0x78] +; CHECK: ldursh w9, [x7, #-1] ; encoding: [0xe9,0xf0,0xdf,0x78] +; CHECK: ldursh x1, [x8, #1] ; encoding: [0x01,0x11,0x80,0x78] +; CHECK: ldursh x2, [x9, #-1] ; encoding: [0x22,0xf1,0x9f,0x78] +; CHECK: ldursw x3, [x10, #10] ; encoding: [0x43,0xa1,0x80,0xb8] +; CHECK: ldursw x4, [x11, #-1] ; encoding: [0x64,0xf1,0x9f,0xb8] + + strb w3, [x1, #-1] + strh w4, [x2, #1] + strh w5, [x3, #-1] + +; CHECK: sturb w3, [x1, #-1] ; encoding: [0x23,0xf0,0x1f,0x38] +; CHECK: sturh w4, [x2, #1] ; encoding: [0x44,0x10,0x00,0x78] +; CHECK: sturh w5, [x3, #-1] ; encoding: [0x65,0xf0,0x1f,0x78] diff --git a/test/MC/AArch64/arm64-nv-cond.s b/test/MC/AArch64/arm64-nv-cond.s new file mode 100644 index 0000000..1b4d054 --- /dev/null +++ b/test/MC/AArch64/arm64-nv-cond.s @@ -0,0 +1,11 @@ +// RUN: llvm-mc < %s -triple arm64 -mattr=neon -show-encoding | FileCheck %s + +fcsel d28,d31,d31,nv +csel x0,x0,x0,nv +ccmp x0,x0,#0,nv +b.nv #0 + +// CHECK: fcsel d28, d31, d31, nv // encoding: [0xfc,0xff,0x7f,0x1e] +// CHECK: csel x0, x0, x0, nv // encoding: [0x00,0xf0,0x80,0x9a] +// CHECK: ccmp x0, x0, #0, nv // encoding: [0x00,0xf0,0x40,0xfa] +// CHECK: b.nv #0 // encoding: [0x0f,0x00,0x00,0x54] diff --git a/test/MC/AArch64/arm64-optional-hash.s b/test/MC/AArch64/arm64-optional-hash.s new file mode 100644 index 0000000..71e2fda --- /dev/null +++ b/test/MC/AArch64/arm64-optional-hash.s @@ -0,0 +1,31 @@ +; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s +.text +; parseOperand check +; CHECK: add sp, sp, #32 ; encoding: [0xff,0x83,0x00,0x91] + add sp, sp, 32 + +; Optional shift +; CHECK: adds x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xb1] +adds x3, x4, 1024, lsl 12 + +; Optional extend +; CHECK: add sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0x8b] +add sp, x2, x3, uxtx 0 + +; FP immediates +; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e] +fmov s1, 0.125 + +; Barrier operand +; CHECK: dmb osh ; encoding: [0xbf,0x33,0x03,0xd5] +dmb 3 + +; Prefetch and memory + +; Single register inside [] +; CHECK: ldnp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x42,0x28] +ldnp w3, w2, [x15, 16] + +; Memory, two registers inside [] +; CHECK: prfm pstl3strm, [x4, x5, lsl #3] ; encoding: [0x95,0x78,0xa5,0xf8] +prfm pstl3strm, [x4, x5, lsl 3] diff --git a/test/MC/AArch64/arm64-separator.s b/test/MC/AArch64/arm64-separator.s new file mode 100644 index 0000000..e67deba --- /dev/null +++ b/test/MC/AArch64/arm64-separator.s @@ -0,0 +1,20 @@ +; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s + +; ARM64 uses a multi-character statement separator, "%%". Check that we lex +; it properly and recognize the multiple assembly statements on the line. + +; To make sure the output assembly correctly handled the instructions, +; tell it to show encodings. That will result in the two 'mov' instructions +; being on separate lines in the output. We look for the "; encoding" string +; to verify that. For this test, we don't care what the encoding is, just that +; there is one for each 'mov' instruction. + + +_foo: +; CHECK: foo +; CHECK: mov x0, x1 ; encoding +; CHECK: mov x1, x0 ; encoding + mov x0, x1 %% mov x1, x0 + ret lr + + diff --git a/test/MC/AArch64/arm64-simd-ldst.s b/test/MC/AArch64/arm64-simd-ldst.s new file mode 100644 index 0000000..3085485 --- /dev/null +++ b/test/MC/AArch64/arm64-simd-ldst.s @@ -0,0 +1,2404 @@ +; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -output-asm-variant=1 -show-encoding < %s | FileCheck %s + +_ld1st1_multiple: + ld1.8b {v0}, [x1] + ld1.8b {v0, v1}, [x1] + ld1.8b {v0, v1, v2}, [x1] + ld1.8b {v0, v1, v2, v3}, [x1] + + ld1.8b {v3}, [x1] + ld1.8b {v3, v4}, [x2] + ld1.8b {v4, v5, v6}, [x3] + ld1.8b {v7, v8, v9, v10}, [x4] + + ld1.16b {v0}, [x1] + ld1.16b {v0, v1}, [x1] + ld1.16b {v0, v1, v2}, [x1] + ld1.16b {v0, v1, v2, v3}, [x1] + + ld1.4h {v0}, [x1] + ld1.4h {v0, v1}, [x1] + ld1.4h {v0, v1, v2}, [x1] + ld1.4h {v0, v1, v2, v3}, [x1] + + ld1.8h {v0}, [x1] + ld1.8h {v0, v1}, [x1] + ld1.8h {v0, v1, v2}, [x1] + ld1.8h {v0, v1, v2, v3}, [x1] + + ld1.2s {v0}, [x1] + ld1.2s {v0, v1}, [x1] + ld1.2s {v0, v1, v2}, [x1] + ld1.2s {v0, v1, v2, v3}, [x1] + + ld1.4s {v0}, [x1] + ld1.4s {v0, v1}, [x1] + ld1.4s {v0, v1, v2}, [x1] + ld1.4s {v0, v1, v2, v3}, [x1] + + ld1.1d {v0}, [x1] + ld1.1d {v0, v1}, [x1] + ld1.1d {v0, v1, v2}, [x1] + ld1.1d {v0, v1, v2, v3}, [x1] + + ld1.2d {v0}, [x1] + ld1.2d {v0, v1}, [x1] + ld1.2d {v0, v1, v2}, [x1] + ld1.2d {v0, v1, v2, v3}, [x1] + + st1.8b {v0}, [x1] + st1.8b {v0, v1}, [x1] + st1.8b {v0, v1, v2}, [x1] + st1.8b {v0, v1, v2, v3}, [x1] + + st1.16b {v0}, [x1] + st1.16b {v0, v1}, [x1] + st1.16b {v0, v1, v2}, [x1] + st1.16b {v0, v1, v2, v3}, [x1] + + st1.4h {v0}, [x1] + st1.4h {v0, v1}, [x1] + st1.4h {v0, v1, v2}, [x1] + st1.4h {v0, v1, v2, v3}, [x1] + + st1.8h {v0}, [x1] + st1.8h {v0, v1}, [x1] + st1.8h {v0, v1, v2}, [x1] + st1.8h {v0, v1, v2, v3}, [x1] + + st1.2s {v0}, [x1] + st1.2s {v0, v1}, [x1] + st1.2s {v0, v1, v2}, [x1] + st1.2s {v0, v1, v2, v3}, [x1] + + st1.4s {v0}, [x1] + st1.4s {v0, v1}, [x1] + st1.4s {v0, v1, v2}, [x1] + st1.4s {v0, v1, v2, v3}, [x1] + + st1.1d {v0}, [x1] + st1.1d {v0, v1}, [x1] + st1.1d {v0, v1, v2}, [x1] + st1.1d {v0, v1, v2, v3}, [x1] + + st1.2d {v0}, [x1] + st1.2d {v0, v1}, [x1] + st1.2d {v0, v1, v2}, [x1] + st1.2d {v0, v1, v2, v3}, [x1] + + st1.2d {v5}, [x1] + st1.2d {v7, v8}, [x10] + st1.2d {v11, v12, v13}, [x1] + st1.2d {v28, v29, v30, v31}, [x13] + +; CHECK: _ld1st1_multiple: +; CHECK: ld1.8b { v0 }, [x1] ; encoding: [0x20,0x70,0x40,0x0c] +; CHECK: ld1.8b { v0, v1 }, [x1] ; encoding: [0x20,0xa0,0x40,0x0c] +; CHECK: ld1.8b { v0, v1, v2 }, [x1] ; encoding: [0x20,0x60,0x40,0x0c] +; CHECK: ld1.8b { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x20,0x40,0x0c] + +; CHECK: ld1.8b { v3 }, [x1] ; encoding: [0x23,0x70,0x40,0x0c] +; CHECK: ld1.8b { v3, v4 }, [x2] ; encoding: [0x43,0xa0,0x40,0x0c] +; CHECK: ld1.8b { v4, v5, v6 }, [x3] ; encoding: [0x64,0x60,0x40,0x0c] +; CHECK: ld1.8b { v7, v8, v9, v10 }, [x4] ; encoding: [0x87,0x20,0x40,0x0c] + +; CHECK: ld1.16b { v0 }, [x1] ; encoding: [0x20,0x70,0x40,0x4c] +; CHECK: ld1.16b { v0, v1 }, [x1] ; encoding: [0x20,0xa0,0x40,0x4c] +; CHECK: ld1.16b { v0, v1, v2 }, [x1] ; encoding: [0x20,0x60,0x40,0x4c] +; CHECK: ld1.16b { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x20,0x40,0x4c] + +; CHECK: ld1.4h { v0 }, [x1] ; encoding: [0x20,0x74,0x40,0x0c] +; CHECK: ld1.4h { v0, v1 }, [x1] ; encoding: [0x20,0xa4,0x40,0x0c] +; CHECK: ld1.4h { v0, v1, v2 }, [x1] ; encoding: [0x20,0x64,0x40,0x0c] +; CHECK: ld1.4h { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x24,0x40,0x0c] + +; CHECK: ld1.8h { v0 }, [x1] ; encoding: [0x20,0x74,0x40,0x4c] +; CHECK: ld1.8h { v0, v1 }, [x1] ; encoding: [0x20,0xa4,0x40,0x4c] +; CHECK: ld1.8h { v0, v1, v2 }, [x1] ; encoding: [0x20,0x64,0x40,0x4c] +; CHECK: ld1.8h { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x24,0x40,0x4c] + +; CHECK: ld1.2s { v0 }, [x1] ; encoding: [0x20,0x78,0x40,0x0c] +; CHECK: ld1.2s { v0, v1 }, [x1] ; encoding: [0x20,0xa8,0x40,0x0c] +; CHECK: ld1.2s { v0, v1, v2 }, [x1] ; encoding: [0x20,0x68,0x40,0x0c] +; CHECK: ld1.2s { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x28,0x40,0x0c] + +; CHECK: ld1.4s { v0 }, [x1] ; encoding: [0x20,0x78,0x40,0x4c] +; CHECK: ld1.4s { v0, v1 }, [x1] ; encoding: [0x20,0xa8,0x40,0x4c] +; CHECK: ld1.4s { v0, v1, v2 }, [x1] ; encoding: [0x20,0x68,0x40,0x4c] +; CHECK: ld1.4s { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x28,0x40,0x4c] + +; CHECK: ld1.1d { v0 }, [x1] ; encoding: [0x20,0x7c,0x40,0x0c] +; CHECK: ld1.1d { v0, v1 }, [x1] ; encoding: [0x20,0xac,0x40,0x0c] +; CHECK: ld1.1d { v0, v1, v2 }, [x1] ; encoding: [0x20,0x6c,0x40,0x0c] +; CHECK: ld1.1d { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x2c,0x40,0x0c] + +; CHECK: ld1.2d { v0 }, [x1] ; encoding: [0x20,0x7c,0x40,0x4c] +; CHECK: ld1.2d { v0, v1 }, [x1] ; encoding: [0x20,0xac,0x40,0x4c] +; CHECK: ld1.2d { v0, v1, v2 }, [x1] ; encoding: [0x20,0x6c,0x40,0x4c] +; CHECK: ld1.2d { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x2c,0x40,0x4c] + + +; CHECK: st1.8b { v0 }, [x1] ; encoding: [0x20,0x70,0x00,0x0c] +; CHECK: st1.8b { v0, v1 }, [x1] ; encoding: [0x20,0xa0,0x00,0x0c] +; CHECK: st1.8b { v0, v1, v2 }, [x1] ; encoding: [0x20,0x60,0x00,0x0c] +; CHECK: st1.8b { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x20,0x00,0x0c] + +; CHECK: st1.16b { v0 }, [x1] ; encoding: [0x20,0x70,0x00,0x4c] +; CHECK: st1.16b { v0, v1 }, [x1] ; encoding: [0x20,0xa0,0x00,0x4c] +; CHECK: st1.16b { v0, v1, v2 }, [x1] ; encoding: [0x20,0x60,0x00,0x4c] +; CHECK: st1.16b { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x20,0x00,0x4c] + +; CHECK: st1.4h { v0 }, [x1] ; encoding: [0x20,0x74,0x00,0x0c] +; CHECK: st1.4h { v0, v1 }, [x1] ; encoding: [0x20,0xa4,0x00,0x0c] +; CHECK: st1.4h { v0, v1, v2 }, [x1] ; encoding: [0x20,0x64,0x00,0x0c] +; CHECK: st1.4h { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x24,0x00,0x0c] + +; CHECK: st1.8h { v0 }, [x1] ; encoding: [0x20,0x74,0x00,0x4c] +; CHECK: st1.8h { v0, v1 }, [x1] ; encoding: [0x20,0xa4,0x00,0x4c] +; CHECK: st1.8h { v0, v1, v2 }, [x1] ; encoding: [0x20,0x64,0x00,0x4c] +; CHECK: st1.8h { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x24,0x00,0x4c] + +; CHECK: st1.2s { v0 }, [x1] ; encoding: [0x20,0x78,0x00,0x0c] +; CHECK: st1.2s { v0, v1 }, [x1] ; encoding: [0x20,0xa8,0x00,0x0c] +; CHECK: st1.2s { v0, v1, v2 }, [x1] ; encoding: [0x20,0x68,0x00,0x0c] +; CHECK: st1.2s { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x28,0x00,0x0c] + +; CHECK: st1.4s { v0 }, [x1] ; encoding: [0x20,0x78,0x00,0x4c] +; CHECK: st1.4s { v0, v1 }, [x1] ; encoding: [0x20,0xa8,0x00,0x4c] +; CHECK: st1.4s { v0, v1, v2 }, [x1] ; encoding: [0x20,0x68,0x00,0x4c] +; CHECK: st1.4s { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x28,0x00,0x4c] + +; CHECK: st1.1d { v0 }, [x1] ; encoding: [0x20,0x7c,0x00,0x0c] +; CHECK: st1.1d { v0, v1 }, [x1] ; encoding: [0x20,0xac,0x00,0x0c] +; CHECK: st1.1d { v0, v1, v2 }, [x1] ; encoding: [0x20,0x6c,0x00,0x0c] +; CHECK: st1.1d { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x2c,0x00,0x0c] + +; CHECK: st1.2d { v0 }, [x1] ; encoding: [0x20,0x7c,0x00,0x4c] +; CHECK: st1.2d { v0, v1 }, [x1] ; encoding: [0x20,0xac,0x00,0x4c] +; CHECK: st1.2d { v0, v1, v2 }, [x1] ; encoding: [0x20,0x6c,0x00,0x4c] +; CHECK: st1.2d { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x2c,0x00,0x4c] + +; CHECK: st1.2d { v5 }, [x1] ; encoding: [0x25,0x7c,0x00,0x4c] +; CHECK: st1.2d { v7, v8 }, [x10] ; encoding: [0x47,0xad,0x00,0x4c] +; CHECK: st1.2d { v11, v12, v13 }, [x1] ; encoding: [0x2b,0x6c,0x00,0x4c] +; CHECK: st1.2d { v28, v29, v30, v31 }, [x13] ; encoding: [0xbc,0x2d,0x00,0x4c] + +_ld2st2_multiple: + ld2.8b {v4, v5}, [x19] + ld2.16b {v4, v5}, [x19] + ld2.4h {v4, v5}, [x19] + ld2.8h {v4, v5}, [x19] + ld2.2s {v4, v5}, [x19] + ld2.4s {v4, v5}, [x19] + ld2.2d {v4, v5}, [x19] + + st2.8b {v4, v5}, [x19] + st2.16b {v4, v5}, [x19] + st2.4h {v4, v5}, [x19] + st2.8h {v4, v5}, [x19] + st2.2s {v4, v5}, [x19] + st2.4s {v4, v5}, [x19] + st2.2d {v4, v5}, [x19] + + +; CHECK: _ld2st2_multiple +; CHECK: ld2.8b { v4, v5 }, [x19] ; encoding: [0x64,0x82,0x40,0x0c] +; CHECK: ld2.16b { v4, v5 }, [x19] ; encoding: [0x64,0x82,0x40,0x4c] +; CHECK: ld2.4h { v4, v5 }, [x19] ; encoding: [0x64,0x86,0x40,0x0c] +; CHECK: ld2.8h { v4, v5 }, [x19] ; encoding: [0x64,0x86,0x40,0x4c] +; CHECK: ld2.2s { v4, v5 }, [x19] ; encoding: [0x64,0x8a,0x40,0x0c] +; CHECK: ld2.4s { v4, v5 }, [x19] ; encoding: [0x64,0x8a,0x40,0x4c] +; CHECK: ld2.2d { v4, v5 }, [x19] ; encoding: [0x64,0x8e,0x40,0x4c] + +; CHECK: st2.8b { v4, v5 }, [x19] ; encoding: [0x64,0x82,0x00,0x0c] +; CHECK: st2.16b { v4, v5 }, [x19] ; encoding: [0x64,0x82,0x00,0x4c] +; CHECK: st2.4h { v4, v5 }, [x19] ; encoding: [0x64,0x86,0x00,0x0c] +; CHECK: st2.8h { v4, v5 }, [x19] ; encoding: [0x64,0x86,0x00,0x4c] +; CHECK: st2.2s { v4, v5 }, [x19] ; encoding: [0x64,0x8a,0x00,0x0c] +; CHECK: st2.4s { v4, v5 }, [x19] ; encoding: [0x64,0x8a,0x00,0x4c] +; CHECK: st2.2d { v4, v5 }, [x19] ; encoding: [0x64,0x8e,0x00,0x4c] + + +ld3st3_multiple: + ld3.8b {v4, v5, v6}, [x19] + ld3.16b {v4, v5, v6}, [x19] + ld3.4h {v4, v5, v6}, [x19] + ld3.8h {v4, v5, v6}, [x19] + ld3.2s {v4, v5, v6}, [x19] + ld3.4s {v4, v5, v6}, [x19] + ld3.2d {v4, v5, v6}, [x19] + + ld3.8b {v9, v10, v11}, [x9] + ld3.16b {v14, v15, v16}, [x19] + ld3.4h {v24, v25, v26}, [x29] + ld3.8h {v30, v31, v0}, [x9] + ld3.2s {v2, v3, v4}, [x19] + ld3.4s {v4, v5, v6}, [x29] + ld3.2d {v7, v8, v9}, [x9] + + st3.8b {v4, v5, v6}, [x19] + st3.16b {v4, v5, v6}, [x19] + st3.4h {v4, v5, v6}, [x19] + st3.8h {v4, v5, v6}, [x19] + st3.2s {v4, v5, v6}, [x19] + st3.4s {v4, v5, v6}, [x19] + st3.2d {v4, v5, v6}, [x19] + + st3.8b {v10, v11, v12}, [x9] + st3.16b {v14, v15, v16}, [x19] + st3.4h {v24, v25, v26}, [x29] + st3.8h {v30, v31, v0}, [x9] + st3.2s {v2, v3, v4}, [x19] + st3.4s {v7, v8, v9}, [x29] + st3.2d {v4, v5, v6}, [x9] + +; CHECK: ld3st3_multiple: +; CHECK: ld3.8b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x40,0x0c] +; CHECK: ld3.16b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x40,0x4c] +; CHECK: ld3.4h { v4, v5, v6 }, [x19] ; encoding: [0x64,0x46,0x40,0x0c] +; CHECK: ld3.8h { v4, v5, v6 }, [x19] ; encoding: [0x64,0x46,0x40,0x4c] +; CHECK: ld3.2s { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4a,0x40,0x0c] +; CHECK: ld3.4s { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4a,0x40,0x4c] +; CHECK: ld3.2d { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4e,0x40,0x4c] + +; CHECK: ld3.8b { v9, v10, v11 }, [x9] ; encoding: [0x29,0x41,0x40,0x0c] +; CHECK: ld3.16b { v14, v15, v16 }, [x19] ; encoding: [0x6e,0x42,0x40,0x4c] +; CHECK: ld3.4h { v24, v25, v26 }, [x29] ; encoding: [0xb8,0x47,0x40,0x0c] +; CHECK: ld3.8h { v30, v31, v0 }, [x9] ; encoding: [0x3e,0x45,0x40,0x4c] +; CHECK: ld3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x40,0x0c] +; CHECK: ld3.4s { v4, v5, v6 }, [x29] ; encoding: [0xa4,0x4b,0x40,0x4c] +; CHECK: ld3.2d { v7, v8, v9 }, [x9] ; encoding: [0x27,0x4d,0x40,0x4c] + +; CHECK: st3.8b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x00,0x0c] +; CHECK: st3.16b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x00,0x4c] +; CHECK: st3.4h { v4, v5, v6 }, [x19] ; encoding: [0x64,0x46,0x00,0x0c] +; CHECK: st3.8h { v4, v5, v6 }, [x19] ; encoding: [0x64,0x46,0x00,0x4c] +; CHECK: st3.2s { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4a,0x00,0x0c] +; CHECK: st3.4s { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4a,0x00,0x4c] +; CHECK: st3.2d { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4e,0x00,0x4c] + +; CHECK: st3.8b { v10, v11, v12 }, [x9] ; encoding: [0x2a,0x41,0x00,0x0c] +; CHECK: st3.16b { v14, v15, v16 }, [x19] ; encoding: [0x6e,0x42,0x00,0x4c] +; CHECK: st3.4h { v24, v25, v26 }, [x29] ; encoding: [0xb8,0x47,0x00,0x0c] +; CHECK: st3.8h { v30, v31, v0 }, [x9] ; encoding: [0x3e,0x45,0x00,0x4c] +; CHECK: st3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x00,0x0c] +; CHECK: st3.4s { v7, v8, v9 }, [x29] ; encoding: [0xa7,0x4b,0x00,0x4c] +; CHECK: st3.2d { v4, v5, v6 }, [x9] ; encoding: [0x24,0x4d,0x00,0x4c] + +ld4st4_multiple: + ld4.8b {v4, v5, v6, v7}, [x19] + ld4.16b {v4, v5, v6, v7}, [x19] + ld4.4h {v4, v5, v6, v7}, [x19] + ld4.8h {v4, v5, v6, v7}, [x19] + ld4.2s {v4, v5, v6, v7}, [x19] + ld4.4s {v4, v5, v6, v7}, [x19] + ld4.2d {v4, v5, v6, v7}, [x19] + + st4.8b {v4, v5, v6, v7}, [x19] + st4.16b {v4, v5, v6, v7}, [x19] + st4.4h {v4, v5, v6, v7}, [x19] + st4.8h {v4, v5, v6, v7}, [x19] + st4.2s {v4, v5, v6, v7}, [x19] + st4.4s {v4, v5, v6, v7}, [x19] + st4.2d {v4, v5, v6, v7}, [x19] + +; CHECK: ld4st4_multiple: +; CHECK: ld4.8b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x40,0x0c] +; CHECK: ld4.16b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x40,0x4c] +; CHECK: ld4.4h { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x06,0x40,0x0c] +; CHECK: ld4.8h { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x06,0x40,0x4c] +; CHECK: ld4.2s { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0a,0x40,0x0c] +; CHECK: ld4.4s { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0a,0x40,0x4c] +; CHECK: ld4.2d { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0e,0x40,0x4c] + +; CHECK: st4.8b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x00,0x0c] +; CHECK: st4.16b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x00,0x4c] +; CHECK: st4.4h { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x06,0x00,0x0c] +; CHECK: st4.8h { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x06,0x00,0x4c] +; CHECK: st4.2s { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0a,0x00,0x0c] +; CHECK: st4.4s { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0a,0x00,0x4c] +; CHECK: st4.2d { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0e,0x00,0x4c] + +;----------------------------------------------------------------------------- +; Post-increment versions. +;----------------------------------------------------------------------------- + +_ld1st1_multiple_post: + ld1.8b {v0}, [x1], x15 + ld1.8b {v0, v1}, [x1], x15 + ld1.8b {v0, v1, v2}, [x1], x15 + ld1.8b {v0, v1, v2, v3}, [x1], x15 + + ld1.16b {v0}, [x1], x15 + ld1.16b {v0, v1}, [x1], x15 + ld1.16b {v0, v1, v2}, [x1], x15 + ld1.16b {v0, v1, v2, v3}, [x1], x15 + + ld1.4h {v0}, [x1], x15 + ld1.4h {v0, v1}, [x1], x15 + ld1.4h {v0, v1, v2}, [x1], x15 + ld1.4h {v0, v1, v2, v3}, [x1], x15 + + ld1.8h {v0}, [x1], x15 + ld1.8h {v0, v1}, [x1], x15 + ld1.8h {v0, v1, v2}, [x1], x15 + ld1.8h {v0, v1, v2, v3}, [x1], x15 + + ld1.2s {v0}, [x1], x15 + ld1.2s {v0, v1}, [x1], x15 + ld1.2s {v0, v1, v2}, [x1], x15 + ld1.2s {v0, v1, v2, v3}, [x1], x15 + + ld1.4s {v0}, [x1], x15 + ld1.4s {v0, v1}, [x1], x15 + ld1.4s {v0, v1, v2}, [x1], x15 + ld1.4s {v0, v1, v2, v3}, [x1], x15 + + ld1.1d {v0}, [x1], x15 + ld1.1d {v0, v1}, [x1], x15 + ld1.1d {v0, v1, v2}, [x1], x15 + ld1.1d {v0, v1, v2, v3}, [x1], x15 + + ld1.2d {v0}, [x1], x15 + ld1.2d {v0, v1}, [x1], x15 + ld1.2d {v0, v1, v2}, [x1], x15 + ld1.2d {v0, v1, v2, v3}, [x1], x15 + + st1.8b {v0}, [x1], x15 + st1.8b {v0, v1}, [x1], x15 + st1.8b {v0, v1, v2}, [x1], x15 + st1.8b {v0, v1, v2, v3}, [x1], x15 + + st1.16b {v0}, [x1], x15 + st1.16b {v0, v1}, [x1], x15 + st1.16b {v0, v1, v2}, [x1], x15 + st1.16b {v0, v1, v2, v3}, [x1], x15 + + st1.4h {v0}, [x1], x15 + st1.4h {v0, v1}, [x1], x15 + st1.4h {v0, v1, v2}, [x1], x15 + st1.4h {v0, v1, v2, v3}, [x1], x15 + + st1.8h {v0}, [x1], x15 + st1.8h {v0, v1}, [x1], x15 + st1.8h {v0, v1, v2}, [x1], x15 + st1.8h {v0, v1, v2, v3}, [x1], x15 + + st1.2s {v0}, [x1], x15 + st1.2s {v0, v1}, [x1], x15 + st1.2s {v0, v1, v2}, [x1], x15 + st1.2s {v0, v1, v2, v3}, [x1], x15 + + st1.4s {v0}, [x1], x15 + st1.4s {v0, v1}, [x1], x15 + st1.4s {v0, v1, v2}, [x1], x15 + st1.4s {v0, v1, v2, v3}, [x1], x15 + + st1.1d {v0}, [x1], x15 + st1.1d {v0, v1}, [x1], x15 + st1.1d {v0, v1, v2}, [x1], x15 + st1.1d {v0, v1, v2, v3}, [x1], x15 + + st1.2d {v0}, [x1], x15 + st1.2d {v0, v1}, [x1], x15 + st1.2d {v0, v1, v2}, [x1], x15 + st1.2d {v0, v1, v2, v3}, [x1], x15 + + ld1.8b {v0}, [x1], #8 + ld1.8b {v0, v1}, [x1], #16 + ld1.8b {v0, v1, v2}, [x1], #24 + ld1.8b {v0, v1, v2, v3}, [x1], #32 + + ld1.16b {v0}, [x1], #16 + ld1.16b {v0, v1}, [x1], #32 + ld1.16b {v0, v1, v2}, [x1], #48 + ld1.16b {v0, v1, v2, v3}, [x1], #64 + + ld1.4h {v0}, [x1], #8 + ld1.4h {v0, v1}, [x1], #16 + ld1.4h {v0, v1, v2}, [x1], #24 + ld1.4h {v0, v1, v2, v3}, [x1], #32 + + ld1.8h {v0}, [x1], #16 + ld1.8h {v0, v1}, [x1], #32 + ld1.8h {v0, v1, v2}, [x1], #48 + ld1.8h {v0, v1, v2, v3}, [x1], #64 + + ld1.2s {v0}, [x1], #8 + ld1.2s {v0, v1}, [x1], #16 + ld1.2s {v0, v1, v2}, [x1], #24 + ld1.2s {v0, v1, v2, v3}, [x1], #32 + + ld1.4s {v0}, [x1], #16 + ld1.4s {v0, v1}, [x1], #32 + ld1.4s {v0, v1, v2}, [x1], #48 + ld1.4s {v0, v1, v2, v3}, [x1], #64 + + ld1.1d {v0}, [x1], #8 + ld1.1d {v0, v1}, [x1], #16 + ld1.1d {v0, v1, v2}, [x1], #24 + ld1.1d {v0, v1, v2, v3}, [x1], #32 + + ld1.2d {v0}, [x1], #16 + ld1.2d {v0, v1}, [x1], #32 + ld1.2d {v0, v1, v2}, [x1], #48 + ld1.2d {v0, v1, v2, v3}, [x1], #64 + + st1.8b {v0}, [x1], #8 + st1.8b {v0, v1}, [x1], #16 + st1.8b {v0, v1, v2}, [x1], #24 + st1.8b {v0, v1, v2, v3}, [x1], #32 + + st1.16b {v0}, [x1], #16 + st1.16b {v0, v1}, [x1], #32 + st1.16b {v0, v1, v2}, [x1], #48 + st1.16b {v0, v1, v2, v3}, [x1], #64 + + st1.4h {v0}, [x1], #8 + st1.4h {v0, v1}, [x1], #16 + st1.4h {v0, v1, v2}, [x1], #24 + st1.4h {v0, v1, v2, v3}, [x1], #32 + + st1.8h {v0}, [x1], #16 + st1.8h {v0, v1}, [x1], #32 + st1.8h {v0, v1, v2}, [x1], #48 + st1.8h {v0, v1, v2, v3}, [x1], #64 + + st1.2s {v0}, [x1], #8 + st1.2s {v0, v1}, [x1], #16 + st1.2s {v0, v1, v2}, [x1], #24 + st1.2s {v0, v1, v2, v3}, [x1], #32 + + st1.4s {v0}, [x1], #16 + st1.4s {v0, v1}, [x1], #32 + st1.4s {v0, v1, v2}, [x1], #48 + st1.4s {v0, v1, v2, v3}, [x1], #64 + + st1.1d {v0}, [x1], #8 + st1.1d {v0, v1}, [x1], #16 + st1.1d {v0, v1, v2}, [x1], #24 + st1.1d {v0, v1, v2, v3}, [x1], #32 + + st1.2d {v0}, [x1], #16 + st1.2d {v0, v1}, [x1], #32 + st1.2d {v0, v1, v2}, [x1], #48 + st1.2d {v0, v1, v2, v3}, [x1], #64 + +; CHECK: ld1st1_multiple_post: +; CHECK: ld1.8b { v0 }, [x1], x15 ; encoding: [0x20,0x70,0xcf,0x0c] +; CHECK: ld1.8b { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa0,0xcf,0x0c] +; CHECK: ld1.8b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x60,0xcf,0x0c] +; CHECK: ld1.8b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x20,0xcf,0x0c] + +; CHECK: ld1.16b { v0 }, [x1], x15 ; encoding: [0x20,0x70,0xcf,0x4c] +; CHECK: ld1.16b { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa0,0xcf,0x4c] +; CHECK: ld1.16b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x60,0xcf,0x4c] +; CHECK: ld1.16b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x20,0xcf,0x4c] + +; CHECK: ld1.4h { v0 }, [x1], x15 ; encoding: [0x20,0x74,0xcf,0x0c] +; CHECK: ld1.4h { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa4,0xcf,0x0c] +; CHECK: ld1.4h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x64,0xcf,0x0c] +; CHECK: ld1.4h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x24,0xcf,0x0c] + +; CHECK: ld1.8h { v0 }, [x1], x15 ; encoding: [0x20,0x74,0xcf,0x4c] +; CHECK: ld1.8h { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa4,0xcf,0x4c] +; CHECK: ld1.8h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x64,0xcf,0x4c] +; CHECK: ld1.8h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x24,0xcf,0x4c] + +; CHECK: ld1.2s { v0 }, [x1], x15 ; encoding: [0x20,0x78,0xcf,0x0c] +; CHECK: ld1.2s { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa8,0xcf,0x0c] +; CHECK: ld1.2s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x68,0xcf,0x0c] +; CHECK: ld1.2s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x28,0xcf,0x0c] + +; CHECK: ld1.4s { v0 }, [x1], x15 ; encoding: [0x20,0x78,0xcf,0x4c] +; CHECK: ld1.4s { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa8,0xcf,0x4c] +; CHECK: ld1.4s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x68,0xcf,0x4c] +; CHECK: ld1.4s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x28,0xcf,0x4c] + +; CHECK: ld1.1d { v0 }, [x1], x15 ; encoding: [0x20,0x7c,0xcf,0x0c] +; CHECK: ld1.1d { v0, v1 }, [x1], x15 ; encoding: [0x20,0xac,0xcf,0x0c] +; CHECK: ld1.1d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x6c,0xcf,0x0c] +; CHECK: ld1.1d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x2c,0xcf,0x0c] + +; CHECK: ld1.2d { v0 }, [x1], x15 ; encoding: [0x20,0x7c,0xcf,0x4c] +; CHECK: ld1.2d { v0, v1 }, [x1], x15 ; encoding: [0x20,0xac,0xcf,0x4c] +; CHECK: ld1.2d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x6c,0xcf,0x4c] +; CHECK: ld1.2d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x2c,0xcf,0x4c] + +; CHECK: st1.8b { v0 }, [x1], x15 ; encoding: [0x20,0x70,0x8f,0x0c] +; CHECK: st1.8b { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa0,0x8f,0x0c] +; CHECK: st1.8b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x60,0x8f,0x0c] +; CHECK: st1.8b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x20,0x8f,0x0c] + +; CHECK: st1.16b { v0 }, [x1], x15 ; encoding: [0x20,0x70,0x8f,0x4c] +; CHECK: st1.16b { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa0,0x8f,0x4c] +; CHECK: st1.16b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x60,0x8f,0x4c] +; CHECK: st1.16b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x20,0x8f,0x4c] + +; CHECK: st1.4h { v0 }, [x1], x15 ; encoding: [0x20,0x74,0x8f,0x0c] +; CHECK: st1.4h { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa4,0x8f,0x0c] +; CHECK: st1.4h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x64,0x8f,0x0c] +; CHECK: st1.4h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x24,0x8f,0x0c] + +; CHECK: st1.8h { v0 }, [x1], x15 ; encoding: [0x20,0x74,0x8f,0x4c] +; CHECK: st1.8h { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa4,0x8f,0x4c] +; CHECK: st1.8h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x64,0x8f,0x4c] +; CHECK: st1.8h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x24,0x8f,0x4c] + +; CHECK: st1.2s { v0 }, [x1], x15 ; encoding: [0x20,0x78,0x8f,0x0c] +; CHECK: st1.2s { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa8,0x8f,0x0c] +; CHECK: st1.2s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x68,0x8f,0x0c] +; CHECK: st1.2s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x28,0x8f,0x0c] + +; CHECK: st1.4s { v0 }, [x1], x15 ; encoding: [0x20,0x78,0x8f,0x4c] +; CHECK: st1.4s { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa8,0x8f,0x4c] +; CHECK: st1.4s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x68,0x8f,0x4c] +; CHECK: st1.4s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x28,0x8f,0x4c] + +; CHECK: st1.1d { v0 }, [x1], x15 ; encoding: [0x20,0x7c,0x8f,0x0c] +; CHECK: st1.1d { v0, v1 }, [x1], x15 ; encoding: [0x20,0xac,0x8f,0x0c] +; CHECK: st1.1d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x6c,0x8f,0x0c] +; CHECK: st1.1d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x2c,0x8f,0x0c] + +; CHECK: st1.2d { v0 }, [x1], x15 ; encoding: [0x20,0x7c,0x8f,0x4c] +; CHECK: st1.2d { v0, v1 }, [x1], x15 ; encoding: [0x20,0xac,0x8f,0x4c] +; CHECK: st1.2d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x6c,0x8f,0x4c] +; CHECK: st1.2d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x2c,0x8f,0x4c] + +; CHECK: ld1.8b { v0 }, [x1], #8 ; encoding: [0x20,0x70,0xdf,0x0c] +; CHECK: ld1.8b { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa0,0xdf,0x0c] +; CHECK: ld1.8b { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x60,0xdf,0x0c] +; CHECK: ld1.8b { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x20,0xdf,0x0c] + +; CHECK: ld1.16b { v0 }, [x1], #16 ; encoding: [0x20,0x70,0xdf,0x4c] +; CHECK: ld1.16b { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa0,0xdf,0x4c] +; CHECK: ld1.16b { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x60,0xdf,0x4c] +; CHECK: ld1.16b { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x20,0xdf,0x4c] + +; CHECK: ld1.4h { v0 }, [x1], #8 ; encoding: [0x20,0x74,0xdf,0x0c] +; CHECK: ld1.4h { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa4,0xdf,0x0c] +; CHECK: ld1.4h { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x64,0xdf,0x0c] +; CHECK: ld1.4h { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x24,0xdf,0x0c] + +; CHECK: ld1.8h { v0 }, [x1], #16 ; encoding: [0x20,0x74,0xdf,0x4c] +; CHECK: ld1.8h { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa4,0xdf,0x4c] +; CHECK: ld1.8h { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x64,0xdf,0x4c] +; CHECK: ld1.8h { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x24,0xdf,0x4c] + +; CHECK: ld1.2s { v0 }, [x1], #8 ; encoding: [0x20,0x78,0xdf,0x0c] +; CHECK: ld1.2s { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa8,0xdf,0x0c] +; CHECK: ld1.2s { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x68,0xdf,0x0c] +; CHECK: ld1.2s { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x28,0xdf,0x0c] + +; CHECK: ld1.4s { v0 }, [x1], #16 ; encoding: [0x20,0x78,0xdf,0x4c] +; CHECK: ld1.4s { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa8,0xdf,0x4c] +; CHECK: ld1.4s { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x68,0xdf,0x4c] +; CHECK: ld1.4s { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x28,0xdf,0x4c] + +; CHECK: ld1.1d { v0 }, [x1], #8 ; encoding: [0x20,0x7c,0xdf,0x0c] +; CHECK: ld1.1d { v0, v1 }, [x1], #16 ; encoding: [0x20,0xac,0xdf,0x0c] +; CHECK: ld1.1d { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x6c,0xdf,0x0c] +; CHECK: ld1.1d { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x2c,0xdf,0x0c] + +; CHECK: ld1.2d { v0 }, [x1], #16 ; encoding: [0x20,0x7c,0xdf,0x4c] +; CHECK: ld1.2d { v0, v1 }, [x1], #32 ; encoding: [0x20,0xac,0xdf,0x4c] +; CHECK: ld1.2d { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x6c,0xdf,0x4c] +; CHECK: ld1.2d { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x2c,0xdf,0x4c] + +; CHECK: st1.8b { v0 }, [x1], #8 ; encoding: [0x20,0x70,0x9f,0x0c] +; CHECK: st1.8b { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa0,0x9f,0x0c] +; CHECK: st1.8b { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x60,0x9f,0x0c] +; CHECK: st1.8b { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x20,0x9f,0x0c] + +; CHECK: st1.16b { v0 }, [x1], #16 ; encoding: [0x20,0x70,0x9f,0x4c] +; CHECK: st1.16b { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa0,0x9f,0x4c] +; CHECK: st1.16b { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x60,0x9f,0x4c] +; CHECK: st1.16b { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x20,0x9f,0x4c] + +; CHECK: st1.4h { v0 }, [x1], #8 ; encoding: [0x20,0x74,0x9f,0x0c] +; CHECK: st1.4h { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa4,0x9f,0x0c] +; CHECK: st1.4h { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x64,0x9f,0x0c] +; CHECK: st1.4h { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x24,0x9f,0x0c] + +; CHECK: st1.8h { v0 }, [x1], #16 ; encoding: [0x20,0x74,0x9f,0x4c] +; CHECK: st1.8h { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa4,0x9f,0x4c] +; CHECK: st1.8h { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x64,0x9f,0x4c] +; CHECK: st1.8h { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x24,0x9f,0x4c] + +; CHECK: st1.2s { v0 }, [x1], #8 ; encoding: [0x20,0x78,0x9f,0x0c] +; CHECK: st1.2s { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa8,0x9f,0x0c] +; CHECK: st1.2s { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x68,0x9f,0x0c] +; CHECK: st1.2s { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x28,0x9f,0x0c] + +; CHECK: st1.4s { v0 }, [x1], #16 ; encoding: [0x20,0x78,0x9f,0x4c] +; CHECK: st1.4s { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa8,0x9f,0x4c] +; CHECK: st1.4s { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x68,0x9f,0x4c] +; CHECK: st1.4s { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x28,0x9f,0x4c] + +; CHECK: st1.1d { v0 }, [x1], #8 ; encoding: [0x20,0x7c,0x9f,0x0c] +; CHECK: st1.1d { v0, v1 }, [x1], #16 ; encoding: [0x20,0xac,0x9f,0x0c] +; CHECK: st1.1d { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x6c,0x9f,0x0c] +; CHECK: st1.1d { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x2c,0x9f,0x0c] + +; CHECK: st1.2d { v0 }, [x1], #16 ; encoding: [0x20,0x7c,0x9f,0x4c] +; CHECK: st1.2d { v0, v1 }, [x1], #32 ; encoding: [0x20,0xac,0x9f,0x4c] +; CHECK: st1.2d { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x6c,0x9f,0x4c] +; CHECK: st1.2d { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x2c,0x9f,0x4c] + + +_ld2st2_multiple_post: + ld2.8b {v0, v1}, [x1], x15 + ld2.16b {v0, v1}, [x1], x15 + ld2.4h {v0, v1}, [x1], x15 + ld2.8h {v0, v1}, [x1], x15 + ld2.2s {v0, v1}, [x1], x15 + ld2.4s {v0, v1}, [x1], x15 + ld2.2d {v0, v1}, [x1], x15 + + st2.8b {v0, v1}, [x1], x15 + st2.16b {v0, v1}, [x1], x15 + st2.4h {v0, v1}, [x1], x15 + st2.8h {v0, v1}, [x1], x15 + st2.2s {v0, v1}, [x1], x15 + st2.4s {v0, v1}, [x1], x15 + st2.2d {v0, v1}, [x1], x15 + + ld2.8b {v0, v1}, [x1], #16 + ld2.16b {v0, v1}, [x1], #32 + ld2.4h {v0, v1}, [x1], #16 + ld2.8h {v0, v1}, [x1], #32 + ld2.2s {v0, v1}, [x1], #16 + ld2.4s {v0, v1}, [x1], #32 + ld2.2d {v0, v1}, [x1], #32 + + st2.8b {v0, v1}, [x1], #16 + st2.16b {v0, v1}, [x1], #32 + st2.4h {v0, v1}, [x1], #16 + st2.8h {v0, v1}, [x1], #32 + st2.2s {v0, v1}, [x1], #16 + st2.4s {v0, v1}, [x1], #32 + st2.2d {v0, v1}, [x1], #32 + + +; CHECK: ld2st2_multiple_post: +; CHECK: ld2.8b { v0, v1 }, [x1], x15 ; encoding: [0x20,0x80,0xcf,0x0c] +; CHECK: ld2.16b { v0, v1 }, [x1], x15 ; encoding: [0x20,0x80,0xcf,0x4c] +; CHECK: ld2.4h { v0, v1 }, [x1], x15 ; encoding: [0x20,0x84,0xcf,0x0c] +; CHECK: ld2.8h { v0, v1 }, [x1], x15 ; encoding: [0x20,0x84,0xcf,0x4c] +; CHECK: ld2.2s { v0, v1 }, [x1], x15 ; encoding: [0x20,0x88,0xcf,0x0c] +; CHECK: ld2.4s { v0, v1 }, [x1], x15 ; encoding: [0x20,0x88,0xcf,0x4c] +; CHECK: ld2.2d { v0, v1 }, [x1], x15 ; encoding: [0x20,0x8c,0xcf,0x4c] + +; CHECK: st2.8b { v0, v1 }, [x1], x15 ; encoding: [0x20,0x80,0x8f,0x0c] +; CHECK: st2.16b { v0, v1 }, [x1], x15 ; encoding: [0x20,0x80,0x8f,0x4c] +; CHECK: st2.4h { v0, v1 }, [x1], x15 ; encoding: [0x20,0x84,0x8f,0x0c] +; CHECK: st2.8h { v0, v1 }, [x1], x15 ; encoding: [0x20,0x84,0x8f,0x4c] +; CHECK: st2.2s { v0, v1 }, [x1], x15 ; encoding: [0x20,0x88,0x8f,0x0c] +; CHECK: st2.4s { v0, v1 }, [x1], x15 ; encoding: [0x20,0x88,0x8f,0x4c] +; CHECK: st2.2d { v0, v1 }, [x1], x15 ; encoding: [0x20,0x8c,0x8f,0x4c] + +; CHECK: ld2.8b { v0, v1 }, [x1], #16 ; encoding: [0x20,0x80,0xdf,0x0c] +; CHECK: ld2.16b { v0, v1 }, [x1], #32 ; encoding: [0x20,0x80,0xdf,0x4c] +; CHECK: ld2.4h { v0, v1 }, [x1], #16 ; encoding: [0x20,0x84,0xdf,0x0c] +; CHECK: ld2.8h { v0, v1 }, [x1], #32 ; encoding: [0x20,0x84,0xdf,0x4c] +; CHECK: ld2.2s { v0, v1 }, [x1], #16 ; encoding: [0x20,0x88,0xdf,0x0c] +; CHECK: ld2.4s { v0, v1 }, [x1], #32 ; encoding: [0x20,0x88,0xdf,0x4c] +; CHECK: ld2.2d { v0, v1 }, [x1], #32 ; encoding: [0x20,0x8c,0xdf,0x4c] + +; CHECK: st2.8b { v0, v1 }, [x1], #16 ; encoding: [0x20,0x80,0x9f,0x0c] +; CHECK: st2.16b { v0, v1 }, [x1], #32 ; encoding: [0x20,0x80,0x9f,0x4c] +; CHECK: st2.4h { v0, v1 }, [x1], #16 ; encoding: [0x20,0x84,0x9f,0x0c] +; CHECK: st2.8h { v0, v1 }, [x1], #32 ; encoding: [0x20,0x84,0x9f,0x4c] +; CHECK: st2.2s { v0, v1 }, [x1], #16 ; encoding: [0x20,0x88,0x9f,0x0c] +; CHECK: st2.4s { v0, v1 }, [x1], #32 ; encoding: [0x20,0x88,0x9f,0x4c] +; CHECK: st2.2d { v0, v1 }, [x1], #32 ; encoding: [0x20,0x8c,0x9f,0x4c] + + +_ld3st3_multiple_post: + ld3.8b {v0, v1, v2}, [x1], x15 + ld3.16b {v0, v1, v2}, [x1], x15 + ld3.4h {v0, v1, v2}, [x1], x15 + ld3.8h {v0, v1, v2}, [x1], x15 + ld3.2s {v0, v1, v2}, [x1], x15 + ld3.4s {v0, v1, v2}, [x1], x15 + ld3.2d {v0, v1, v2}, [x1], x15 + + st3.8b {v0, v1, v2}, [x1], x15 + st3.16b {v0, v1, v2}, [x1], x15 + st3.4h {v0, v1, v2}, [x1], x15 + st3.8h {v0, v1, v2}, [x1], x15 + st3.2s {v0, v1, v2}, [x1], x15 + st3.4s {v0, v1, v2}, [x1], x15 + st3.2d {v0, v1, v2}, [x1], x15 + + ld3.8b {v0, v1, v2}, [x1], #24 + ld3.16b {v0, v1, v2}, [x1], #48 + ld3.4h {v0, v1, v2}, [x1], #24 + ld3.8h {v0, v1, v2}, [x1], #48 + ld3.2s {v0, v1, v2}, [x1], #24 + ld3.4s {v0, v1, v2}, [x1], #48 + ld3.2d {v0, v1, v2}, [x1], #48 + + st3.8b {v0, v1, v2}, [x1], #24 + st3.16b {v0, v1, v2}, [x1], #48 + st3.4h {v0, v1, v2}, [x1], #24 + st3.8h {v0, v1, v2}, [x1], #48 + st3.2s {v0, v1, v2}, [x1], #24 + st3.4s {v0, v1, v2}, [x1], #48 + st3.2d {v0, v1, v2}, [x1], #48 + +; CHECK: ld3st3_multiple_post: +; CHECK: ld3.8b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x40,0xcf,0x0c] +; CHECK: ld3.16b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x40,0xcf,0x4c] +; CHECK: ld3.4h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x44,0xcf,0x0c] +; CHECK: ld3.8h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x44,0xcf,0x4c] +; CHECK: ld3.2s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x48,0xcf,0x0c] +; CHECK: ld3.4s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x48,0xcf,0x4c] +; CHECK: ld3.2d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x4c,0xcf,0x4c] + +; CHECK: st3.8b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x40,0x8f,0x0c] +; CHECK: st3.16b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x40,0x8f,0x4c] +; CHECK: st3.4h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x44,0x8f,0x0c] +; CHECK: st3.8h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x44,0x8f,0x4c] +; CHECK: st3.2s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x48,0x8f,0x0c] +; CHECK: st3.4s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x48,0x8f,0x4c] +; CHECK: st3.2d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x4c,0x8f,0x4c] + +; CHECK: ld3.8b { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x40,0xdf,0x0c] +; CHECK: ld3.16b { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x40,0xdf,0x4c] +; CHECK: ld3.4h { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x44,0xdf,0x0c] +; CHECK: ld3.8h { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x44,0xdf,0x4c] +; CHECK: ld3.2s { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x48,0xdf,0x0c] +; CHECK: ld3.4s { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x48,0xdf,0x4c] +; CHECK: ld3.2d { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x4c,0xdf,0x4c] + +; CHECK: st3.8b { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x40,0x9f,0x0c] +; CHECK: st3.16b { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x40,0x9f,0x4c] +; CHECK: st3.4h { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x44,0x9f,0x0c] +; CHECK: st3.8h { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x44,0x9f,0x4c] +; CHECK: st3.2s { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x48,0x9f,0x0c] +; CHECK: st3.4s { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x48,0x9f,0x4c] +; CHECK: st3.2d { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x4c,0x9f,0x4c] + +_ld4st4_multiple_post: + ld4.8b {v0, v1, v2, v3}, [x1], x15 + ld4.16b {v0, v1, v2, v3}, [x1], x15 + ld4.4h {v0, v1, v2, v3}, [x1], x15 + ld4.8h {v0, v1, v2, v3}, [x1], x15 + ld4.2s {v0, v1, v2, v3}, [x1], x15 + ld4.4s {v0, v1, v2, v3}, [x1], x15 + ld4.2d {v0, v1, v2, v3}, [x1], x15 + + st4.8b {v0, v1, v2, v3}, [x1], x15 + st4.16b {v0, v1, v2, v3}, [x1], x15 + st4.4h {v0, v1, v2, v3}, [x1], x15 + st4.8h {v0, v1, v2, v3}, [x1], x15 + st4.2s {v0, v1, v2, v3}, [x1], x15 + st4.4s {v0, v1, v2, v3}, [x1], x15 + st4.2d {v0, v1, v2, v3}, [x1], x15 + + ld4.8b {v0, v1, v2, v3}, [x1], #32 + ld4.16b {v0, v1, v2, v3}, [x1], #64 + ld4.4h {v0, v1, v2, v3}, [x1], #32 + ld4.8h {v0, v1, v2, v3}, [x1], #64 + ld4.2s {v0, v1, v2, v3}, [x1], #32 + ld4.4s {v0, v1, v2, v3}, [x1], #64 + ld4.2d {v0, v1, v2, v3}, [x1], #64 + + st4.8b {v0, v1, v2, v3}, [x1], #32 + st4.16b {v0, v1, v2, v3}, [x1], #64 + st4.4h {v0, v1, v2, v3}, [x1], #32 + st4.8h {v0, v1, v2, v3}, [x1], #64 + st4.2s {v0, v1, v2, v3}, [x1], #32 + st4.4s {v0, v1, v2, v3}, [x1], #64 + st4.2d {v0, v1, v2, v3}, [x1], #64 + + +; CHECK: ld4st4_multiple_post: +; CHECK: ld4.8b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x00,0xcf,0x0c] +; CHECK: ld4.16b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x00,0xcf,0x4c] +; CHECK: ld4.4h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x04,0xcf,0x0c] +; CHECK: ld4.8h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x04,0xcf,0x4c] +; CHECK: ld4.2s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x08,0xcf,0x0c] +; CHECK: ld4.4s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x08,0xcf,0x4c] +; CHECK: ld4.2d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x0c,0xcf,0x4c] + +; CHECK: st4.8b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x00,0x8f,0x0c] +; CHECK: st4.16b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x00,0x8f,0x4c] +; CHECK: st4.4h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x04,0x8f,0x0c] +; CHECK: st4.8h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x04,0x8f,0x4c] +; CHECK: st4.2s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x08,0x8f,0x0c] +; CHECK: st4.4s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x08,0x8f,0x4c] +; CHECK: st4.2d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x0c,0x8f,0x4c] + +; CHECK: ld4.8b { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x00,0xdf,0x0c] +; CHECK: ld4.16b { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x00,0xdf,0x4c] +; CHECK: ld4.4h { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x04,0xdf,0x0c] +; CHECK: ld4.8h { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x04,0xdf,0x4c] +; CHECK: ld4.2s { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x08,0xdf,0x0c] +; CHECK: ld4.4s { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x08,0xdf,0x4c] +; CHECK: ld4.2d { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x0c,0xdf,0x4c] + +; CHECK: st4.8b { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x00,0x9f,0x0c] +; CHECK: st4.16b { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x00,0x9f,0x4c] +; CHECK: st4.4h { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x04,0x9f,0x0c] +; CHECK: st4.8h { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x04,0x9f,0x4c] +; CHECK: st4.2s { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x08,0x9f,0x0c] +; CHECK: st4.4s { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x08,0x9f,0x4c] +; CHECK: st4.2d { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x0c,0x9f,0x4c] + +ld1r: + ld1r.8b {v4}, [x2] + ld1r.8b {v4}, [x2], x3 + ld1r.16b {v4}, [x2] + ld1r.16b {v4}, [x2], x3 + ld1r.4h {v4}, [x2] + ld1r.4h {v4}, [x2], x3 + ld1r.8h {v4}, [x2] + ld1r.8h {v4}, [x2], x3 + ld1r.2s {v4}, [x2] + ld1r.2s {v4}, [x2], x3 + ld1r.4s {v4}, [x2] + ld1r.4s {v4}, [x2], x3 + ld1r.1d {v4}, [x2] + ld1r.1d {v4}, [x2], x3 + ld1r.2d {v4}, [x2] + ld1r.2d {v4}, [x2], x3 + + ld1r.8b {v4}, [x2], #1 + ld1r.16b {v4}, [x2], #1 + ld1r.4h {v4}, [x2], #2 + ld1r.8h {v4}, [x2], #2 + ld1r.2s {v4}, [x2], #4 + ld1r.4s {v4}, [x2], #4 + ld1r.1d {v4}, [x2], #8 + ld1r.2d {v4}, [x2], #8 + +; CHECK: ld1r: +; CHECK: ld1r.8b { v4 }, [x2] ; encoding: [0x44,0xc0,0x40,0x0d] +; CHECK: ld1r.8b { v4 }, [x2], x3 ; encoding: [0x44,0xc0,0xc3,0x0d] +; CHECK: ld1r.16b { v4 }, [x2] ; encoding: [0x44,0xc0,0x40,0x4d] +; CHECK: ld1r.16b { v4 }, [x2], x3 ; encoding: [0x44,0xc0,0xc3,0x4d] +; CHECK: ld1r.4h { v4 }, [x2] ; encoding: [0x44,0xc4,0x40,0x0d] +; CHECK: ld1r.4h { v4 }, [x2], x3 ; encoding: [0x44,0xc4,0xc3,0x0d] +; CHECK: ld1r.8h { v4 }, [x2] ; encoding: [0x44,0xc4,0x40,0x4d] +; CHECK: ld1r.8h { v4 }, [x2], x3 ; encoding: [0x44,0xc4,0xc3,0x4d] +; CHECK: ld1r.2s { v4 }, [x2] ; encoding: [0x44,0xc8,0x40,0x0d] +; CHECK: ld1r.2s { v4 }, [x2], x3 ; encoding: [0x44,0xc8,0xc3,0x0d] +; CHECK: ld1r.4s { v4 }, [x2] ; encoding: [0x44,0xc8,0x40,0x4d] +; CHECK: ld1r.4s { v4 }, [x2], x3 ; encoding: [0x44,0xc8,0xc3,0x4d] +; CHECK: ld1r.1d { v4 }, [x2] ; encoding: [0x44,0xcc,0x40,0x0d] +; CHECK: ld1r.1d { v4 }, [x2], x3 ; encoding: [0x44,0xcc,0xc3,0x0d] +; CHECK: ld1r.2d { v4 }, [x2] ; encoding: [0x44,0xcc,0x40,0x4d] +; CHECK: ld1r.2d { v4 }, [x2], x3 ; encoding: [0x44,0xcc,0xc3,0x4d] + +; CHECK: ld1r.8b { v4 }, [x2], #1 ; encoding: [0x44,0xc0,0xdf,0x0d] +; CHECK: ld1r.16b { v4 }, [x2], #1 ; encoding: [0x44,0xc0,0xdf,0x4d] +; CHECK: ld1r.4h { v4 }, [x2], #2 ; encoding: [0x44,0xc4,0xdf,0x0d] +; CHECK: ld1r.8h { v4 }, [x2], #2 ; encoding: [0x44,0xc4,0xdf,0x4d] +; CHECK: ld1r.2s { v4 }, [x2], #4 ; encoding: [0x44,0xc8,0xdf,0x0d] +; CHECK: ld1r.4s { v4 }, [x2], #4 ; encoding: [0x44,0xc8,0xdf,0x4d] +; CHECK: ld1r.1d { v4 }, [x2], #8 ; encoding: [0x44,0xcc,0xdf,0x0d] +; CHECK: ld1r.2d { v4 }, [x2], #8 ; encoding: [0x44,0xcc,0xdf,0x4d] + +ld2r: + ld2r.8b {v4, v5}, [x2] + ld2r.8b {v4, v5}, [x2], x3 + ld2r.16b {v4, v5}, [x2] + ld2r.16b {v4, v5}, [x2], x3 + ld2r.4h {v4, v5}, [x2] + ld2r.4h {v4, v5}, [x2], x3 + ld2r.8h {v4, v5}, [x2] + ld2r.8h {v4, v5}, [x2], x3 + ld2r.2s {v4, v5}, [x2] + ld2r.2s {v4, v5}, [x2], x3 + ld2r.4s {v4, v5}, [x2] + ld2r.4s {v4, v5}, [x2], x3 + ld2r.1d {v4, v5}, [x2] + ld2r.1d {v4, v5}, [x2], x3 + ld2r.2d {v4, v5}, [x2] + ld2r.2d {v4, v5}, [x2], x3 + + ld2r.8b {v4, v5}, [x2], #2 + ld2r.16b {v4, v5}, [x2], #2 + ld2r.4h {v4, v5}, [x2], #4 + ld2r.8h {v4, v5}, [x2], #4 + ld2r.2s {v4, v5}, [x2], #8 + ld2r.4s {v4, v5}, [x2], #8 + ld2r.1d {v4, v5}, [x2], #16 + ld2r.2d {v4, v5}, [x2], #16 + +; CHECK: ld2r: +; CHECK: ld2r.8b { v4, v5 }, [x2] ; encoding: [0x44,0xc0,0x60,0x0d] +; CHECK: ld2r.8b { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc0,0xe3,0x0d] +; CHECK: ld2r.16b { v4, v5 }, [x2] ; encoding: [0x44,0xc0,0x60,0x4d] +; CHECK: ld2r.16b { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc0,0xe3,0x4d] +; CHECK: ld2r.4h { v4, v5 }, [x2] ; encoding: [0x44,0xc4,0x60,0x0d] +; CHECK: ld2r.4h { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc4,0xe3,0x0d] +; CHECK: ld2r.8h { v4, v5 }, [x2] ; encoding: [0x44,0xc4,0x60,0x4d] +; CHECK: ld2r.8h { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc4,0xe3,0x4d] +; CHECK: ld2r.2s { v4, v5 }, [x2] ; encoding: [0x44,0xc8,0x60,0x0d] +; CHECK: ld2r.2s { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc8,0xe3,0x0d] +; CHECK: ld2r.4s { v4, v5 }, [x2] ; encoding: [0x44,0xc8,0x60,0x4d] +; CHECK: ld2r.4s { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc8,0xe3,0x4d] +; CHECK: ld2r.1d { v4, v5 }, [x2] ; encoding: [0x44,0xcc,0x60,0x0d] +; CHECK: ld2r.1d { v4, v5 }, [x2], x3 ; encoding: [0x44,0xcc,0xe3,0x0d] +; CHECK: ld2r.2d { v4, v5 }, [x2] ; encoding: [0x44,0xcc,0x60,0x4d] +; CHECK: ld2r.2d { v4, v5 }, [x2], x3 ; encoding: [0x44,0xcc,0xe3,0x4d] + +; CHECK: ld2r.8b { v4, v5 }, [x2], #2 ; encoding: [0x44,0xc0,0xff,0x0d] +; CHECK: ld2r.16b { v4, v5 }, [x2], #2 ; encoding: [0x44,0xc0,0xff,0x4d] +; CHECK: ld2r.4h { v4, v5 }, [x2], #4 ; encoding: [0x44,0xc4,0xff,0x0d] +; CHECK: ld2r.8h { v4, v5 }, [x2], #4 ; encoding: [0x44,0xc4,0xff,0x4d] +; CHECK: ld2r.2s { v4, v5 }, [x2], #8 ; encoding: [0x44,0xc8,0xff,0x0d] +; CHECK: ld2r.4s { v4, v5 }, [x2], #8 ; encoding: [0x44,0xc8,0xff,0x4d] +; CHECK: ld2r.1d { v4, v5 }, [x2], #16 ; encoding: [0x44,0xcc,0xff,0x0d] +; CHECK: ld2r.2d { v4, v5 }, [x2], #16 ; encoding: [0x44,0xcc,0xff,0x4d] + +ld3r: + ld3r.8b {v4, v5, v6}, [x2] + ld3r.8b {v4, v5, v6}, [x2], x3 + ld3r.16b {v4, v5, v6}, [x2] + ld3r.16b {v4, v5, v6}, [x2], x3 + ld3r.4h {v4, v5, v6}, [x2] + ld3r.4h {v4, v5, v6}, [x2], x3 + ld3r.8h {v4, v5, v6}, [x2] + ld3r.8h {v4, v5, v6}, [x2], x3 + ld3r.2s {v4, v5, v6}, [x2] + ld3r.2s {v4, v5, v6}, [x2], x3 + ld3r.4s {v4, v5, v6}, [x2] + ld3r.4s {v4, v5, v6}, [x2], x3 + ld3r.1d {v4, v5, v6}, [x2] + ld3r.1d {v4, v5, v6}, [x2], x3 + ld3r.2d {v4, v5, v6}, [x2] + ld3r.2d {v4, v5, v6}, [x2], x3 + + ld3r.8b {v4, v5, v6}, [x2], #3 + ld3r.16b {v4, v5, v6}, [x2], #3 + ld3r.4h {v4, v5, v6}, [x2], #6 + ld3r.8h {v4, v5, v6}, [x2], #6 + ld3r.2s {v4, v5, v6}, [x2], #12 + ld3r.4s {v4, v5, v6}, [x2], #12 + ld3r.1d {v4, v5, v6}, [x2], #24 + ld3r.2d {v4, v5, v6}, [x2], #24 + +; CHECK: ld3r: +; CHECK: ld3r.8b { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe0,0x40,0x0d] +; CHECK: ld3r.8b { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe0,0xc3,0x0d] +; CHECK: ld3r.16b { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe0,0x40,0x4d] +; CHECK: ld3r.16b { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe0,0xc3,0x4d] +; CHECK: ld3r.4h { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe4,0x40,0x0d] +; CHECK: ld3r.4h { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe4,0xc3,0x0d] +; CHECK: ld3r.8h { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe4,0x40,0x4d] +; CHECK: ld3r.8h { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe4,0xc3,0x4d] +; CHECK: ld3r.2s { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe8,0x40,0x0d] +; CHECK: ld3r.2s { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe8,0xc3,0x0d] +; CHECK: ld3r.4s { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe8,0x40,0x4d] +; CHECK: ld3r.4s { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe8,0xc3,0x4d] +; CHECK: ld3r.1d { v4, v5, v6 }, [x2] ; encoding: [0x44,0xec,0x40,0x0d] +; CHECK: ld3r.1d { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xec,0xc3,0x0d] +; CHECK: ld3r.2d { v4, v5, v6 }, [x2] ; encoding: [0x44,0xec,0x40,0x4d] +; CHECK: ld3r.2d { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xec,0xc3,0x4d] + +; CHECK: ld3r.8b { v4, v5, v6 }, [x2], #3 ; encoding: [0x44,0xe0,0xdf,0x0d] +; CHECK: ld3r.16b { v4, v5, v6 }, [x2], #3 ; encoding: [0x44,0xe0,0xdf,0x4d] +; CHECK: ld3r.4h { v4, v5, v6 }, [x2], #6 ; encoding: [0x44,0xe4,0xdf,0x0d] +; CHECK: ld3r.8h { v4, v5, v6 }, [x2], #6 ; encoding: [0x44,0xe4,0xdf,0x4d] +; CHECK: ld3r.2s { v4, v5, v6 }, [x2], #12 ; encoding: [0x44,0xe8,0xdf,0x0d] +; CHECK: ld3r.4s { v4, v5, v6 }, [x2], #12 ; encoding: [0x44,0xe8,0xdf,0x4d] +; CHECK: ld3r.1d { v4, v5, v6 }, [x2], #24 ; encoding: [0x44,0xec,0xdf,0x0d] +; CHECK: ld3r.2d { v4, v5, v6 }, [x2], #24 ; encoding: [0x44,0xec,0xdf,0x4d] + +ld4r: + ld4r.8b {v4, v5, v6, v7}, [x2] + ld4r.8b {v4, v5, v6, v7}, [x2], x3 + ld4r.16b {v4, v5, v6, v7}, [x2] + ld4r.16b {v4, v5, v6, v7}, [x2], x3 + ld4r.4h {v4, v5, v6, v7}, [x2] + ld4r.4h {v4, v5, v6, v7}, [x2], x3 + ld4r.8h {v4, v5, v6, v7}, [x2] + ld4r.8h {v4, v5, v6, v7}, [x2], x3 + ld4r.2s {v4, v5, v6, v7}, [x2] + ld4r.2s {v4, v5, v6, v7}, [x2], x3 + ld4r.4s {v4, v5, v6, v7}, [x2] + ld4r.4s {v4, v5, v6, v7}, [x2], x3 + ld4r.1d {v4, v5, v6, v7}, [x2] + ld4r.1d {v4, v5, v6, v7}, [x2], x3 + ld4r.2d {v4, v5, v6, v7}, [x2] + ld4r.2d {v4, v5, v6, v7}, [x2], x3 + + ld4r.8b {v4, v5, v6, v7}, [x2], #4 + ld4r.16b {v5, v6, v7, v8}, [x2], #4 + ld4r.4h {v6, v7, v8, v9}, [x2], #8 + ld4r.8h {v1, v2, v3, v4}, [x2], #8 + ld4r.2s {v2, v3, v4, v5}, [x2], #16 + ld4r.4s {v3, v4, v5, v6}, [x2], #16 + ld4r.1d {v0, v1, v2, v3}, [x2], #32 + ld4r.2d {v4, v5, v6, v7}, [x2], #32 + +; CHECK: ld4r: +; CHECK: ld4r.8b { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe0,0x60,0x0d] +; CHECK: ld4r.8b { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe0,0xe3,0x0d] +; CHECK: ld4r.16b { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe0,0x60,0x4d] +; CHECK: ld4r.16b { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe0,0xe3,0x4d] +; CHECK: ld4r.4h { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe4,0x60,0x0d] +; CHECK: ld4r.4h { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe4,0xe3,0x0d] +; CHECK: ld4r.8h { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe4,0x60,0x4d] +; CHECK: ld4r.8h { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe4,0xe3,0x4d] +; CHECK: ld4r.2s { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe8,0x60,0x0d] +; CHECK: ld4r.2s { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe8,0xe3,0x0d] +; CHECK: ld4r.4s { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe8,0x60,0x4d] +; CHECK: ld4r.4s { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe8,0xe3,0x4d] +; CHECK: ld4r.1d { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xec,0x60,0x0d] +; CHECK: ld4r.1d { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xec,0xe3,0x0d] +; CHECK: ld4r.2d { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xec,0x60,0x4d] +; CHECK: ld4r.2d { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xec,0xe3,0x4d] + +; CHECK: ld4r.8b { v4, v5, v6, v7 }, [x2], #4 ; encoding: [0x44,0xe0,0xff,0x0d] +; CHECK: ld4r.16b { v5, v6, v7, v8 }, [x2], #4 ; encoding: [0x45,0xe0,0xff,0x4d] +; CHECK: ld4r.4h { v6, v7, v8, v9 }, [x2], #8 ; encoding: [0x46,0xe4,0xff,0x0d] +; CHECK: ld4r.8h { v1, v2, v3, v4 }, [x2], #8 ; encoding: [0x41,0xe4,0xff,0x4d] +; CHECK: ld4r.2s { v2, v3, v4, v5 }, [x2], #16 ; encoding: [0x42,0xe8,0xff,0x0d] +; CHECK: ld4r.4s { v3, v4, v5, v6 }, [x2], #16 ; encoding: [0x43,0xe8,0xff,0x4d] +; CHECK: ld4r.1d { v0, v1, v2, v3 }, [x2], #32 ; encoding: [0x40,0xec,0xff,0x0d] +; CHECK: ld4r.2d { v4, v5, v6, v7 }, [x2], #32 ; encoding: [0x44,0xec,0xff,0x4d] + + +_ld1: + ld1.b {v4}[13], [x3] + ld1.h {v4}[2], [x3] + ld1.s {v4}[2], [x3] + ld1.d {v4}[1], [x3] + ld1.b {v4}[13], [x3], x5 + ld1.h {v4}[2], [x3], x5 + ld1.s {v4}[2], [x3], x5 + ld1.d {v4}[1], [x3], x5 + ld1.b {v4}[13], [x3], #1 + ld1.h {v4}[2], [x3], #2 + ld1.s {v4}[2], [x3], #4 + ld1.d {v4}[1], [x3], #8 + +; CHECK: _ld1: +; CHECK: ld1.b { v4 }[13], [x3] ; encoding: [0x64,0x14,0x40,0x4d] +; CHECK: ld1.h { v4 }[2], [x3] ; encoding: [0x64,0x50,0x40,0x0d] +; CHECK: ld1.s { v4 }[2], [x3] ; encoding: [0x64,0x80,0x40,0x4d] +; CHECK: ld1.d { v4 }[1], [x3] ; encoding: [0x64,0x84,0x40,0x4d] +; CHECK: ld1.b { v4 }[13], [x3], x5 ; encoding: [0x64,0x14,0xc5,0x4d] +; CHECK: ld1.h { v4 }[2], [x3], x5 ; encoding: [0x64,0x50,0xc5,0x0d] +; CHECK: ld1.s { v4 }[2], [x3], x5 ; encoding: [0x64,0x80,0xc5,0x4d] +; CHECK: ld1.d { v4 }[1], [x3], x5 ; encoding: [0x64,0x84,0xc5,0x4d] +; CHECK: ld1.b { v4 }[13], [x3], #1 ; encoding: [0x64,0x14,0xdf,0x4d] +; CHECK: ld1.h { v4 }[2], [x3], #2 ; encoding: [0x64,0x50,0xdf,0x0d] +; CHECK: ld1.s { v4 }[2], [x3], #4 ; encoding: [0x64,0x80,0xdf,0x4d] +; CHECK: ld1.d { v4 }[1], [x3], #8 ; encoding: [0x64,0x84,0xdf,0x4d] + +_ld2: + ld2.b {v4, v5}[13], [x3] + ld2.h {v4, v5}[2], [x3] + ld2.s {v4, v5}[2], [x3] + ld2.d {v4, v5}[1], [x3] + ld2.b {v4, v5}[13], [x3], x5 + ld2.h {v4, v5}[2], [x3], x5 + ld2.s {v4, v5}[2], [x3], x5 + ld2.d {v4, v5}[1], [x3], x5 + ld2.b {v4, v5}[13], [x3], #2 + ld2.h {v4, v5}[2], [x3], #4 + ld2.s {v4, v5}[2], [x3], #8 + ld2.d {v4, v5}[1], [x3], #16 + + +; CHECK: _ld2: +; CHECK: ld2.b { v4, v5 }[13], [x3] ; encoding: [0x64,0x14,0x60,0x4d] +; CHECK: ld2.h { v4, v5 }[2], [x3] ; encoding: [0x64,0x50,0x60,0x0d] +; CHECK: ld2.s { v4, v5 }[2], [x3] ; encoding: [0x64,0x80,0x60,0x4d] +; CHECK: ld2.d { v4, v5 }[1], [x3] ; encoding: [0x64,0x84,0x60,0x4d] +; CHECK: ld2.b { v4, v5 }[13], [x3], x5 ; encoding: [0x64,0x14,0xe5,0x4d] +; CHECK: ld2.h { v4, v5 }[2], [x3], x5 ; encoding: [0x64,0x50,0xe5,0x0d] +; CHECK: ld2.s { v4, v5 }[2], [x3], x5 ; encoding: [0x64,0x80,0xe5,0x4d] +; CHECK: ld2.d { v4, v5 }[1], [x3], x5 ; encoding: [0x64,0x84,0xe5,0x4d] +; CHECK: ld2.b { v4, v5 }[13], [x3], #2 ; encoding: [0x64,0x14,0xff,0x4d] +; CHECK: ld2.h { v4, v5 }[2], [x3], #4 ; encoding: [0x64,0x50,0xff,0x0d] +; CHECK: ld2.s { v4, v5 }[2], [x3], #8 ; encoding: [0x64,0x80,0xff,0x4d] +; CHECK: ld2.d { v4, v5 }[1], [x3], #16 ; encoding: [0x64,0x84,0xff,0x4d] + + +_ld3: + ld3.b {v4, v5, v6}[13], [x3] + ld3.h {v4, v5, v6}[2], [x3] + ld3.s {v4, v5, v6}[2], [x3] + ld3.d {v4, v5, v6}[1], [x3] + ld3.b {v4, v5, v6}[13], [x3], x5 + ld3.h {v4, v5, v6}[2], [x3], x5 + ld3.s {v4, v5, v6}[2], [x3], x5 + ld3.d {v4, v5, v6}[1], [x3], x5 + ld3.b {v4, v5, v6}[13], [x3], #3 + ld3.h {v4, v5, v6}[2], [x3], #6 + ld3.s {v4, v5, v6}[2], [x3], #12 + ld3.d {v4, v5, v6}[1], [x3], #24 + + +; CHECK: _ld3: +; CHECK: ld3.b { v4, v5, v6 }[13], [x3] ; encoding: [0x64,0x34,0x40,0x4d] +; CHECK: ld3.h { v4, v5, v6 }[2], [x3] ; encoding: [0x64,0x70,0x40,0x0d] +; CHECK: ld3.s { v4, v5, v6 }[2], [x3] ; encoding: [0x64,0xa0,0x40,0x4d] +; CHECK: ld3.d { v4, v5, v6 }[1], [x3] ; encoding: [0x64,0xa4,0x40,0x4d] +; CHECK: ld3.b { v4, v5, v6 }[13], [x3], x5 ; encoding: [0x64,0x34,0xc5,0x4d] +; CHECK: ld3.h { v4, v5, v6 }[2], [x3], x5 ; encoding: [0x64,0x70,0xc5,0x0d] +; CHECK: ld3.s { v4, v5, v6 }[2], [x3], x5 ; encoding: [0x64,0xa0,0xc5,0x4d] +; CHECK: ld3.d { v4, v5, v6 }[1], [x3], x5 ; encoding: [0x64,0xa4,0xc5,0x4d] +; CHECK: ld3.b { v4, v5, v6 }[13], [x3], #3 ; encoding: [0x64,0x34,0xdf,0x4d] +; CHECK: ld3.h { v4, v5, v6 }[2], [x3], #6 ; encoding: [0x64,0x70,0xdf,0x0d] +; CHECK: ld3.s { v4, v5, v6 }[2], [x3], #12 ; encoding: [0x64,0xa0,0xdf,0x4d] +; CHECK: ld3.d { v4, v5, v6 }[1], [x3], #24 ; encoding: [0x64,0xa4,0xdf,0x4d] + + +_ld4: + ld4.b {v4, v5, v6, v7}[13], [x3] + ld4.h {v4, v5, v6, v7}[2], [x3] + ld4.s {v4, v5, v6, v7}[2], [x3] + ld4.d {v4, v5, v6, v7}[1], [x3] + ld4.b {v4, v5, v6, v7}[13], [x3], x5 + ld4.h {v4, v5, v6, v7}[2], [x3], x5 + ld4.s {v4, v5, v6, v7}[2], [x3], x5 + ld4.d {v4, v5, v6, v7}[1], [x3], x5 + ld4.b {v4, v5, v6, v7}[13], [x3], #4 + ld4.h {v4, v5, v6, v7}[2], [x3], #8 + ld4.s {v4, v5, v6, v7}[2], [x3], #16 + ld4.d {v4, v5, v6, v7}[1], [x3], #32 + +; CHECK: _ld4: +; CHECK: ld4.b { v4, v5, v6, v7 }[13], [x3] ; encoding: [0x64,0x34,0x60,0x4d] +; CHECK: ld4.h { v4, v5, v6, v7 }[2], [x3] ; encoding: [0x64,0x70,0x60,0x0d] +; CHECK: ld4.s { v4, v5, v6, v7 }[2], [x3] ; encoding: [0x64,0xa0,0x60,0x4d] +; CHECK: ld4.d { v4, v5, v6, v7 }[1], [x3] ; encoding: [0x64,0xa4,0x60,0x4d] +; CHECK: ld4.b { v4, v5, v6, v7 }[13], [x3], x5 ; encoding: [0x64,0x34,0xe5,0x4d] +; CHECK: ld4.h { v4, v5, v6, v7 }[2], [x3], x5 ; encoding: [0x64,0x70,0xe5,0x0d] +; CHECK: ld4.s { v4, v5, v6, v7 }[2], [x3], x5 ; encoding: [0x64,0xa0,0xe5,0x4d] +; CHECK: ld4.d { v4, v5, v6, v7 }[1], [x3], x5 ; encoding: [0x64,0xa4,0xe5,0x4d] +; CHECK: ld4.b { v4, v5, v6, v7 }[13], [x3], #4 ; encoding: [0x64,0x34,0xff,0x4d] +; CHECK: ld4.h { v4, v5, v6, v7 }[2], [x3], #8 ; encoding: [0x64,0x70,0xff,0x0d] +; CHECK: ld4.s { v4, v5, v6, v7 }[2], [x3], #16 ; encoding: [0x64,0xa0,0xff,0x4d] +; CHECK: ld4.d { v4, v5, v6, v7 }[1], [x3], #32 ; encoding: [0x64,0xa4,0xff,0x4d] + +_st1: + st1.b {v4}[13], [x3] + st1.h {v4}[2], [x3] + st1.s {v4}[2], [x3] + st1.d {v4}[1], [x3] + st1.b {v4}[13], [x3], x5 + st1.h {v4}[2], [x3], x5 + st1.s {v4}[2], [x3], x5 + st1.d {v4}[1], [x3], x5 + st1.b {v4}[13], [x3], #1 + st1.h {v4}[2], [x3], #2 + st1.s {v4}[2], [x3], #4 + st1.d {v4}[1], [x3], #8 + +; CHECK: _st1: +; CHECK: st1.b { v4 }[13], [x3] ; encoding: [0x64,0x14,0x00,0x4d] +; CHECK: st1.h { v4 }[2], [x3] ; encoding: [0x64,0x50,0x00,0x0d] +; CHECK: st1.s { v4 }[2], [x3] ; encoding: [0x64,0x80,0x00,0x4d] +; CHECK: st1.d { v4 }[1], [x3] ; encoding: [0x64,0x84,0x00,0x4d] +; CHECK: st1.b { v4 }[13], [x3], x5 ; encoding: [0x64,0x14,0x85,0x4d] +; CHECK: st1.h { v4 }[2], [x3], x5 ; encoding: [0x64,0x50,0x85,0x0d] +; CHECK: st1.s { v4 }[2], [x3], x5 ; encoding: [0x64,0x80,0x85,0x4d] +; CHECK: st1.d { v4 }[1], [x3], x5 ; encoding: [0x64,0x84,0x85,0x4d] +; CHECK: st1.b { v4 }[13], [x3], #1 ; encoding: [0x64,0x14,0x9f,0x4d] +; CHECK: st1.h { v4 }[2], [x3], #2 ; encoding: [0x64,0x50,0x9f,0x0d] +; CHECK: st1.s { v4 }[2], [x3], #4 ; encoding: [0x64,0x80,0x9f,0x4d] +; CHECK: st1.d { v4 }[1], [x3], #8 ; encoding: [0x64,0x84,0x9f,0x4d] + +_st2: + st2.b {v4, v5}[13], [x3] + st2.h {v4, v5}[2], [x3] + st2.s {v4, v5}[2], [x3] + st2.d {v4, v5}[1], [x3] + st2.b {v4, v5}[13], [x3], x5 + st2.h {v4, v5}[2], [x3], x5 + st2.s {v4, v5}[2], [x3], x5 + st2.d {v4, v5}[1], [x3], x5 + st2.b {v4, v5}[13], [x3], #2 + st2.h {v4, v5}[2], [x3], #4 + st2.s {v4, v5}[2], [x3], #8 + st2.d {v4, v5}[1], [x3], #16 + +; CHECK: _st2: +; CHECK: st2.b { v4, v5 }[13], [x3] ; encoding: [0x64,0x14,0x20,0x4d] +; CHECK: st2.h { v4, v5 }[2], [x3] ; encoding: [0x64,0x50,0x20,0x0d] +; CHECK: st2.s { v4, v5 }[2], [x3] ; encoding: [0x64,0x80,0x20,0x4d] +; CHECK: st2.d { v4, v5 }[1], [x3] ; encoding: [0x64,0x84,0x20,0x4d] +; CHECK: st2.b { v4, v5 }[13], [x3], x5 ; encoding: [0x64,0x14,0xa5,0x4d] +; CHECK: st2.h { v4, v5 }[2], [x3], x5 ; encoding: [0x64,0x50,0xa5,0x0d] +; CHECK: st2.s { v4, v5 }[2], [x3], x5 ; encoding: [0x64,0x80,0xa5,0x4d] +; CHECK: st2.d { v4, v5 }[1], [x3], x5 ; encoding: [0x64,0x84,0xa5,0x4d] +; CHECK: st2.b { v4, v5 }[13], [x3], #2 ; encoding: [0x64,0x14,0xbf,0x4d] +; CHECK: st2.h { v4, v5 }[2], [x3], #4 ; encoding: [0x64,0x50,0xbf,0x0d] +; CHECK: st2.s { v4, v5 }[2], [x3], #8 ; encoding: [0x64,0x80,0xbf,0x4d] +; CHECK: st2.d { v4, v5 }[1], [x3], #16 ; encoding: [0x64,0x84,0xbf,0x4d] + + +_st3: + st3.b {v4, v5, v6}[13], [x3] + st3.h {v4, v5, v6}[2], [x3] + st3.s {v4, v5, v6}[2], [x3] + st3.d {v4, v5, v6}[1], [x3] + st3.b {v4, v5, v6}[13], [x3], x5 + st3.h {v4, v5, v6}[2], [x3], x5 + st3.s {v4, v5, v6}[2], [x3], x5 + st3.d {v4, v5, v6}[1], [x3], x5 + st3.b {v4, v5, v6}[13], [x3], #3 + st3.h {v4, v5, v6}[2], [x3], #6 + st3.s {v4, v5, v6}[2], [x3], #12 + st3.d {v4, v5, v6}[1], [x3], #24 + +; CHECK: _st3: +; CHECK: st3.b { v4, v5, v6 }[13], [x3] ; encoding: [0x64,0x34,0x00,0x4d] +; CHECK: st3.h { v4, v5, v6 }[2], [x3] ; encoding: [0x64,0x70,0x00,0x0d] +; CHECK: st3.s { v4, v5, v6 }[2], [x3] ; encoding: [0x64,0xa0,0x00,0x4d] +; CHECK: st3.d { v4, v5, v6 }[1], [x3] ; encoding: [0x64,0xa4,0x00,0x4d] +; CHECK: st3.b { v4, v5, v6 }[13], [x3], x5 ; encoding: [0x64,0x34,0x85,0x4d] +; CHECK: st3.h { v4, v5, v6 }[2], [x3], x5 ; encoding: [0x64,0x70,0x85,0x0d] +; CHECK: st3.s { v4, v5, v6 }[2], [x3], x5 ; encoding: [0x64,0xa0,0x85,0x4d] +; CHECK: st3.d { v4, v5, v6 }[1], [x3], x5 ; encoding: [0x64,0xa4,0x85,0x4d] +; CHECK: st3.b { v4, v5, v6 }[13], [x3], #3 ; encoding: [0x64,0x34,0x9f,0x4d] +; CHECK: st3.h { v4, v5, v6 }[2], [x3], #6 ; encoding: [0x64,0x70,0x9f,0x0d] +; CHECK: st3.s { v4, v5, v6 }[2], [x3], #12 ; encoding: [0x64,0xa0,0x9f,0x4d] +; CHECK: st3.d { v4, v5, v6 }[1], [x3], #24 ; encoding: [0x64,0xa4,0x9f,0x4d] + +_st4: + st4.b {v4, v5, v6, v7}[13], [x3] + st4.h {v4, v5, v6, v7}[2], [x3] + st4.s {v4, v5, v6, v7}[2], [x3] + st4.d {v4, v5, v6, v7}[1], [x3] + st4.b {v4, v5, v6, v7}[13], [x3], x5 + st4.h {v4, v5, v6, v7}[2], [x3], x5 + st4.s {v4, v5, v6, v7}[2], [x3], x5 + st4.d {v4, v5, v6, v7}[1], [x3], x5 + st4.b {v4, v5, v6, v7}[13], [x3], #4 + st4.h {v4, v5, v6, v7}[2], [x3], #8 + st4.s {v4, v5, v6, v7}[2], [x3], #16 + st4.d {v4, v5, v6, v7}[1], [x3], #32 + +; CHECK: _st4: +; CHECK: st4.b { v4, v5, v6, v7 }[13], [x3] ; encoding: [0x64,0x34,0x20,0x4d] +; CHECK: st4.h { v4, v5, v6, v7 }[2], [x3] ; encoding: [0x64,0x70,0x20,0x0d] +; CHECK: st4.s { v4, v5, v6, v7 }[2], [x3] ; encoding: [0x64,0xa0,0x20,0x4d] +; CHECK: st4.d { v4, v5, v6, v7 }[1], [x3] ; encoding: [0x64,0xa4,0x20,0x4d] +; CHECK: st4.b { v4, v5, v6, v7 }[13], [x3], x5 ; encoding: [0x64,0x34,0xa5,0x4d] +; CHECK: st4.h { v4, v5, v6, v7 }[2], [x3], x5 ; encoding: [0x64,0x70,0xa5,0x0d] +; CHECK: st4.s { v4, v5, v6, v7 }[2], [x3], x5 ; encoding: [0x64,0xa0,0xa5,0x4d] +; CHECK: st4.d { v4, v5, v6, v7 }[1], [x3], x5 ; encoding: [0x64,0xa4,0xa5,0x4d] +; CHECK: st4.b { v4, v5, v6, v7 }[13], [x3], #4 ; encoding: [0x64,0x34,0xbf,0x4d] +; CHECK: st4.h { v4, v5, v6, v7 }[2], [x3], #8 ; encoding: [0x64,0x70,0xbf,0x0d] +; CHECK: st4.s { v4, v5, v6, v7 }[2], [x3], #16 ; encoding: [0x64,0xa0,0xbf,0x4d] +; CHECK: st4.d { v4, v5, v6, v7 }[1], [x3], #32 ; encoding: [0x64,0xa4,0xbf,0x4d] + + +;--------- +; ARM verbose syntax equivalents to the above. +;--------- +verbose_syntax: + + ld1 { v1.8b }, [x1] + ld1 { v2.8b, v3.8b }, [x1] + ld1 { v3.8b, v4.8b, v5.8b }, [x1] + ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1] + + ld1 { v1.16b }, [x1] + ld1 { v2.16b, v3.16b }, [x1] + ld1 { v3.16b, v4.16b, v5.16b }, [x1] + ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1] + + ld1 { v1.4h }, [x1] + ld1 { v2.4h, v3.4h }, [x1] + ld1 { v3.4h, v4.4h, v5.4h }, [x1] + ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1] + + ld1 { v1.8h }, [x1] + ld1 { v2.8h, v3.8h }, [x1] + ld1 { v3.8h, v4.8h, v5.8h }, [x1] + ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1] + + ld1 { v1.2s }, [x1] + ld1 { v2.2s, v3.2s }, [x1] + ld1 { v3.2s, v4.2s, v5.2s }, [x1] + ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1] + + ld1 { v1.4s }, [x1] + ld1 { v2.4s, v3.4s }, [x1] + ld1 { v3.4s, v4.4s, v5.4s }, [x1] + ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1] + + ld1 { v1.1d }, [x1] + ld1 { v2.1d, v3.1d }, [x1] + ld1 { v3.1d, v4.1d, v5.1d }, [x1] + ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1] + + ld1 { v1.2d }, [x1] + ld1 { v2.2d, v3.2d }, [x1] + ld1 { v3.2d, v4.2d, v5.2d }, [x1] + ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1] + + st1 { v1.8b }, [x1] + st1 { v2.8b, v3.8b }, [x1] + st1 { v3.8b, v4.8b, v5.8b }, [x1] + st1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1] + + st1 { v1.16b }, [x1] + st1 { v2.16b, v3.16b }, [x1] + st1 { v3.16b, v4.16b, v5.16b }, [x1] + st1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1] + + st1 { v1.4h }, [x1] + st1 { v2.4h, v3.4h }, [x1] + st1 { v3.4h, v4.4h, v5.4h }, [x1] + st1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1] + + st1 { v1.8h }, [x1] + st1 { v2.8h, v3.8h }, [x1] + st1 { v3.8h, v4.8h, v5.8h }, [x1] + st1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1] + + st1 { v1.2s }, [x1] + st1 { v2.2s, v3.2s }, [x1] + st1 { v3.2s, v4.2s, v5.2s }, [x1] + st1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1] + + st1 { v1.4s }, [x1] + st1 { v2.4s, v3.4s }, [x1] + st1 { v3.4s, v4.4s, v5.4s }, [x1] + st1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1] + + st1 { v1.1d }, [x1] + st1 { v2.1d, v3.1d }, [x1] + st1 { v3.1d, v4.1d, v5.1d }, [x1] + st1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1] + + st1 { v1.2d }, [x1] + st1 { v2.2d, v3.2d }, [x1] + st1 { v3.2d, v4.2d, v5.2d }, [x1] + st1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1] + + ld2 { v3.8b, v4.8b }, [x19] + ld2 { v3.16b, v4.16b }, [x19] + ld2 { v3.4h, v4.4h }, [x19] + ld2 { v3.8h, v4.8h }, [x19] + ld2 { v3.2s, v4.2s }, [x19] + ld2 { v3.4s, v4.4s }, [x19] + ld2 { v3.2d, v4.2d }, [x19] + + st2 { v3.8b, v4.8b }, [x19] + st2 { v3.16b, v4.16b }, [x19] + st2 { v3.4h, v4.4h }, [x19] + st2 { v3.8h, v4.8h }, [x19] + st2 { v3.2s, v4.2s }, [x19] + st2 { v3.4s, v4.4s }, [x19] + st2 { v3.2d, v4.2d }, [x19] + + ld3 { v2.8b, v3.8b, v4.8b }, [x19] + ld3 { v2.16b, v3.16b, v4.16b }, [x19] + ld3 { v2.4h, v3.4h, v4.4h }, [x19] + ld3 { v2.8h, v3.8h, v4.8h }, [x19] + ld3 { v2.2s, v3.2s, v4.2s }, [x19] + ld3 { v2.4s, v3.4s, v4.4s }, [x19] + ld3 { v2.2d, v3.2d, v4.2d }, [x19] + + st3 { v2.8b, v3.8b, v4.8b }, [x19] + st3 { v2.16b, v3.16b, v4.16b }, [x19] + st3 { v2.4h, v3.4h, v4.4h }, [x19] + st3 { v2.8h, v3.8h, v4.8h }, [x19] + st3 { v2.2s, v3.2s, v4.2s }, [x19] + st3 { v2.4s, v3.4s, v4.4s }, [x19] + st3 { v2.2d, v3.2d, v4.2d }, [x19] + + ld4 { v2.8b, v3.8b, v4.8b, v5.8b }, [x19] + ld4 { v2.16b, v3.16b, v4.16b, v5.16b }, [x19] + ld4 { v2.4h, v3.4h, v4.4h, v5.4h }, [x19] + ld4 { v2.8h, v3.8h, v4.8h, v5.8h }, [x19] + ld4 { v2.2s, v3.2s, v4.2s, v5.2s }, [x19] + ld4 { v2.4s, v3.4s, v4.4s, v5.4s }, [x19] + ld4 { v2.2d, v3.2d, v4.2d, v5.2d }, [x19] + + st4 { v2.8b, v3.8b, v4.8b, v5.8b }, [x19] + st4 { v2.16b, v3.16b, v4.16b, v5.16b }, [x19] + st4 { v2.4h, v3.4h, v4.4h, v5.4h }, [x19] + st4 { v2.8h, v3.8h, v4.8h, v5.8h }, [x19] + st4 { v2.2s, v3.2s, v4.2s, v5.2s }, [x19] + st4 { v2.4s, v3.4s, v4.4s, v5.4s }, [x19] + st4 { v2.2d, v3.2d, v4.2d, v5.2d }, [x19] + + ld1 { v1.8b }, [x1], x15 + ld1 { v2.8b, v3.8b }, [x1], x15 + ld1 { v3.8b, v4.8b, v5.8b }, [x1], x15 + ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], x15 + + ld1 { v1.16b }, [x1], x15 + ld1 { v2.16b, v3.16b }, [x1], x15 + ld1 { v3.16b, v4.16b, v5.16b }, [x1], x15 + ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], x15 + + ld1 { v1.4h }, [x1], x15 + ld1 { v2.4h, v3.4h }, [x1], x15 + ld1 { v3.4h, v4.4h, v5.4h }, [x1], x15 + ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], x15 + + ld1 { v1.8h }, [x1], x15 + ld1 { v2.8h, v3.8h }, [x1], x15 + ld1 { v3.8h, v4.8h, v5.8h }, [x1], x15 + ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], x15 + + ld1 { v1.2s }, [x1], x15 + ld1 { v2.2s, v3.2s }, [x1], x15 + ld1 { v3.2s, v4.2s, v5.2s }, [x1], x15 + ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], x15 + + ld1 { v1.4s }, [x1], x15 + ld1 { v2.4s, v3.4s }, [x1], x15 + ld1 { v3.4s, v4.4s, v5.4s }, [x1], x15 + ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], x15 + + ld1 { v1.1d }, [x1], x15 + ld1 { v2.1d, v3.1d }, [x1], x15 + ld1 { v3.1d, v4.1d, v5.1d }, [x1], x15 + ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1], x15 + + ld1 { v1.2d }, [x1], x15 + ld1 { v2.2d, v3.2d }, [x1], x15 + ld1 { v3.2d, v4.2d, v5.2d }, [x1], x15 + ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], x15 + + st1 { v1.8b }, [x1], x15 + st1 { v2.8b, v3.8b }, [x1], x15 + st1 { v3.8b, v4.8b, v5.8b }, [x1], x15 + st1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], x15 + + st1 { v1.16b }, [x1], x15 + st1 { v2.16b, v3.16b }, [x1], x15 + st1 { v3.16b, v4.16b, v5.16b }, [x1], x15 + st1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], x15 + + st1 { v1.4h }, [x1], x15 + st1 { v2.4h, v3.4h }, [x1], x15 + st1 { v3.4h, v4.4h, v5.4h }, [x1], x15 + st1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], x15 + + st1 { v1.8h }, [x1], x15 + st1 { v2.8h, v3.8h }, [x1], x15 + st1 { v3.8h, v4.8h, v5.8h }, [x1], x15 + st1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], x15 + + st1 { v1.2s }, [x1], x15 + st1 { v2.2s, v3.2s }, [x1], x15 + st1 { v3.2s, v4.2s, v5.2s }, [x1], x15 + st1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], x15 + + st1 { v1.4s }, [x1], x15 + st1 { v2.4s, v3.4s }, [x1], x15 + st1 { v3.4s, v4.4s, v5.4s }, [x1], x15 + st1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], x15 + + st1 { v1.1d }, [x1], x15 + st1 { v2.1d, v3.1d }, [x1], x15 + st1 { v3.1d, v4.1d, v5.1d }, [x1], x15 + st1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1], x15 + + st1 { v1.2d }, [x1], x15 + st1 { v2.2d, v3.2d }, [x1], x15 + st1 { v3.2d, v4.2d, v5.2d }, [x1], x15 + st1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], x15 + + ld1 { v1.8b }, [x1], #8 + ld1 { v2.8b, v3.8b }, [x1], #16 + ld1 { v3.8b, v4.8b, v5.8b }, [x1], #24 + ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], #32 + + ld1 { v1.16b }, [x1], #16 + ld1 { v2.16b, v3.16b }, [x1], #32 + ld1 { v3.16b, v4.16b, v5.16b }, [x1], #48 + ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], #64 + + ld1 { v1.4h }, [x1], #8 + ld1 { v2.4h, v3.4h }, [x1], #16 + ld1 { v3.4h, v4.4h, v5.4h }, [x1], #24 + ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], #32 + + ld1 { v1.8h }, [x1], #16 + ld1 { v2.8h, v3.8h }, [x1], #32 + ld1 { v3.8h, v4.8h, v5.8h }, [x1], #48 + ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], #64 + + ld1 { v1.2s }, [x1], #8 + ld1 { v2.2s, v3.2s }, [x1], #16 + ld1 { v3.2s, v4.2s, v5.2s }, [x1], #24 + ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], #32 + + ld1 { v1.4s }, [x1], #16 + ld1 { v2.4s, v3.4s }, [x1], #32 + ld1 { v3.4s, v4.4s, v5.4s }, [x1], #48 + ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], #64 + + ld1 { v1.1d }, [x1], #8 + ld1 { v2.1d, v3.1d }, [x1], #16 + ld1 { v3.1d, v4.1d, v5.1d }, [x1], #24 + ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1], #32 + + ld1 { v1.2d }, [x1], #16 + ld1 { v2.2d, v3.2d }, [x1], #32 + ld1 { v3.2d, v4.2d, v5.2d }, [x1], #48 + ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], #64 + + st1 { v1.8b }, [x1], #8 + st1 { v2.8b, v3.8b }, [x1], #16 + st1 { v3.8b, v4.8b, v5.8b }, [x1], #24 + st1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], #32 + + st1 { v1.16b }, [x1], #16 + st1 { v2.16b, v3.16b }, [x1], #32 + st1 { v3.16b, v4.16b, v5.16b }, [x1], #48 + st1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], #64 + + st1 { v1.4h }, [x1], #8 + st1 { v2.4h, v3.4h }, [x1], #16 + st1 { v3.4h, v4.4h, v5.4h }, [x1], #24 + st1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], #32 + + st1 { v1.8h }, [x1], #16 + st1 { v2.8h, v3.8h }, [x1], #32 + st1 { v3.8h, v4.8h, v5.8h }, [x1], #48 + st1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], #64 + + st1 { v1.2s }, [x1], #8 + st1 { v2.2s, v3.2s }, [x1], #16 + st1 { v3.2s, v4.2s, v5.2s }, [x1], #24 + st1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], #32 + + st1 { v1.4s }, [x1], #16 + st1 { v2.4s, v3.4s }, [x1], #32 + st1 { v3.4s, v4.4s, v5.4s }, [x1], #48 + st1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], #64 + + st1 { v1.1d }, [x1], #8 + st1 { v2.1d, v3.1d }, [x1], #16 + st1 { v3.1d, v4.1d, v5.1d }, [x1], #24 + st1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1], #32 + + st1 { v1.2d }, [x1], #16 + st1 { v2.2d, v3.2d }, [x1], #32 + st1 { v3.2d, v4.2d, v5.2d }, [x1], #48 + st1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], #64 + + ld2 { v2.8b, v3.8b }, [x1], x15 + ld2 { v2.16b, v3.16b }, [x1], x15 + ld2 { v2.4h, v3.4h }, [x1], x15 + ld2 { v2.8h, v3.8h }, [x1], x15 + ld2 { v2.2s, v3.2s }, [x1], x15 + ld2 { v2.4s, v3.4s }, [x1], x15 + ld2 { v2.2d, v3.2d }, [x1], x15 + + st2 { v2.8b, v3.8b }, [x1], x15 + st2 { v2.16b, v3.16b }, [x1], x15 + st2 { v2.4h, v3.4h }, [x1], x15 + st2 { v2.8h, v3.8h }, [x1], x15 + st2 { v2.2s, v3.2s }, [x1], x15 + st2 { v2.4s, v3.4s }, [x1], x15 + st2 { v2.2d, v3.2d }, [x1], x15 + + ld2 { v2.8b, v3.8b }, [x1], #16 + ld2 { v2.16b, v3.16b }, [x1], #32 + ld2 { v2.4h, v3.4h }, [x1], #16 + ld2 { v2.8h, v3.8h }, [x1], #32 + ld2 { v2.2s, v3.2s }, [x1], #16 + ld2 { v2.4s, v3.4s }, [x1], #32 + ld2 { v2.2d, v3.2d }, [x1], #32 + + st2 { v2.8b, v3.8b }, [x1], #16 + st2 { v2.16b, v3.16b }, [x1], #32 + st2 { v2.4h, v3.4h }, [x1], #16 + st2 { v2.8h, v3.8h }, [x1], #32 + st2 { v2.2s, v3.2s }, [x1], #16 + st2 { v2.4s, v3.4s }, [x1], #32 + st2 { v2.2d, v3.2d }, [x1], #32 + + ld3 { v3.8b, v4.8b, v5.8b }, [x1], x15 + ld3 { v3.16b, v4.16b, v5.16b }, [x1], x15 + ld3 { v3.4h, v4.4h, v5.4h }, [x1], x15 + ld3 { v3.8h, v4.8h, v5.8h }, [x1], x15 + ld3 { v3.2s, v4.2s, v5.2s }, [x1], x15 + ld3 { v3.4s, v4.4s, v5.4s }, [x1], x15 + ld3 { v3.2d, v4.2d, v5.2d }, [x1], x15 + + st3 { v3.8b, v4.8b, v5.8b }, [x1], x15 + st3 { v3.16b, v4.16b, v5.16b }, [x1], x15 + st3 { v3.4h, v4.4h, v5.4h }, [x1], x15 + st3 { v3.8h, v4.8h, v5.8h }, [x1], x15 + st3 { v3.2s, v4.2s, v5.2s }, [x1], x15 + st3 { v3.4s, v4.4s, v5.4s }, [x1], x15 + st3 { v3.2d, v4.2d, v5.2d }, [x1], x15 + ld3 { v3.8b, v4.8b, v5.8b }, [x1], #24 + + ld3 { v3.16b, v4.16b, v5.16b }, [x1], #48 + ld3 { v3.4h, v4.4h, v5.4h }, [x1], #24 + ld3 { v3.8h, v4.8h, v5.8h }, [x1], #48 + ld3 { v3.2s, v4.2s, v5.2s }, [x1], #24 + ld3 { v3.4s, v4.4s, v5.4s }, [x1], #48 + ld3 { v3.2d, v4.2d, v5.2d }, [x1], #48 + + st3 { v3.8b, v4.8b, v5.8b }, [x1], #24 + st3 { v3.16b, v4.16b, v5.16b }, [x1], #48 + st3 { v3.4h, v4.4h, v5.4h }, [x1], #24 + st3 { v3.8h, v4.8h, v5.8h }, [x1], #48 + st3 { v3.2s, v4.2s, v5.2s }, [x1], #24 + st3 { v3.4s, v4.4s, v5.4s }, [x1], #48 + st3 { v3.2d, v4.2d, v5.2d }, [x1], #48 + + ld4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], x15 + ld4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], x15 + ld4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], x15 + ld4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], x15 + ld4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], x15 + ld4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], x15 + ld4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], x15 + + st4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], x15 + st4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], x15 + st4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], x15 + st4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], x15 + st4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], x15 + st4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], x15 + st4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], x15 + + ld4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], #32 + ld4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], #64 + ld4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], #32 + ld4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], #64 + ld4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], #32 + ld4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], #64 + ld4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], #64 + + st4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], #32 + st4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], #64 + st4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], #32 + st4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], #64 + st4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], #32 + st4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], #64 + st4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], #64 + + + ld1r { v12.8b }, [x2] + ld1r { v12.8b }, [x2], x3 + ld1r { v12.16b }, [x2] + ld1r { v12.16b }, [x2], x3 + ld1r { v12.4h }, [x2] + ld1r { v12.4h }, [x2], x3 + ld1r { v12.8h }, [x2] + ld1r { v12.8h }, [x2], x3 + ld1r { v12.2s }, [x2] + ld1r { v12.2s }, [x2], x3 + ld1r { v12.4s }, [x2] + ld1r { v12.4s }, [x2], x3 + ld1r { v12.1d }, [x2] + ld1r { v12.1d }, [x2], x3 + ld1r { v12.2d }, [x2] + ld1r { v12.2d }, [x2], x3 + + ld1r { v12.8b }, [x2], #1 + ld1r { v12.16b }, [x2], #1 + ld1r { v12.4h }, [x2], #2 + ld1r { v12.8h }, [x2], #2 + ld1r { v12.2s }, [x2], #4 + ld1r { v12.4s }, [x2], #4 + ld1r { v12.1d }, [x2], #8 + ld1r { v12.2d }, [x2], #8 + ld2r { v3.8b, v4.8b }, [x2] + ld2r { v3.8b, v4.8b }, [x2], x3 + ld2r { v3.16b, v4.16b }, [x2] + ld2r { v3.16b, v4.16b }, [x2], x3 + ld2r { v3.4h, v4.4h }, [x2] + ld2r { v3.4h, v4.4h }, [x2], x3 + ld2r { v3.8h, v4.8h }, [x2] + ld2r { v3.8h, v4.8h }, [x2], x3 + ld2r { v3.2s, v4.2s }, [x2] + ld2r { v3.2s, v4.2s }, [x2], x3 + ld2r { v3.4s, v4.4s }, [x2] + ld2r { v3.4s, v4.4s }, [x2], x3 + ld2r { v3.1d, v4.1d }, [x2] + ld2r { v3.1d, v4.1d }, [x2], x3 + ld2r { v3.2d, v4.2d }, [x2] + ld2r { v3.2d, v4.2d }, [x2], x3 + + ld2r { v3.8b, v4.8b }, [x2], #2 + ld2r { v3.16b, v4.16b }, [x2], #2 + ld2r { v3.4h, v4.4h }, [x2], #4 + ld2r { v3.8h, v4.8h }, [x2], #4 + ld2r { v3.2s, v4.2s }, [x2], #8 + ld2r { v3.4s, v4.4s }, [x2], #8 + ld2r { v3.1d, v4.1d }, [x2], #16 + ld2r { v3.2d, v4.2d }, [x2], #16 + + ld3r { v2.8b, v3.8b, v4.8b }, [x2] + ld3r { v2.8b, v3.8b, v4.8b }, [x2], x3 + ld3r { v2.16b, v3.16b, v4.16b }, [x2] + ld3r { v2.16b, v3.16b, v4.16b }, [x2], x3 + ld3r { v2.4h, v3.4h, v4.4h }, [x2] + ld3r { v2.4h, v3.4h, v4.4h }, [x2], x3 + ld3r { v2.8h, v3.8h, v4.8h }, [x2] + ld3r { v2.8h, v3.8h, v4.8h }, [x2], x3 + ld3r { v2.2s, v3.2s, v4.2s }, [x2] + ld3r { v2.2s, v3.2s, v4.2s }, [x2], x3 + ld3r { v2.4s, v3.4s, v4.4s }, [x2] + ld3r { v2.4s, v3.4s, v4.4s }, [x2], x3 + ld3r { v2.1d, v3.1d, v4.1d }, [x2] + ld3r { v2.1d, v3.1d, v4.1d }, [x2], x3 + ld3r { v2.2d, v3.2d, v4.2d }, [x2] + ld3r { v2.2d, v3.2d, v4.2d }, [x2], x3 + + ld3r { v2.8b, v3.8b, v4.8b }, [x2], #3 + ld3r { v2.16b, v3.16b, v4.16b }, [x2], #3 + ld3r { v2.4h, v3.4h, v4.4h }, [x2], #6 + ld3r { v2.8h, v3.8h, v4.8h }, [x2], #6 + ld3r { v2.2s, v3.2s, v4.2s }, [x2], #12 + ld3r { v2.4s, v3.4s, v4.4s }, [x2], #12 + ld3r { v2.1d, v3.1d, v4.1d }, [x2], #24 + ld3r { v2.2d, v3.2d, v4.2d }, [x2], #24 + + ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2] + ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2], x3 + ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2] + ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2], x3 + ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2] + ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2], x3 + ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2] + ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2], x3 + ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2] + ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2], x3 + ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2] + ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2], x3 + ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2] + ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2], x3 + ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2] + ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2], x3 + + ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2], #4 + ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2], #4 + ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2], #8 + ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2], #8 + ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2], #16 + ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2], #16 + ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2], #32 + ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2], #32 + + ld1 { v6.b }[13], [x3] + ld1 { v6.h }[2], [x3] + ld1 { v6.s }[2], [x3] + ld1 { v6.d }[1], [x3] + ld1 { v6.b }[13], [x3], x5 + ld1 { v6.h }[2], [x3], x5 + ld1 { v6.s }[2], [x3], x5 + ld1 { v6.d }[1], [x3], x5 + ld1 { v6.b }[13], [x3], #1 + ld1 { v6.h }[2], [x3], #2 + ld1 { v6.s }[2], [x3], #4 + ld1 { v6.d }[1], [x3], #8 + + ld2 { v5.b, v6.b }[13], [x3] + ld2 { v5.h, v6.h }[2], [x3] + ld2 { v5.s, v6.s }[2], [x3] + ld2 { v5.d, v6.d }[1], [x3] + ld2 { v5.b, v6.b }[13], [x3], x5 + ld2 { v5.h, v6.h }[2], [x3], x5 + ld2 { v5.s, v6.s }[2], [x3], x5 + ld2 { v5.d, v6.d }[1], [x3], x5 + ld2 { v5.b, v6.b }[13], [x3], #2 + ld2 { v5.h, v6.h }[2], [x3], #4 + ld2 { v5.s, v6.s }[2], [x3], #8 + ld2 { v5.d, v6.d }[1], [x3], #16 + + ld3 { v7.b, v8.b, v9.b }[13], [x3] + ld3 { v7.h, v8.h, v9.h }[2], [x3] + ld3 { v7.s, v8.s, v9.s }[2], [x3] + ld3 { v7.d, v8.d, v9.d }[1], [x3] + ld3 { v7.b, v8.b, v9.b }[13], [x3], x5 + ld3 { v7.h, v8.h, v9.h }[2], [x3], x5 + ld3 { v7.s, v8.s, v9.s }[2], [x3], x5 + ld3 { v7.d, v8.d, v9.d }[1], [x3], x5 + ld3 { v7.b, v8.b, v9.b }[13], [x3], #3 + ld3 { v7.h, v8.h, v9.h }[2], [x3], #6 + ld3 { v7.s, v8.s, v9.s }[2], [x3], #12 + ld3 { v7.d, v8.d, v9.d }[1], [x3], #24 + + ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3] + ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3] + ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3] + ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3] + ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], x5 + ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], x5 + ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], x5 + ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], x5 + ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], #4 + ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], #8 + ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], #16 + ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], #32 + + st1 { v6.b }[13], [x3] + st1 { v6.h }[2], [x3] + st1 { v6.s }[2], [x3] + st1 { v6.d }[1], [x3] + st1 { v6.b }[13], [x3], x5 + st1 { v6.h }[2], [x3], x5 + st1 { v6.s }[2], [x3], x5 + st1 { v6.d }[1], [x3], x5 + st1 { v6.b }[13], [x3], #1 + st1 { v6.h }[2], [x3], #2 + st1 { v6.s }[2], [x3], #4 + st1 { v6.d }[1], [x3], #8 + + + st2 { v5.b, v6.b }[13], [x3] + st2 { v5.h, v6.h }[2], [x3] + st2 { v5.s, v6.s }[2], [x3] + st2 { v5.d, v6.d }[1], [x3] + st2 { v5.b, v6.b }[13], [x3], x5 + st2 { v5.h, v6.h }[2], [x3], x5 + st2 { v5.s, v6.s }[2], [x3], x5 + st2 { v5.d, v6.d }[1], [x3], x5 + st2 { v5.b, v6.b }[13], [x3], #2 + st2 { v5.h, v6.h }[2], [x3], #4 + st2 { v5.s, v6.s }[2], [x3], #8 + st2 { v5.d, v6.d }[1], [x3], #16 + + st3 { v7.b, v8.b, v9.b }[13], [x3] + st3 { v7.h, v8.h, v9.h }[2], [x3] + st3 { v7.s, v8.s, v9.s }[2], [x3] + st3 { v7.d, v8.d, v9.d }[1], [x3] + st3 { v7.b, v8.b, v9.b }[13], [x3], x5 + st3 { v7.h, v8.h, v9.h }[2], [x3], x5 + st3 { v7.s, v8.s, v9.s }[2], [x3], x5 + st3 { v7.d, v8.d, v9.d }[1], [x3], x5 + st3 { v7.b, v8.b, v9.b }[13], [x3], #3 + st3 { v7.h, v8.h, v9.h }[2], [x3], #6 + st3 { v7.s, v8.s, v9.s }[2], [x3], #12 + st3 { v7.d, v8.d, v9.d }[1], [x3], #24 + + st4 { v7.b, v8.b, v9.b, v10.b }[13], [x3] + st4 { v7.h, v8.h, v9.h, v10.h }[2], [x3] + st4 { v7.s, v8.s, v9.s, v10.s }[2], [x3] + st4 { v7.d, v8.d, v9.d, v10.d }[1], [x3] + st4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], x5 + st4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], x5 + st4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], x5 + st4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], x5 + st4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], #4 + st4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], #8 + st4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], #16 + st4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], #32 + +; CHECK: ld1.8b { v1 }, [x1] ; encoding: [0x21,0x70,0x40,0x0c] +; CHECK: ld1.8b { v2, v3 }, [x1] ; encoding: [0x22,0xa0,0x40,0x0c] +; CHECK: ld1.8b { v3, v4, v5 }, [x1] ; encoding: [0x23,0x60,0x40,0x0c] +; CHECK: ld1.8b { v4, v5, v6, v7 }, [x1] ; encoding: [0x24,0x20,0x40,0x0c] +; CHECK: ld1.16b { v1 }, [x1] ; encoding: [0x21,0x70,0x40,0x4c] +; CHECK: ld1.16b { v2, v3 }, [x1] ; encoding: [0x22,0xa0,0x40,0x4c] +; CHECK: ld1.16b { v3, v4, v5 }, [x1] ; encoding: [0x23,0x60,0x40,0x4c] +; CHECK: ld1.16b { v4, v5, v6, v7 }, [x1] ; encoding: [0x24,0x20,0x40,0x4c] +; CHECK: ld1.4h { v1 }, [x1] ; encoding: [0x21,0x74,0x40,0x0c] +; CHECK: ld1.4h { v2, v3 }, [x1] ; encoding: [0x22,0xa4,0x40,0x0c] +; CHECK: ld1.4h { v3, v4, v5 }, [x1] ; encoding: [0x23,0x64,0x40,0x0c] +; CHECK: ld1.4h { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x24,0x40,0x0c] +; CHECK: ld1.8h { v1 }, [x1] ; encoding: [0x21,0x74,0x40,0x4c] +; CHECK: ld1.8h { v2, v3 }, [x1] ; encoding: [0x22,0xa4,0x40,0x4c] +; CHECK: ld1.8h { v3, v4, v5 }, [x1] ; encoding: [0x23,0x64,0x40,0x4c] +; CHECK: ld1.8h { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x24,0x40,0x4c] +; CHECK: ld1.2s { v1 }, [x1] ; encoding: [0x21,0x78,0x40,0x0c] +; CHECK: ld1.2s { v2, v3 }, [x1] ; encoding: [0x22,0xa8,0x40,0x0c] +; CHECK: ld1.2s { v3, v4, v5 }, [x1] ; encoding: [0x23,0x68,0x40,0x0c] +; CHECK: ld1.2s { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x28,0x40,0x0c] +; CHECK: ld1.4s { v1 }, [x1] ; encoding: [0x21,0x78,0x40,0x4c] +; CHECK: ld1.4s { v2, v3 }, [x1] ; encoding: [0x22,0xa8,0x40,0x4c] +; CHECK: ld1.4s { v3, v4, v5 }, [x1] ; encoding: [0x23,0x68,0x40,0x4c] +; CHECK: ld1.4s { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x28,0x40,0x4c] +; CHECK: ld1.1d { v1 }, [x1] ; encoding: [0x21,0x7c,0x40,0x0c] +; CHECK: ld1.1d { v2, v3 }, [x1] ; encoding: [0x22,0xac,0x40,0x0c] +; CHECK: ld1.1d { v3, v4, v5 }, [x1] ; encoding: [0x23,0x6c,0x40,0x0c] +; CHECK: ld1.1d { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x2c,0x40,0x0c] +; CHECK: ld1.2d { v1 }, [x1] ; encoding: [0x21,0x7c,0x40,0x4c] +; CHECK: ld1.2d { v2, v3 }, [x1] ; encoding: [0x22,0xac,0x40,0x4c] +; CHECK: ld1.2d { v3, v4, v5 }, [x1] ; encoding: [0x23,0x6c,0x40,0x4c] +; CHECK: ld1.2d { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x2c,0x40,0x4c] +; CHECK: st1.8b { v1 }, [x1] ; encoding: [0x21,0x70,0x00,0x0c] +; CHECK: st1.8b { v2, v3 }, [x1] ; encoding: [0x22,0xa0,0x00,0x0c] +; CHECK: st1.8b { v3, v4, v5 }, [x1] ; encoding: [0x23,0x60,0x00,0x0c] +; CHECK: st1.8b { v4, v5, v6, v7 }, [x1] ; encoding: [0x24,0x20,0x00,0x0c] +; CHECK: st1.16b { v1 }, [x1] ; encoding: [0x21,0x70,0x00,0x4c] +; CHECK: st1.16b { v2, v3 }, [x1] ; encoding: [0x22,0xa0,0x00,0x4c] +; CHECK: st1.16b { v3, v4, v5 }, [x1] ; encoding: [0x23,0x60,0x00,0x4c] +; CHECK: st1.16b { v4, v5, v6, v7 }, [x1] ; encoding: [0x24,0x20,0x00,0x4c] +; CHECK: st1.4h { v1 }, [x1] ; encoding: [0x21,0x74,0x00,0x0c] +; CHECK: st1.4h { v2, v3 }, [x1] ; encoding: [0x22,0xa4,0x00,0x0c] +; CHECK: st1.4h { v3, v4, v5 }, [x1] ; encoding: [0x23,0x64,0x00,0x0c] +; CHECK: st1.4h { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x24,0x00,0x0c] +; CHECK: st1.8h { v1 }, [x1] ; encoding: [0x21,0x74,0x00,0x4c] +; CHECK: st1.8h { v2, v3 }, [x1] ; encoding: [0x22,0xa4,0x00,0x4c] +; CHECK: st1.8h { v3, v4, v5 }, [x1] ; encoding: [0x23,0x64,0x00,0x4c] +; CHECK: st1.8h { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x24,0x00,0x4c] +; CHECK: st1.2s { v1 }, [x1] ; encoding: [0x21,0x78,0x00,0x0c] +; CHECK: st1.2s { v2, v3 }, [x1] ; encoding: [0x22,0xa8,0x00,0x0c] +; CHECK: st1.2s { v3, v4, v5 }, [x1] ; encoding: [0x23,0x68,0x00,0x0c] +; CHECK: st1.2s { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x28,0x00,0x0c] +; CHECK: st1.4s { v1 }, [x1] ; encoding: [0x21,0x78,0x00,0x4c] +; CHECK: st1.4s { v2, v3 }, [x1] ; encoding: [0x22,0xa8,0x00,0x4c] +; CHECK: st1.4s { v3, v4, v5 }, [x1] ; encoding: [0x23,0x68,0x00,0x4c] +; CHECK: st1.4s { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x28,0x00,0x4c] +; CHECK: st1.1d { v1 }, [x1] ; encoding: [0x21,0x7c,0x00,0x0c] +; CHECK: st1.1d { v2, v3 }, [x1] ; encoding: [0x22,0xac,0x00,0x0c] +; CHECK: st1.1d { v3, v4, v5 }, [x1] ; encoding: [0x23,0x6c,0x00,0x0c] +; CHECK: st1.1d { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x2c,0x00,0x0c] +; CHECK: st1.2d { v1 }, [x1] ; encoding: [0x21,0x7c,0x00,0x4c] +; CHECK: st1.2d { v2, v3 }, [x1] ; encoding: [0x22,0xac,0x00,0x4c] +; CHECK: st1.2d { v3, v4, v5 }, [x1] ; encoding: [0x23,0x6c,0x00,0x4c] +; CHECK: st1.2d { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x2c,0x00,0x4c] +; CHECK: ld2.8b { v3, v4 }, [x19] ; encoding: [0x63,0x82,0x40,0x0c] +; CHECK: ld2.16b { v3, v4 }, [x19] ; encoding: [0x63,0x82,0x40,0x4c] +; CHECK: ld2.4h { v3, v4 }, [x19] ; encoding: [0x63,0x86,0x40,0x0c] +; CHECK: ld2.8h { v3, v4 }, [x19] ; encoding: [0x63,0x86,0x40,0x4c] +; CHECK: ld2.2s { v3, v4 }, [x19] ; encoding: [0x63,0x8a,0x40,0x0c] +; CHECK: ld2.4s { v3, v4 }, [x19] ; encoding: [0x63,0x8a,0x40,0x4c] +; CHECK: ld2.2d { v3, v4 }, [x19] ; encoding: [0x63,0x8e,0x40,0x4c] +; CHECK: st2.8b { v3, v4 }, [x19] ; encoding: [0x63,0x82,0x00,0x0c] +; CHECK: st2.16b { v3, v4 }, [x19] ; encoding: [0x63,0x82,0x00,0x4c] +; CHECK: st2.4h { v3, v4 }, [x19] ; encoding: [0x63,0x86,0x00,0x0c] +; CHECK: st2.8h { v3, v4 }, [x19] ; encoding: [0x63,0x86,0x00,0x4c] +; CHECK: st2.2s { v3, v4 }, [x19] ; encoding: [0x63,0x8a,0x00,0x0c] +; CHECK: st2.4s { v3, v4 }, [x19] ; encoding: [0x63,0x8a,0x00,0x4c] +; CHECK: st2.2d { v3, v4 }, [x19] ; encoding: [0x63,0x8e,0x00,0x4c] +; CHECK: ld3.8b { v2, v3, v4 }, [x19] ; encoding: [0x62,0x42,0x40,0x0c] +; CHECK: ld3.16b { v2, v3, v4 }, [x19] ; encoding: [0x62,0x42,0x40,0x4c] +; CHECK: ld3.4h { v2, v3, v4 }, [x19] ; encoding: [0x62,0x46,0x40,0x0c] +; CHECK: ld3.8h { v2, v3, v4 }, [x19] ; encoding: [0x62,0x46,0x40,0x4c] +; CHECK: ld3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x40,0x0c] +; CHECK: ld3.4s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x40,0x4c] +; CHECK: ld3.2d { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4e,0x40,0x4c] +; CHECK: st3.8b { v2, v3, v4 }, [x19] ; encoding: [0x62,0x42,0x00,0x0c] +; CHECK: st3.16b { v2, v3, v4 }, [x19] ; encoding: [0x62,0x42,0x00,0x4c] +; CHECK: st3.4h { v2, v3, v4 }, [x19] ; encoding: [0x62,0x46,0x00,0x0c] +; CHECK: st3.8h { v2, v3, v4 }, [x19] ; encoding: [0x62,0x46,0x00,0x4c] +; CHECK: st3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x00,0x0c] +; CHECK: st3.4s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x00,0x4c] +; CHECK: st3.2d { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4e,0x00,0x4c] +; CHECK: ld4.8b { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x02,0x40,0x0c] +; CHECK: ld4.16b { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x02,0x40,0x4c] +; CHECK: ld4.4h { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x06,0x40,0x0c] +; CHECK: ld4.8h { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x06,0x40,0x4c] +; CHECK: ld4.2s { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0a,0x40,0x0c] +; CHECK: ld4.4s { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0a,0x40,0x4c] +; CHECK: ld4.2d { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0e,0x40,0x4c] +; CHECK: st4.8b { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x02,0x00,0x0c] +; CHECK: st4.16b { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x02,0x00,0x4c] +; CHECK: st4.4h { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x06,0x00,0x0c] +; CHECK: st4.8h { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x06,0x00,0x4c] +; CHECK: st4.2s { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0a,0x00,0x0c] +; CHECK: st4.4s { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0a,0x00,0x4c] +; CHECK: st4.2d { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0e,0x00,0x4c] +; CHECK: ld1.8b { v1 }, [x1], x15 ; encoding: [0x21,0x70,0xcf,0x0c] +; CHECK: ld1.8b { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa0,0xcf,0x0c] +; CHECK: ld1.8b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x60,0xcf,0x0c] +; CHECK: ld1.8b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x20,0xcf,0x0c] +; CHECK: ld1.16b { v1 }, [x1], x15 ; encoding: [0x21,0x70,0xcf,0x4c] +; CHECK: ld1.16b { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa0,0xcf,0x4c] +; CHECK: ld1.16b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x60,0xcf,0x4c] +; CHECK: ld1.16b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x20,0xcf,0x4c] +; CHECK: ld1.4h { v1 }, [x1], x15 ; encoding: [0x21,0x74,0xcf,0x0c] +; CHECK: ld1.4h { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa4,0xcf,0x0c] +; CHECK: ld1.4h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x64,0xcf,0x0c] +; CHECK: ld1.4h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x24,0xcf,0x0c] +; CHECK: ld1.8h { v1 }, [x1], x15 ; encoding: [0x21,0x74,0xcf,0x4c] +; CHECK: ld1.8h { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa4,0xcf,0x4c] +; CHECK: ld1.8h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x64,0xcf,0x4c] +; CHECK: ld1.8h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x24,0xcf,0x4c] +; CHECK: ld1.2s { v1 }, [x1], x15 ; encoding: [0x21,0x78,0xcf,0x0c] +; CHECK: ld1.2s { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa8,0xcf,0x0c] +; CHECK: ld1.2s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x68,0xcf,0x0c] +; CHECK: ld1.2s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x28,0xcf,0x0c] +; CHECK: ld1.4s { v1 }, [x1], x15 ; encoding: [0x21,0x78,0xcf,0x4c] +; CHECK: ld1.4s { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa8,0xcf,0x4c] +; CHECK: ld1.4s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x68,0xcf,0x4c] +; CHECK: ld1.4s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x28,0xcf,0x4c] +; CHECK: ld1.1d { v1 }, [x1], x15 ; encoding: [0x21,0x7c,0xcf,0x0c] +; CHECK: ld1.1d { v2, v3 }, [x1], x15 ; encoding: [0x22,0xac,0xcf,0x0c] +; CHECK: ld1.1d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x6c,0xcf,0x0c] +; CHECK: ld1.1d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x2c,0xcf,0x0c] +; CHECK: ld1.2d { v1 }, [x1], x15 ; encoding: [0x21,0x7c,0xcf,0x4c] +; CHECK: ld1.2d { v2, v3 }, [x1], x15 ; encoding: [0x22,0xac,0xcf,0x4c] +; CHECK: ld1.2d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x6c,0xcf,0x4c] +; CHECK: ld1.2d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x2c,0xcf,0x4c] +; CHECK: st1.8b { v1 }, [x1], x15 ; encoding: [0x21,0x70,0x8f,0x0c] +; CHECK: st1.8b { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa0,0x8f,0x0c] +; CHECK: st1.8b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x60,0x8f,0x0c] +; CHECK: st1.8b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x20,0x8f,0x0c] +; CHECK: st1.16b { v1 }, [x1], x15 ; encoding: [0x21,0x70,0x8f,0x4c] +; CHECK: st1.16b { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa0,0x8f,0x4c] +; CHECK: st1.16b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x60,0x8f,0x4c] +; CHECK: st1.16b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x20,0x8f,0x4c] +; CHECK: st1.4h { v1 }, [x1], x15 ; encoding: [0x21,0x74,0x8f,0x0c] +; CHECK: st1.4h { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa4,0x8f,0x0c] +; CHECK: st1.4h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x64,0x8f,0x0c] +; CHECK: st1.4h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x24,0x8f,0x0c] +; CHECK: st1.8h { v1 }, [x1], x15 ; encoding: [0x21,0x74,0x8f,0x4c] +; CHECK: st1.8h { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa4,0x8f,0x4c] +; CHECK: st1.8h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x64,0x8f,0x4c] +; CHECK: st1.8h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x24,0x8f,0x4c] +; CHECK: st1.2s { v1 }, [x1], x15 ; encoding: [0x21,0x78,0x8f,0x0c] +; CHECK: st1.2s { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa8,0x8f,0x0c] +; CHECK: st1.2s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x68,0x8f,0x0c] +; CHECK: st1.2s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x28,0x8f,0x0c] +; CHECK: st1.4s { v1 }, [x1], x15 ; encoding: [0x21,0x78,0x8f,0x4c] +; CHECK: st1.4s { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa8,0x8f,0x4c] +; CHECK: st1.4s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x68,0x8f,0x4c] +; CHECK: st1.4s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x28,0x8f,0x4c] +; CHECK: st1.1d { v1 }, [x1], x15 ; encoding: [0x21,0x7c,0x8f,0x0c] +; CHECK: st1.1d { v2, v3 }, [x1], x15 ; encoding: [0x22,0xac,0x8f,0x0c] +; CHECK: st1.1d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x6c,0x8f,0x0c] +; CHECK: st1.1d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x2c,0x8f,0x0c] +; CHECK: st1.2d { v1 }, [x1], x15 ; encoding: [0x21,0x7c,0x8f,0x4c] +; CHECK: st1.2d { v2, v3 }, [x1], x15 ; encoding: [0x22,0xac,0x8f,0x4c] +; CHECK: st1.2d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x6c,0x8f,0x4c] +; CHECK: st1.2d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x2c,0x8f,0x4c] +; CHECK: ld1.8b { v1 }, [x1], #8 ; encoding: [0x21,0x70,0xdf,0x0c] +; CHECK: ld1.8b { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa0,0xdf,0x0c] +; CHECK: ld1.8b { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x60,0xdf,0x0c] +; CHECK: ld1.8b { v4, v5, v6, v7 }, [x1], #32 ; encoding: [0x24,0x20,0xdf,0x0c] +; CHECK: ld1.16b { v1 }, [x1], #16 ; encoding: [0x21,0x70,0xdf,0x4c] +; CHECK: ld1.16b { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa0,0xdf,0x4c] +; CHECK: ld1.16b { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x60,0xdf,0x4c] +; CHECK: ld1.16b { v4, v5, v6, v7 }, [x1], #64 ; encoding: [0x24,0x20,0xdf,0x4c] +; CHECK: ld1.4h { v1 }, [x1], #8 ; encoding: [0x21,0x74,0xdf,0x0c] +; CHECK: ld1.4h { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa4,0xdf,0x0c] +; CHECK: ld1.4h { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x64,0xdf,0x0c] +; CHECK: ld1.4h { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x24,0xdf,0x0c] +; CHECK: ld1.8h { v1 }, [x1], #16 ; encoding: [0x21,0x74,0xdf,0x4c] +; CHECK: ld1.8h { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa4,0xdf,0x4c] +; CHECK: ld1.8h { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x64,0xdf,0x4c] +; CHECK: ld1.8h { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x24,0xdf,0x4c] +; CHECK: ld1.2s { v1 }, [x1], #8 ; encoding: [0x21,0x78,0xdf,0x0c] +; CHECK: ld1.2s { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa8,0xdf,0x0c] +; CHECK: ld1.2s { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x68,0xdf,0x0c] +; CHECK: ld1.2s { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x28,0xdf,0x0c] +; CHECK: ld1.4s { v1 }, [x1], #16 ; encoding: [0x21,0x78,0xdf,0x4c] +; CHECK: ld1.4s { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa8,0xdf,0x4c] +; CHECK: ld1.4s { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x68,0xdf,0x4c] +; CHECK: ld1.4s { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x28,0xdf,0x4c] +; CHECK: ld1.1d { v1 }, [x1], #8 ; encoding: [0x21,0x7c,0xdf,0x0c] +; CHECK: ld1.1d { v2, v3 }, [x1], #16 ; encoding: [0x22,0xac,0xdf,0x0c] +; CHECK: ld1.1d { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x6c,0xdf,0x0c] +; CHECK: ld1.1d { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x2c,0xdf,0x0c] +; CHECK: ld1.2d { v1 }, [x1], #16 ; encoding: [0x21,0x7c,0xdf,0x4c] +; CHECK: ld1.2d { v2, v3 }, [x1], #32 ; encoding: [0x22,0xac,0xdf,0x4c] +; CHECK: ld1.2d { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x6c,0xdf,0x4c] +; CHECK: ld1.2d { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x2c,0xdf,0x4c] +; CHECK: st1.8b { v1 }, [x1], #8 ; encoding: [0x21,0x70,0x9f,0x0c] +; CHECK: st1.8b { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa0,0x9f,0x0c] +; CHECK: st1.8b { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x60,0x9f,0x0c] +; CHECK: st1.8b { v4, v5, v6, v7 }, [x1], #32 ; encoding: [0x24,0x20,0x9f,0x0c] +; CHECK: st1.16b { v1 }, [x1], #16 ; encoding: [0x21,0x70,0x9f,0x4c] +; CHECK: st1.16b { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa0,0x9f,0x4c] +; CHECK: st1.16b { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x60,0x9f,0x4c] +; CHECK: st1.16b { v4, v5, v6, v7 }, [x1], #64 ; encoding: [0x24,0x20,0x9f,0x4c] +; CHECK: st1.4h { v1 }, [x1], #8 ; encoding: [0x21,0x74,0x9f,0x0c] +; CHECK: st1.4h { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa4,0x9f,0x0c] +; CHECK: st1.4h { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x64,0x9f,0x0c] +; CHECK: st1.4h { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x24,0x9f,0x0c] +; CHECK: st1.8h { v1 }, [x1], #16 ; encoding: [0x21,0x74,0x9f,0x4c] +; CHECK: st1.8h { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa4,0x9f,0x4c] +; CHECK: st1.8h { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x64,0x9f,0x4c] +; CHECK: st1.8h { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x24,0x9f,0x4c] +; CHECK: st1.2s { v1 }, [x1], #8 ; encoding: [0x21,0x78,0x9f,0x0c] +; CHECK: st1.2s { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa8,0x9f,0x0c] +; CHECK: st1.2s { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x68,0x9f,0x0c] +; CHECK: st1.2s { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x28,0x9f,0x0c] +; CHECK: st1.4s { v1 }, [x1], #16 ; encoding: [0x21,0x78,0x9f,0x4c] +; CHECK: st1.4s { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa8,0x9f,0x4c] +; CHECK: st1.4s { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x68,0x9f,0x4c] +; CHECK: st1.4s { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x28,0x9f,0x4c] +; CHECK: st1.1d { v1 }, [x1], #8 ; encoding: [0x21,0x7c,0x9f,0x0c] +; CHECK: st1.1d { v2, v3 }, [x1], #16 ; encoding: [0x22,0xac,0x9f,0x0c] +; CHECK: st1.1d { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x6c,0x9f,0x0c] +; CHECK: st1.1d { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x2c,0x9f,0x0c] +; CHECK: st1.2d { v1 }, [x1], #16 ; encoding: [0x21,0x7c,0x9f,0x4c] +; CHECK: st1.2d { v2, v3 }, [x1], #32 ; encoding: [0x22,0xac,0x9f,0x4c] +; CHECK: st1.2d { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x6c,0x9f,0x4c] +; CHECK: st1.2d { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x2c,0x9f,0x4c] +; CHECK: ld2.8b { v2, v3 }, [x1], x15 ; encoding: [0x22,0x80,0xcf,0x0c] +; CHECK: ld2.16b { v2, v3 }, [x1], x15 ; encoding: [0x22,0x80,0xcf,0x4c] +; CHECK: ld2.4h { v2, v3 }, [x1], x15 ; encoding: [0x22,0x84,0xcf,0x0c] +; CHECK: ld2.8h { v2, v3 }, [x1], x15 ; encoding: [0x22,0x84,0xcf,0x4c] +; CHECK: ld2.2s { v2, v3 }, [x1], x15 ; encoding: [0x22,0x88,0xcf,0x0c] +; CHECK: ld2.4s { v2, v3 }, [x1], x15 ; encoding: [0x22,0x88,0xcf,0x4c] +; CHECK: ld2.2d { v2, v3 }, [x1], x15 ; encoding: [0x22,0x8c,0xcf,0x4c] +; CHECK: st2.8b { v2, v3 }, [x1], x15 ; encoding: [0x22,0x80,0x8f,0x0c] +; CHECK: st2.16b { v2, v3 }, [x1], x15 ; encoding: [0x22,0x80,0x8f,0x4c] +; CHECK: st2.4h { v2, v3 }, [x1], x15 ; encoding: [0x22,0x84,0x8f,0x0c] +; CHECK: st2.8h { v2, v3 }, [x1], x15 ; encoding: [0x22,0x84,0x8f,0x4c] +; CHECK: st2.2s { v2, v3 }, [x1], x15 ; encoding: [0x22,0x88,0x8f,0x0c] +; CHECK: st2.4s { v2, v3 }, [x1], x15 ; encoding: [0x22,0x88,0x8f,0x4c] +; CHECK: st2.2d { v2, v3 }, [x1], x15 ; encoding: [0x22,0x8c,0x8f,0x4c] +; CHECK: ld2.8b { v2, v3 }, [x1], #16 ; encoding: [0x22,0x80,0xdf,0x0c] +; CHECK: ld2.16b { v2, v3 }, [x1], #32 ; encoding: [0x22,0x80,0xdf,0x4c] +; CHECK: ld2.4h { v2, v3 }, [x1], #16 ; encoding: [0x22,0x84,0xdf,0x0c] +; CHECK: ld2.8h { v2, v3 }, [x1], #32 ; encoding: [0x22,0x84,0xdf,0x4c] +; CHECK: ld2.2s { v2, v3 }, [x1], #16 ; encoding: [0x22,0x88,0xdf,0x0c] +; CHECK: ld2.4s { v2, v3 }, [x1], #32 ; encoding: [0x22,0x88,0xdf,0x4c] +; CHECK: ld2.2d { v2, v3 }, [x1], #32 ; encoding: [0x22,0x8c,0xdf,0x4c] +; CHECK: st2.8b { v2, v3 }, [x1], #16 ; encoding: [0x22,0x80,0x9f,0x0c] +; CHECK: st2.16b { v2, v3 }, [x1], #32 ; encoding: [0x22,0x80,0x9f,0x4c] +; CHECK: st2.4h { v2, v3 }, [x1], #16 ; encoding: [0x22,0x84,0x9f,0x0c] +; CHECK: st2.8h { v2, v3 }, [x1], #32 ; encoding: [0x22,0x84,0x9f,0x4c] +; CHECK: st2.2s { v2, v3 }, [x1], #16 ; encoding: [0x22,0x88,0x9f,0x0c] +; CHECK: st2.4s { v2, v3 }, [x1], #32 ; encoding: [0x22,0x88,0x9f,0x4c] +; CHECK: st2.2d { v2, v3 }, [x1], #32 ; encoding: [0x22,0x8c,0x9f,0x4c] +; CHECK: ld3.8b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x40,0xcf,0x0c] +; CHECK: ld3.16b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x40,0xcf,0x4c] +; CHECK: ld3.4h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x44,0xcf,0x0c] +; CHECK: ld3.8h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x44,0xcf,0x4c] +; CHECK: ld3.2s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x48,0xcf,0x0c] +; CHECK: ld3.4s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x48,0xcf,0x4c] +; CHECK: ld3.2d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x4c,0xcf,0x4c] +; CHECK: st3.8b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x40,0x8f,0x0c] +; CHECK: st3.16b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x40,0x8f,0x4c] +; CHECK: st3.4h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x44,0x8f,0x0c] +; CHECK: st3.8h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x44,0x8f,0x4c] +; CHECK: st3.2s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x48,0x8f,0x0c] +; CHECK: st3.4s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x48,0x8f,0x4c] +; CHECK: st3.2d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x4c,0x8f,0x4c] +; CHECK: ld3.8b { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x40,0xdf,0x0c] +; CHECK: ld3.16b { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x40,0xdf,0x4c] +; CHECK: ld3.4h { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x44,0xdf,0x0c] +; CHECK: ld3.8h { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x44,0xdf,0x4c] +; CHECK: ld3.2s { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x48,0xdf,0x0c] +; CHECK: ld3.4s { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x48,0xdf,0x4c] +; CHECK: ld3.2d { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x4c,0xdf,0x4c] +; CHECK: st3.8b { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x40,0x9f,0x0c] +; CHECK: st3.16b { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x40,0x9f,0x4c] +; CHECK: st3.4h { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x44,0x9f,0x0c] +; CHECK: st3.8h { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x44,0x9f,0x4c] +; CHECK: st3.2s { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x48,0x9f,0x0c] +; CHECK: st3.4s { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x48,0x9f,0x4c] +; CHECK: st3.2d { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x4c,0x9f,0x4c] +; CHECK: ld4.8b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x00,0xcf,0x0c] +; CHECK: ld4.16b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x00,0xcf,0x4c] +; CHECK: ld4.4h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x04,0xcf,0x0c] +; CHECK: ld4.8h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x04,0xcf,0x4c] +; CHECK: ld4.2s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x08,0xcf,0x0c] +; CHECK: ld4.4s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x08,0xcf,0x4c] +; CHECK: ld4.2d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x0c,0xcf,0x4c] +; CHECK: st4.8b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x00,0x8f,0x0c] +; CHECK: st4.16b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x00,0x8f,0x4c] +; CHECK: st4.4h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x04,0x8f,0x0c] +; CHECK: st4.8h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x04,0x8f,0x4c] +; CHECK: st4.2s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x08,0x8f,0x0c] +; CHECK: st4.4s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x08,0x8f,0x4c] +; CHECK: st4.2d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x0c,0x8f,0x4c] +; CHECK: ld4.8b { v4, v5, v6, v7 }, [x1], #32 ; encoding: [0x24,0x00,0xdf,0x0c] +; CHECK: ld4.16b { v4, v5, v6, v7 }, [x1], #64 ; encoding: [0x24,0x00,0xdf,0x4c] +; CHECK: ld4.4h { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x04,0xdf,0x0c] +; CHECK: ld4.8h { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x04,0xdf,0x4c] +; CHECK: ld4.2s { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x08,0xdf,0x0c] +; CHECK: ld4.4s { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x08,0xdf,0x4c] +; CHECK: ld4.2d { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x0c,0xdf,0x4c] +; CHECK: st4.8b { v4, v5, v6, v7 }, [x1], #32 ; encoding: [0x24,0x00,0x9f,0x0c] +; CHECK: st4.16b { v4, v5, v6, v7 }, [x1], #64 ; encoding: [0x24,0x00,0x9f,0x4c] +; CHECK: st4.4h { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x04,0x9f,0x0c] +; CHECK: st4.8h { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x04,0x9f,0x4c] +; CHECK: st4.2s { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x08,0x9f,0x0c] +; CHECK: st4.4s { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x08,0x9f,0x4c] +; CHECK: st4.2d { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x0c,0x9f,0x4c] +; CHECK: ld1r.8b { v12 }, [x2] ; encoding: [0x4c,0xc0,0x40,0x0d] +; CHECK: ld1r.8b { v12 }, [x2], x3 ; encoding: [0x4c,0xc0,0xc3,0x0d] +; CHECK: ld1r.16b { v12 }, [x2] ; encoding: [0x4c,0xc0,0x40,0x4d] +; CHECK: ld1r.16b { v12 }, [x2], x3 ; encoding: [0x4c,0xc0,0xc3,0x4d] +; CHECK: ld1r.4h { v12 }, [x2] ; encoding: [0x4c,0xc4,0x40,0x0d] +; CHECK: ld1r.4h { v12 }, [x2], x3 ; encoding: [0x4c,0xc4,0xc3,0x0d] +; CHECK: ld1r.8h { v12 }, [x2] ; encoding: [0x4c,0xc4,0x40,0x4d] +; CHECK: ld1r.8h { v12 }, [x2], x3 ; encoding: [0x4c,0xc4,0xc3,0x4d] +; CHECK: ld1r.2s { v12 }, [x2] ; encoding: [0x4c,0xc8,0x40,0x0d] +; CHECK: ld1r.2s { v12 }, [x2], x3 ; encoding: [0x4c,0xc8,0xc3,0x0d] +; CHECK: ld1r.4s { v12 }, [x2] ; encoding: [0x4c,0xc8,0x40,0x4d] +; CHECK: ld1r.4s { v12 }, [x2], x3 ; encoding: [0x4c,0xc8,0xc3,0x4d] +; CHECK: ld1r.1d { v12 }, [x2] ; encoding: [0x4c,0xcc,0x40,0x0d] +; CHECK: ld1r.1d { v12 }, [x2], x3 ; encoding: [0x4c,0xcc,0xc3,0x0d] +; CHECK: ld1r.2d { v12 }, [x2] ; encoding: [0x4c,0xcc,0x40,0x4d] +; CHECK: ld1r.2d { v12 }, [x2], x3 ; encoding: [0x4c,0xcc,0xc3,0x4d] +; CHECK: ld1r.8b { v12 }, [x2], #1 ; encoding: [0x4c,0xc0,0xdf,0x0d] +; CHECK: ld1r.16b { v12 }, [x2], #1 ; encoding: [0x4c,0xc0,0xdf,0x4d] +; CHECK: ld1r.4h { v12 }, [x2], #2 ; encoding: [0x4c,0xc4,0xdf,0x0d] +; CHECK: ld1r.8h { v12 }, [x2], #2 ; encoding: [0x4c,0xc4,0xdf,0x4d] +; CHECK: ld1r.2s { v12 }, [x2], #4 ; encoding: [0x4c,0xc8,0xdf,0x0d] +; CHECK: ld1r.4s { v12 }, [x2], #4 ; encoding: [0x4c,0xc8,0xdf,0x4d] +; CHECK: ld1r.1d { v12 }, [x2], #8 ; encoding: [0x4c,0xcc,0xdf,0x0d] +; CHECK: ld1r.2d { v12 }, [x2], #8 ; encoding: [0x4c,0xcc,0xdf,0x4d] +; CHECK: ld2r.8b { v3, v4 }, [x2] ; encoding: [0x43,0xc0,0x60,0x0d] +; CHECK: ld2r.8b { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc0,0xe3,0x0d] +; CHECK: ld2r.16b { v3, v4 }, [x2] ; encoding: [0x43,0xc0,0x60,0x4d] +; CHECK: ld2r.16b { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc0,0xe3,0x4d] +; CHECK: ld2r.4h { v3, v4 }, [x2] ; encoding: [0x43,0xc4,0x60,0x0d] +; CHECK: ld2r.4h { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc4,0xe3,0x0d] +; CHECK: ld2r.8h { v3, v4 }, [x2] ; encoding: [0x43,0xc4,0x60,0x4d] +; CHECK: ld2r.8h { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc4,0xe3,0x4d] +; CHECK: ld2r.2s { v3, v4 }, [x2] ; encoding: [0x43,0xc8,0x60,0x0d] +; CHECK: ld2r.2s { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc8,0xe3,0x0d] +; CHECK: ld2r.4s { v3, v4 }, [x2] ; encoding: [0x43,0xc8,0x60,0x4d] +; CHECK: ld2r.4s { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc8,0xe3,0x4d] +; CHECK: ld2r.1d { v3, v4 }, [x2] ; encoding: [0x43,0xcc,0x60,0x0d] +; CHECK: ld2r.1d { v3, v4 }, [x2], x3 ; encoding: [0x43,0xcc,0xe3,0x0d] +; CHECK: ld2r.2d { v3, v4 }, [x2] ; encoding: [0x43,0xcc,0x60,0x4d] +; CHECK: ld2r.2d { v3, v4 }, [x2], x3 ; encoding: [0x43,0xcc,0xe3,0x4d] +; CHECK: ld2r.8b { v3, v4 }, [x2], #2 ; encoding: [0x43,0xc0,0xff,0x0d] +; CHECK: ld2r.16b { v3, v4 }, [x2], #2 ; encoding: [0x43,0xc0,0xff,0x4d] +; CHECK: ld2r.4h { v3, v4 }, [x2], #4 ; encoding: [0x43,0xc4,0xff,0x0d] +; CHECK: ld2r.8h { v3, v4 }, [x2], #4 ; encoding: [0x43,0xc4,0xff,0x4d] +; CHECK: ld2r.2s { v3, v4 }, [x2], #8 ; encoding: [0x43,0xc8,0xff,0x0d] +; CHECK: ld2r.4s { v3, v4 }, [x2], #8 ; encoding: [0x43,0xc8,0xff,0x4d] +; CHECK: ld2r.1d { v3, v4 }, [x2], #16 ; encoding: [0x43,0xcc,0xff,0x0d] +; CHECK: ld2r.2d { v3, v4 }, [x2], #16 ; encoding: [0x43,0xcc,0xff,0x4d] +; CHECK: ld3r.8b { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe0,0x40,0x0d] +; CHECK: ld3r.8b { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe0,0xc3,0x0d] +; CHECK: ld3r.16b { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe0,0x40,0x4d] +; CHECK: ld3r.16b { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe0,0xc3,0x4d] +; CHECK: ld3r.4h { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe4,0x40,0x0d] +; CHECK: ld3r.4h { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe4,0xc3,0x0d] +; CHECK: ld3r.8h { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe4,0x40,0x4d] +; CHECK: ld3r.8h { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe4,0xc3,0x4d] +; CHECK: ld3r.2s { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe8,0x40,0x0d] +; CHECK: ld3r.2s { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe8,0xc3,0x0d] +; CHECK: ld3r.4s { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe8,0x40,0x4d] +; CHECK: ld3r.4s { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe8,0xc3,0x4d] +; CHECK: ld3r.1d { v2, v3, v4 }, [x2] ; encoding: [0x42,0xec,0x40,0x0d] +; CHECK: ld3r.1d { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xec,0xc3,0x0d] +; CHECK: ld3r.2d { v2, v3, v4 }, [x2] ; encoding: [0x42,0xec,0x40,0x4d] +; CHECK: ld3r.2d { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xec,0xc3,0x4d] +; CHECK: ld3r.8b { v2, v3, v4 }, [x2], #3 ; encoding: [0x42,0xe0,0xdf,0x0d] +; CHECK: ld3r.16b { v2, v3, v4 }, [x2], #3 ; encoding: [0x42,0xe0,0xdf,0x4d] +; CHECK: ld3r.4h { v2, v3, v4 }, [x2], #6 ; encoding: [0x42,0xe4,0xdf,0x0d] +; CHECK: ld3r.8h { v2, v3, v4 }, [x2], #6 ; encoding: [0x42,0xe4,0xdf,0x4d] +; CHECK: ld3r.2s { v2, v3, v4 }, [x2], #12 ; encoding: [0x42,0xe8,0xdf,0x0d] +; CHECK: ld3r.4s { v2, v3, v4 }, [x2], #12 ; encoding: [0x42,0xe8,0xdf,0x4d] +; CHECK: ld3r.1d { v2, v3, v4 }, [x2], #24 ; encoding: [0x42,0xec,0xdf,0x0d] +; CHECK: ld3r.2d { v2, v3, v4 }, [x2], #24 ; encoding: [0x42,0xec,0xdf,0x4d] +; CHECK: ld4r.8b { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe0,0x60,0x0d] +; CHECK: ld4r.8b { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe0,0xe3,0x0d] +; CHECK: ld4r.16b { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe0,0x60,0x4d] +; CHECK: ld4r.16b { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe0,0xe3,0x4d] +; CHECK: ld4r.4h { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe4,0x60,0x0d] +; CHECK: ld4r.4h { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe4,0xe3,0x0d] +; CHECK: ld4r.8h { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe4,0x60,0x4d] +; CHECK: ld4r.8h { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe4,0xe3,0x4d] +; CHECK: ld4r.2s { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe8,0x60,0x0d] +; CHECK: ld4r.2s { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe8,0xe3,0x0d] +; CHECK: ld4r.4s { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe8,0x60,0x4d] +; CHECK: ld4r.4s { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe8,0xe3,0x4d] +; CHECK: ld4r.1d { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xec,0x60,0x0d] +; CHECK: ld4r.1d { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xec,0xe3,0x0d] +; CHECK: ld4r.2d { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xec,0x60,0x4d] +; CHECK: ld4r.2d { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xec,0xe3,0x4d] +; CHECK: ld4r.8b { v2, v3, v4, v5 }, [x2], #4 ; encoding: [0x42,0xe0,0xff,0x0d] +; CHECK: ld4r.16b { v2, v3, v4, v5 }, [x2], #4 ; encoding: [0x42,0xe0,0xff,0x4d] +; CHECK: ld4r.4h { v2, v3, v4, v5 }, [x2], #8 ; encoding: [0x42,0xe4,0xff,0x0d] +; CHECK: ld4r.8h { v2, v3, v4, v5 }, [x2], #8 ; encoding: [0x42,0xe4,0xff,0x4d] +; CHECK: ld4r.2s { v2, v3, v4, v5 }, [x2], #16 ; encoding: [0x42,0xe8,0xff,0x0d] +; CHECK: ld4r.4s { v2, v3, v4, v5 }, [x2], #16 ; encoding: [0x42,0xe8,0xff,0x4d] +; CHECK: ld4r.1d { v2, v3, v4, v5 }, [x2], #32 ; encoding: [0x42,0xec,0xff,0x0d] +; CHECK: ld4r.2d { v2, v3, v4, v5 }, [x2], #32 ; encoding: [0x42,0xec,0xff,0x4d] +; CHECK: ld1.b { v6 }[13], [x3] ; encoding: [0x66,0x14,0x40,0x4d] +; CHECK: ld1.h { v6 }[2], [x3] ; encoding: [0x66,0x50,0x40,0x0d] +; CHECK: ld1.s { v6 }[2], [x3] ; encoding: [0x66,0x80,0x40,0x4d] +; CHECK: ld1.d { v6 }[1], [x3] ; encoding: [0x66,0x84,0x40,0x4d] +; CHECK: ld1.b { v6 }[13], [x3], x5 ; encoding: [0x66,0x14,0xc5,0x4d] +; CHECK: ld1.h { v6 }[2], [x3], x5 ; encoding: [0x66,0x50,0xc5,0x0d] +; CHECK: ld1.s { v6 }[2], [x3], x5 ; encoding: [0x66,0x80,0xc5,0x4d] +; CHECK: ld1.d { v6 }[1], [x3], x5 ; encoding: [0x66,0x84,0xc5,0x4d] +; CHECK: ld1.b { v6 }[13], [x3], #1 ; encoding: [0x66,0x14,0xdf,0x4d] +; CHECK: ld1.h { v6 }[2], [x3], #2 ; encoding: [0x66,0x50,0xdf,0x0d] +; CHECK: ld1.s { v6 }[2], [x3], #4 ; encoding: [0x66,0x80,0xdf,0x4d] +; CHECK: ld1.d { v6 }[1], [x3], #8 ; encoding: [0x66,0x84,0xdf,0x4d] +; CHECK: ld2.b { v5, v6 }[13], [x3] ; encoding: [0x65,0x14,0x60,0x4d] +; CHECK: ld2.h { v5, v6 }[2], [x3] ; encoding: [0x65,0x50,0x60,0x0d] +; CHECK: ld2.s { v5, v6 }[2], [x3] ; encoding: [0x65,0x80,0x60,0x4d] +; CHECK: ld2.d { v5, v6 }[1], [x3] ; encoding: [0x65,0x84,0x60,0x4d] +; CHECK: ld2.b { v5, v6 }[13], [x3], x5 ; encoding: [0x65,0x14,0xe5,0x4d] +; CHECK: ld2.h { v5, v6 }[2], [x3], x5 ; encoding: [0x65,0x50,0xe5,0x0d] +; CHECK: ld2.s { v5, v6 }[2], [x3], x5 ; encoding: [0x65,0x80,0xe5,0x4d] +; CHECK: ld2.d { v5, v6 }[1], [x3], x5 ; encoding: [0x65,0x84,0xe5,0x4d] +; CHECK: ld2.b { v5, v6 }[13], [x3], #2 ; encoding: [0x65,0x14,0xff,0x4d] +; CHECK: ld2.h { v5, v6 }[2], [x3], #4 ; encoding: [0x65,0x50,0xff,0x0d] +; CHECK: ld2.s { v5, v6 }[2], [x3], #8 ; encoding: [0x65,0x80,0xff,0x4d] +; CHECK: ld2.d { v5, v6 }[1], [x3], #16 ; encoding: [0x65,0x84,0xff,0x4d] +; CHECK: ld3.b { v7, v8, v9 }[13], [x3] ; encoding: [0x67,0x34,0x40,0x4d] +; CHECK: ld3.h { v7, v8, v9 }[2], [x3] ; encoding: [0x67,0x70,0x40,0x0d] +; CHECK: ld3.s { v7, v8, v9 }[2], [x3] ; encoding: [0x67,0xa0,0x40,0x4d] +; CHECK: ld3.d { v7, v8, v9 }[1], [x3] ; encoding: [0x67,0xa4,0x40,0x4d] +; CHECK: ld3.b { v7, v8, v9 }[13], [x3], x5 ; encoding: [0x67,0x34,0xc5,0x4d] +; CHECK: ld3.h { v7, v8, v9 }[2], [x3], x5 ; encoding: [0x67,0x70,0xc5,0x0d] +; CHECK: ld3.s { v7, v8, v9 }[2], [x3], x5 ; encoding: [0x67,0xa0,0xc5,0x4d] +; CHECK: ld3.d { v7, v8, v9 }[1], [x3], x5 ; encoding: [0x67,0xa4,0xc5,0x4d] +; CHECK: ld3.b { v7, v8, v9 }[13], [x3], #3 ; encoding: [0x67,0x34,0xdf,0x4d] +; CHECK: ld3.h { v7, v8, v9 }[2], [x3], #6 ; encoding: [0x67,0x70,0xdf,0x0d] +; CHECK: ld3.s { v7, v8, v9 }[2], [x3], #12 ; encoding: [0x67,0xa0,0xdf,0x4d] +; CHECK: ld3.d { v7, v8, v9 }[1], [x3], #24 ; encoding: [0x67,0xa4,0xdf,0x4d] +; CHECK: ld4.b { v7, v8, v9, v10 }[13], [x3] ; encoding: [0x67,0x34,0x60,0x4d] +; CHECK: ld4.h { v7, v8, v9, v10 }[2], [x3] ; encoding: [0x67,0x70,0x60,0x0d] +; CHECK: ld4.s { v7, v8, v9, v10 }[2], [x3] ; encoding: [0x67,0xa0,0x60,0x4d] +; CHECK: ld4.d { v7, v8, v9, v10 }[1], [x3] ; encoding: [0x67,0xa4,0x60,0x4d] +; CHECK: ld4.b { v7, v8, v9, v10 }[13], [x3], x5 ; encoding: [0x67,0x34,0xe5,0x4d] +; CHECK: ld4.h { v7, v8, v9, v10 }[2], [x3], x5 ; encoding: [0x67,0x70,0xe5,0x0d] +; CHECK: ld4.s { v7, v8, v9, v10 }[2], [x3], x5 ; encoding: [0x67,0xa0,0xe5,0x4d] +; CHECK: ld4.d { v7, v8, v9, v10 }[1], [x3], x5 ; encoding: [0x67,0xa4,0xe5,0x4d] +; CHECK: ld4.b { v7, v8, v9, v10 }[13], [x3], #4 ; encoding: [0x67,0x34,0xff,0x4d] +; CHECK: ld4.h { v7, v8, v9, v10 }[2], [x3], #8 ; encoding: [0x67,0x70,0xff,0x0d] +; CHECK: ld4.s { v7, v8, v9, v10 }[2], [x3], #16 ; encoding: [0x67,0xa0,0xff,0x4d] +; CHECK: ld4.d { v7, v8, v9, v10 }[1], [x3], #32 ; encoding: [0x67,0xa4,0xff,0x4d] +; CHECK: st1.b { v6 }[13], [x3] ; encoding: [0x66,0x14,0x00,0x4d] +; CHECK: st1.h { v6 }[2], [x3] ; encoding: [0x66,0x50,0x00,0x0d] +; CHECK: st1.s { v6 }[2], [x3] ; encoding: [0x66,0x80,0x00,0x4d] +; CHECK: st1.d { v6 }[1], [x3] ; encoding: [0x66,0x84,0x00,0x4d] +; CHECK: st1.b { v6 }[13], [x3], x5 ; encoding: [0x66,0x14,0x85,0x4d] +; CHECK: st1.h { v6 }[2], [x3], x5 ; encoding: [0x66,0x50,0x85,0x0d] +; CHECK: st1.s { v6 }[2], [x3], x5 ; encoding: [0x66,0x80,0x85,0x4d] +; CHECK: st1.d { v6 }[1], [x3], x5 ; encoding: [0x66,0x84,0x85,0x4d] +; CHECK: st1.b { v6 }[13], [x3], #1 ; encoding: [0x66,0x14,0x9f,0x4d] +; CHECK: st1.h { v6 }[2], [x3], #2 ; encoding: [0x66,0x50,0x9f,0x0d] +; CHECK: st1.s { v6 }[2], [x3], #4 ; encoding: [0x66,0x80,0x9f,0x4d] +; CHECK: st1.d { v6 }[1], [x3], #8 ; encoding: [0x66,0x84,0x9f,0x4d] +; CHECK: st2.b { v5, v6 }[13], [x3] ; encoding: [0x65,0x14,0x20,0x4d] +; CHECK: st2.h { v5, v6 }[2], [x3] ; encoding: [0x65,0x50,0x20,0x0d] +; CHECK: st2.s { v5, v6 }[2], [x3] ; encoding: [0x65,0x80,0x20,0x4d] +; CHECK: st2.d { v5, v6 }[1], [x3] ; encoding: [0x65,0x84,0x20,0x4d] +; CHECK: st2.b { v5, v6 }[13], [x3], x5 ; encoding: [0x65,0x14,0xa5,0x4d] +; CHECK: st2.h { v5, v6 }[2], [x3], x5 ; encoding: [0x65,0x50,0xa5,0x0d] +; CHECK: st2.s { v5, v6 }[2], [x3], x5 ; encoding: [0x65,0x80,0xa5,0x4d] +; CHECK: st2.d { v5, v6 }[1], [x3], x5 ; encoding: [0x65,0x84,0xa5,0x4d] +; CHECK: st2.b { v5, v6 }[13], [x3], #2 ; encoding: [0x65,0x14,0xbf,0x4d] +; CHECK: st2.h { v5, v6 }[2], [x3], #4 ; encoding: [0x65,0x50,0xbf,0x0d] +; CHECK: st2.s { v5, v6 }[2], [x3], #8 ; encoding: [0x65,0x80,0xbf,0x4d] +; CHECK: st2.d { v5, v6 }[1], [x3], #16 ; encoding: [0x65,0x84,0xbf,0x4d] +; CHECK: st3.b { v7, v8, v9 }[13], [x3] ; encoding: [0x67,0x34,0x00,0x4d] +; CHECK: st3.h { v7, v8, v9 }[2], [x3] ; encoding: [0x67,0x70,0x00,0x0d] +; CHECK: st3.s { v7, v8, v9 }[2], [x3] ; encoding: [0x67,0xa0,0x00,0x4d] +; CHECK: st3.d { v7, v8, v9 }[1], [x3] ; encoding: [0x67,0xa4,0x00,0x4d] +; CHECK: st3.b { v7, v8, v9 }[13], [x3], x5 ; encoding: [0x67,0x34,0x85,0x4d] +; CHECK: st3.h { v7, v8, v9 }[2], [x3], x5 ; encoding: [0x67,0x70,0x85,0x0d] +; CHECK: st3.s { v7, v8, v9 }[2], [x3], x5 ; encoding: [0x67,0xa0,0x85,0x4d] +; CHECK: st3.d { v7, v8, v9 }[1], [x3], x5 ; encoding: [0x67,0xa4,0x85,0x4d] +; CHECK: st3.b { v7, v8, v9 }[13], [x3], #3 ; encoding: [0x67,0x34,0x9f,0x4d] +; CHECK: st3.h { v7, v8, v9 }[2], [x3], #6 ; encoding: [0x67,0x70,0x9f,0x0d] +; CHECK: st3.s { v7, v8, v9 }[2], [x3], #12 ; encoding: [0x67,0xa0,0x9f,0x4d] +; CHECK: st3.d { v7, v8, v9 }[1], [x3], #24 ; encoding: [0x67,0xa4,0x9f,0x4d] +; CHECK: st4.b { v7, v8, v9, v10 }[13], [x3] ; encoding: [0x67,0x34,0x20,0x4d] +; CHECK: st4.h { v7, v8, v9, v10 }[2], [x3] ; encoding: [0x67,0x70,0x20,0x0d] +; CHECK: st4.s { v7, v8, v9, v10 }[2], [x3] ; encoding: [0x67,0xa0,0x20,0x4d] +; CHECK: st4.d { v7, v8, v9, v10 }[1], [x3] ; encoding: [0x67,0xa4,0x20,0x4d] +; CHECK: st4.b { v7, v8, v9, v10 }[13], [x3], x5 ; encoding: [0x67,0x34,0xa5,0x4d] +; CHECK: st4.h { v7, v8, v9, v10 }[2], [x3], x5 ; encoding: [0x67,0x70,0xa5,0x0d] +; CHECK: st4.s { v7, v8, v9, v10 }[2], [x3], x5 ; encoding: [0x67,0xa0,0xa5,0x4d] +; CHECK: st4.d { v7, v8, v9, v10 }[1], [x3], x5 ; encoding: [0x67,0xa4,0xa5,0x4d] +; CHECK: st4.b { v7, v8, v9, v10 }[13], [x3], #4 ; encoding: [0x67,0x34,0xbf,0x4d] +; CHECK: st4.h { v7, v8, v9, v10 }[2], [x3], #8 ; encoding: [0x67,0x70,0xbf,0x0d] +; CHECK: st4.s { v7, v8, v9, v10 }[2], [x3], #16 ; encoding: [0x67,0xa0,0xbf,0x4d] +; CHECK: st4.d { v7, v8, v9, v10 }[1], [x3], #32 ; encoding: [0x67,0xa4,0xbf,0x4d] diff --git a/test/MC/AArch64/arm64-small-data-fixups.s b/test/MC/AArch64/arm64-small-data-fixups.s new file mode 100644 index 0000000..3fe7c75 --- /dev/null +++ b/test/MC/AArch64/arm64-small-data-fixups.s @@ -0,0 +1,24 @@ +; RUN: llvm-mc -triple arm64-apple-darwin -filetype=obj -o - %s | macho-dump | FileCheck %s + +foo: + .long 0 +bar: + .long 1 + +baz: + .byte foo - bar + .short foo - bar + +; CHECK: # Relocation 0 +; CHECK: (('word-0', 0x9), +; CHECK: ('word-1', 0x1a000002)), +; CHECK: # Relocation 1 +; CHECK: (('word-0', 0x9), +; CHECK: ('word-1', 0xa000001)), +; CHECK: # Relocation 2 +; CHECK: (('word-0', 0x8), +; CHECK: ('word-1', 0x18000002)), +; CHECK: # Relocation 3 +; CHECK: (('word-0', 0x8), +; CHECK: ('word-1', 0x8000001)), + diff --git a/test/MC/AArch64/arm64-spsel-sysreg.s b/test/MC/AArch64/arm64-spsel-sysreg.s new file mode 100644 index 0000000..f1d94d8 --- /dev/null +++ b/test/MC/AArch64/arm64-spsel-sysreg.s @@ -0,0 +1,24 @@ +// RUN: not llvm-mc -triple arm64 -show-encoding < %s 2>%t | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +msr SPSel, #0 +msr SPSel, x0 +msr DAIFSet, #0 +msr ESR_EL1, x0 +mrs x0, SPSel +mrs x0, ESR_EL1 + +// CHECK: msr SPSEL, #0 // encoding: [0xbf,0x40,0x00,0xd5] +// CHECK: msr SPSEL, x0 // encoding: [0x00,0x42,0x18,0xd5] +// CHECK: msr DAIFSET, #0 // encoding: [0xdf,0x40,0x03,0xd5] +// CHECK: msr ESR_EL1, x0 // encoding: [0x00,0x52,0x18,0xd5] +// CHECK: mrs x0, SPSEL // encoding: [0x00,0x42,0x38,0xd5] +// CHECK: mrs x0, ESR_EL1 // encoding: [0x00,0x52,0x38,0xd5] + + +msr DAIFSet, x0 +msr ESR_EL1, #0 +mrs x0, DAIFSet +// CHECK-ERRORS: error: immediate must be an integer in range [0, 15] +// CHECK-ERRORS: error: invalid operand for instruction +// CHECK-ERRORS: error: expected readable system register diff --git a/test/MC/AArch64/arm64-system-encoding.s b/test/MC/AArch64/arm64-system-encoding.s new file mode 100644 index 0000000..9246608 --- /dev/null +++ b/test/MC/AArch64/arm64-system-encoding.s @@ -0,0 +1,623 @@ +; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s +; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +foo: + +;----------------------------------------------------------------------------- +; Simple encodings (instuctions w/ no operands) +;----------------------------------------------------------------------------- + + nop + sev + sevl + wfe + wfi + yield + +; CHECK: nop ; encoding: [0x1f,0x20,0x03,0xd5] +; CHECK: sev ; encoding: [0x9f,0x20,0x03,0xd5] +; CHECK: sevl ; encoding: [0xbf,0x20,0x03,0xd5] +; CHECK: wfe ; encoding: [0x5f,0x20,0x03,0xd5] +; CHECK: wfi ; encoding: [0x7f,0x20,0x03,0xd5] +; CHECK: yield ; encoding: [0x3f,0x20,0x03,0xd5] + +;----------------------------------------------------------------------------- +; Single-immediate operand instructions +;----------------------------------------------------------------------------- + + clrex #10 +; CHECK: clrex #10 ; encoding: [0x5f,0x3a,0x03,0xd5] + isb #15 + isb sy +; CHECK: isb ; encoding: [0xdf,0x3f,0x03,0xd5] +; CHECK: isb ; encoding: [0xdf,0x3f,0x03,0xd5] + dmb #3 + dmb osh +; CHECK: dmb osh ; encoding: [0xbf,0x33,0x03,0xd5] +; CHECK: dmb osh ; encoding: [0xbf,0x33,0x03,0xd5] + dsb #7 + dsb nsh +; CHECK: dsb nsh ; encoding: [0x9f,0x37,0x03,0xd5] +; CHECK: dsb nsh ; encoding: [0x9f,0x37,0x03,0xd5] + +;----------------------------------------------------------------------------- +; Generic system instructions +;----------------------------------------------------------------------------- + sys #2, c0, c5, #7 +; CHECK: encoding: [0xff,0x05,0x0a,0xd5] + sys #7, C6, c10, #7, x7 +; CHECK: encoding: [0xe7,0x6a,0x0f,0xd5] + sysl x20, #6, c3, C15, #7 +; CHECK: encoding: [0xf4,0x3f,0x2e,0xd5] + +; Check for error on invalid 'C' operand value. + sys #2, c16, c5, #7 +; CHECK-ERRORS: error: Expected cN operand where 0 <= N <= 15 + +;----------------------------------------------------------------------------- +; MSR/MRS instructions +;----------------------------------------------------------------------------- + msr ACTLR_EL1, x3 + msr ACTLR_EL2, x3 + msr ACTLR_EL3, x3 + msr AFSR0_EL1, x3 + msr AFSR0_EL2, x3 + msr AFSR0_EL3, x3 + msr AFSR1_EL1, x3 + msr AFSR1_EL2, x3 + msr AFSR1_EL3, x3 + msr AMAIR_EL1, x3 + msr AMAIR_EL2, x3 + msr AMAIR_EL3, x3 + msr CNTFRQ_EL0, x3 + msr CNTHCTL_EL2, x3 + msr CNTHP_CTL_EL2, x3 + msr CNTHP_CVAL_EL2, x3 + msr CNTHP_TVAL_EL2, x3 + msr CNTKCTL_EL1, x3 + msr CNTP_CTL_EL0, x3 + msr CNTP_CVAL_EL0, x3 + msr CNTP_TVAL_EL0, x3 + msr CNTVOFF_EL2, x3 + msr CNTV_CTL_EL0, x3 + msr CNTV_CVAL_EL0, x3 + msr CNTV_TVAL_EL0, x3 + msr CONTEXTIDR_EL1, x3 + msr CPACR_EL1, x3 + msr CPTR_EL2, x3 + msr CPTR_EL3, x3 + msr CSSELR_EL1, x3 + msr CURRENTEL, x3 + msr DACR32_EL2, x3 + msr ESR_EL1, x3 + msr ESR_EL2, x3 + msr ESR_EL3, x3 + msr FAR_EL1, x3 + msr FAR_EL2, x3 + msr FAR_EL3, x3 + msr FPEXC32_EL2, x3 + msr HACR_EL2, x3 + msr HCR_EL2, x3 + msr HPFAR_EL2, x3 + msr HSTR_EL2, x3 + msr IFSR32_EL2, x3 + msr MAIR_EL1, x3 + msr MAIR_EL2, x3 + msr MAIR_EL3, x3 + msr MDCR_EL2, x3 + msr MDCR_EL3, x3 + msr PAR_EL1, x3 + msr SCR_EL3, x3 + msr SCTLR_EL1, x3 + msr SCTLR_EL2, x3 + msr SCTLR_EL3, x3 + msr SDER32_EL3, x3 + msr TCR_EL1, x3 + msr TCR_EL2, x3 + msr TCR_EL3, x3 + msr TEECR32_EL1, x3 + msr TEEHBR32_EL1, x3 + msr TPIDRRO_EL0, x3 + msr TPIDR_EL0, x3 + msr TPIDR_EL1, x3 + msr TPIDR_EL2, x3 + msr TPIDR_EL3, x3 + msr TTBR0_EL1, x3 + msr TTBR0_EL2, x3 + msr TTBR0_EL3, x3 + msr TTBR1_EL1, x3 + msr VBAR_EL1, x3 + msr VBAR_EL2, x3 + msr VBAR_EL3, x3 + msr VMPIDR_EL2, x3 + msr VPIDR_EL2, x3 + msr VTCR_EL2, x3 + msr VTTBR_EL2, x3 + msr SPSel, x3 + msr S3_2_C11_C6_4, x1 +; CHECK: msr ACTLR_EL1, x3 ; encoding: [0x23,0x10,0x18,0xd5] +; CHECK: msr ACTLR_EL2, x3 ; encoding: [0x23,0x10,0x1c,0xd5] +; CHECK: msr ACTLR_EL3, x3 ; encoding: [0x23,0x10,0x1e,0xd5] +; CHECK: msr AFSR0_EL1, x3 ; encoding: [0x03,0x51,0x18,0xd5] +; CHECK: msr AFSR0_EL2, x3 ; encoding: [0x03,0x51,0x1c,0xd5] +; CHECK: msr AFSR0_EL3, x3 ; encoding: [0x03,0x51,0x1e,0xd5] +; CHECK: msr AFSR1_EL1, x3 ; encoding: [0x23,0x51,0x18,0xd5] +; CHECK: msr AFSR1_EL2, x3 ; encoding: [0x23,0x51,0x1c,0xd5] +; CHECK: msr AFSR1_EL3, x3 ; encoding: [0x23,0x51,0x1e,0xd5] +; CHECK: msr AMAIR_EL1, x3 ; encoding: [0x03,0xa3,0x18,0xd5] +; CHECK: msr AMAIR_EL2, x3 ; encoding: [0x03,0xa3,0x1c,0xd5] +; CHECK: msr AMAIR_EL3, x3 ; encoding: [0x03,0xa3,0x1e,0xd5] +; CHECK: msr CNTFRQ_EL0, x3 ; encoding: [0x03,0xe0,0x1b,0xd5] +; CHECK: msr CNTHCTL_EL2, x3 ; encoding: [0x03,0xe1,0x1c,0xd5] +; CHECK: msr CNTHP_CTL_EL2, x3 ; encoding: [0x23,0xe2,0x1c,0xd5] +; CHECK: msr CNTHP_CVAL_EL2, x3 ; encoding: [0x43,0xe2,0x1c,0xd5] +; CHECK: msr CNTHP_TVAL_EL2, x3 ; encoding: [0x03,0xe2,0x1c,0xd5] +; CHECK: msr CNTKCTL_EL1, x3 ; encoding: [0x03,0xe1,0x18,0xd5] +; CHECK: msr CNTP_CTL_EL0, x3 ; encoding: [0x23,0xe2,0x1b,0xd5] +; CHECK: msr CNTP_CVAL_EL0, x3 ; encoding: [0x43,0xe2,0x1b,0xd5] +; CHECK: msr CNTP_TVAL_EL0, x3 ; encoding: [0x03,0xe2,0x1b,0xd5] +; CHECK: msr CNTVOFF_EL2, x3 ; encoding: [0x63,0xe0,0x1c,0xd5] +; CHECK: msr CNTV_CTL_EL0, x3 ; encoding: [0x23,0xe3,0x1b,0xd5] +; CHECK: msr CNTV_CVAL_EL0, x3 ; encoding: [0x43,0xe3,0x1b,0xd5] +; CHECK: msr CNTV_TVAL_EL0, x3 ; encoding: [0x03,0xe3,0x1b,0xd5] +; CHECK: msr CONTEXTIDR_EL1, x3 ; encoding: [0x23,0xd0,0x18,0xd5] +; CHECK: msr CPACR_EL1, x3 ; encoding: [0x43,0x10,0x18,0xd5] +; CHECK: msr CPTR_EL2, x3 ; encoding: [0x43,0x11,0x1c,0xd5] +; CHECK: msr CPTR_EL3, x3 ; encoding: [0x43,0x11,0x1e,0xd5] +; CHECK: msr CSSELR_EL1, x3 ; encoding: [0x03,0x00,0x1a,0xd5] +; CHECK: msr CURRENTEL, x3 ; encoding: [0x43,0x42,0x18,0xd5] +; CHECK: msr DACR32_EL2, x3 ; encoding: [0x03,0x30,0x1c,0xd5] +; CHECK: msr ESR_EL1, x3 ; encoding: [0x03,0x52,0x18,0xd5] +; CHECK: msr ESR_EL2, x3 ; encoding: [0x03,0x52,0x1c,0xd5] +; CHECK: msr ESR_EL3, x3 ; encoding: [0x03,0x52,0x1e,0xd5] +; CHECK: msr FAR_EL1, x3 ; encoding: [0x03,0x60,0x18,0xd5] +; CHECK: msr FAR_EL2, x3 ; encoding: [0x03,0x60,0x1c,0xd5] +; CHECK: msr FAR_EL3, x3 ; encoding: [0x03,0x60,0x1e,0xd5] +; CHECK: msr FPEXC32_EL2, x3 ; encoding: [0x03,0x53,0x1c,0xd5] +; CHECK: msr HACR_EL2, x3 ; encoding: [0xe3,0x11,0x1c,0xd5] +; CHECK: msr HCR_EL2, x3 ; encoding: [0x03,0x11,0x1c,0xd5] +; CHECK: msr HPFAR_EL2, x3 ; encoding: [0x83,0x60,0x1c,0xd5] +; CHECK: msr HSTR_EL2, x3 ; encoding: [0x63,0x11,0x1c,0xd5] +; CHECK: msr IFSR32_EL2, x3 ; encoding: [0x23,0x50,0x1c,0xd5] +; CHECK: msr MAIR_EL1, x3 ; encoding: [0x03,0xa2,0x18,0xd5] +; CHECK: msr MAIR_EL2, x3 ; encoding: [0x03,0xa2,0x1c,0xd5] +; CHECK: msr MAIR_EL3, x3 ; encoding: [0x03,0xa2,0x1e,0xd5] +; CHECK: msr MDCR_EL2, x3 ; encoding: [0x23,0x11,0x1c,0xd5] +; CHECK: msr MDCR_EL3, x3 ; encoding: [0x23,0x13,0x1e,0xd5] +; CHECK: msr PAR_EL1, x3 ; encoding: [0x03,0x74,0x18,0xd5] +; CHECK: msr SCR_EL3, x3 ; encoding: [0x03,0x11,0x1e,0xd5] +; CHECK: msr SCTLR_EL1, x3 ; encoding: [0x03,0x10,0x18,0xd5] +; CHECK: msr SCTLR_EL2, x3 ; encoding: [0x03,0x10,0x1c,0xd5] +; CHECK: msr SCTLR_EL3, x3 ; encoding: [0x03,0x10,0x1e,0xd5] +; CHECK: msr SDER32_EL3, x3 ; encoding: [0x23,0x11,0x1e,0xd5] +; CHECK: msr TCR_EL1, x3 ; encoding: [0x43,0x20,0x18,0xd5] +; CHECK: msr TCR_EL2, x3 ; encoding: [0x43,0x20,0x1c,0xd5] +; CHECK: msr TCR_EL3, x3 ; encoding: [0x43,0x20,0x1e,0xd5] +; CHECK: msr TEECR32_EL1, x3 ; encoding: [0x03,0x00,0x12,0xd5] +; CHECK: msr TEEHBR32_EL1, x3 ; encoding: [0x03,0x10,0x12,0xd5] +; CHECK: msr TPIDRRO_EL0, x3 ; encoding: [0x63,0xd0,0x1b,0xd5] +; CHECK: msr TPIDR_EL0, x3 ; encoding: [0x43,0xd0,0x1b,0xd5] +; CHECK: msr TPIDR_EL1, x3 ; encoding: [0x83,0xd0,0x18,0xd5] +; CHECK: msr TPIDR_EL2, x3 ; encoding: [0x43,0xd0,0x1c,0xd5] +; CHECK: msr TPIDR_EL3, x3 ; encoding: [0x43,0xd0,0x1e,0xd5] +; CHECK: msr TTBR0_EL1, x3 ; encoding: [0x03,0x20,0x18,0xd5] +; CHECK: msr TTBR0_EL2, x3 ; encoding: [0x03,0x20,0x1c,0xd5] +; CHECK: msr TTBR0_EL3, x3 ; encoding: [0x03,0x20,0x1e,0xd5] +; CHECK: msr TTBR1_EL1, x3 ; encoding: [0x23,0x20,0x18,0xd5] +; CHECK: msr VBAR_EL1, x3 ; encoding: [0x03,0xc0,0x18,0xd5] +; CHECK: msr VBAR_EL2, x3 ; encoding: [0x03,0xc0,0x1c,0xd5] +; CHECK: msr VBAR_EL3, x3 ; encoding: [0x03,0xc0,0x1e,0xd5] +; CHECK: msr VMPIDR_EL2, x3 ; encoding: [0xa3,0x00,0x1c,0xd5] +; CHECK: msr VPIDR_EL2, x3 ; encoding: [0x03,0x00,0x1c,0xd5] +; CHECK: msr VTCR_EL2, x3 ; encoding: [0x43,0x21,0x1c,0xd5] +; CHECK: msr VTTBR_EL2, x3 ; encoding: [0x03,0x21,0x1c,0xd5] +; CHECK: msr SPSEL, x3 ; encoding: [0x03,0x42,0x18,0xd5] +; CHECK: msr S3_2_C11_C6_4, x1 ; encoding: [0x81,0xb6,0x1a,0xd5] + + mrs x3, ACTLR_EL1 + mrs x3, ACTLR_EL2 + mrs x3, ACTLR_EL3 + mrs x3, AFSR0_EL1 + mrs x3, AFSR0_EL2 + mrs x3, AFSR0_EL3 + mrs x3, AIDR_EL1 + mrs x3, AFSR1_EL1 + mrs x3, AFSR1_EL2 + mrs x3, AFSR1_EL3 + mrs x3, AMAIR_EL1 + mrs x3, AMAIR_EL2 + mrs x3, AMAIR_EL3 + mrs x3, CCSIDR_EL1 + mrs x3, CLIDR_EL1 + mrs x3, CNTFRQ_EL0 + mrs x3, CNTHCTL_EL2 + mrs x3, CNTHP_CTL_EL2 + mrs x3, CNTHP_CVAL_EL2 + mrs x3, CNTHP_TVAL_EL2 + mrs x3, CNTKCTL_EL1 + mrs x3, CNTPCT_EL0 + mrs x3, CNTP_CTL_EL0 + mrs x3, CNTP_CVAL_EL0 + mrs x3, CNTP_TVAL_EL0 + mrs x3, CNTVCT_EL0 + mrs x3, CNTVOFF_EL2 + mrs x3, CNTV_CTL_EL0 + mrs x3, CNTV_CVAL_EL0 + mrs x3, CNTV_TVAL_EL0 + mrs x3, CONTEXTIDR_EL1 + mrs x3, CPACR_EL1 + mrs x3, CPTR_EL2 + mrs x3, CPTR_EL3 + mrs x3, CSSELR_EL1 + mrs x3, CTR_EL0 + mrs x3, CURRENTEL + mrs x3, DACR32_EL2 + mrs x3, DCZID_EL0 + mrs x3, REVIDR_EL1 + mrs x3, ESR_EL1 + mrs x3, ESR_EL2 + mrs x3, ESR_EL3 + mrs x3, FAR_EL1 + mrs x3, FAR_EL2 + mrs x3, FAR_EL3 + mrs x3, FPEXC32_EL2 + mrs x3, HACR_EL2 + mrs x3, HCR_EL2 + mrs x3, HPFAR_EL2 + mrs x3, HSTR_EL2 + mrs x3, ID_AA64DFR0_EL1 + mrs x3, ID_AA64DFR1_EL1 + mrs x3, ID_AA64ISAR0_EL1 + mrs x3, ID_AA64ISAR1_EL1 + mrs x3, ID_AA64MMFR0_EL1 + mrs x3, ID_AA64MMFR1_EL1 + mrs x3, ID_AA64PFR0_EL1 + mrs x3, ID_AA64PFR1_EL1 + mrs x3, IFSR32_EL2 + mrs x3, ISR_EL1 + mrs x3, MAIR_EL1 + mrs x3, MAIR_EL2 + mrs x3, MAIR_EL3 + mrs x3, MDCR_EL2 + mrs x3, MDCR_EL3 + mrs x3, MIDR_EL1 + mrs x3, MPIDR_EL1 + mrs x3, MVFR0_EL1 + mrs x3, MVFR1_EL1 + mrs x3, PAR_EL1 + mrs x3, RVBAR_EL1 + mrs x3, RVBAR_EL2 + mrs x3, RVBAR_EL3 + mrs x3, SCR_EL3 + mrs x3, SCTLR_EL1 + mrs x3, SCTLR_EL2 + mrs x3, SCTLR_EL3 + mrs x3, SDER32_EL3 + mrs x3, TCR_EL1 + mrs x3, TCR_EL2 + mrs x3, TCR_EL3 + mrs x3, TEECR32_EL1 + mrs x3, TEEHBR32_EL1 + mrs x3, TPIDRRO_EL0 + mrs x3, TPIDR_EL0 + mrs x3, TPIDR_EL1 + mrs x3, TPIDR_EL2 + mrs x3, TPIDR_EL3 + mrs x3, TTBR0_EL1 + mrs x3, TTBR0_EL2 + mrs x3, TTBR0_EL3 + mrs x3, TTBR1_EL1 + mrs x3, VBAR_EL1 + mrs x3, VBAR_EL2 + mrs x3, VBAR_EL3 + mrs x3, VMPIDR_EL2 + mrs x3, VPIDR_EL2 + mrs x3, VTCR_EL2 + mrs x3, VTTBR_EL2 + + mrs x3, MDCCSR_EL0 + mrs x3, MDCCINT_EL1 + mrs x3, DBGDTR_EL0 + mrs x3, DBGDTRRX_EL0 + mrs x3, DBGVCR32_EL2 + mrs x3, OSDTRRX_EL1 + mrs x3, MDSCR_EL1 + mrs x3, OSDTRTX_EL1 + mrs x3, OSECCR_EL1 + mrs x3, DBGBVR0_EL1 + mrs x3, DBGBVR1_EL1 + mrs x3, DBGBVR2_EL1 + mrs x3, DBGBVR3_EL1 + mrs x3, DBGBVR4_EL1 + mrs x3, DBGBVR5_EL1 + mrs x3, DBGBVR6_EL1 + mrs x3, DBGBVR7_EL1 + mrs x3, DBGBVR8_EL1 + mrs x3, DBGBVR9_EL1 + mrs x3, DBGBVR10_EL1 + mrs x3, DBGBVR11_EL1 + mrs x3, DBGBVR12_EL1 + mrs x3, DBGBVR13_EL1 + mrs x3, DBGBVR14_EL1 + mrs x3, DBGBVR15_EL1 + mrs x3, DBGBCR0_EL1 + mrs x3, DBGBCR1_EL1 + mrs x3, DBGBCR2_EL1 + mrs x3, DBGBCR3_EL1 + mrs x3, DBGBCR4_EL1 + mrs x3, DBGBCR5_EL1 + mrs x3, DBGBCR6_EL1 + mrs x3, DBGBCR7_EL1 + mrs x3, DBGBCR8_EL1 + mrs x3, DBGBCR9_EL1 + mrs x3, DBGBCR10_EL1 + mrs x3, DBGBCR11_EL1 + mrs x3, DBGBCR12_EL1 + mrs x3, DBGBCR13_EL1 + mrs x3, DBGBCR14_EL1 + mrs x3, DBGBCR15_EL1 + mrs x3, DBGWVR0_EL1 + mrs x3, DBGWVR1_EL1 + mrs x3, DBGWVR2_EL1 + mrs x3, DBGWVR3_EL1 + mrs x3, DBGWVR4_EL1 + mrs x3, DBGWVR5_EL1 + mrs x3, DBGWVR6_EL1 + mrs x3, DBGWVR7_EL1 + mrs x3, DBGWVR8_EL1 + mrs x3, DBGWVR9_EL1 + mrs x3, DBGWVR10_EL1 + mrs x3, DBGWVR11_EL1 + mrs x3, DBGWVR12_EL1 + mrs x3, DBGWVR13_EL1 + mrs x3, DBGWVR14_EL1 + mrs x3, DBGWVR15_EL1 + mrs x3, DBGWCR0_EL1 + mrs x3, DBGWCR1_EL1 + mrs x3, DBGWCR2_EL1 + mrs x3, DBGWCR3_EL1 + mrs x3, DBGWCR4_EL1 + mrs x3, DBGWCR5_EL1 + mrs x3, DBGWCR6_EL1 + mrs x3, DBGWCR7_EL1 + mrs x3, DBGWCR8_EL1 + mrs x3, DBGWCR9_EL1 + mrs x3, DBGWCR10_EL1 + mrs x3, DBGWCR11_EL1 + mrs x3, DBGWCR12_EL1 + mrs x3, DBGWCR13_EL1 + mrs x3, DBGWCR14_EL1 + mrs x3, DBGWCR15_EL1 + mrs x3, MDRAR_EL1 + mrs x3, OSLSR_EL1 + mrs x3, OSDLR_EL1 + mrs x3, DBGPRCR_EL1 + mrs x3, DBGCLAIMSET_EL1 + mrs x3, DBGCLAIMCLR_EL1 + mrs x3, DBGAUTHSTATUS_EL1 + mrs x1, S3_2_C15_C6_4 + mrs x3, s3_3_c11_c1_4 + mrs x3, S3_3_c11_c1_4 + +; CHECK: mrs x3, ACTLR_EL1 ; encoding: [0x23,0x10,0x38,0xd5] +; CHECK: mrs x3, ACTLR_EL2 ; encoding: [0x23,0x10,0x3c,0xd5] +; CHECK: mrs x3, ACTLR_EL3 ; encoding: [0x23,0x10,0x3e,0xd5] +; CHECK: mrs x3, AFSR0_EL1 ; encoding: [0x03,0x51,0x38,0xd5] +; CHECK: mrs x3, AFSR0_EL2 ; encoding: [0x03,0x51,0x3c,0xd5] +; CHECK: mrs x3, AFSR0_EL3 ; encoding: [0x03,0x51,0x3e,0xd5] +; CHECK: mrs x3, AIDR_EL1 ; encoding: [0xe3,0x00,0x39,0xd5] +; CHECK: mrs x3, AFSR1_EL1 ; encoding: [0x23,0x51,0x38,0xd5] +; CHECK: mrs x3, AFSR1_EL2 ; encoding: [0x23,0x51,0x3c,0xd5] +; CHECK: mrs x3, AFSR1_EL3 ; encoding: [0x23,0x51,0x3e,0xd5] +; CHECK: mrs x3, AMAIR_EL1 ; encoding: [0x03,0xa3,0x38,0xd5] +; CHECK: mrs x3, AMAIR_EL2 ; encoding: [0x03,0xa3,0x3c,0xd5] +; CHECK: mrs x3, AMAIR_EL3 ; encoding: [0x03,0xa3,0x3e,0xd5] +; CHECK: mrs x3, CCSIDR_EL1 ; encoding: [0x03,0x00,0x39,0xd5] +; CHECK: mrs x3, CLIDR_EL1 ; encoding: [0x23,0x00,0x39,0xd5] +; CHECK: mrs x3, CNTFRQ_EL0 ; encoding: [0x03,0xe0,0x3b,0xd5] +; CHECK: mrs x3, CNTHCTL_EL2 ; encoding: [0x03,0xe1,0x3c,0xd5] +; CHECK: mrs x3, CNTHP_CTL_EL2 ; encoding: [0x23,0xe2,0x3c,0xd5] +; CHECK: mrs x3, CNTHP_CVAL_EL2 ; encoding: [0x43,0xe2,0x3c,0xd5] +; CHECK: mrs x3, CNTHP_TVAL_EL2 ; encoding: [0x03,0xe2,0x3c,0xd5] +; CHECK: mrs x3, CNTKCTL_EL1 ; encoding: [0x03,0xe1,0x38,0xd5] +; CHECK: mrs x3, CNTPCT_EL0 ; encoding: [0x23,0xe0,0x3b,0xd5] +; CHECK: mrs x3, CNTP_CTL_EL0 ; encoding: [0x23,0xe2,0x3b,0xd5] +; CHECK: mrs x3, CNTP_CVAL_EL0 ; encoding: [0x43,0xe2,0x3b,0xd5] +; CHECK: mrs x3, CNTP_TVAL_EL0 ; encoding: [0x03,0xe2,0x3b,0xd5] +; CHECK: mrs x3, CNTVCT_EL0 ; encoding: [0x43,0xe0,0x3b,0xd5] +; CHECK: mrs x3, CNTVOFF_EL2 ; encoding: [0x63,0xe0,0x3c,0xd5] +; CHECK: mrs x3, CNTV_CTL_EL0 ; encoding: [0x23,0xe3,0x3b,0xd5] +; CHECK: mrs x3, CNTV_CVAL_EL0 ; encoding: [0x43,0xe3,0x3b,0xd5] +; CHECK: mrs x3, CNTV_TVAL_EL0 ; encoding: [0x03,0xe3,0x3b,0xd5] +; CHECK: mrs x3, CONTEXTIDR_EL1 ; encoding: [0x23,0xd0,0x38,0xd5] +; CHECK: mrs x3, CPACR_EL1 ; encoding: [0x43,0x10,0x38,0xd5] +; CHECK: mrs x3, CPTR_EL2 ; encoding: [0x43,0x11,0x3c,0xd5] +; CHECK: mrs x3, CPTR_EL3 ; encoding: [0x43,0x11,0x3e,0xd5] +; CHECK: mrs x3, CSSELR_EL1 ; encoding: [0x03,0x00,0x3a,0xd5] +; CHECK: mrs x3, CTR_EL0 ; encoding: [0x23,0x00,0x3b,0xd5] +; CHECK: mrs x3, CURRENTEL ; encoding: [0x43,0x42,0x38,0xd5] +; CHECK: mrs x3, DACR32_EL2 ; encoding: [0x03,0x30,0x3c,0xd5] +; CHECK: mrs x3, DCZID_EL0 ; encoding: [0xe3,0x00,0x3b,0xd5] +; CHECK: mrs x3, REVIDR_EL1 ; encoding: [0xc3,0x00,0x38,0xd5] +; CHECK: mrs x3, ESR_EL1 ; encoding: [0x03,0x52,0x38,0xd5] +; CHECK: mrs x3, ESR_EL2 ; encoding: [0x03,0x52,0x3c,0xd5] +; CHECK: mrs x3, ESR_EL3 ; encoding: [0x03,0x52,0x3e,0xd5] +; CHECK: mrs x3, FAR_EL1 ; encoding: [0x03,0x60,0x38,0xd5] +; CHECK: mrs x3, FAR_EL2 ; encoding: [0x03,0x60,0x3c,0xd5] +; CHECK: mrs x3, FAR_EL3 ; encoding: [0x03,0x60,0x3e,0xd5] +; CHECK: mrs x3, FPEXC32_EL2 ; encoding: [0x03,0x53,0x3c,0xd5] +; CHECK: mrs x3, HACR_EL2 ; encoding: [0xe3,0x11,0x3c,0xd5] +; CHECK: mrs x3, HCR_EL2 ; encoding: [0x03,0x11,0x3c,0xd5] +; CHECK: mrs x3, HPFAR_EL2 ; encoding: [0x83,0x60,0x3c,0xd5] +; CHECK: mrs x3, HSTR_EL2 ; encoding: [0x63,0x11,0x3c,0xd5] +; CHECK: mrs x3, ID_AA64DFR0_EL1 ; encoding: [0x03,0x05,0x38,0xd5] +; CHECK: mrs x3, ID_AA64DFR1_EL1 ; encoding: [0x23,0x05,0x38,0xd5] +; CHECK: mrs x3, ID_AA64ISAR0_EL1 ; encoding: [0x03,0x06,0x38,0xd5] +; CHECK: mrs x3, ID_AA64ISAR1_EL1 ; encoding: [0x23,0x06,0x38,0xd5] +; CHECK: mrs x3, ID_AA64MMFR0_EL1 ; encoding: [0x03,0x07,0x38,0xd5] +; CHECK: mrs x3, ID_AA64MMFR1_EL1 ; encoding: [0x23,0x07,0x38,0xd5] +; CHECK: mrs x3, ID_AA64PFR0_EL1 ; encoding: [0x03,0x04,0x38,0xd5] +; CHECK: mrs x3, ID_AA64PFR1_EL1 ; encoding: [0x23,0x04,0x38,0xd5] +; CHECK: mrs x3, IFSR32_EL2 ; encoding: [0x23,0x50,0x3c,0xd5] +; CHECK: mrs x3, ISR_EL1 ; encoding: [0x03,0xc1,0x38,0xd5] +; CHECK: mrs x3, MAIR_EL1 ; encoding: [0x03,0xa2,0x38,0xd5] +; CHECK: mrs x3, MAIR_EL2 ; encoding: [0x03,0xa2,0x3c,0xd5] +; CHECK: mrs x3, MAIR_EL3 ; encoding: [0x03,0xa2,0x3e,0xd5] +; CHECK: mrs x3, MDCR_EL2 ; encoding: [0x23,0x11,0x3c,0xd5] +; CHECK: mrs x3, MDCR_EL3 ; encoding: [0x23,0x13,0x3e,0xd5] +; CHECK: mrs x3, MIDR_EL1 ; encoding: [0x03,0x00,0x38,0xd5] +; CHECK: mrs x3, MPIDR_EL1 ; encoding: [0xa3,0x00,0x38,0xd5] +; CHECK: mrs x3, MVFR0_EL1 ; encoding: [0x03,0x03,0x38,0xd5] +; CHECK: mrs x3, MVFR1_EL1 ; encoding: [0x23,0x03,0x38,0xd5] +; CHECK: mrs x3, PAR_EL1 ; encoding: [0x03,0x74,0x38,0xd5] +; CHECK: mrs x3, RVBAR_EL1 ; encoding: [0x23,0xc0,0x38,0xd5] +; CHECK: mrs x3, RVBAR_EL2 ; encoding: [0x23,0xc0,0x3c,0xd5] +; CHECK: mrs x3, RVBAR_EL3 ; encoding: [0x23,0xc0,0x3e,0xd5] +; CHECK: mrs x3, SCR_EL3 ; encoding: [0x03,0x11,0x3e,0xd5] +; CHECK: mrs x3, SCTLR_EL1 ; encoding: [0x03,0x10,0x38,0xd5] +; CHECK: mrs x3, SCTLR_EL2 ; encoding: [0x03,0x10,0x3c,0xd5] +; CHECK: mrs x3, SCTLR_EL3 ; encoding: [0x03,0x10,0x3e,0xd5] +; CHECK: mrs x3, SDER32_EL3 ; encoding: [0x23,0x11,0x3e,0xd5] +; CHECK: mrs x3, TCR_EL1 ; encoding: [0x43,0x20,0x38,0xd5] +; CHECK: mrs x3, TCR_EL2 ; encoding: [0x43,0x20,0x3c,0xd5] +; CHECK: mrs x3, TCR_EL3 ; encoding: [0x43,0x20,0x3e,0xd5] +; CHECK: mrs x3, TEECR32_EL1 ; encoding: [0x03,0x00,0x32,0xd5] +; CHECK: mrs x3, TEEHBR32_EL1 ; encoding: [0x03,0x10,0x32,0xd5] +; CHECK: mrs x3, TPIDRRO_EL0 ; encoding: [0x63,0xd0,0x3b,0xd5] +; CHECK: mrs x3, TPIDR_EL0 ; encoding: [0x43,0xd0,0x3b,0xd5] +; CHECK: mrs x3, TPIDR_EL1 ; encoding: [0x83,0xd0,0x38,0xd5] +; CHECK: mrs x3, TPIDR_EL2 ; encoding: [0x43,0xd0,0x3c,0xd5] +; CHECK: mrs x3, TPIDR_EL3 ; encoding: [0x43,0xd0,0x3e,0xd5] +; CHECK: mrs x3, TTBR0_EL1 ; encoding: [0x03,0x20,0x38,0xd5] +; CHECK: mrs x3, TTBR0_EL2 ; encoding: [0x03,0x20,0x3c,0xd5] +; CHECK: mrs x3, TTBR0_EL3 ; encoding: [0x03,0x20,0x3e,0xd5] +; CHECK: mrs x3, TTBR1_EL1 ; encoding: [0x23,0x20,0x38,0xd5] +; CHECK: mrs x3, VBAR_EL1 ; encoding: [0x03,0xc0,0x38,0xd5] +; CHECK: mrs x3, VBAR_EL2 ; encoding: [0x03,0xc0,0x3c,0xd5] +; CHECK: mrs x3, VBAR_EL3 ; encoding: [0x03,0xc0,0x3e,0xd5] +; CHECK: mrs x3, VMPIDR_EL2 ; encoding: [0xa3,0x00,0x3c,0xd5] +; CHECK: mrs x3, VPIDR_EL2 ; encoding: [0x03,0x00,0x3c,0xd5] +; CHECK: mrs x3, VTCR_EL2 ; encoding: [0x43,0x21,0x3c,0xd5] +; CHECK: mrs x3, VTTBR_EL2 ; encoding: [0x03,0x21,0x3c,0xd5] +; CHECK: mrs x3, MDCCSR_EL0 ; encoding: [0x03,0x01,0x33,0xd5] +; CHECK: mrs x3, MDCCINT_EL1 ; encoding: [0x03,0x02,0x30,0xd5] +; CHECK: mrs x3, DBGDTR_EL0 ; encoding: [0x03,0x04,0x33,0xd5] +; CHECK: mrs x3, DBGDTRRX_EL0 ; encoding: [0x03,0x05,0x33,0xd5] +; CHECK: mrs x3, DBGVCR32_EL2 ; encoding: [0x03,0x07,0x34,0xd5] +; CHECK: mrs x3, OSDTRRX_EL1 ; encoding: [0x43,0x00,0x30,0xd5] +; CHECK: mrs x3, MDSCR_EL1 ; encoding: [0x43,0x02,0x30,0xd5] +; CHECK: mrs x3, OSDTRTX_EL1 ; encoding: [0x43,0x03,0x30,0xd5] +; CHECK: mrs x3, OSECCR_EL1 ; encoding: [0x43,0x06,0x30,0xd5] +; CHECK: mrs x3, DBGBVR0_EL1 ; encoding: [0x83,0x00,0x30,0xd5] +; CHECK: mrs x3, DBGBVR1_EL1 ; encoding: [0x83,0x01,0x30,0xd5] +; CHECK: mrs x3, DBGBVR2_EL1 ; encoding: [0x83,0x02,0x30,0xd5] +; CHECK: mrs x3, DBGBVR3_EL1 ; encoding: [0x83,0x03,0x30,0xd5] +; CHECK: mrs x3, DBGBVR4_EL1 ; encoding: [0x83,0x04,0x30,0xd5] +; CHECK: mrs x3, DBGBVR5_EL1 ; encoding: [0x83,0x05,0x30,0xd5] +; CHECK: mrs x3, DBGBVR6_EL1 ; encoding: [0x83,0x06,0x30,0xd5] +; CHECK: mrs x3, DBGBVR7_EL1 ; encoding: [0x83,0x07,0x30,0xd5] +; CHECK: mrs x3, DBGBVR8_EL1 ; encoding: [0x83,0x08,0x30,0xd5] +; CHECK: mrs x3, DBGBVR9_EL1 ; encoding: [0x83,0x09,0x30,0xd5] +; CHECK: mrs x3, DBGBVR10_EL1 ; encoding: [0x83,0x0a,0x30,0xd5] +; CHECK: mrs x3, DBGBVR11_EL1 ; encoding: [0x83,0x0b,0x30,0xd5] +; CHECK: mrs x3, DBGBVR12_EL1 ; encoding: [0x83,0x0c,0x30,0xd5] +; CHECK: mrs x3, DBGBVR13_EL1 ; encoding: [0x83,0x0d,0x30,0xd5] +; CHECK: mrs x3, DBGBVR14_EL1 ; encoding: [0x83,0x0e,0x30,0xd5] +; CHECK: mrs x3, DBGBVR15_EL1 ; encoding: [0x83,0x0f,0x30,0xd5] +; CHECK: mrs x3, DBGBCR0_EL1 ; encoding: [0xa3,0x00,0x30,0xd5] +; CHECK: mrs x3, DBGBCR1_EL1 ; encoding: [0xa3,0x01,0x30,0xd5] +; CHECK: mrs x3, DBGBCR2_EL1 ; encoding: [0xa3,0x02,0x30,0xd5] +; CHECK: mrs x3, DBGBCR3_EL1 ; encoding: [0xa3,0x03,0x30,0xd5] +; CHECK: mrs x3, DBGBCR4_EL1 ; encoding: [0xa3,0x04,0x30,0xd5] +; CHECK: mrs x3, DBGBCR5_EL1 ; encoding: [0xa3,0x05,0x30,0xd5] +; CHECK: mrs x3, DBGBCR6_EL1 ; encoding: [0xa3,0x06,0x30,0xd5] +; CHECK: mrs x3, DBGBCR7_EL1 ; encoding: [0xa3,0x07,0x30,0xd5] +; CHECK: mrs x3, DBGBCR8_EL1 ; encoding: [0xa3,0x08,0x30,0xd5] +; CHECK: mrs x3, DBGBCR9_EL1 ; encoding: [0xa3,0x09,0x30,0xd5] +; CHECK: mrs x3, DBGBCR10_EL1 ; encoding: [0xa3,0x0a,0x30,0xd5] +; CHECK: mrs x3, DBGBCR11_EL1 ; encoding: [0xa3,0x0b,0x30,0xd5] +; CHECK: mrs x3, DBGBCR12_EL1 ; encoding: [0xa3,0x0c,0x30,0xd5] +; CHECK: mrs x3, DBGBCR13_EL1 ; encoding: [0xa3,0x0d,0x30,0xd5] +; CHECK: mrs x3, DBGBCR14_EL1 ; encoding: [0xa3,0x0e,0x30,0xd5] +; CHECK: mrs x3, DBGBCR15_EL1 ; encoding: [0xa3,0x0f,0x30,0xd5] +; CHECK: mrs x3, DBGWVR0_EL1 ; encoding: [0xc3,0x00,0x30,0xd5] +; CHECK: mrs x3, DBGWVR1_EL1 ; encoding: [0xc3,0x01,0x30,0xd5] +; CHECK: mrs x3, DBGWVR2_EL1 ; encoding: [0xc3,0x02,0x30,0xd5] +; CHECK: mrs x3, DBGWVR3_EL1 ; encoding: [0xc3,0x03,0x30,0xd5] +; CHECK: mrs x3, DBGWVR4_EL1 ; encoding: [0xc3,0x04,0x30,0xd5] +; CHECK: mrs x3, DBGWVR5_EL1 ; encoding: [0xc3,0x05,0x30,0xd5] +; CHECK: mrs x3, DBGWVR6_EL1 ; encoding: [0xc3,0x06,0x30,0xd5] +; CHECK: mrs x3, DBGWVR7_EL1 ; encoding: [0xc3,0x07,0x30,0xd5] +; CHECK: mrs x3, DBGWVR8_EL1 ; encoding: [0xc3,0x08,0x30,0xd5] +; CHECK: mrs x3, DBGWVR9_EL1 ; encoding: [0xc3,0x09,0x30,0xd5] +; CHECK: mrs x3, DBGWVR10_EL1 ; encoding: [0xc3,0x0a,0x30,0xd5] +; CHECK: mrs x3, DBGWVR11_EL1 ; encoding: [0xc3,0x0b,0x30,0xd5] +; CHECK: mrs x3, DBGWVR12_EL1 ; encoding: [0xc3,0x0c,0x30,0xd5] +; CHECK: mrs x3, DBGWVR13_EL1 ; encoding: [0xc3,0x0d,0x30,0xd5] +; CHECK: mrs x3, DBGWVR14_EL1 ; encoding: [0xc3,0x0e,0x30,0xd5] +; CHECK: mrs x3, DBGWVR15_EL1 ; encoding: [0xc3,0x0f,0x30,0xd5] +; CHECK: mrs x3, DBGWCR0_EL1 ; encoding: [0xe3,0x00,0x30,0xd5] +; CHECK: mrs x3, DBGWCR1_EL1 ; encoding: [0xe3,0x01,0x30,0xd5] +; CHECK: mrs x3, DBGWCR2_EL1 ; encoding: [0xe3,0x02,0x30,0xd5] +; CHECK: mrs x3, DBGWCR3_EL1 ; encoding: [0xe3,0x03,0x30,0xd5] +; CHECK: mrs x3, DBGWCR4_EL1 ; encoding: [0xe3,0x04,0x30,0xd5] +; CHECK: mrs x3, DBGWCR5_EL1 ; encoding: [0xe3,0x05,0x30,0xd5] +; CHECK: mrs x3, DBGWCR6_EL1 ; encoding: [0xe3,0x06,0x30,0xd5] +; CHECK: mrs x3, DBGWCR7_EL1 ; encoding: [0xe3,0x07,0x30,0xd5] +; CHECK: mrs x3, DBGWCR8_EL1 ; encoding: [0xe3,0x08,0x30,0xd5] +; CHECK: mrs x3, DBGWCR9_EL1 ; encoding: [0xe3,0x09,0x30,0xd5] +; CHECK: mrs x3, DBGWCR10_EL1 ; encoding: [0xe3,0x0a,0x30,0xd5] +; CHECK: mrs x3, DBGWCR11_EL1 ; encoding: [0xe3,0x0b,0x30,0xd5] +; CHECK: mrs x3, DBGWCR12_EL1 ; encoding: [0xe3,0x0c,0x30,0xd5] +; CHECK: mrs x3, DBGWCR13_EL1 ; encoding: [0xe3,0x0d,0x30,0xd5] +; CHECK: mrs x3, DBGWCR14_EL1 ; encoding: [0xe3,0x0e,0x30,0xd5] +; CHECK: mrs x3, DBGWCR15_EL1 ; encoding: [0xe3,0x0f,0x30,0xd5] +; CHECK: mrs x3, MDRAR_EL1 ; encoding: [0x03,0x10,0x30,0xd5] +; CHECK: mrs x3, OSLSR_EL1 ; encoding: [0x83,0x11,0x30,0xd5] +; CHECK: mrs x3, OSDLR_EL1 ; encoding: [0x83,0x13,0x30,0xd5] +; CHECK: mrs x3, DBGPRCR_EL1 ; encoding: [0x83,0x14,0x30,0xd5] +; CHECK: mrs x3, DBGCLAIMSET_EL1 ; encoding: [0xc3,0x78,0x30,0xd5] +; CHECK: mrs x3, DBGCLAIMCLR_EL1 ; encoding: [0xc3,0x79,0x30,0xd5] +; CHECK: mrs x3, DBGAUTHSTATUS_EL1 ; encoding: [0xc3,0x7e,0x30,0xd5] +; CHECK: mrs x1, S3_2_C15_C6_4 ; encoding: [0x81,0xf6,0x3a,0xd5] +; CHECK: mrs x3, S3_3_C11_C1_4 ; encoding: [0x83,0xb1,0x3b,0xd5] +; CHECK: mrs x3, S3_3_C11_C1_4 ; encoding: [0x83,0xb1,0x3b,0xd5] + + msr RMR_EL3, x0 + msr RMR_EL2, x0 + msr RMR_EL1, x0 + msr OSLAR_EL1, x3 + msr DBGDTRTX_EL0, x3 + +; CHECK: msr RMR_EL3, x0 ; encoding: [0x40,0xc0,0x1e,0xd5] +; CHECK: msr RMR_EL2, x0 ; encoding: [0x40,0xc0,0x1c,0xd5] +; CHECK: msr RMR_EL1, x0 ; encoding: [0x40,0xc0,0x18,0xd5] +; CHECK: msr OSLAR_EL1, x3 ; encoding: [0x83,0x10,0x10,0xd5] +; CHECK: msr DBGDTRTX_EL0, x3 ; encoding: [0x03,0x05,0x13,0xd5] + + mrs x0, ID_PFR0_EL1 + mrs x0, ID_PFR1_EL1 + mrs x0, ID_DFR0_EL1 + mrs x0, ID_AFR0_EL1 + mrs x0, ID_ISAR0_EL1 + mrs x0, ID_ISAR1_EL1 + mrs x0, ID_ISAR2_EL1 + mrs x0, ID_ISAR3_EL1 + mrs x0, ID_ISAR4_EL1 + mrs x0, ID_ISAR5_EL1 + mrs x0, AFSR1_EL1 + mrs x0, AFSR0_EL1 + mrs x0, REVIDR_EL1 +; CHECK: mrs x0, ID_PFR0_EL1 ; encoding: [0x00,0x01,0x38,0xd5] +; CHECK: mrs x0, ID_PFR1_EL1 ; encoding: [0x20,0x01,0x38,0xd5] +; CHECK: mrs x0, ID_DFR0_EL1 ; encoding: [0x40,0x01,0x38,0xd5] +; CHECK: mrs x0, ID_AFR0_EL1 ; encoding: [0x60,0x01,0x38,0xd5] +; CHECK: mrs x0, ID_ISAR0_EL1 ; encoding: [0x00,0x02,0x38,0xd5] +; CHECK: mrs x0, ID_ISAR1_EL1 ; encoding: [0x20,0x02,0x38,0xd5] +; CHECK: mrs x0, ID_ISAR2_EL1 ; encoding: [0x40,0x02,0x38,0xd5] +; CHECK: mrs x0, ID_ISAR3_EL1 ; encoding: [0x60,0x02,0x38,0xd5] +; CHECK: mrs x0, ID_ISAR4_EL1 ; encoding: [0x80,0x02,0x38,0xd5] +; CHECK: mrs x0, ID_ISAR5_EL1 ; encoding: [0xa0,0x02,0x38,0xd5] +; CHECK: mrs x0, AFSR1_EL1 ; encoding: [0x20,0x51,0x38,0xd5] +; CHECK: mrs x0, AFSR0_EL1 ; encoding: [0x00,0x51,0x38,0xd5] +; CHECK: mrs x0, REVIDR_EL1 ; encoding: [0xc0,0x00,0x38,0xd5] diff --git a/test/MC/AArch64/arm64-target-specific-sysreg.s b/test/MC/AArch64/arm64-target-specific-sysreg.s new file mode 100644 index 0000000..05cea3a --- /dev/null +++ b/test/MC/AArch64/arm64-target-specific-sysreg.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple arm64 -mcpu=generic -show-encoding < %s 2>&1 | \ +// RUN: FileCheck %s --check-prefix=CHECK-GENERIC +// +// RUN: llvm-mc -triple arm64 -mcpu=cyclone -show-encoding < %s 2>&1 | \ +// RUN: FileCheck %s --check-prefix=CHECK-CYCLONE + +msr CPM_IOACC_CTL_EL3, x0 + +// CHECK-GENERIC: error: expected writable system register or pstate +// CHECK-CYCLONE: msr CPM_IOACC_CTL_EL3, x0 // encoding: [0x00,0xf2,0x1f,0xd5] diff --git a/test/MC/AArch64/arm64-tls-modifiers-darwin.s b/test/MC/AArch64/arm64-tls-modifiers-darwin.s new file mode 100644 index 0000000..8ff07cd --- /dev/null +++ b/test/MC/AArch64/arm64-tls-modifiers-darwin.s @@ -0,0 +1,13 @@ +; RUN: llvm-mc -triple=arm64-apple-ios7.0 %s -o - | FileCheck %s +; RUN: llvm-mc -triple=arm64-apple-ios7.0 -filetype=obj %s -o - | llvm-objdump -r - | FileCheck %s --check-prefix=CHECK-OBJ + + adrp x2, _var@TLVPPAGE + ldr x0, [x15, _var@TLVPPAGEOFF] + add x30, x0, _var@TLVPPAGEOFF +; CHECK: adrp x2, _var@TLVPPAG +; CHECK: ldr x0, [x15, _var@TLVPPAGEOFF] +; CHECK: add x30, x0, _var@TLVPPAGEOFF + +; CHECK-OBJ: 8 ARM64_RELOC_TLVP_LOAD_PAGEOFF12 _var +; CHECK-OBJ: 4 ARM64_RELOC_TLVP_LOAD_PAGEOFF12 _var +; CHECK-OBJ: 0 ARM64_RELOC_TLVP_LOAD_PAGE21 _var diff --git a/test/MC/AArch64/arm64-tls-relocs.s b/test/MC/AArch64/arm64-tls-relocs.s new file mode 100644 index 0000000..96c2b55 --- /dev/null +++ b/test/MC/AArch64/arm64-tls-relocs.s @@ -0,0 +1,320 @@ +// RUN: llvm-mc -triple=arm64-none-linux-gnu -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s -o - | \ +// RUN: llvm-readobj -r -t | FileCheck --check-prefix=CHECK-ELF %s + + +//////////////////////////////////////////////////////////////////////////////// +// TLS initial-exec forms +//////////////////////////////////////////////////////////////////////////////// + + movz x15, #:gottprel_g1:var +// CHECK: movz x15, #:gottprel_g1:var // encoding: [0bAAA01111,A,0b101AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_aarch64_movw + +// CHECK-ELF: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM:[^ ]+]] + + + movk x13, #:gottprel_g0_nc:var +// CHECK: movk x13, #:gottprel_g0_nc:var // encoding: [0bAAA01101,A,0b100AAAAA,0xf2] +// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_aarch64_movw + + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]] + + adrp x11, :gottprel:var + ldr x10, [x0, #:gottprel_lo12:var] + ldr x9, :gottprel:var +// CHECK: adrp x11, :gottprel:var // encoding: [0x0b'A',A,A,0x90'A'] +// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_pcrel_adrp_imm21 +// CHECK: ldr x10, [x0, :gottprel_lo12:var] // encoding: [0x0a,0bAAAAAA00,0b01AAAAAA,0xf9] +// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: ldr x9, :gottprel:var // encoding: [0bAAA01001,A,A,0x58] +// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_ldr_pcrel_imm19 + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 [[VARSYM]] + + +//////////////////////////////////////////////////////////////////////////////// +// TLS local-exec forms +//////////////////////////////////////////////////////////////////////////////// + + movz x3, #:tprel_g2:var + movn x4, #:tprel_g2:var +// CHECK: movz x3, #:tprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_aarch64_movw +// CHECK: movn x4, #:tprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_aarch64_movw + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]] + + + movz x5, #:tprel_g1:var + movn x6, #:tprel_g1:var + movz w7, #:tprel_g1:var +// CHECK: movz x5, #:tprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movn x6, #:tprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movz w7, #:tprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]] + + + movk x9, #:tprel_g1_nc:var + movk w10, #:tprel_g1_nc:var +// CHECK: movk x9, #:tprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_aarch64_movw +// CHECK: movk w10, #:tprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_aarch64_movw + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]] + + + movz x11, #:tprel_g0:var + movn x12, #:tprel_g0:var + movz w13, #:tprel_g0:var +// CHECK: movz x11, #:tprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movn x12, #:tprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movz w13, #:tprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]] + + + movk x15, #:tprel_g0_nc:var + movk w16, #:tprel_g0_nc:var +// CHECK: movk x15, #:tprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw +// CHECK: movk w16, #:tprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]] + + + add x21, x22, #:tprel_lo12:var +// CHECK: add x21, x22, :tprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_add_imm12 + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]] + + + add x25, x26, #:tprel_lo12_nc:var +// CHECK: add x25, x26, :tprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_add_imm12 + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]] + + + ldrb w29, [x30, #:tprel_lo12:var] + ldrsb x29, [x28, #:tprel_lo12_nc:var] +// CHECK: ldrb w29, [x30, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1 +// CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1 + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST8_TPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC [[VARSYM]] + + + strh w27, [x26, #:tprel_lo12:var] + ldrsh x25, [x24, #:tprel_lo12_nc:var] +// CHECK: strh w27, [x26, :tprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2 +// CHECK: ldrsh x25, [x24, :tprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2 + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST16_TPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC [[VARSYM]] + + + ldr w23, [x22, #:tprel_lo12:var] + ldrsw x21, [x20, #:tprel_lo12_nc:var] +// CHECK: ldr w23, [x22, :tprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4 +// CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4 + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST32_TPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC [[VARSYM]] + + ldr x19, [x18, #:tprel_lo12:var] + str x17, [x16, #:tprel_lo12_nc:var] +// CHECK: ldr x19, [x18, :tprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: str x17, [x16, :tprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8 + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST64_TPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC [[VARSYM]] + + +//////////////////////////////////////////////////////////////////////////////// +// TLS local-dynamic forms +//////////////////////////////////////////////////////////////////////////////// + + movz x3, #:dtprel_g2:var + movn x4, #:dtprel_g2:var +// CHECK: movz x3, #:dtprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw +// CHECK: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] + + + movz x5, #:dtprel_g1:var + movn x6, #:dtprel_g1:var + movz w7, #:dtprel_g1:var +// CHECK: movz x5, #:dtprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movz w7, #:dtprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] + + + movk x9, #:dtprel_g1_nc:var + movk w10, #:dtprel_g1_nc:var +// CHECK: movk x9, #:dtprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_aarch64_movw +// CHECK: movk w10, #:dtprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_aarch64_movw + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]] + + + movz x11, #:dtprel_g0:var + movn x12, #:dtprel_g0:var + movz w13, #:dtprel_g0:var +// CHECK: movz x11, #:dtprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movn x12, #:dtprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movz w13, #:dtprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] + + + movk x15, #:dtprel_g0_nc:var + movk w16, #:dtprel_g0_nc:var +// CHECK: movk x15, #:dtprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw +// CHECK: movk w16, #:dtprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]] + + + add x21, x22, #:dtprel_lo12:var +// CHECK: add x21, x22, :dtprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_add_imm12 + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]] + + + add x25, x26, #:dtprel_lo12_nc:var +// CHECK: add x25, x26, :dtprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_add_imm12 + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]] + + + ldrb w29, [x30, #:dtprel_lo12:var] + ldrsb x29, [x28, #:dtprel_lo12_nc:var] +// CHECK: ldrb w29, [x30, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1 +// CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1 + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC [[VARSYM]] + + + strh w27, [x26, #:dtprel_lo12:var] + ldrsh x25, [x24, #:dtprel_lo12_nc:var] +// CHECK: strh w27, [x26, :dtprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2 +// CHECK: ldrsh x25, [x24, :dtprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2 + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST16_DTPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC [[VARSYM]] + + + ldr w23, [x22, #:dtprel_lo12:var] + ldrsw x21, [x20, #:dtprel_lo12_nc:var] +// CHECK: ldr w23, [x22, :dtprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4 +// CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4 + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST32_DTPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC [[VARSYM]] + + ldr x19, [x18, #:dtprel_lo12:var] + str x17, [x16, #:dtprel_lo12_nc:var] +// CHECK: ldr x19, [x18, :dtprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: str x17, [x16, :dtprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8 + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST64_DTPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC [[VARSYM]] + +//////////////////////////////////////////////////////////////////////////////// +// TLS descriptor forms +//////////////////////////////////////////////////////////////////////////////// + + adrp x8, :tlsdesc:var + ldr x7, [x6, #:tlsdesc_lo12:var] + add x5, x4, #:tlsdesc_lo12:var + .tlsdesccall var + blr x3 + +// CHECK: adrp x8, :tlsdesc:var // encoding: [0x08'A',A,A,0x90'A'] +// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_aarch64_pcrel_adrp_imm21 +// CHECK: ldr x7, [x6, :tlsdesc_lo12:var] // encoding: [0xc7,0bAAAAAA00,0b01AAAAAA,0xf9] +// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: add x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91] +// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_add_imm12 +// CHECK: .tlsdesccall var // encoding: [] +// CHECK-NEXT: // fixup A - offset: 0, value: var, kind: fixup_aarch64_tlsdesc_call +// CHECK: blr x3 // encoding: [0x60,0x00,0x3f,0xd6] + + +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_ADR_PAGE [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_LD64_LO12_NC [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_ADD_LO12_NC [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_CALL [[VARSYM]] + + // Make sure symbol 5 has type STT_TLS: + +// CHECK-ELF: Symbols [ +// CHECK-ELF: Symbol { +// CHECK-ELF: Name: var +// CHECK-ELF-NEXT: Value: +// CHECK-ELF-NEXT: Size: +// CHECK-ELF-NEXT: Binding: Global +// CHECK-ELF-NEXT: Type: TLS diff --git a/test/MC/AArch64/arm64-v128_lo-diagnostics.s b/test/MC/AArch64/arm64-v128_lo-diagnostics.s new file mode 100644 index 0000000..ffe29cf --- /dev/null +++ b/test/MC/AArch64/arm64-v128_lo-diagnostics.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple arm64 -mattr=neon %s 2> %t > /dev/null +// RUN: FileCheck %s < %t + + sqrdmulh v0.8h, v1.8h, v16.h[0] +// CHECK: error: invalid operand for instruction + + sqrdmulh h0, h1, v16.h[0] +// CHECK: error: invalid operand for instruction + + sqdmull2 v0.4h, v1.8h, v16.h[0] +// CHECK: error: invalid operand for instruction diff --git a/test/MC/AArch64/arm64-variable-exprs.s b/test/MC/AArch64/arm64-variable-exprs.s new file mode 100644 index 0000000..0120442 --- /dev/null +++ b/test/MC/AArch64/arm64-variable-exprs.s @@ -0,0 +1,40 @@ +// RUN: llvm-mc -triple arm64-apple-darwin10 %s -filetype=obj -o %t.o + +.data + + .long 0 +a: + .long 0 +b = a + +c: .long b + +d2 = d +.globl d2 +d3 = d + 4 +.globl d3 + +e = a + 4 + +g: +f = g + .long 0 + + .long b + .long e + .long a + 4 + .long d + .long d2 + .long d3 + .long f + .long g + +/// + .text +t0: +Lt0_a: + .long 0 + + .section __DWARF,__debug_frame,regular,debug +Lt1 = Lt0_a + .long Lt1 diff --git a/test/MC/AArch64/arm64-vector-lists.s b/test/MC/AArch64/arm64-vector-lists.s new file mode 100644 index 0000000..a9b2d19 --- /dev/null +++ b/test/MC/AArch64/arm64-vector-lists.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple arm64 -mattr=neon -show-encoding < %s 2>%t | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + + ST4 {v0.8B-v3.8B}, [x0] + ST4 {v0.4H-v3.4H}, [x0] + +// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x00,0x0c] +// CHECK: st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0] // encoding: [0x00,0x04,0x00,0x0c] + + ST4 {v0.8B-v4.8B}, [x0] + ST4 {v0.8B-v3.8B,v4.8B}, [x0] + ST4 {v0.8B-v3.8H}, [x0] + ST4 {v0.8B-v3.16B}, [x0] + ST4 {v0.8B-},[x0] + +// CHECK-ERRORS: error: invalid number of vectors +// CHECK-ERRORS: error: '}' expected +// CHECK-ERRORS: error: mismatched register size suffix +// CHECK-ERRORS: error: mismatched register size suffix +// CHECK-ERRORS: error: vector register expected diff --git a/test/MC/AArch64/arm64-verbose-vector-case.s b/test/MC/AArch64/arm64-verbose-vector-case.s new file mode 100644 index 0000000..6f0a381 --- /dev/null +++ b/test/MC/AArch64/arm64-verbose-vector-case.s @@ -0,0 +1,19 @@ +// RUN: llvm-mc -triple arm64 -mattr=crypto -show-encoding < %s | FileCheck %s + +pmull v8.8h, v8.8b, v8.8b +pmull2 v8.8h, v8.16b, v8.16b +pmull v8.1q, v8.1d, v8.1d +pmull2 v8.1q, v8.2d, v8.2d +// CHECK: pmull v8.8h, v8.8b, v8.8b // encoding: [0x08,0xe1,0x28,0x0e] +// CHECK: pmull2 v8.8h, v8.16b, v8.16b // encoding: [0x08,0xe1,0x28,0x4e] +// CHECK: pmull v8.1q, v8.1d, v8.1d // encoding: [0x08,0xe1,0xe8,0x0e] +// CHECK: pmull2 v8.1q, v8.2d, v8.2d // encoding: [0x08,0xe1,0xe8,0x4e] + +pmull v8.8H, v8.8B, v8.8B +pmull2 v8.8H, v8.16B, v8.16B +pmull v8.1Q, v8.1D, v8.1D +pmull2 v8.1Q, v8.2D, v8.2D +// CHECK: pmull v8.8h, v8.8b, v8.8b // encoding: [0x08,0xe1,0x28,0x0e] +// CHECK: pmull2 v8.8h, v8.16b, v8.16b // encoding: [0x08,0xe1,0x28,0x4e] +// CHECK: pmull v8.1q, v8.1d, v8.1d // encoding: [0x08,0xe1,0xe8,0x0e] +// CHECK: pmull2 v8.1q, v8.2d, v8.2d // encoding: [0x08,0xe1,0xe8,0x4e] diff --git a/test/MC/AArch64/basic-a64-diagnostics.s b/test/MC/AArch64/basic-a64-diagnostics.s index 792538c..a4a3b13 100644 --- a/test/MC/AArch64/basic-a64-diagnostics.s +++ b/test/MC/AArch64/basic-a64-diagnostics.s @@ -1,5 +1,5 @@ // RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s +// RUN: FileCheck --check-prefix=CHECK-ERROR --check-prefix=CHECK-ERROR-ARM64 < %t %s //------------------------------------------------------------------------------ // Add/sub (extended register) @@ -83,9 +83,9 @@ // CHECK-ERROR: error: expected compatible register, symbol or integer in range [0, 4095] // CHECK-ERROR-NEXT: add w4, w5, #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected compatible register, symbol or integer in range [0, 4095] -// CHECK-ERROR-NEXT: add w5, w6, #0x1000 -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: expected compatible register, symbol or integer in range [0, 4095] +// CHECK-ERROR-AARCH64-NEXT: add w5, w6, #0x1000 +// CHECK-ERROR-AARCH64-NEXT: ^ // CHECK-ERROR-NEXT: error: expected compatible register, symbol or integer in range [0, 4095] // CHECK-ERROR-NEXT: add w4, w5, #-1, lsl #12 // CHECK-ERROR-NEXT: ^ @@ -141,9 +141,9 @@ // Out of range immediate adds w0, w5, #0x10000 -// CHECK-ERROR: error: expected compatible register, symbol or integer in range [0, 4095] -// CHECK-ERROR-NEXT: adds w0, w5, #0x10000 -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-AARCH64: error: expected compatible register, symbol or integer in range [0, 4095] +// CHECK-ERROR-AARCH64-NEXT: adds w0, w5, #0x10000 +// CHECK-ERROR-AARCH64-NEXT: ^ // Wn|WSP should be in second place adds w4, wzr, #0x123 @@ -750,10 +750,10 @@ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: sbfm w3, wsp, #1, #9 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: sbfm x9, x5, #-1, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: sbfm x9, x5, #0, #-1 // CHECK-ERROR-NEXT: ^ @@ -761,16 +761,16 @@ sbfm w7, w11, #19, #32 sbfm x29, x30, #64, #0 sbfm x10, x20, #63, #64 -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: sbfm w3, w5, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: sbfm w7, w11, #19, #32 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: sbfm x29, x30, #64, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: sbfm x10, x20, #63, #64 // CHECK-ERROR-NEXT: ^ @@ -778,16 +778,16 @@ ubfm w7, w11, #19, #32 ubfm x29, x30, #64, #0 ubfm x10, x20, #63, #64 -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ubfm w3, w5, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ubfm w7, w11, #19, #32 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: ubfm x29, x30, #64, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: ubfm x10, x20, #63, #64 // CHECK-ERROR-NEXT: ^ @@ -795,31 +795,31 @@ bfm w7, w11, #19, #32 bfm x29, x30, #64, #0 bfm x10, x20, #63, #64 -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: bfm w3, w5, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: bfm w7, w11, #19, #32 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: bfm x29, x30, #64, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: bfm x10, x20, #63, #64 // CHECK-ERROR-NEXT: ^ sxtb x3, x2 sxth xzr, xzr sxtw x3, x5 -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR-NEXT: sxtb x3, x2 -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: sxth xzr, xzr -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: sxtw x3, x5 -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-AARCH64: error: invalid operand for instruction +// CHECK-ERROR-AARCH64-NEXT: sxtb x3, x2 +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: invalid operand for instruction +// CHECK-ERROR-AARCH64-NEXT: sxth xzr, xzr +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: invalid operand for instruction +// CHECK-ERROR-AARCH64-NEXT: sxtw x3, x5 +// CHECK-ERROR-AARCH64-NEXT: ^ uxtb x3, x12 uxth x5, x9 @@ -832,9 +832,9 @@ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: uxth x5, x9 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid instruction -// CHECK-ERROR-NEXT: uxtw x3, x5 -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: invalid instruction +// CHECK-ERROR-AARCH64-NEXT: uxtw x3, x5 +// CHECK-ERROR-AARCH64-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: uxtb x2, sp // CHECK-ERROR-NEXT: ^ @@ -853,13 +853,13 @@ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: asr sp, x2, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: asr x25, x26, #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: asr x25, x26, #64 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: asr w9, w8, #32 // CHECK-ERROR-NEXT: ^ @@ -869,18 +869,19 @@ sbfiz w11, w12, #32, #0 sbfiz w9, w10, #10, #23 sbfiz x3, x5, #12, #53 - sbfiz sp, x3, #5, #6 - sbfiz w3, wsp, #7, #8 -// CHECK-ERROR: error: expected integer in range [<lsb>, 31] + sbfiz sp, x3, #7, #6 + sbfiz w3, wsp, #10, #8 +// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: sbfiz w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: sbfiz wsp, w9, #0, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: sbfiz w9, w10, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: sbfiz w11, w12, #32, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: requested insert overflows register @@ -890,10 +891,10 @@ // CHECK-ERROR-NEXT: sbfiz x3, x5, #12, #53 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: sbfiz sp, x3, #5, #6 +// CHECK-ERROR-NEXT: sbfiz sp, x3, #7, #6 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: sbfiz w3, wsp, #7, #8 +// CHECK-ERROR-NEXT: sbfiz w3, wsp, #10, #8 // CHECK-ERROR-NEXT: ^ sbfx w1, w2, #0, #0 @@ -902,18 +903,19 @@ sbfx w11, w12, #32, #0 sbfx w9, w10, #10, #23 sbfx x3, x5, #12, #53 - sbfx sp, x3, #5, #6 - sbfx w3, wsp, #7, #8 -// CHECK-ERROR: error: expected integer in range [<lsb>, 31] + sbfx sp, x3, #7, #6 + sbfx w3, wsp, #10, #8 +// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: sbfx w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: sbfx wsp, w9, #0, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: sbfx w9, w10, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: sbfx w11, w12, #32, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: requested extract overflows register @@ -923,10 +925,10 @@ // CHECK-ERROR-NEXT: sbfx x3, x5, #12, #53 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: sbfx sp, x3, #5, #6 +// CHECK-ERROR-NEXT: sbfx sp, x3, #7, #6 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: sbfx w3, wsp, #7, #8 +// CHECK-ERROR-NEXT: sbfx w3, wsp, #10, #8 // CHECK-ERROR-NEXT: ^ bfi w1, w2, #0, #0 @@ -935,18 +937,19 @@ bfi w11, w12, #32, #0 bfi w9, w10, #10, #23 bfi x3, x5, #12, #53 - bfi sp, x3, #5, #6 - bfi w3, wsp, #7, #8 -// CHECK-ERROR: error: expected integer in range [<lsb>, 31] + bfi sp, x3, #7, #6 + bfi w3, wsp, #10, #8 +// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: bfi w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: bfi wsp, w9, #0, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: bfi w9, w10, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: bfi w11, w12, #32, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: requested insert overflows register @@ -956,10 +959,10 @@ // CHECK-ERROR-NEXT: bfi x3, x5, #12, #53 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: bfi sp, x3, #5, #6 +// CHECK-ERROR-NEXT: bfi sp, x3, #7, #6 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: bfi w3, wsp, #7, #8 +// CHECK-ERROR-NEXT: bfi w3, wsp, #10, #8 // CHECK-ERROR-NEXT: ^ bfxil w1, w2, #0, #0 @@ -968,18 +971,19 @@ bfxil w11, w12, #32, #0 bfxil w9, w10, #10, #23 bfxil x3, x5, #12, #53 - bfxil sp, x3, #5, #6 - bfxil w3, wsp, #7, #8 -// CHECK-ERROR: error: expected integer in range [<lsb>, 31] + bfxil sp, x3, #7, #6 + bfxil w3, wsp, #10, #8 +// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: bfxil w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: bfxil wsp, w9, #0, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: bfxil w9, w10, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: bfxil w11, w12, #32, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: requested extract overflows register @@ -989,10 +993,10 @@ // CHECK-ERROR-NEXT: bfxil x3, x5, #12, #53 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: bfxil sp, x3, #5, #6 +// CHECK-ERROR-NEXT: bfxil sp, x3, #7, #6 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: bfxil w3, wsp, #7, #8 +// CHECK-ERROR-NEXT: bfxil w3, wsp, #10, #8 // CHECK-ERROR-NEXT: ^ ubfiz w1, w2, #0, #0 @@ -1001,18 +1005,19 @@ ubfiz w11, w12, #32, #0 ubfiz w9, w10, #10, #23 ubfiz x3, x5, #12, #53 - ubfiz sp, x3, #5, #6 - ubfiz w3, wsp, #7, #8 -// CHECK-ERROR: error: expected integer in range [<lsb>, 31] + ubfiz sp, x3, #7, #6 + ubfiz w3, wsp, #10, #8 +// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: ubfiz w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ubfiz wsp, w9, #0, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ubfiz w9, w10, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ubfiz w11, w12, #32, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: requested insert overflows register @@ -1022,10 +1027,10 @@ // CHECK-ERROR-NEXT: ubfiz x3, x5, #12, #53 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: ubfiz sp, x3, #5, #6 +// CHECK-ERROR-NEXT: ubfiz sp, x3, #7, #6 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: ubfiz w3, wsp, #7, #8 +// CHECK-ERROR-NEXT: ubfiz w3, wsp, #10, #8 // CHECK-ERROR-NEXT: ^ ubfx w1, w2, #0, #0 @@ -1034,18 +1039,19 @@ ubfx w11, w12, #32, #0 ubfx w9, w10, #10, #23 ubfx x3, x5, #12, #53 - ubfx sp, x3, #5, #6 - ubfx w3, wsp, #7, #8 -// CHECK-ERROR: error: expected integer in range [<lsb>, 31] + ubfx sp, x3, #7, #6 + ubfx w3, wsp, #10, #8 +// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: ubfx w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ubfx wsp, w9, #0, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ubfx w9, w10, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ubfx w11, w12, #32, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: requested extract overflows register @@ -1055,10 +1061,10 @@ // CHECK-ERROR-NEXT: ubfx x3, x5, #12, #53 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: ubfx sp, x3, #5, #6 +// CHECK-ERROR-NEXT: ubfx sp, x3, #7, #6 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: ubfx w3, wsp, #7, #8 +// CHECK-ERROR-NEXT: ubfx w3, wsp, #10, #8 // CHECK-ERROR-NEXT: ^ //------------------------------------------------------------------------------ @@ -1125,16 +1131,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmp wsp, #4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmp w25, #-1, #15, hs // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmp w3, #32, #0, ge // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp w19, #5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp w20, #7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1146,16 +1152,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmp sp, #4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmp x25, #-1, #15, hs // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmp x3, #32, #0, ge // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp x19, #5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp x20, #7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1167,16 +1173,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmn wsp, #4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmn w25, #-1, #15, hs // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmn w3, #32, #0, ge // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn w19, #5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn w20, #7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1188,16 +1194,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmn sp, #4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmn x25, #-1, #15, hs // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmn x3, #32, #0, ge // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn x19, #5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn x20, #7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1212,13 +1218,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmp wsp, w4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmp w3, wsp, #0, ge // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp w19, w5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp w20, w7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1229,13 +1235,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmp sp, x4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmp x25, sp, #15, hs // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp x19, x5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp x20, x7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1246,13 +1252,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmn wsp, w4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmn w25, wsp, #15, hs // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn w19, w5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn w20, w7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1263,13 +1269,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmn sp, x4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmn x25, sp, #15, hs // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn x19, x5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn x20, x7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1418,16 +1424,16 @@ hlt #65536 dcps4 #43 dcps4 -// CHECK-ERROR: error: expected integer in range [0, 65535] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: svc #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: hlt #65536 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid instruction +// CHECK-ERROR-NEXT: error: {{invalid instruction|unrecognized instruction mnemonic}} // CHECK-ERROR-NEXT: dcps4 #43 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid instruction +// CHECK-ERROR-NEXT: error: {{invalid instruction|unrecognized instruction mnemonic}} // CHECK-ERROR-NEXT: dcps4 // CHECK-ERROR-NEXT: ^ @@ -1437,28 +1443,28 @@ extr w2, w20, w30, #-1 extr w9, w19, w20, #32 -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: extr w2, w20, w30, #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: extr w9, w19, w20, #32 // CHECK-ERROR-NEXT: ^ extr x10, x15, x20, #-1 extr x20, x25, x30, #64 -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: extr x10, x15, x20, #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: extr x20, x25, x30, #64 // CHECK-ERROR-NEXT: ^ ror w9, w10, #32 ror x10, x11, #64 -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ror w9, w10, #32 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: ror x10, x11, #64 // CHECK-ERROR-NEXT: ^ @@ -1467,7 +1473,8 @@ //------------------------------------------------------------------------------ fcmp s3, d2 -// CHECK-ERROR: error: expected floating-point constant #0.0 +// CHECK-ERROR-AARCH64: error: expected floating-point constant #0.0 +// CHECK-ERROR-ARM64: error: invalid operand for instruction // CHECK-ERROR-NEXT: fcmp s3, d2 // CHECK-ERROR-NEXT: ^ @@ -1494,37 +1501,37 @@ fccmp s19, s5, #-1, lt fccmp s20, s7, #16, hs -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmp s19, s5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmp s20, s7, #16, hs // CHECK-ERROR-NEXT: ^ fccmp d19, d5, #-1, lt fccmp d20, d7, #16, hs -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmp d19, d5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmp d20, d7, #16, hs // CHECK-ERROR-NEXT: ^ fccmpe s19, s5, #-1, lt fccmpe s20, s7, #16, hs -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmpe s19, s5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmpe s20, s7, #16, hs // CHECK-ERROR-NEXT: ^ fccmpe d19, d5, #-1, lt fccmpe d20, d7, #16, hs -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmpe d19, d5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmpe d20, d7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1604,10 +1611,10 @@ fcvtzs w13, s31, #0 fcvtzs w19, s20, #33 fcvtzs wsp, s19, #14 -// CHECK-ERROR-NEXT: error: expected integer in range [1, 32] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR-NEXT: fcvtzs w13, s31, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [1, 32] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR-NEXT: fcvtzs w19, s20, #33 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -1617,10 +1624,10 @@ fcvtzs x13, s31, #0 fcvtzs x19, s20, #65 fcvtzs sp, s19, #14 -// CHECK-ERROR-NEXT: error: expected integer in range [1, 64] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR-NEXT: fcvtzs x13, s31, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [1, 64] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR-NEXT: fcvtzs x19, s20, #65 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -1630,10 +1637,10 @@ fcvtzu w13, s31, #0 fcvtzu w19, s20, #33 fcvtzu wsp, s19, #14 -// CHECK-ERROR-NEXT: error: expected integer in range [1, 32] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR-NEXT: fcvtzu w13, s31, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [1, 32] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR-NEXT: fcvtzu w19, s20, #33 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -1643,10 +1650,10 @@ fcvtzu x13, s31, #0 fcvtzu x19, s20, #65 fcvtzu sp, s19, #14 -// CHECK-ERROR-NEXT: error: expected integer in range [1, 64] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR-NEXT: fcvtzu x13, s31, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [1, 64] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR-NEXT: fcvtzu x19, s20, #65 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -1730,9 +1737,9 @@ ;; No particular reason, but a striking omission fmov d0, #0.0 -// CHECK-ERROR: error: expected compatible register or floating-point constant -// CHECK-ERROR-NEXT: fmov d0, #0.0 -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-AARCH64: error: expected compatible register or floating-point constant +// CHECK-ERROR-AARCH64-NEXT: fmov d0, #0.0 +// CHECK-ERROR-AARCH64-NEXT: ^ //------------------------------------------------------------------------------ // Floating-point <-> integer conversion @@ -1746,10 +1753,12 @@ // CHECK-ERROR: error: expected lane specifier '[1]' // CHECK-ERROR-NEXT: fmov x3, v0.d[0] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: lane number incompatible with layout +// CHECK-ERROR-AARCH64-NEXT: error: lane number incompatible with layout +// CHECK-ERROR-ARM64-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: fmov v29.1d[1], x2 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: lane number incompatible with layout +// CHECK-ERROR-AARCH64-NEXT: error: lane number incompatible with layout +// CHECK-ERROR-ARM64-NEXT: error: expected lane specifier '[1]' // CHECK-ERROR-NEXT: fmov x7, v0.d[2] // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -1789,10 +1798,11 @@ // Load/store exclusive //------------------------------------------------------------------------------ - stxrb w2, x3, [x4, #20] + stxrb w2, w3, [x4, #20] stlxrh w10, w11, [w2] -// CHECK-ERROR: error: expected '#0' -// CHECK-ERROR-NEXT: stxrb w2, x3, [x4, #20] +// CHECK-ERROR-AARCH64: error: expected '#0' +// CHECK-ERROR-ARM64: error: index must be absent or #0 +// CHECK-ERROR-NEXT: stxrb w2, w3, [x4, #20] // CHECK-ERROR-NEXT: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: stlxrh w10, w11, [w2] @@ -1831,16 +1841,16 @@ sturh w17, [x1, #256] ldursw x20, [x1, #256] ldur x12, [sp, #256] -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldurb w2, [sp, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: sturh w17, [x1, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldursw x20, [x1, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldur x12, [sp, #256] // CHECK-ERROR-NEXT: ^ @@ -1849,19 +1859,19 @@ ldursb x9, [sp, #-257] ldur w2, [x30, #-257] stur q9, [x20, #-257] -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: stur h2, [x2, #-257] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: stur b2, [x2, #-257] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldursb x9, [sp, #-257] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldur w2, [x30, #-257] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: stur q9, [x20, #-257] // CHECK-ERROR-NEXT: ^ @@ -1875,12 +1885,13 @@ //------------------------------------------------------------------------------ ldr x3, [x4, #25], #0 ldr x4, [x9, #0], #4 -// CHECK-ERROR: error: expected symbolic reference or integer in range [0, 32760] +// CHECK-ERROR-AARCH64: error: {{expected symbolic reference or integer|index must be a multiple of 8}} in range [0, 32760] +// CHECK-ERROR-ARM64: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldr x3, [x4, #25], #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: ldr x4, [x9, #0], #4 -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: invalid operand for instruction +// CHECK-ERROR-AARCH64-NEXT: ldr x4, [x9, #0], #4 +// CHECK-ERROR-AARCH64-NEXT: ^ strb w1, [x19], #256 strb w9, [sp], #-257 @@ -1888,22 +1899,22 @@ strh w9, [sp], #-257 str w1, [x19], #256 str w9, [sp], #-257 -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: strb w1, [x19], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: strb w9, [sp], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: strh w1, [x19], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: strh w9, [sp], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str w1, [x19], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str w9, [sp], #-257 // CHECK-ERROR-NEXT: ^ @@ -1913,22 +1924,22 @@ ldrh w9, [sp], #-257 ldr w1, [x19], #256 ldr w9, [sp], #-257 -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrb w1, [x19], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrb w9, [sp], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrh w1, [x19], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrh w9, [sp], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr w1, [x19], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr w9, [sp], #-257 // CHECK-ERROR-NEXT: ^ @@ -1938,22 +1949,22 @@ ldrsh x22, [x13], #-257 ldrsw x2, [x3], #256 ldrsw x22, [x13], #-257 -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsb x2, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsb x22, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsh x2, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsh x22, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsw x2, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsw x22, [x13], #-257 // CHECK-ERROR-NEXT: ^ @@ -1961,16 +1972,16 @@ ldrsb w22, [x13], #-257 ldrsh w2, [x3], #256 ldrsh w22, [x13], #-257 -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsb w2, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsb w22, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsh w2, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsh w22, [x13], #-257 // CHECK-ERROR-NEXT: ^ @@ -1984,34 +1995,34 @@ str d3, [x13], #-257 str q3, [x3], #256 str q3, [x13], #-257 -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str b3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str b3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str h3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str h3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str s3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str s3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str d3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str d3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str q3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str q3, [x13], #-257 // CHECK-ERROR-NEXT: ^ @@ -2025,34 +2036,34 @@ ldr d3, [x13], #-257 ldr q3, [x3], #256 ldr q3, [x13], #-257 -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr b3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr b3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr h3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr h3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr s3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr s3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr d3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr d3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr q3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr q3, [x13], #-257 // CHECK-ERROR-NEXT: ^ @@ -2074,19 +2085,19 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: strb w1, [x19, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: strb w9, [sp, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: strh w1, [x19, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: strh w9, [sp, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: str w1, [x19, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str w9, [sp, #-257]! // CHECK-ERROR-NEXT: ^ @@ -2099,19 +2110,19 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrb w1, [x19, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrb w9, [sp, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrh w1, [x19, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrh w9, [sp, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldr w1, [x19, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr w9, [sp, #-257]! // CHECK-ERROR-NEXT: ^ @@ -2124,19 +2135,19 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrsb x2, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsb x22, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrsh x2, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsh x22, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrsw x2, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsw x22, [x13, #-257]! // CHECK-ERROR-NEXT: ^ @@ -2147,13 +2158,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrsb w2, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsb w22, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrsh w2, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsh w22, [x13, #-257]! // CHECK-ERROR-NEXT: ^ @@ -2168,25 +2179,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: str b3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str b3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: str h3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str h3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: str s3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str s3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: str d3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str d3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ @@ -2201,25 +2212,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldr b3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr b3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldr h3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr h3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldr s3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr s3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldr d3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr d3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ @@ -2231,16 +2242,16 @@ sttrh w17, [x1, #256] ldtrsw x20, [x1, #256] ldtr x12, [sp, #256] -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldtrb w2, [sp, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: sttrh w17, [x1, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldtrsw x20, [x1, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldtr x12, [sp, #256] // CHECK-ERROR-NEXT: ^ @@ -2255,10 +2266,10 @@ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: sttr b2, [x2, #-257] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldtrsb x9, [sp, #-257] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldtr w2, [x30, #-257] // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -2276,19 +2287,19 @@ ldr w0, [x4, #16384] ldrh w2, [x21, #8192] ldrb w3, [x12, #4096] -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr q0, [x11, #65536] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr x0, [sp, #32768] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr w0, [x4, #16384] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrh w2, [x21, #8192] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrb w3, [x12, #4096] // CHECK-ERROR-NEXT: ^ @@ -2296,15 +2307,15 @@ ldr w0, [x0, #2] ldrsh w2, [x0, #123] str q0, [x0, #8] -// CHECK-ERROR: error: too few operands for instruction -// CHECK-ERROR-NEXT: ldr w0, [x0, #2] -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: too few operands for instruction -// CHECK-ERROR-NEXT: ldrsh w2, [x0, #123] -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: too few operands for instruction -// CHECK-ERROR-NEXT: str q0, [x0, #8] -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-AARCH64: error: too few operands for instruction +// CHECK-ERROR-AARCH64-NEXT: ldr w0, [x0, #2] +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: too few operands for instruction +// CHECK-ERROR-AARCH64-NEXT: ldrsh w2, [x0, #123] +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: too few operands for instruction +// CHECK-ERROR-AARCH64-NEXT: str q0, [x0, #8] +// CHECK-ERROR-AARCH64-NEXT: ^ //// 32-bit addresses ldr w0, [w20] @@ -2324,13 +2335,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: strb w0, [wsp] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR-NEXT: strh w31, [x23, #1] -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: too few operands for instruction -// CHECK-ERROR-NEXT: str x5, [x22, #12] -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-AARCH64: error: invalid operand for instruction +// CHECK-ERROR-AARCH64-NEXT: strh w31, [x23, #1] +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: too few operands for instruction +// CHECK-ERROR-AARCH64-NEXT: str x5, [x22, #12] +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str w7, [x12, #16384] // CHECK-ERROR-NEXT: ^ @@ -2339,16 +2350,19 @@ prfm #32, [sp, #8] prfm pldl1strm, [w3, #8] prfm wibble, [sp] -// CHECK-ERROR: error: Invalid immediate for instruction +// CHECK-ERROR-AARCH64: error: Invalid immediate for instruction +// CHECK-ERROR-ARM64: error: prefetch operand out of range, [0,31] expected // CHECK-ERROR-NEXT: prfm #-1, [sp] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-AARCH64-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-ARM64-NEXT: error: prefetch operand out of range, [0,31] expected // CHECK-ERROR-NEXT: prfm #32, [sp, #8] // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: prfm pldl1strm, [w3, #8] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: operand specifier not recognised +// CHECK-ERROR-AARCH64-NEXT: error: operand specifier not recognised +// CHECK-ERROR-ARM64-NEXT: error: pre-fetch hint expected // CHECK-ERROR-NEXT: prfm wibble, [sp] // CHECK-ERROR-NEXT: ^ @@ -2431,10 +2445,12 @@ // CHECK-ERROR-NEXT: error: expected integer shift amount // CHECK-ERROR-NEXT: ldr q5, [sp, x2, lsl #-1] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4 +// CHECK-ERROR-AARCH64-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4 +// CHECK-ERROR-ARM64-NEXT: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4 // CHECK-ERROR-NEXT: ldr q10, [x20, w4, uxtw #2] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4 +// CHECK-ERROR-AARCH64-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4 +// CHECK-ERROR-ARM64-NEXT: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4 // CHECK-ERROR-NEXT: str q21, [x20, w4, uxtw #5] // CHECK-ERROR-NEXT: ^ @@ -2446,16 +2462,16 @@ stp w9, w10, [x5, #256] ldp w11, w12, [x9, #-260] stp wsp, w9, [sp] -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp w3, w2, [x4, #1] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp w1, w2, [x3, #253] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp w9, w10, [x5, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp w11, w12, [x9, #-260] // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -2465,26 +2481,26 @@ ldpsw x9, x2, [sp, #2] ldpsw x1, x2, [x10, #256] ldpsw x3, x4, [x11, #-260] -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x9, x2, [sp, #2] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x1, x2, [x10, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x3, x4, [x11, #-260] // CHECK-ERROR-NEXT: ^ ldp x2, x5, [sp, #4] ldp x5, x6, [x9, #512] stp x7, x8, [x10, #-520] -// CHECK-ERROR: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp x2, x5, [sp, #4] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp x5, x6, [x9, #512] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stp x7, x8, [x10, #-520] // CHECK-ERROR-NEXT: ^ @@ -2500,13 +2516,13 @@ stp s3, s5, [sp, #-2] ldp s6, s26, [x4, #-260] stp s13, s19, [x5, #256] -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp s3, s5, [sp, #-2] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp s6, s26, [x4, #-260] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp s13, s19, [x5, #256] // CHECK-ERROR-NEXT: ^ @@ -2516,10 +2532,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldp d3, d4, [xzr] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp d5, d6, [x0, #512] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stp d7, d8, [x0, #-520] // CHECK-ERROR-NEXT: ^ @@ -2530,13 +2546,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldp d3, q2, [sp] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldp q3, q5, [sp, #8] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: stp q20, q25, [x5, #1024] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldp q30, q15, [x23, #-1040] // CHECK-ERROR-NEXT: ^ @@ -2549,16 +2565,16 @@ stp w9, w10, [x5], #256 ldp w11, w12, [x9], #-260 stp wsp, w9, [sp], #0 -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp w3, w2, [x4], #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp w1, w2, [x3], #253 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp w9, w10, [x5], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp w11, w12, [x9], #-260 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -2568,26 +2584,26 @@ ldpsw x9, x2, [sp], #2 ldpsw x1, x2, [x10], #256 ldpsw x3, x4, [x11], #-260 -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x9, x2, [sp], #2 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x1, x2, [x10], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x3, x4, [x11], #-260 // CHECK-ERROR-NEXT: ^ ldp x2, x5, [sp], #4 ldp x5, x6, [x9], #512 stp x7, x8, [x10], #-520 -// CHECK-ERROR: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp x2, x5, [sp], #4 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp x5, x6, [x9], #512 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stp x7, x8, [x10], #-520 // CHECK-ERROR-NEXT: ^ @@ -2603,13 +2619,13 @@ stp s3, s5, [sp], #-2 ldp s6, s26, [x4], #-260 stp s13, s19, [x5], #256 -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp s3, s5, [sp], #-2 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp s6, s26, [x4], #-260 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp s13, s19, [x5], #256 // CHECK-ERROR-NEXT: ^ @@ -2619,10 +2635,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldp d3, d4, [xzr], #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp d5, d6, [x0], #512 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stp d7, d8, [x0], #-520 // CHECK-ERROR-NEXT: ^ @@ -2633,13 +2649,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldp d3, q2, [sp], #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldp q3, q5, [sp], #8 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: stp q20, q25, [x5], #1024 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldp q30, q15, [x23], #-1040 // CHECK-ERROR-NEXT: ^ @@ -2652,16 +2668,16 @@ stp w9, w10, [x5, #256]! ldp w11, w12, [x9, #-260]! stp wsp, w9, [sp, #0]! -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp w3, w2, [x4, #1]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp w1, w2, [x3, #253]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp w9, w10, [x5, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp w11, w12, [x9, #-260]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -2671,26 +2687,26 @@ ldpsw x9, x2, [sp, #2]! ldpsw x1, x2, [x10, #256]! ldpsw x3, x4, [x11, #-260]! -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x9, x2, [sp, #2]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x1, x2, [x10, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x3, x4, [x11, #-260]! // CHECK-ERROR-NEXT: ^ ldp x2, x5, [sp, #4]! ldp x5, x6, [x9, #512]! stp x7, x8, [x10, #-520]! -// CHECK-ERROR: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp x2, x5, [sp, #4]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp x5, x6, [x9, #512]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stp x7, x8, [x10, #-520]! // CHECK-ERROR-NEXT: ^ @@ -2706,13 +2722,13 @@ stp s3, s5, [sp, #-2]! ldp s6, s26, [x4, #-260]! stp s13, s19, [x5, #256]! -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp s3, s5, [sp, #-2]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp s6, s26, [x4, #-260]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp s13, s19, [x5, #256]! // CHECK-ERROR-NEXT: ^ @@ -2722,10 +2738,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldp d3, d4, [xzr, #0]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp d5, d6, [x0, #512]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stp d7, d8, [x0, #-520]! // CHECK-ERROR-NEXT: ^ @@ -2736,13 +2752,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldp d3, q2, [sp, #0]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldp q3, q5, [sp, #8]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: stp q20, q25, [x5, #1024]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldp q30, q15, [x23, #-1040]! // CHECK-ERROR-NEXT: ^ @@ -2754,16 +2770,16 @@ stnp w9, w10, [x5, #256] ldnp w11, w12, [x9, #-260] stnp wsp, w9, [sp] -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldnp w3, w2, [x4, #1] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stnp w1, w2, [x3, #253] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stnp w9, w10, [x5, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldnp w11, w12, [x9, #-260] // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -2773,13 +2789,13 @@ ldnp x2, x5, [sp, #4] ldnp x5, x6, [x9, #512] stnp x7, x8, [x10, #-520] -// CHECK-ERROR: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldnp x2, x5, [sp, #4] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldnp x5, x6, [x9, #512] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stnp x7, x8, [x10, #-520] // CHECK-ERROR-NEXT: ^ @@ -2795,13 +2811,13 @@ stnp s3, s5, [sp, #-2] ldnp s6, s26, [x4, #-260] stnp s13, s19, [x5, #256] -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stnp s3, s5, [sp, #-2] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldnp s6, s26, [x4, #-260] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stnp s13, s19, [x5, #256] // CHECK-ERROR-NEXT: ^ @@ -2811,10 +2827,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldnp d3, d4, [xzr] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldnp d5, d6, [x0, #512] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stnp d7, d8, [x0, #-520] // CHECK-ERROR-NEXT: ^ @@ -2825,13 +2841,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldnp d3, q2, [sp] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldnp q3, q5, [sp, #8] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: stnp q20, q25, [x5, #1024] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldnp q30, q15, [x23, #-1040] // CHECK-ERROR-NEXT: ^ @@ -2974,28 +2990,32 @@ movz x3, #-1 movk w3, #1, lsl #32 movn x2, #12, lsl #64 -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz w3, #65536, lsl #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz w4, #65536 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' with optional integer 0 or 16 // CHECK-ERROR-NEXT: movn w1, #2, lsl #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: only 'lsl #+N' valid after immediate +// CHECK-ERROR-AARCH64-NEXT: error: only 'lsl #+N' valid after immediate +// CHECK-ERROR-ARM64-NEXT: error: expected integer shift amount // CHECK-ERROR-NEXT: movk w3, #0, lsl #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movn w2, #-1, lsl #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz x3, #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' with optional integer 0 or 16 // CHECK-ERROR-NEXT: movk w3, #1, lsl #32 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' with optional integer 0, 16, 32 or 48 // CHECK-ERROR-NEXT: movn x2, #12, lsl #64 // CHECK-ERROR-NEXT: ^ @@ -3005,22 +3025,22 @@ movk w3, #:abs_g0:sym movz x3, #:abs_g0_nc:sym movn x4, #:abs_g0_nc:sym -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz x12, #:abs_g0:sym, lsl #16 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz x12, #:abs_g0:sym, lsl #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] -// CHECK-ERROR-NEXT: movn x2, #:abs_g0:sym -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: movn x2, #:abs_g0:sym +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk w3, #:abs_g0:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz x3, #:abs_g0_nc:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movn x4, #:abs_g0_nc:sym // CHECK-ERROR-NEXT: ^ @@ -3028,16 +3048,16 @@ movk w3, #:abs_g1:sym movz x3, #:abs_g1_nc:sym movn x4, #:abs_g1_nc:sym -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] -// CHECK-ERROR-NEXT: movn x2, #:abs_g1:sym -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-AARCH64: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: movn x2, #:abs_g1:sym +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk w3, #:abs_g1:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz x3, #:abs_g1_nc:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movn x4, #:abs_g1_nc:sym // CHECK-ERROR-NEXT: ^ @@ -3047,53 +3067,53 @@ movk w3, #:abs_g2_nc:sym movz x13, #:abs_g2_nc:sym movn x24, #:abs_g2_nc:sym -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz w12, #:abs_g2:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] -// CHECK-ERROR-NEXT: movn x12, #:abs_g2:sym -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: movn x12, #:abs_g2:sym +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk x13, #:abs_g2:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk w3, #:abs_g2_nc:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz x13, #:abs_g2_nc:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movn x24, #:abs_g2_nc:sym // CHECK-ERROR-NEXT: ^ movn x19, #:abs_g3:sym movz w20, #:abs_g3:sym movk w21, #:abs_g3:sym -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] -// CHECK-ERROR-NEXT: movn x19, #:abs_g3:sym -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-AARCH64: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: movn x19, #:abs_g3:sym +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz w20, #:abs_g3:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk w21, #:abs_g3:sym // CHECK-ERROR-NEXT: ^ movk x19, #:abs_g0_s:sym movk w23, #:abs_g0_s:sym -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk x19, #:abs_g0_s:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk w23, #:abs_g0_s:sym // CHECK-ERROR-NEXT: ^ movk x19, #:abs_g1_s:sym movk w23, #:abs_g1_s:sym -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk x19, #:abs_g1_s:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk w23, #:abs_g1_s:sym // CHECK-ERROR-NEXT: ^ @@ -3101,16 +3121,16 @@ movn w29, #:abs_g2_s:sym movk x19, #:abs_g2_s:sym movk w23, #:abs_g2_s:sym -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz w2, #:abs_g2_s:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movn w29, #:abs_g2_s:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk x19, #:abs_g2_s:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk w23, #:abs_g2_s:sym // CHECK-ERROR-NEXT: ^ @@ -3154,19 +3174,19 @@ hint #-1 hint #128 -// CHECK-ERROR: error: expected integer in range [0, 127] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 127] // CHECK-ERROR-NEXT: hint #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 127] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 127] // CHECK-ERROR-NEXT: hint #128 // CHECK-ERROR-NEXT: ^ clrex #-1 clrex #16 -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: clrex #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: clrex #16 // CHECK-ERROR-NEXT: ^ @@ -3174,25 +3194,25 @@ dsb #16 dmb #-1 dmb #16 -// CHECK-ERROR-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}} // CHECK-ERROR-NEXT: dsb #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}} // CHECK-ERROR-NEXT: dsb #16 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}} // CHECK-ERROR-NEXT: dmb #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}} // CHECK-ERROR-NEXT: dmb #16 // CHECK-ERROR-NEXT: ^ isb #-1 isb #16 -// CHECK-ERROR-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}} // CHECK-ERROR-NEXT: isb #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}} // CHECK-ERROR-NEXT: isb #16 // CHECK-ERROR-NEXT: ^ @@ -3200,16 +3220,16 @@ msr spsel, #-1 msr spsel #-1 msr daifclr, #16 -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: msr daifset, x4 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: msr spsel, #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected comma before next operand +// CHECK-ERROR-NEXT: error: {{expected comma before next operand|unexpected token in argument list}} // CHECK-ERROR-NEXT: msr spsel #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: msr daifclr, #16 // CHECK-ERROR-NEXT: ^ @@ -3221,7 +3241,7 @@ sysl x13, #3, c16, c2, #3 sysl x9, #2, c11, c16, #5 sysl x4, #4, c9, c8, #8 -// CHECK-ERROR-NEXT: error: expected integer in range [0, 7] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR-NEXT: sys #8, c1, c2, #7, x9 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: Expected cN operand where 0 <= N <= 15 @@ -3230,10 +3250,10 @@ // CHECK-ERROR-NEXT: error: Expected cN operand where 0 <= N <= 15 // CHECK-ERROR-NEXT: sys #2, c11, c16, #5 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 7] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR-NEXT: sys #4, c9, c8, #8, xzr // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 7] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR-NEXT: sysl x11, #8, c1, c2, #7 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: Expected cN operand where 0 <= N <= 15 @@ -3242,20 +3262,21 @@ // CHECK-ERROR-NEXT: error: Expected cN operand where 0 <= N <= 15 // CHECK-ERROR-NEXT: sysl x9, #2, c11, c16, #5 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 7] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR-NEXT: sysl x4, #4, c9, c8, #8 // CHECK-ERROR-NEXT: ^ ic ialluis, x2 ic allu, x7 ic ivau -// CHECK-ERROR-NEXT: error: specified IC op does not use a register +// CHECK-ERROR-NEXT: error: specified {{IC|ic}} op does not use a register // CHECK-ERROR-NEXT: ic ialluis, x2 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: operand specifier not recognised +// CHECK-ERROR-AARCH64-NEXT: error: operand specifier not recognised +// CHECK-ERROR-ARM64-NEXT: error: invalid operand for IC instruction // CHECK-ERROR-NEXT: ic allu, x7 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified IC op requires a register +// CHECK-ERROR-NEXT: error: specified {{IC|ic}} op requires a register // CHECK-ERROR-NEXT: ic ivau // CHECK-ERROR-NEXT: ^ @@ -3291,100 +3312,100 @@ tlbi VALE3 tlbi VMALLS12E1, x15 tlbi VAALE1 -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi IPAS2E1IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi IPAS2LE1IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi VMALLE1IS, x12 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi ALLE2IS, x11 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi ALLE3IS, x20 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAE1IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAE2IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAE3IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi ASIDE1IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAAE1IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi ALLE1IS, x0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VALE1IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VALE2IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VALE3IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi VMALLS12E1IS, xzr // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAALE1IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi IPAS2E1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi IPAS2LE1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi VMALLE1, x9 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi ALLE2, x10 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi ALLE3, x11 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAE1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAE2 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAE3 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi ASIDE1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAAE1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi ALLE1, x25 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VALE1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VALE2 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VALE3 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi VMALLS12E1, x15 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAALE1 // CHECK-ERROR-NEXT: ^ @@ -3642,16 +3663,16 @@ tbz w3, #32, nowhere tbz x9, #-1, there tbz x20, #64, dont -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: tbz w3, #-1, addr // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: tbz w3, #32, nowhere // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: tbz x9, #-1, there // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: tbz x20, #64, dont // CHECK-ERROR-NEXT: ^ @@ -3659,16 +3680,16 @@ tbnz w3, #32, nowhere tbnz x9, #-1, there tbnz x20, #64, dont -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: tbnz w3, #-1, addr // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: tbnz w3, #32, nowhere // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: tbnz x9, #-1, there // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: tbnz x20, #64, dont //------------------------------------------------------------------------------ diff --git a/test/MC/AArch64/basic-a64-instructions.s b/test/MC/AArch64/basic-a64-instructions.s index be00e14..a12968b 100644 --- a/test/MC/AArch64/basic-a64-instructions.s +++ b/test/MC/AArch64/basic-a64-instructions.s @@ -108,9 +108,9 @@ _func: // CHECK: adds x20, sp, w19, uxth #4 // encoding: [0xf4,0x33,0x33,0xab] // CHECK: adds x12, x1, w20, uxtw // encoding: [0x2c,0x40,0x34,0xab] // CHECK: adds x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xab] -// CHECK: adds xzr, x25, w20, sxtb #3 // encoding: [0x3f,0x8f,0x34,0xab] +// CHECK: {{adds xzr,|cmn}} x25, w20, sxtb #3 // encoding: [0x3f,0x8f,0x34,0xab] // CHECK: adds x18, sp, w19, sxth // encoding: [0xf2,0xa3,0x33,0xab] -// CHECK: adds xzr, x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0xab] +// CHECK: {{adds xzr,|cmn}} x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0xab] // CHECK: adds x3, x5, x9, sxtx #2 // encoding: [0xa3,0xe8,0x29,0xab] adds w2, w5, w7, uxtb @@ -127,7 +127,7 @@ _func: // CHECK: adds w19, w17, w1, uxtx // encoding: [0x33,0x62,0x21,0x2b] // CHECK: adds w2, w5, w1, sxtb #1 // encoding: [0xa2,0x84,0x21,0x2b] // CHECK: adds w26, wsp, w19, sxth // encoding: [0xfa,0xa3,0x33,0x2b] -// CHECK: adds wzr, w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b] +// CHECK: cmn w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b] // CHECK: adds w2, w3, w5, sxtx // encoding: [0x62,0xe0,0x25,0x2b] // subs @@ -143,9 +143,9 @@ _func: // CHECK: subs x20, sp, w19, uxth #4 // encoding: [0xf4,0x33,0x33,0xeb] // CHECK: subs x12, x1, w20, uxtw // encoding: [0x2c,0x40,0x34,0xeb] // CHECK: subs x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xeb] -// CHECK: subs xzr, x25, w20, sxtb #3 // encoding: [0x3f,0x8f,0x34,0xeb] +// CHECK: {{subs xzr,|cmp}} x25, w20, sxtb #3 // encoding: [0x3f,0x8f,0x34,0xeb] // CHECK: subs x18, sp, w19, sxth // encoding: [0xf2,0xa3,0x33,0xeb] -// CHECK: subs xzr, x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0xeb] +// CHECK: {{subs xzr,|cmp}} x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0xeb] // CHECK: subs x3, x5, x9, sxtx #2 // encoding: [0xa3,0xe8,0x29,0xeb] subs w2, w5, w7, uxtb @@ -162,7 +162,7 @@ _func: // CHECK: subs w19, w17, w1, uxtx // encoding: [0x33,0x62,0x21,0x6b] // CHECK: subs w2, w5, w1, sxtb #1 // encoding: [0xa2,0x84,0x21,0x6b] // CHECK: subs w26, wsp, w19, sxth // encoding: [0xfa,0xa3,0x33,0x6b] -// CHECK: subs wzr, w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x6b] +// CHECK: {{subs wzr,|cmp}} w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x6b] // CHECK: subs w2, w3, w5, sxtx // encoding: [0x62,0xe0,0x25,0x6b] // cmp @@ -227,14 +227,14 @@ _func: cmn wsp, w19, sxth cmn w2, w3, sxtw cmn w3, w5, sxtx -// CHECK: cmn w5, w7, uxtb // encoding: [0xbf,0x00,0x27,0x2b] -// CHECK: cmn w15, w17, uxth // encoding: [0xff,0x21,0x31,0x2b] -// CHECK: cmn w29, wzr, uxtw // encoding: [0xbf,0x43,0x3f,0x2b] -// CHECK: cmn w17, w1, uxtx // encoding: [0x3f,0x62,0x21,0x2b] -// CHECK: cmn w5, w1, sxtb #1 // encoding: [0xbf,0x84,0x21,0x2b] -// CHECK: cmn wsp, w19, sxth // encoding: [0xff,0xa3,0x33,0x2b] -// CHECK: cmn w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b] -// CHECK: cmn w3, w5, sxtx // encoding: [0x7f,0xe0,0x25,0x2b] +// CHECK: {{cmn|adds wzr,}} w5, w7, uxtb // encoding: [0xbf,0x00,0x27,0x2b] +// CHECK: {{cmn|adds wzr,}} w15, w17, uxth // encoding: [0xff,0x21,0x31,0x2b] +// CHECK: {{cmn|adds wzr,}} w29, wzr, uxtw // encoding: [0xbf,0x43,0x3f,0x2b] +// CHECK: {{cmn|adds wzr,}} w17, w1, uxtx // encoding: [0x3f,0x62,0x21,0x2b] +// CHECK: {{cmn|adds wzr,}} w5, w1, sxtb #1 // encoding: [0xbf,0x84,0x21,0x2b] +// CHECK: {{cmn|adds wzr,}} wsp, w19, sxth // encoding: [0xff,0xa3,0x33,0x2b] +// CHECK: {{cmn|adds wzr,}} w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b] +// CHECK: {{cmn|adds wzr,}} w3, w5, sxtx // encoding: [0x7f,0xe0,0x25,0x2b] // operands for cmp cmp x20, w29, uxtb #3 @@ -244,7 +244,7 @@ _func: // CHECK: cmp x20, w29, uxtb #3 // encoding: [0x9f,0x0e,0x3d,0xeb] // CHECK: cmp x12, x13, uxtx #4 // encoding: [0x9f,0x71,0x2d,0xeb] // CHECK: cmp wsp, w1, uxtb // encoding: [0xff,0x03,0x21,0x6b] -// CHECK: cmn wsp, wzr, sxtw // encoding: [0xff,0xc3,0x3f,0x2b] +// CHECK: {{cmn|adds wzr,}} wsp, wzr, sxtw // encoding: [0xff,0xc3,0x3f,0x2b] // LSL variant if sp involved sub sp, x3, x7, lsl #4 @@ -255,7 +255,7 @@ _func: // CHECK: sub sp, x3, x7, lsl #4 // encoding: [0x7f,0x70,0x27,0xcb] // CHECK: add w2, wsp, w3, lsl #1 // encoding: [0xe2,0x47,0x23,0x0b] // CHECK: cmp wsp, w9 // encoding: [0xff,0x43,0x29,0x6b] -// CHECK: adds wzr, wsp, w3, lsl #4 // encoding: [0xff,0x53,0x23,0x2b] +// CHECK: cmn wsp, w3, lsl #4 // encoding: [0xff,0x53,0x23,0x2b] // CHECK: subs x3, sp, x9, lsl #2 // encoding: [0xe3,0x6b,0x29,0xeb] //------------------------------------------------------------------------------ @@ -309,16 +309,16 @@ _func: adds w20, wsp, #0x0 adds xzr, x3, #0x1, lsl #12 // FIXME: canonically should be cmn // CHECK: adds w13, w23, #291, lsl #12 // encoding: [0xed,0x8e,0x44,0x31] -// CHECK: adds wzr, w2, #4095 // encoding: [0x5f,0xfc,0x3f,0x31] +// CHECK: {{adds wzr,|cmn}} w2, #4095 // encoding: [0x5f,0xfc,0x3f,0x31] // CHECK: adds w20, wsp, #0 // encoding: [0xf4,0x03,0x00,0x31] -// CHECK: adds xzr, x3, #1, lsl #12 // encoding: [0x7f,0x04,0x40,0xb1] +// CHECK: {{adds xzr,|cmn}} x3, #1, lsl #12 // encoding: [0x7f,0x04,0x40,0xb1] // Checks for subs subs xzr, sp, #20, lsl #12 // FIXME: canonically should be cmp subs xzr, x30, #4095, lsl #0 // FIXME: canonically should be cmp subs x4, sp, #3822 -// CHECK: subs xzr, sp, #20, lsl #12 // encoding: [0xff,0x53,0x40,0xf1] -// CHECK: subs xzr, x30, #4095 // encoding: [0xdf,0xff,0x3f,0xf1] +// CHECK: {{subs xzr,|cmp}} sp, #20, lsl #12 // encoding: [0xff,0x53,0x40,0xf1] +// CHECK: {{subs xzr,|cmp}} x30, #4095 // encoding: [0xdf,0xff,0x3f,0xf1] // CHECK: subs x4, sp, #3822 // encoding: [0xe4,0xbb,0x3b,0xf1] // cmn is an alias for adds zr, ... @@ -349,8 +349,8 @@ _func: // A relocation check (default to lo12, which is the only sane relocation anyway really) add x0, x4, #:lo12:var -// CHECK: add x0, x4, #:lo12:var // encoding: [0x80'A',A,A,0x91'A'] -// CHECK: // fixup A - offset: 0, value: :lo12:var, kind: fixup_a64_add_lo12 +// CHECK: add x0, x4, :lo12:var // encoding: [0x80,0bAAAAAA00,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :lo12:var, kind: fixup_aarch64_add_imm12 //------------------------------------------------------------------------------ // Add-sub (shifted register) @@ -423,7 +423,7 @@ _func: adds w20, wzr, w4 adds w4, w6, wzr // CHECK: adds w3, w5, w7 // encoding: [0xa3,0x00,0x07,0x2b] -// CHECK: adds wzr, w3, w5 // encoding: [0x7f,0x00,0x05,0x2b] +// CHECK: {{adds wzr,|cmn}} w3, w5 // encoding: [0x7f,0x00,0x05,0x2b] // CHECK: adds w20, wzr, w4 // encoding: [0xf4,0x03,0x04,0x2b] // CHECK: adds w4, w6, wzr // encoding: [0xc4,0x00,0x1f,0x2b] @@ -453,7 +453,7 @@ _func: adds x20, xzr, x4 adds x4, x6, xzr // CHECK: adds x3, x5, x7 // encoding: [0xa3,0x00,0x07,0xab] -// CHECK: adds xzr, x3, x5 // encoding: [0x7f,0x00,0x05,0xab] +// CHECK: {{adds xzr,|cmn}} x3, x5 // encoding: [0x7f,0x00,0x05,0xab] // CHECK: adds x20, xzr, x4 // encoding: [0xf4,0x03,0x04,0xab] // CHECK: adds x4, x6, xzr // encoding: [0xc4,0x00,0x1f,0xab] @@ -484,7 +484,7 @@ _func: sub w4, w6, wzr // CHECK: sub w3, w5, w7 // encoding: [0xa3,0x00,0x07,0x4b] // CHECK: sub wzr, w3, w5 // encoding: [0x7f,0x00,0x05,0x4b] -// CHECK: sub w20, wzr, w4 // encoding: [0xf4,0x03,0x04,0x4b] +// CHECK: neg w20, w4 // encoding: [0xf4,0x03,0x04,0x4b] // CHECK: sub w4, w6, wzr // encoding: [0xc4,0x00,0x1f,0x4b] sub w11, w13, w15, lsl #0 @@ -514,7 +514,7 @@ _func: sub x4, x6, xzr // CHECK: sub x3, x5, x7 // encoding: [0xa3,0x00,0x07,0xcb] // CHECK: sub xzr, x3, x5 // encoding: [0x7f,0x00,0x05,0xcb] -// CHECK: sub x20, xzr, x4 // encoding: [0xf4,0x03,0x04,0xcb] +// CHECK: neg x20, x4 // encoding: [0xf4,0x03,0x04,0xcb] // CHECK: sub x4, x6, xzr // encoding: [0xc4,0x00,0x1f,0xcb] sub x11, x13, x15, lsl #0 @@ -543,8 +543,8 @@ _func: subs w20, wzr, w4 subs w4, w6, wzr // CHECK: subs w3, w5, w7 // encoding: [0xa3,0x00,0x07,0x6b] -// CHECK: subs wzr, w3, w5 // encoding: [0x7f,0x00,0x05,0x6b] -// CHECK: subs w20, wzr, w4 // encoding: [0xf4,0x03,0x04,0x6b] +// CHECK: {{subs wzr,|cmp}} w3, w5 // encoding: [0x7f,0x00,0x05,0x6b] +// CHECK: negs w20, w4 // encoding: [0xf4,0x03,0x04,0x6b] // CHECK: subs w4, w6, wzr // encoding: [0xc4,0x00,0x1f,0x6b] subs w11, w13, w15, lsl #0 @@ -573,8 +573,8 @@ _func: subs x20, xzr, x4 subs x4, x6, xzr // CHECK: subs x3, x5, x7 // encoding: [0xa3,0x00,0x07,0xeb] -// CHECK: subs xzr, x3, x5 // encoding: [0x7f,0x00,0x05,0xeb] -// CHECK: subs x20, xzr, x4 // encoding: [0xf4,0x03,0x04,0xeb] +// CHECK: {{subs xzr,|cmp}} x3, x5 // encoding: [0x7f,0x00,0x05,0xeb] +// CHECK: negs x20, x4 // encoding: [0xf4,0x03,0x04,0xeb] // CHECK: subs x4, x6, xzr // encoding: [0xc4,0x00,0x1f,0xeb] subs x11, x13, x15, lsl #0 @@ -713,114 +713,118 @@ _func: neg w29, w30 neg w30, wzr neg wzr, w0 -// CHECK: sub w29, wzr, w30 // encoding: [0xfd,0x03,0x1e,0x4b] -// CHECK: sub w30, wzr, wzr // encoding: [0xfe,0x03,0x1f,0x4b] -// CHECK: sub wzr, wzr, w0 // encoding: [0xff,0x03,0x00,0x4b] +// CHECK: neg w29, w30 // encoding: [0xfd,0x03,0x1e,0x4b] +// CHECK: neg w30, wzr // encoding: [0xfe,0x03,0x1f,0x4b] +// CHECK: neg wzr, w0 // encoding: [0xff,0x03,0x00,0x4b] neg w28, w27, lsl #0 neg w26, w25, lsl #29 neg w24, w23, lsl #31 -// CHECK: sub w28, wzr, w27 // encoding: [0xfc,0x03,0x1b,0x4b] -// CHECK: sub w26, wzr, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b] -// CHECK: sub w24, wzr, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b] + +// CHECK: neg w28, w27 // encoding: [0xfc,0x03,0x1b,0x4b] +// CHECK: neg w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b] +// CHECK: neg w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b] neg w22, w21, lsr #0 neg w20, w19, lsr #1 neg w18, w17, lsr #31 -// CHECK: sub w22, wzr, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x4b] -// CHECK: sub w20, wzr, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x4b] -// CHECK: sub w18, wzr, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x4b] +// CHECK: neg w22, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x4b] +// CHECK: neg w20, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x4b] +// CHECK: neg w18, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x4b] neg w16, w15, asr #0 neg w14, w13, asr #12 neg w12, w11, asr #31 -// CHECK: sub w16, wzr, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x4b] -// CHECK: sub w14, wzr, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x4b] -// CHECK: sub w12, wzr, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x4b] +// CHECK: neg w16, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x4b] +// CHECK: neg w14, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x4b] +// CHECK: neg w12, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x4b] neg x29, x30 neg x30, xzr neg xzr, x0 -// CHECK: sub x29, xzr, x30 // encoding: [0xfd,0x03,0x1e,0xcb] -// CHECK: sub x30, xzr, xzr // encoding: [0xfe,0x03,0x1f,0xcb] -// CHECK: sub xzr, xzr, x0 // encoding: [0xff,0x03,0x00,0xcb] +// CHECK: neg x29, x30 // encoding: [0xfd,0x03,0x1e,0xcb] +// CHECK: neg x30, xzr // encoding: [0xfe,0x03,0x1f,0xcb] +// CHECK: neg xzr, x0 // encoding: [0xff,0x03,0x00,0xcb] neg x28, x27, lsl #0 neg x26, x25, lsl #29 neg x24, x23, lsl #31 -// CHECK: sub x28, xzr, x27 // encoding: [0xfc,0x03,0x1b,0xcb] -// CHECK: sub x26, xzr, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb] -// CHECK: sub x24, xzr, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb] + +// CHECK: neg x28, x27 // encoding: [0xfc,0x03,0x1b,0xcb] +// CHECK: neg x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb] +// CHECK: neg x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb] neg x22, x21, lsr #0 neg x20, x19, lsr #1 neg x18, x17, lsr #31 -// CHECK: sub x22, xzr, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xcb] -// CHECK: sub x20, xzr, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xcb] -// CHECK: sub x18, xzr, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xcb] +// CHECK: neg x22, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xcb] +// CHECK: neg x20, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xcb] +// CHECK: neg x18, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xcb] neg x16, x15, asr #0 neg x14, x13, asr #12 neg x12, x11, asr #31 -// CHECK: sub x16, xzr, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xcb] -// CHECK: sub x14, xzr, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xcb] -// CHECK: sub x12, xzr, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xcb] +// CHECK: neg x16, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xcb] +// CHECK: neg x14, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xcb] +// CHECK: neg x12, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xcb] negs w29, w30 negs w30, wzr negs wzr, w0 -// CHECK: subs w29, wzr, w30 // encoding: [0xfd,0x03,0x1e,0x6b] -// CHECK: subs w30, wzr, wzr // encoding: [0xfe,0x03,0x1f,0x6b] -// CHECK: subs wzr, wzr, w0 // encoding: [0xff,0x03,0x00,0x6b] +// CHECK: negs w29, w30 // encoding: [0xfd,0x03,0x1e,0x6b] +// CHECK: negs w30, wzr // encoding: [0xfe,0x03,0x1f,0x6b] +// CHECK: cmp wzr, w0 // encoding: [0xff,0x03,0x00,0x6b] negs w28, w27, lsl #0 negs w26, w25, lsl #29 negs w24, w23, lsl #31 -// CHECK: subs w28, wzr, w27 // encoding: [0xfc,0x03,0x1b,0x6b] -// CHECK: subs w26, wzr, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b] -// CHECK: subs w24, wzr, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b] + +// CHECK: negs w28, w27 // encoding: [0xfc,0x03,0x1b,0x6b] +// CHECK: negs w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b] +// CHECK: negs w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b] negs w22, w21, lsr #0 negs w20, w19, lsr #1 negs w18, w17, lsr #31 -// CHECK: subs w22, wzr, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x6b] -// CHECK: subs w20, wzr, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x6b] -// CHECK: subs w18, wzr, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x6b] +// CHECK: negs w22, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x6b] +// CHECK: negs w20, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x6b] +// CHECK: negs w18, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x6b] negs w16, w15, asr #0 negs w14, w13, asr #12 negs w12, w11, asr #31 -// CHECK: subs w16, wzr, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x6b] -// CHECK: subs w14, wzr, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x6b] -// CHECK: subs w12, wzr, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x6b] +// CHECK: negs w16, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x6b] +// CHECK: negs w14, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x6b] +// CHECK: negs w12, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x6b] negs x29, x30 negs x30, xzr negs xzr, x0 -// CHECK: subs x29, xzr, x30 // encoding: [0xfd,0x03,0x1e,0xeb] -// CHECK: subs x30, xzr, xzr // encoding: [0xfe,0x03,0x1f,0xeb] -// CHECK: subs xzr, xzr, x0 // encoding: [0xff,0x03,0x00,0xeb] +// CHECK: negs x29, x30 // encoding: [0xfd,0x03,0x1e,0xeb] +// CHECK: negs x30, xzr // encoding: [0xfe,0x03,0x1f,0xeb] +// CHECK: cmp xzr, x0 // encoding: [0xff,0x03,0x00,0xeb] negs x28, x27, lsl #0 negs x26, x25, lsl #29 negs x24, x23, lsl #31 -// CHECK: subs x28, xzr, x27 // encoding: [0xfc,0x03,0x1b,0xeb] -// CHECK: subs x26, xzr, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb] -// CHECK: subs x24, xzr, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb] + +// CHECK: negs x28, x27 // encoding: [0xfc,0x03,0x1b,0xeb] +// CHECK: negs x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb] +// CHECK: negs x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb] negs x22, x21, lsr #0 negs x20, x19, lsr #1 negs x18, x17, lsr #31 -// CHECK: subs x22, xzr, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xeb] -// CHECK: subs x20, xzr, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xeb] -// CHECK: subs x18, xzr, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xeb] +// CHECK: negs x22, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xeb] +// CHECK: negs x20, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xeb] +// CHECK: negs x18, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xeb] negs x16, x15, asr #0 negs x14, x13, asr #12 negs x12, x11, asr #31 -// CHECK: subs x16, xzr, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xeb] -// CHECK: subs x14, xzr, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xeb] -// CHECK: subs x12, xzr, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xeb] +// CHECK: negs x16, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xeb] +// CHECK: negs x14, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xeb] +// CHECK: negs x12, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xeb] //------------------------------------------------------------------------------ // Add-sub (shifted register) @@ -933,28 +937,29 @@ _func: sbfm x3, x4, #63, #63 sbfm wzr, wzr, #31, #31 sbfm w12, w9, #0, #0 -// CHECK: sbfm x1, x2, #3, #4 // encoding: [0x41,0x10,0x43,0x93] -// CHECK: sbfm x3, x4, #63, #63 // encoding: [0x83,0xfc,0x7f,0x93] -// CHECK: sbfm wzr, wzr, #31, #31 // encoding: [0xff,0x7f,0x1f,0x13] -// CHECK: sbfm w12, w9, #0, #0 // encoding: [0x2c,0x01,0x00,0x13] + +// CHECK: sbfx x1, x2, #3, #2 // encoding: [0x41,0x10,0x43,0x93] +// CHECK: asr x3, x4, #63 // encoding: [0x83,0xfc,0x7f,0x93] +// CHECK: asr wzr, wzr, #31 // encoding: [0xff,0x7f,0x1f,0x13] +// CHECK: sbfx w12, w9, #0, #1 // encoding: [0x2c,0x01,0x00,0x13] ubfm x4, x5, #12, #10 ubfm xzr, x4, #0, #0 ubfm x4, xzr, #63, #5 ubfm x5, x6, #12, #63 -// CHECK: ubfm x4, x5, #12, #10 // encoding: [0xa4,0x28,0x4c,0xd3] -// CHECK: ubfm xzr, x4, #0, #0 // encoding: [0x9f,0x00,0x40,0xd3] -// CHECK: ubfm x4, xzr, #63, #5 // encoding: [0xe4,0x17,0x7f,0xd3] -// CHECK: ubfm x5, x6, #12, #63 // encoding: [0xc5,0xfc,0x4c,0xd3] +// CHECK: ubfiz x4, x5, #52, #11 // encoding: [0xa4,0x28,0x4c,0xd3] +// CHECK: ubfx xzr, x4, #0, #1 // encoding: [0x9f,0x00,0x40,0xd3] +// CHECK: ubfiz x4, xzr, #1, #6 // encoding: [0xe4,0x17,0x7f,0xd3] +// CHECK: lsr x5, x6, #12 // encoding: [0xc5,0xfc,0x4c,0xd3] bfm x4, x5, #12, #10 bfm xzr, x4, #0, #0 bfm x4, xzr, #63, #5 bfm x5, x6, #12, #63 -// CHECK: bfm x4, x5, #12, #10 // encoding: [0xa4,0x28,0x4c,0xb3] -// CHECK: bfm xzr, x4, #0, #0 // encoding: [0x9f,0x00,0x40,0xb3] -// CHECK: bfm x4, xzr, #63, #5 // encoding: [0xe4,0x17,0x7f,0xb3] -// CHECK: bfm x5, x6, #12, #63 // encoding: [0xc5,0xfc,0x4c,0xb3] +// CHECK: bfi x4, x5, #52, #11 // encoding: [0xa4,0x28,0x4c,0xb3] +// CHECK: bfxil xzr, x4, #0, #1 // encoding: [0x9f,0x00,0x40,0xb3] +// CHECK: bfi x4, xzr, #1, #6 // encoding: [0xe4,0x17,0x7f,0xb3] +// CHECK: bfxil x5, x6, #12, #52 // encoding: [0xc5,0xfc,0x4c,0xb3] sxtb w1, w2 sxtb xzr, w3 @@ -972,9 +977,9 @@ _func: uxth w9, w10 uxth x0, w1 // CHECK: uxtb w1, w2 // encoding: [0x41,0x1c,0x00,0x53] -// CHECK: uxtb xzr, w3 // encoding: [0x7f,0x1c,0x00,0x53] +// CHECK: uxtb {{[wx]}}zr, w3 // encoding: [0x7f,0x1c,0x00,0x53] // CHECK: uxth w9, w10 // encoding: [0x49,0x3d,0x00,0x53] -// CHECK: uxth x0, w1 // encoding: [0x20,0x3c,0x00,0x53] +// CHECK: uxth {{[wx]}}0, w1 // encoding: [0x20,0x3c,0x00,0x53] asr w3, w2, #0 asr w9, w10, #31 @@ -998,7 +1003,7 @@ _func: lsl w9, w10, #31 lsl x20, x21, #63 lsl w1, wzr, #3 -// CHECK: lsl w3, w2, #0 // encoding: [0x43,0x7c,0x00,0x53] +// CHECK: {{lsl|lsr}} w3, w2, #0 // encoding: [0x43,0x7c,0x00,0x53] // CHECK: lsl w9, w10, #31 // encoding: [0x49,0x01,0x01,0x53] // CHECK: lsl x20, x21, #63 // encoding: [0xb4,0x02,0x41,0xd3] // CHECK: lsl w1, wzr, #3 // encoding: [0xe1,0x73,0x1d,0x53] @@ -1011,11 +1016,11 @@ _func: sbfiz w11, w12, #31, #1 sbfiz w13, w14, #29, #3 sbfiz xzr, xzr, #10, #11 -// CHECK: sbfiz w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x13] +// CHECK: {{sbfiz|sbfx}} w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x13] // CHECK: sbfiz x2, x3, #63, #1 // encoding: [0x62,0x00,0x41,0x93] -// CHECK: sbfiz x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0x93] +// CHECK: asr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0x93] // CHECK: sbfiz x9, x10, #5, #59 // encoding: [0x49,0xe9,0x7b,0x93] -// CHECK: sbfiz w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x13] +// CHECK: asr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x13] // CHECK: sbfiz w11, w12, #31, #1 // encoding: [0x8b,0x01,0x01,0x13] // CHECK: sbfiz w13, w14, #29, #3 // encoding: [0xcd,0x09,0x03,0x13] // CHECK: sbfiz xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0x93] @@ -1029,12 +1034,12 @@ _func: sbfx w13, w14, #29, #3 sbfx xzr, xzr, #10, #11 // CHECK: sbfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x13] -// CHECK: sbfx x2, x3, #63, #1 // encoding: [0x62,0xfc,0x7f,0x93] -// CHECK: sbfx x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0x93] -// CHECK: sbfx x9, x10, #5, #59 // encoding: [0x49,0xfd,0x45,0x93] -// CHECK: sbfx w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x13] -// CHECK: sbfx w11, w12, #31, #1 // encoding: [0x8b,0x7d,0x1f,0x13] -// CHECK: sbfx w13, w14, #29, #3 // encoding: [0xcd,0x7d,0x1d,0x13] +// CHECK: asr x2, x3, #63 // encoding: [0x62,0xfc,0x7f,0x93] +// CHECK: asr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0x93] +// CHECK: asr x9, x10, #5 // encoding: [0x49,0xfd,0x45,0x93] +// CHECK: asr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x13] +// CHECK: asr w11, w12, #31 // encoding: [0x8b,0x7d,0x1f,0x13] +// CHECK: asr w13, w14, #29 // encoding: [0xcd,0x7d,0x1d,0x13] // CHECK: sbfx xzr, xzr, #10, #11 // encoding: [0xff,0x53,0x4a,0x93] bfi w9, w10, #0, #1 @@ -1045,11 +1050,12 @@ _func: bfi w11, w12, #31, #1 bfi w13, w14, #29, #3 bfi xzr, xzr, #10, #11 -// CHECK: bfi w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x33] + +// CHECK: bfxil w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x33] // CHECK: bfi x2, x3, #63, #1 // encoding: [0x62,0x00,0x41,0xb3] -// CHECK: bfi x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0xb3] +// CHECK: bfxil x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0xb3] // CHECK: bfi x9, x10, #5, #59 // encoding: [0x49,0xe9,0x7b,0xb3] -// CHECK: bfi w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x33] +// CHECK: bfxil w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x33] // CHECK: bfi w11, w12, #31, #1 // encoding: [0x8b,0x01,0x01,0x33] // CHECK: bfi w13, w14, #29, #3 // encoding: [0xcd,0x09,0x03,0x33] // CHECK: bfi xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0xb3] @@ -1079,14 +1085,15 @@ _func: ubfiz w11, w12, #31, #1 ubfiz w13, w14, #29, #3 ubfiz xzr, xzr, #10, #11 -// CHECK: ubfiz w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53] -// CHECK: ubfiz x2, x3, #63, #1 // encoding: [0x62,0x00,0x41,0xd3] -// CHECK: ubfiz x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0xd3] -// CHECK: ubfiz x9, x10, #5, #59 // encoding: [0x49,0xe9,0x7b,0xd3] -// CHECK: ubfiz w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x53] -// CHECK: ubfiz w11, w12, #31, #1 // encoding: [0x8b,0x01,0x01,0x53] -// CHECK: ubfiz w13, w14, #29, #3 // encoding: [0xcd,0x09,0x03,0x53] -// CHECK: ubfiz xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0xd3] + +// CHECK: ubfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53] +// CHECK: lsl x2, x3, #63 // encoding: [0x62,0x00,0x41,0xd3] +// CHECK: lsr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0xd3] +// CHECK: lsl x9, x10, #5 // encoding: [0x49,0xe9,0x7b,0xd3] +// CHECK: lsr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x53] +// CHECK: lsl w11, w12, #31 // encoding: [0x8b,0x01,0x01,0x53] +// CHECK: lsl w13, w14, #29 // encoding: [0xcd,0x09,0x03,0x53] +// CHECK: ubfiz xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0xd3] ubfx w9, w10, #0, #1 ubfx x2, x3, #63, #1 @@ -1096,15 +1103,15 @@ _func: ubfx w11, w12, #31, #1 ubfx w13, w14, #29, #3 ubfx xzr, xzr, #10, #11 -// CHECK: ubfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53] -// CHECK: ubfx x2, x3, #63, #1 // encoding: [0x62,0xfc,0x7f,0xd3] -// CHECK: ubfx x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0xd3] -// CHECK: ubfx x9, x10, #5, #59 // encoding: [0x49,0xfd,0x45,0xd3] -// CHECK: ubfx w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x53] -// CHECK: ubfx w11, w12, #31, #1 // encoding: [0x8b,0x7d,0x1f,0x53] -// CHECK: ubfx w13, w14, #29, #3 // encoding: [0xcd,0x7d,0x1d,0x53] -// CHECK: ubfx xzr, xzr, #10, #11 // encoding: [0xff,0x53,0x4a,0xd3] +// CHECK: ubfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53] +// CHECK: lsr x2, x3, #63 // encoding: [0x62,0xfc,0x7f,0xd3] +// CHECK: lsr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0xd3] +// CHECK: lsr x9, x10, #5 // encoding: [0x49,0xfd,0x45,0xd3] +// CHECK: lsr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x53] +// CHECK: lsr w11, w12, #31 // encoding: [0x8b,0x7d,0x1f,0x53] +// CHECK: lsr w13, w14, #29 // encoding: [0xcd,0x7d,0x1d,0x53] +// CHECK: ubfx xzr, xzr, #10, #11 // encoding: [0xff,0x53,0x4a,0xd3] //------------------------------------------------------------------------------ // Compare & branch (immediate) //------------------------------------------------------------------------------ @@ -1113,21 +1120,22 @@ _func: cbz x5, lbl cbnz x2, lbl cbnz x26, lbl -// CHECK: cbz w5, lbl // encoding: [0x05'A',A,A,0x34'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: cbz x5, lbl // encoding: [0x05'A',A,A,0xb4'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: cbnz x2, lbl // encoding: [0x02'A',A,A,0xb5'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: cbnz x26, lbl // encoding: [0x1a'A',A,A,0xb5'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr +// CHECK: cbz w5, lbl // encoding: [0bAAA00101,A,A,0x34] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: cbz x5, lbl // encoding: [0bAAA00101,A,A,0xb4] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: cbnz x2, lbl // encoding: [0bAAA00010,A,A,0xb5] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: cbnz x26, lbl // encoding: [0bAAA11010,A,A,0xb5] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 cbz wzr, lbl cbnz xzr, lbl -// CHECK: cbz wzr, lbl // encoding: [0x1f'A',A,A,0x34'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: cbnz xzr, lbl // encoding: [0x1f'A',A,A,0xb5'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr + +// CHECK: cbz wzr, lbl // encoding: [0bAAA11111,A,A,0x34] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: cbnz xzr, lbl // encoding: [0bAAA11111,A,A,0xb5] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 cbz w5, #0 cbnz x3, #-4 @@ -1159,41 +1167,43 @@ _func: b.gt lbl b.le lbl b.al lbl -// CHECK: b.eq lbl // encoding: [A,A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.ne lbl // encoding: [0x01'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.hs lbl // encoding: [0x02'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.hs lbl // encoding: [0x02'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.lo lbl // encoding: [0x03'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.lo lbl // encoding: [0x03'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.mi lbl // encoding: [0x04'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.pl lbl // encoding: [0x05'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.vs lbl // encoding: [0x06'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.vc lbl // encoding: [0x07'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.hi lbl // encoding: [0x08'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.ls lbl // encoding: [0x09'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.ge lbl // encoding: [0x0a'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.lt lbl // encoding: [0x0b'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.gt lbl // encoding: [0x0c'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.le lbl // encoding: [0x0d'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.al lbl // encoding: [0x0e'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr +// CHECK: b.eq lbl // encoding: [0bAAA00000,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.ne lbl // encoding: [0bAAA00001,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.hs lbl // encoding: [0bAAA00010,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.hs lbl // encoding: [0bAAA00010,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.lo lbl // encoding: [0bAAA00011,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.lo lbl // encoding: [0bAAA00011,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.mi lbl // encoding: [0bAAA00100,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.pl lbl // encoding: [0bAAA00101,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.vs lbl // encoding: [0bAAA00110,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.vc lbl // encoding: [0bAAA00111,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.hi lbl // encoding: [0bAAA01000,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.ls lbl // encoding: [0bAAA01001,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.ge lbl // encoding: [0bAAA01010,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.lt lbl // encoding: [0bAAA01011,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.gt lbl // encoding: [0bAAA01100,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.le lbl // encoding: [0bAAA01101,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.al lbl // encoding: [0bAAA01110,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 + + // ARM64 has these in a separate file beq lbl bne lbl bcs lbl @@ -1211,40 +1221,6 @@ _func: bgt lbl ble lbl bal lbl -// CHECK: b.eq lbl // encoding: [A,A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.ne lbl // encoding: [0x01'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.hs lbl // encoding: [0x02'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.hs lbl // encoding: [0x02'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.lo lbl // encoding: [0x03'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.lo lbl // encoding: [0x03'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.mi lbl // encoding: [0x04'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.pl lbl // encoding: [0x05'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.vs lbl // encoding: [0x06'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.vc lbl // encoding: [0x07'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.hi lbl // encoding: [0x08'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.ls lbl // encoding: [0x09'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.ge lbl // encoding: [0x0a'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.lt lbl // encoding: [0x0b'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.gt lbl // encoding: [0x0c'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.le lbl // encoding: [0x0d'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.al lbl // encoding: [0x0e'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr b.eq #0 b.lt #-4 @@ -1394,55 +1370,55 @@ _func: cset w3, eq cset x9, pl -// CHECK: csinc w3, wzr, wzr, ne // encoding: [0xe3,0x17,0x9f,0x1a] -// CHECK: csinc x9, xzr, xzr, mi // encoding: [0xe9,0x47,0x9f,0x9a] +// CHECK: cset w3, eq // encoding: [0xe3,0x17,0x9f,0x1a] +// CHECK: cset x9, pl // encoding: [0xe9,0x47,0x9f,0x9a] csetm w20, ne csetm x30, ge -// CHECK: csinv w20, wzr, wzr, eq // encoding: [0xf4,0x03,0x9f,0x5a] -// CHECK: csinv x30, xzr, xzr, lt // encoding: [0xfe,0xb3,0x9f,0xda] +// CHECK: csetm w20, ne // encoding: [0xf4,0x03,0x9f,0x5a] +// CHECK: csetm x30, ge // encoding: [0xfe,0xb3,0x9f,0xda] cinc w3, w5, gt cinc wzr, w4, le cinc w9, wzr, lt -// CHECK: csinc w3, w5, w5, le // encoding: [0xa3,0xd4,0x85,0x1a] -// CHECK: csinc wzr, w4, w4, gt // encoding: [0x9f,0xc4,0x84,0x1a] -// CHECK: csinc w9, wzr, wzr, ge // encoding: [0xe9,0xa7,0x9f,0x1a] +// CHECK: cinc w3, w5, gt // encoding: [0xa3,0xd4,0x85,0x1a] +// CHECK: cinc wzr, w4, le // encoding: [0x9f,0xc4,0x84,0x1a] +// CHECK: cset w9, lt // encoding: [0xe9,0xa7,0x9f,0x1a] cinc x3, x5, gt cinc xzr, x4, le cinc x9, xzr, lt -// CHECK: csinc x3, x5, x5, le // encoding: [0xa3,0xd4,0x85,0x9a] -// CHECK: csinc xzr, x4, x4, gt // encoding: [0x9f,0xc4,0x84,0x9a] -// CHECK: csinc x9, xzr, xzr, ge // encoding: [0xe9,0xa7,0x9f,0x9a] +// CHECK: cinc x3, x5, gt // encoding: [0xa3,0xd4,0x85,0x9a] +// CHECK: cinc xzr, x4, le // encoding: [0x9f,0xc4,0x84,0x9a] +// CHECK: cset x9, lt // encoding: [0xe9,0xa7,0x9f,0x9a] cinv w3, w5, gt cinv wzr, w4, le cinv w9, wzr, lt -// CHECK: csinv w3, w5, w5, le // encoding: [0xa3,0xd0,0x85,0x5a] -// CHECK: csinv wzr, w4, w4, gt // encoding: [0x9f,0xc0,0x84,0x5a] -// CHECK: csinv w9, wzr, wzr, ge // encoding: [0xe9,0xa3,0x9f,0x5a] +// CHECK: cinv w3, w5, gt // encoding: [0xa3,0xd0,0x85,0x5a] +// CHECK: cinv wzr, w4, le // encoding: [0x9f,0xc0,0x84,0x5a] +// CHECK: csetm w9, lt // encoding: [0xe9,0xa3,0x9f,0x5a] cinv x3, x5, gt cinv xzr, x4, le cinv x9, xzr, lt -// CHECK: csinv x3, x5, x5, le // encoding: [0xa3,0xd0,0x85,0xda] -// CHECK: csinv xzr, x4, x4, gt // encoding: [0x9f,0xc0,0x84,0xda] -// CHECK: csinv x9, xzr, xzr, ge // encoding: [0xe9,0xa3,0x9f,0xda] +// CHECK: cinv x3, x5, gt // encoding: [0xa3,0xd0,0x85,0xda] +// CHECK: cinv xzr, x4, le // encoding: [0x9f,0xc0,0x84,0xda] +// CHECK: csetm x9, lt // encoding: [0xe9,0xa3,0x9f,0xda] cneg w3, w5, gt cneg wzr, w4, le cneg w9, wzr, lt -// CHECK: csneg w3, w5, w5, le // encoding: [0xa3,0xd4,0x85,0x5a] -// CHECK: csneg wzr, w4, w4, gt // encoding: [0x9f,0xc4,0x84,0x5a] -// CHECK: csneg w9, wzr, wzr, ge // encoding: [0xe9,0xa7,0x9f,0x5a] +// CHECK: cneg w3, w5, gt // encoding: [0xa3,0xd4,0x85,0x5a] +// CHECK: cneg wzr, w4, le // encoding: [0x9f,0xc4,0x84,0x5a] +// CHECK: cneg w9, wzr, lt // encoding: [0xe9,0xa7,0x9f,0x5a] cneg x3, x5, gt cneg xzr, x4, le cneg x9, xzr, lt -// CHECK: csneg x3, x5, x5, le // encoding: [0xa3,0xd4,0x85,0xda] -// CHECK: csneg xzr, x4, x4, gt // encoding: [0x9f,0xc4,0x84,0xda] -// CHECK: csneg x9, xzr, xzr, ge // encoding: [0xe9,0xa7,0x9f,0xda] +// CHECK: cneg x3, x5, gt // encoding: [0xa3,0xd4,0x85,0xda] +// CHECK: cneg xzr, x4, le // encoding: [0x9f,0xc4,0x84,0xda] +// CHECK: cneg x9, xzr, lt // encoding: [0xe9,0xa7,0x9f,0xda] //------------------------------------------------------------------------------ // Data-processing (1 source) @@ -1699,23 +1675,23 @@ _func: svc #0 svc #65535 // CHECK: svc #0 // encoding: [0x01,0x00,0x00,0xd4] -// CHECK: svc #65535 // encoding: [0xe1,0xff,0x1f,0xd4] +// CHECK: svc #{{65535|0xffff}} // encoding: [0xe1,0xff,0x1f,0xd4] hvc #1 smc #12000 brk #12 hlt #123 -// CHECK: hvc #1 // encoding: [0x22,0x00,0x00,0xd4] -// CHECK: smc #12000 // encoding: [0x03,0xdc,0x05,0xd4] -// CHECK: brk #12 // encoding: [0x80,0x01,0x20,0xd4] -// CHECK: hlt #123 // encoding: [0x60,0x0f,0x40,0xd4] +// CHECK: hvc #{{1|0x1}} // encoding: [0x22,0x00,0x00,0xd4] +// CHECK: smc #{{12000|0x2ee0}} // encoding: [0x03,0xdc,0x05,0xd4] +// CHECK: brk #{{12|0xc}} // encoding: [0x80,0x01,0x20,0xd4] +// CHECK: hlt #{{123|0x7b}} // encoding: [0x60,0x0f,0x40,0xd4] dcps1 #42 dcps2 #9 dcps3 #1000 -// CHECK: dcps1 #42 // encoding: [0x41,0x05,0xa0,0xd4] -// CHECK: dcps2 #9 // encoding: [0x22,0x01,0xa0,0xd4] -// CHECK: dcps3 #1000 // encoding: [0x03,0x7d,0xa0,0xd4] +// CHECK: dcps1 #{{42|0x2a}} // encoding: [0x41,0x05,0xa0,0xd4] +// CHECK: dcps2 #{{9|0x9}} // encoding: [0x22,0x01,0xa0,0xd4] +// CHECK: dcps3 #{{1000|0x3e8}} // encoding: [0x03,0x7d,0xa0,0xd4] dcps1 dcps2 @@ -1740,11 +1716,11 @@ _func: ror x19, x23, #24 ror x29, xzr, #63 -// CHECK: extr x19, x23, x23, #24 // encoding: [0xf3,0x62,0xd7,0x93] -// CHECK: extr x29, xzr, xzr, #63 // encoding: [0xfd,0xff,0xdf,0x93] +// CHECK: ror x19, x23, #24 // encoding: [0xf3,0x62,0xd7,0x93] +// CHECK: ror x29, xzr, #63 // encoding: [0xfd,0xff,0xdf,0x93] ror w9, w13, #31 -// CHECK: extr w9, w13, w13, #31 // encoding: [0xa9,0x7d,0x8d,0x13] +// CHECK: ror w9, w13, #31 // encoding: [0xa9,0x7d,0x8d,0x13] //------------------------------------------------------------------------------ // Floating-point compare @@ -2176,7 +2152,7 @@ _func: fmov x3, v12.d[1] fmov v1.d[1], x19 - fmov v3.2d[1], xzr + fmov v3.d[1], xzr // CHECK: fmov x3, v12.d[1] // encoding: [0x83,0x01,0xae,0x9e] // CHECK: fmov v1.d[1], x19 // encoding: [0x61,0x02,0xaf,0x9e] // CHECK: fmov v3.d[1], xzr // encoding: [0xe3,0x03,0xaf,0x9e] @@ -2188,20 +2164,20 @@ _func: fmov s2, #0.125 fmov s3, #1.0 fmov d30, #16.0 -// CHECK: fmov s2, #0.12500000 // encoding: [0x02,0x10,0x28,0x1e] -// CHECK: fmov s3, #1.00000000 // encoding: [0x03,0x10,0x2e,0x1e] -// CHECK: fmov d30, #16.00000000 // encoding: [0x1e,0x10,0x66,0x1e] +// CHECK: fmov s2, #{{0.12500000|1.250*e-01}} // encoding: [0x02,0x10,0x28,0x1e] +// CHECK: fmov s3, #{{1.00000000|1.0*e\+00}} // encoding: [0x03,0x10,0x2e,0x1e] +// CHECK: fmov d30, #{{16.00000000|1.60*e\+01}} // encoding: [0x1e,0x10,0x66,0x1e] fmov s4, #1.0625 fmov d10, #1.9375 -// CHECK: fmov s4, #1.06250000 // encoding: [0x04,0x30,0x2e,0x1e] -// CHECK: fmov d10, #1.93750000 // encoding: [0x0a,0xf0,0x6f,0x1e] +// CHECK: fmov s4, #{{1.06250*(e\+00)?}} // encoding: [0x04,0x30,0x2e,0x1e] +// CHECK: fmov d10, #{{1.93750*(e\+00)?}} // encoding: [0x0a,0xf0,0x6f,0x1e] fmov s12, #-1.0 -// CHECK: fmov s12, #-1.00000000 // encoding: [0x0c,0x10,0x3e,0x1e] +// CHECK: fmov s12, #{{-1.0*(e\+00)?}} // encoding: [0x0c,0x10,0x3e,0x1e] fmov d16, #8.5 -// CHECK: fmov d16, #8.50000000 // encoding: [0x10,0x30,0x64,0x1e] +// CHECK: fmov d16, #{{8.50*(e\+00)?}} // encoding: [0x10,0x30,0x64,0x1e] //------------------------------------------------------------------------------ // Load-register (literal) @@ -2209,22 +2185,24 @@ _func: ldr w3, here ldr x29, there ldrsw xzr, everywhere -// CHECK: ldr w3, here // encoding: [0x03'A',A,A,0x18'A'] -// CHECK: // fixup A - offset: 0, value: here, kind: fixup_a64_ld_prel -// CHECK: ldr x29, there // encoding: [0x1d'A',A,A,0x58'A'] -// CHECK: // fixup A - offset: 0, value: there, kind: fixup_a64_ld_prel -// CHECK: ldrsw xzr, everywhere // encoding: [0x1f'A',A,A,0x98'A'] -// CHECK: // fixup A - offset: 0, value: everywhere, kind: fixup_a64_ld_prel + +// CHECK: ldr w3, here // encoding: [0bAAA00011,A,A,0x18] +// CHECK: // fixup A - offset: 0, value: here, kind: fixup_aarch64_ldr_pcrel_imm19 +// CHECK: ldr x29, there // encoding: [0bAAA11101,A,A,0x58] +// CHECK: // fixup A - offset: 0, value: there, kind: fixup_aarch64_ldr_pcrel_imm19 +// CHECK: ldrsw xzr, everywhere // encoding: [0bAAA11111,A,A,0x98] +// CHECK: // fixup A - offset: 0, value: everywhere, kind: fixup_aarch64_ldr_pcrel_imm19 ldr s0, who_knows ldr d0, i_dont ldr q0, there_must_be_a_better_way -// CHECK: ldr s0, who_knows // encoding: [A,A,A,0x1c'A'] -// CHECK: // fixup A - offset: 0, value: who_knows, kind: fixup_a64_ld_prel -// CHECK: ldr d0, i_dont // encoding: [A,A,A,0x5c'A'] -// CHECK: // fixup A - offset: 0, value: i_dont, kind: fixup_a64_ld_prel -// CHECK: ldr q0, there_must_be_a_better_way // encoding: [A,A,A,0x9c'A'] -// CHECK: // fixup A - offset: 0, value: there_must_be_a_better_way, kind: fixup_a64_ld_prel + +// CHECK: ldr s0, who_knows // encoding: [0bAAA00000,A,A,0x1c] +// CHECK: // fixup A - offset: 0, value: who_knows, kind: fixup_aarch64_ldr_pcrel_imm19 +// CHECK: ldr d0, i_dont // encoding: [0bAAA00000,A,A,0x5c] +// CHECK: // fixup A - offset: 0, value: i_dont, kind: fixup_aarch64_ldr_pcrel_imm19 +// CHECK: ldr q0, there_must_be_a_better_way // encoding: [0bAAA00000,A,A,0x9c] +// CHECK: // fixup A - offset: 0, value: there_must_be_a_better_way, kind: fixup_aarch64_ldr_pcrel_imm19 ldr w0, #1048572 ldr x10, #-1048576 @@ -2233,32 +2211,11 @@ _func: prfm pldl1strm, nowhere prfm #22, somewhere -// CHECK: prfm pldl1strm, nowhere // encoding: [0x01'A',A,A,0xd8'A'] -// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_a64_ld_prel -// CHECK: prfm #22, somewhere // encoding: [0x16'A',A,A,0xd8'A'] -// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_a64_ld_prel - -//------------------------------------------------------------------------------ -// Floating-point immediate -//------------------------------------------------------------------------------ - fmov s2, #0.125 - fmov s3, #1.0 - fmov d30, #16.0 -// CHECK: fmov s2, #0.12500000 // encoding: [0x02,0x10,0x28,0x1e] -// CHECK: fmov s3, #1.00000000 // encoding: [0x03,0x10,0x2e,0x1e] -// CHECK: fmov d30, #16.00000000 // encoding: [0x1e,0x10,0x66,0x1e] - - fmov s4, #1.0625 - fmov d10, #1.9375 -// CHECK: fmov s4, #1.06250000 // encoding: [0x04,0x30,0x2e,0x1e] -// CHECK: fmov d10, #1.93750000 // encoding: [0x0a,0xf0,0x6f,0x1e] - - fmov s12, #-1.0 -// CHECK: fmov s12, #-1.00000000 // encoding: [0x0c,0x10,0x3e,0x1e] - - fmov d16, #8.5 -// CHECK: fmov d16, #8.50000000 // encoding: [0x10,0x30,0x64,0x1e] +// CHECK: prfm pldl1strm, nowhere // encoding: [0bAAA00001,A,A,0xd8] +// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_aarch64_ldr_pcrel_imm19 +// CHECK: prfm #22, somewhere // encoding: [0bAAA10110,A,A,0xd8] +// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_aarch64_ldr_pcrel_imm19 //------------------------------------------------------------------------------ // Load/store exclusive @@ -2473,18 +2430,19 @@ _func: ldrsw x15, [x5, #:lo12:sym] ldr x15, [x5, #:lo12:sym] ldr q3, [x2, #:lo12:sym] -// CHECK: str x15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,A,0xf9'A'] -// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst64_lo12 -// CHECK: ldrb w15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,0x40'A',0x39'A'] -// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst8_lo12 -// CHECK: ldrsh x15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,0x80'A',0x79'A'] -// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst16_lo12 -// CHECK: ldrsw x15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,0x80'A',0xb9'A'] -// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst32_lo12 -// CHECK: ldr x15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,0x40'A',0xf9'A'] -// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst64_lo12 -// CHECK: ldr q3, [x2, #:lo12:sym] // encoding: [0x43'A',A,0xc0'A',0x3d'A'] -// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst128_lo12 + +// CHECK: str x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b00AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: ldrb w15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b01AAAAAA,0x39] +// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale1 +// CHECK: ldrsh x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b10AAAAAA,0x79] +// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale2 +// CHECK: ldrsw x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b10AAAAAA,0xb9] +// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale4 +// CHECK: ldr x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b01AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: ldr q3, [x2, :lo12:sym] // encoding: [0x43,0bAAAAAA00,0b11AAAAAA,0x3d] +// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale16 prfm pldl1keep, [sp, #8] prfm pldl1strm, [x3] @@ -2506,24 +2464,24 @@ _func: prfm pstl3strm, [x6] prfm #15, [sp] // CHECK: prfm pldl1keep, [sp, #8] // encoding: [0xe0,0x07,0x80,0xf9] -// CHECK: prfm pldl1strm, [x3, #0] // encoding: [0x61,0x00,0x80,0xf9] +// CHECK: prfm pldl1strm, [x3{{(, #0)?}}] // encoding: [0x61,0x00,0x80,0xf9] // CHECK: prfm pldl2keep, [x5, #16] // encoding: [0xa2,0x08,0x80,0xf9] -// CHECK: prfm pldl2strm, [x2, #0] // encoding: [0x43,0x00,0x80,0xf9] -// CHECK: prfm pldl3keep, [x5, #0] // encoding: [0xa4,0x00,0x80,0xf9] -// CHECK: prfm pldl3strm, [x6, #0] // encoding: [0xc5,0x00,0x80,0xf9] +// CHECK: prfm pldl2strm, [x2{{(, #0)?}}] // encoding: [0x43,0x00,0x80,0xf9] +// CHECK: prfm pldl3keep, [x5{{(, #0)?}}] // encoding: [0xa4,0x00,0x80,0xf9] +// CHECK: prfm pldl3strm, [x6{{(, #0)?}}] // encoding: [0xc5,0x00,0x80,0xf9] // CHECK: prfm plil1keep, [sp, #8] // encoding: [0xe8,0x07,0x80,0xf9] -// CHECK: prfm plil1strm, [x3, #0] // encoding: [0x69,0x00,0x80,0xf9] +// CHECK: prfm plil1strm, [x3{{(, #0)?}}] // encoding: [0x69,0x00,0x80,0xf9] // CHECK: prfm plil2keep, [x5, #16] // encoding: [0xaa,0x08,0x80,0xf9] -// CHECK: prfm plil2strm, [x2, #0] // encoding: [0x4b,0x00,0x80,0xf9] -// CHECK: prfm plil3keep, [x5, #0] // encoding: [0xac,0x00,0x80,0xf9] -// CHECK: prfm plil3strm, [x6, #0] // encoding: [0xcd,0x00,0x80,0xf9] +// CHECK: prfm plil2strm, [x2{{(, #0)?}}] // encoding: [0x4b,0x00,0x80,0xf9] +// CHECK: prfm plil3keep, [x5{{(, #0)?}}] // encoding: [0xac,0x00,0x80,0xf9] +// CHECK: prfm plil3strm, [x6{{(, #0)?}}] // encoding: [0xcd,0x00,0x80,0xf9] // CHECK: prfm pstl1keep, [sp, #8] // encoding: [0xf0,0x07,0x80,0xf9] -// CHECK: prfm pstl1strm, [x3, #0] // encoding: [0x71,0x00,0x80,0xf9] +// CHECK: prfm pstl1strm, [x3{{(, #0)?}}] // encoding: [0x71,0x00,0x80,0xf9] // CHECK: prfm pstl2keep, [x5, #16] // encoding: [0xb2,0x08,0x80,0xf9] -// CHECK: prfm pstl2strm, [x2, #0] // encoding: [0x53,0x00,0x80,0xf9] -// CHECK: prfm pstl3keep, [x5, #0] // encoding: [0xb4,0x00,0x80,0xf9] -// CHECK: prfm pstl3strm, [x6, #0] // encoding: [0xd5,0x00,0x80,0xf9] -// CHECK: prfm #15, [sp, #0] // encoding: [0xef,0x03,0x80,0xf9] +// CHECK: prfm pstl2strm, [x2{{(, #0)?}}] // encoding: [0x53,0x00,0x80,0xf9] +// CHECK: prfm pstl3keep, [x5{{(, #0)?}}] // encoding: [0xb4,0x00,0x80,0xf9] +// CHECK: prfm pstl3strm, [x6{{(, #0)?}}] // encoding: [0xd5,0x00,0x80,0xf9] +// CHECK: prfm #15, [sp{{(, #0)?}}] // encoding: [0xef,0x03,0x80,0xf9] //// Floating-point versions @@ -2636,7 +2594,7 @@ _func: // CHECK: ldr x17, [x23, w9, sxtw] // encoding: [0xf1,0xca,0x69,0xf8] // CHECK: ldr x18, [x22, w10, sxtw] // encoding: [0xd2,0xca,0x6a,0xf8] // CHECK: str d19, [x21, wzr, sxtw #3] // encoding: [0xb3,0xda,0x3f,0xfc] -// CHECK: prfm #6, [x0, x5, lsl #0] // encoding: [0x06,0x68,0xa5,0xf8] +// CHECK: prfm #6, [x0, x5{{(, lsl #0)?}}] // encoding: [0x06,0x68,0xa5,0xf8] ldr q3, [sp, x5] ldr q9, [x27, x6, lsl #0] @@ -3218,15 +3176,15 @@ _func: ands wzr, w18, #0xcccccccc ands w19, w20, #0x33333333 ands w21, w22, #0x99999999 -// CHECK: ands wzr, w18, #0xcccccccc // encoding: [0x5f,0xe6,0x02,0x72] +// CHECK: {{ands wzr,|tst}} w18, #0xcccccccc // encoding: [0x5f,0xe6,0x02,0x72] // CHECK: ands w19, w20, #0x33333333 // encoding: [0x93,0xe6,0x00,0x72] // CHECK: ands w21, w22, #0x99999999 // encoding: [0xd5,0xe6,0x01,0x72] // 2 bit replication width tst w3, #0xaaaaaaaa tst wzr, #0x55555555 -// CHECK: ands wzr, w3, #0xaaaaaaaa // encoding: [0x7f,0xf0,0x01,0x72] -// CHECK: ands wzr, wzr, #0x55555555 // encoding: [0xff,0xf3,0x00,0x72] +// CHECK: {{ands wzr,|tst}} w3, #0xaaaaaaaa // encoding: [0x7f,0xf0,0x01,0x72] +// CHECK: {{ands wzr,|tst}} wzr, #0x55555555 // encoding: [0xff,0xf3,0x00,0x72] // 64 bit replication-width eor x3, x5, #0xffffffffc000000 @@ -3264,20 +3222,20 @@ _func: ands xzr, x18, #0xcccccccccccccccc ands x19, x20, #0x3333333333333333 ands x21, x22, #0x9999999999999999 -// CHECK: ands xzr, x18, #0xcccccccccccccccc // encoding: [0x5f,0xe6,0x02,0xf2] +// CHECK: {{ands xzr,|tst}} x18, #0xcccccccccccccccc // encoding: [0x5f,0xe6,0x02,0xf2] // CHECK: ands x19, x20, #0x3333333333333333 // encoding: [0x93,0xe6,0x00,0xf2] // CHECK: ands x21, x22, #0x9999999999999999 // encoding: [0xd5,0xe6,0x01,0xf2] // 2 bit replication-width tst x3, #0xaaaaaaaaaaaaaaaa tst xzr, #0x5555555555555555 -// CHECK: ands xzr, x3, #0xaaaaaaaaaaaaaaaa // encoding: [0x7f,0xf0,0x01,0xf2] -// CHECK: ands xzr, xzr, #0x5555555555555555 // encoding: [0xff,0xf3,0x00,0xf2] +// CHECK: {{ands xzr,|tst}} x3, #0xaaaaaaaaaaaaaaaa // encoding: [0x7f,0xf0,0x01,0xf2] +// CHECK: {{ands xzr,|tst}} xzr, #0x5555555555555555 // encoding: [0xff,0xf3,0x00,0xf2] mov w3, #0xf000f mov x10, #0xaaaaaaaaaaaaaaaa // CHECK: orr w3, wzr, #0xf000f // encoding: [0xe3,0x8f,0x00,0x32] -// CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa // encoding: [0xea,0xf3,0x01,0xb2] +// CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa // encoding: [0xea,0xf3,0x01,0xb2] //------------------------------------------------------------------------------ // Logical (shifted register) @@ -3353,75 +3311,83 @@ _func: movz w1, #65535, lsl #0 movz w2, #0, lsl #16 movn w2, #1234, lsl #0 -// CHECK: movz w1, #65535 // encoding: [0xe1,0xff,0x9f,0x52] +// CHECK: movz w1, #{{65535|0xffff}} // encoding: [0xe1,0xff,0x9f,0x52] // CHECK: movz w2, #0, lsl #16 // encoding: [0x02,0x00,0xa0,0x52] -// CHECK: movn w2, #1234 // encoding: [0x42,0x9a,0x80,0x12] +// CHECK: movn w2, #{{1234|0x4d2}} // encoding: [0x42,0x9a,0x80,0x12] movz x2, #1234, lsl #32 movk xzr, #4321, lsl #48 -// CHECK: movz x2, #1234, lsl #32 // encoding: [0x42,0x9a,0xc0,0xd2] -// CHECK: movk xzr, #4321, lsl #48 // encoding: [0x3f,0x1c,0xe2,0xf2] +// CHECK: movz x2, #{{1234|0x4d2}}, lsl #32 // encoding: [0x42,0x9a,0xc0,0xd2] +// CHECK: movk xzr, #{{4321|0x10e1}}, lsl #48 // encoding: [0x3f,0x1c,0xe2,0xf2] movz x2, #:abs_g0:sym movk w3, #:abs_g0_nc:sym -// CHECK: movz x2, #:abs_g0:sym // encoding: [0x02'A',A,0x80'A',0xd2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_a64_movw_uabs_g0 -// CHECK: movk w3, #:abs_g0_nc:sym // encoding: [0x03'A',A,0x80'A',0x72'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_a64_movw_uabs_g0_nc + +// CHECK: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_aarch64_movw +// CHECK: movk w3, #:abs_g0_nc:sym // encoding: [0bAAA00011,A,0b100AAAAA,0x72] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_aarch64_movw movz x4, #:abs_g1:sym movk w5, #:abs_g1_nc:sym -// CHECK: movz x4, #:abs_g1:sym // encoding: [0x04'A',A,0xa0'A',0xd2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_a64_movw_uabs_g1 -// CHECK: movk w5, #:abs_g1_nc:sym // encoding: [0x05'A',A,0xa0'A',0x72'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_a64_movw_uabs_g1_nc + +// CHECK: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_aarch64_movw +// CHECK: movk w5, #:abs_g1_nc:sym // encoding: [0bAAA00101,A,0b101AAAAA,0x72] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_aarch64_movw movz x6, #:abs_g2:sym movk x7, #:abs_g2_nc:sym -// CHECK: movz x6, #:abs_g2:sym // encoding: [0x06'A',A,0xc0'A',0xd2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_a64_movw_uabs_g2 -// CHECK: movk x7, #:abs_g2_nc:sym // encoding: [0x07'A',A,0xc0'A',0xf2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_a64_movw_uabs_g2_nc + +// CHECK: movz x6, #:abs_g2:sym // encoding: [0bAAA00110,A,0b110AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_aarch64_movw +// CHECK: movk x7, #:abs_g2_nc:sym // encoding: [0bAAA00111,A,0b110AAAAA,0xf2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_aarch64_movw movz x8, #:abs_g3:sym movk x9, #:abs_g3:sym -// CHECK: movz x8, #:abs_g3:sym // encoding: [0x08'A',A,0xe0'A',0xd2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_a64_movw_uabs_g3 -// CHECK: movk x9, #:abs_g3:sym // encoding: [0x09'A',A,0xe0'A',0xf2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_a64_movw_uabs_g3 + +// CHECK: movz x8, #:abs_g3:sym // encoding: [0bAAA01000,A,0b111AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_aarch64_movw +// CHECK: movk x9, #:abs_g3:sym // encoding: [0bAAA01001,A,0b111AAAAA,0xf2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_aarch64_movw + movn x30, #:abs_g0_s:sym movz x19, #:abs_g0_s:sym movn w10, #:abs_g0_s:sym movz w25, #:abs_g0_s:sym -// CHECK: movn x30, #:abs_g0_s:sym // encoding: [0x1e'A',A,0x80'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0 -// CHECK: movz x19, #:abs_g0_s:sym // encoding: [0x13'A',A,0x80'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0 -// CHECK: movn w10, #:abs_g0_s:sym // encoding: [0x0a'A',A,0x80'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0 -// CHECK: movz w25, #:abs_g0_s:sym // encoding: [0x19'A',A,0x80'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0 + +// CHECK: movn x30, #:abs_g0_s:sym // encoding: [0bAAA11110,A,0b100AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw +// CHECK: movz x19, #:abs_g0_s:sym // encoding: [0bAAA10011,A,0b100AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw +// CHECK: movn w10, #:abs_g0_s:sym // encoding: [0bAAA01010,A,0b100AAAAA,0x12] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw +// CHECK: movz w25, #:abs_g0_s:sym // encoding: [0bAAA11001,A,0b100AAAAA,0x52] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw movn x30, #:abs_g1_s:sym movz x19, #:abs_g1_s:sym movn w10, #:abs_g1_s:sym movz w25, #:abs_g1_s:sym -// CHECK: movn x30, #:abs_g1_s:sym // encoding: [0x1e'A',A,0xa0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1 -// CHECK: movz x19, #:abs_g1_s:sym // encoding: [0x13'A',A,0xa0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1 -// CHECK: movn w10, #:abs_g1_s:sym // encoding: [0x0a'A',A,0xa0'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1 -// CHECK: movz w25, #:abs_g1_s:sym // encoding: [0x19'A',A,0xa0'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1 + +// CHECK: movn x30, #:abs_g1_s:sym // encoding: [0bAAA11110,A,0b101AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_aarch64_movw +// CHECK: movz x19, #:abs_g1_s:sym // encoding: [0bAAA10011,A,0b101AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_aarch64_movw +// CHECK: movn w10, #:abs_g1_s:sym // encoding: [0bAAA01010,A,0b101AAAAA,0x12] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_aarch64_movw +// CHECK: movz w25, #:abs_g1_s:sym // encoding: [0bAAA11001,A,0b101AAAAA,0x52] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_aarch64_movw movn x30, #:abs_g2_s:sym movz x19, #:abs_g2_s:sym -// CHECK: movn x30, #:abs_g2_s:sym // encoding: [0x1e'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_a64_movw_sabs_g2 -// CHECK: movz x19, #:abs_g2_s:sym // encoding: [0x13'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_a64_movw_sabs_g2 + +// CHECK: movn x30, #:abs_g2_s:sym // encoding: [0bAAA11110,A,0b110AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_aarch64_movw +// CHECK: movz x19, #:abs_g2_s:sym // encoding: [0bAAA10011,A,0b110AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_aarch64_movw //------------------------------------------------------------------------------ // PC-relative addressing @@ -3429,15 +3395,16 @@ _func: adr x2, loc adr xzr, loc - // CHECK: adr x2, loc // encoding: [0x02'A',A,A,0x10'A'] - // CHECK: // fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel - // CHECK: adr xzr, loc // encoding: [0x1f'A',A,A,0x10'A'] - // CHECK: // fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel + +// CHECK: adr x2, loc // encoding: [0x02'A',A,A,0x10'A'] +// CHECK: // fixup A - offset: 0, value: loc, kind: fixup_aarch64_pcrel_adr_imm21 +// CHECK: adr xzr, loc // encoding: [0x1f'A',A,A,0x10'A'] +// CHECK: // fixup A - offset: 0, value: loc, kind: fixup_aarch64_pcrel_adr_imm21 adrp x29, loc - // CHECK: adrp x29, loc // encoding: [0x1d'A',A,A,0x90'A'] - // CHECK: // fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel_page +// CHECK: adrp x29, loc // encoding: [0x1d'A',A,A,0x90'A'] +// CHECK: // fixup A - offset: 0, value: loc, kind: fixup_aarch64_pcrel_adrp_imm21 adrp x30, #4096 adr x20, #0 adr x9, #-1 @@ -3463,7 +3430,7 @@ _func: hint #0 hint #127 // CHECK: nop // encoding: [0x1f,0x20,0x03,0xd5] -// CHECK: hint #127 // encoding: [0xff,0x2f,0x03,0xd5] +// CHECK: hint #{{127|0x7f}} // encoding: [0xff,0x2f,0x03,0xd5] nop yield @@ -3560,14 +3527,14 @@ _func: msr spsel, #0 msr daifset, #15 msr daifclr, #12 -// CHECK: msr spsel, #0 // encoding: [0xbf,0x40,0x00,0xd5] -// CHECK: msr daifset, #15 // encoding: [0xdf,0x4f,0x03,0xd5] -// CHECK: msr daifclr, #12 // encoding: [0xff,0x4c,0x03,0xd5] +// CHECK: msr {{spsel|SPSEL}}, #0 // encoding: [0xbf,0x40,0x00,0xd5] +// CHECK: msr {{daifset|DAIFSET}}, #15 // encoding: [0xdf,0x4f,0x03,0xd5] +// CHECK: msr {{daifclr|DAIFCLR}}, #12 // encoding: [0xff,0x4c,0x03,0xd5] sys #7, c5, c9, #7, x5 sys #0, c15, c15, #2 // CHECK: sys #7, c5, c9, #7, x5 // encoding: [0xe5,0x59,0x0f,0xd5] -// CHECK: sys #0, c15, c15, #2, xzr // encoding: [0x5f,0xff,0x08,0xd5] +// CHECK: sys #0, c15, c15, #2 // encoding: [0x5f,0xff,0x08,0xd5] sysl x9, #7, c5, c9, #7 sysl x1, #0, c15, c15, #2 @@ -3942,260 +3909,260 @@ _func: msr PMEVTYPER28_EL0, x12 msr PMEVTYPER29_EL0, x12 msr PMEVTYPER30_EL0, x12 -// CHECK: msr teecr32_el1, x12 // encoding: [0x0c,0x00,0x12,0xd5] -// CHECK: msr osdtrrx_el1, x12 // encoding: [0x4c,0x00,0x10,0xd5] -// CHECK: msr mdccint_el1, x12 // encoding: [0x0c,0x02,0x10,0xd5] -// CHECK: msr mdscr_el1, x12 // encoding: [0x4c,0x02,0x10,0xd5] -// CHECK: msr osdtrtx_el1, x12 // encoding: [0x4c,0x03,0x10,0xd5] -// CHECK: msr dbgdtr_el0, x12 // encoding: [0x0c,0x04,0x13,0xd5] -// CHECK: msr dbgdtrtx_el0, x12 // encoding: [0x0c,0x05,0x13,0xd5] -// CHECK: msr oseccr_el1, x12 // encoding: [0x4c,0x06,0x10,0xd5] -// CHECK: msr dbgvcr32_el2, x12 // encoding: [0x0c,0x07,0x14,0xd5] -// CHECK: msr dbgbvr0_el1, x12 // encoding: [0x8c,0x00,0x10,0xd5] -// CHECK: msr dbgbvr1_el1, x12 // encoding: [0x8c,0x01,0x10,0xd5] -// CHECK: msr dbgbvr2_el1, x12 // encoding: [0x8c,0x02,0x10,0xd5] -// CHECK: msr dbgbvr3_el1, x12 // encoding: [0x8c,0x03,0x10,0xd5] -// CHECK: msr dbgbvr4_el1, x12 // encoding: [0x8c,0x04,0x10,0xd5] -// CHECK: msr dbgbvr5_el1, x12 // encoding: [0x8c,0x05,0x10,0xd5] -// CHECK: msr dbgbvr6_el1, x12 // encoding: [0x8c,0x06,0x10,0xd5] -// CHECK: msr dbgbvr7_el1, x12 // encoding: [0x8c,0x07,0x10,0xd5] -// CHECK: msr dbgbvr8_el1, x12 // encoding: [0x8c,0x08,0x10,0xd5] -// CHECK: msr dbgbvr9_el1, x12 // encoding: [0x8c,0x09,0x10,0xd5] -// CHECK: msr dbgbvr10_el1, x12 // encoding: [0x8c,0x0a,0x10,0xd5] -// CHECK: msr dbgbvr11_el1, x12 // encoding: [0x8c,0x0b,0x10,0xd5] -// CHECK: msr dbgbvr12_el1, x12 // encoding: [0x8c,0x0c,0x10,0xd5] -// CHECK: msr dbgbvr13_el1, x12 // encoding: [0x8c,0x0d,0x10,0xd5] -// CHECK: msr dbgbvr14_el1, x12 // encoding: [0x8c,0x0e,0x10,0xd5] -// CHECK: msr dbgbvr15_el1, x12 // encoding: [0x8c,0x0f,0x10,0xd5] -// CHECK: msr dbgbcr0_el1, x12 // encoding: [0xac,0x00,0x10,0xd5] -// CHECK: msr dbgbcr1_el1, x12 // encoding: [0xac,0x01,0x10,0xd5] -// CHECK: msr dbgbcr2_el1, x12 // encoding: [0xac,0x02,0x10,0xd5] -// CHECK: msr dbgbcr3_el1, x12 // encoding: [0xac,0x03,0x10,0xd5] -// CHECK: msr dbgbcr4_el1, x12 // encoding: [0xac,0x04,0x10,0xd5] -// CHECK: msr dbgbcr5_el1, x12 // encoding: [0xac,0x05,0x10,0xd5] -// CHECK: msr dbgbcr6_el1, x12 // encoding: [0xac,0x06,0x10,0xd5] -// CHECK: msr dbgbcr7_el1, x12 // encoding: [0xac,0x07,0x10,0xd5] -// CHECK: msr dbgbcr8_el1, x12 // encoding: [0xac,0x08,0x10,0xd5] -// CHECK: msr dbgbcr9_el1, x12 // encoding: [0xac,0x09,0x10,0xd5] -// CHECK: msr dbgbcr10_el1, x12 // encoding: [0xac,0x0a,0x10,0xd5] -// CHECK: msr dbgbcr11_el1, x12 // encoding: [0xac,0x0b,0x10,0xd5] -// CHECK: msr dbgbcr12_el1, x12 // encoding: [0xac,0x0c,0x10,0xd5] -// CHECK: msr dbgbcr13_el1, x12 // encoding: [0xac,0x0d,0x10,0xd5] -// CHECK: msr dbgbcr14_el1, x12 // encoding: [0xac,0x0e,0x10,0xd5] -// CHECK: msr dbgbcr15_el1, x12 // encoding: [0xac,0x0f,0x10,0xd5] -// CHECK: msr dbgwvr0_el1, x12 // encoding: [0xcc,0x00,0x10,0xd5] -// CHECK: msr dbgwvr1_el1, x12 // encoding: [0xcc,0x01,0x10,0xd5] -// CHECK: msr dbgwvr2_el1, x12 // encoding: [0xcc,0x02,0x10,0xd5] -// CHECK: msr dbgwvr3_el1, x12 // encoding: [0xcc,0x03,0x10,0xd5] -// CHECK: msr dbgwvr4_el1, x12 // encoding: [0xcc,0x04,0x10,0xd5] -// CHECK: msr dbgwvr5_el1, x12 // encoding: [0xcc,0x05,0x10,0xd5] -// CHECK: msr dbgwvr6_el1, x12 // encoding: [0xcc,0x06,0x10,0xd5] -// CHECK: msr dbgwvr7_el1, x12 // encoding: [0xcc,0x07,0x10,0xd5] -// CHECK: msr dbgwvr8_el1, x12 // encoding: [0xcc,0x08,0x10,0xd5] -// CHECK: msr dbgwvr9_el1, x12 // encoding: [0xcc,0x09,0x10,0xd5] -// CHECK: msr dbgwvr10_el1, x12 // encoding: [0xcc,0x0a,0x10,0xd5] -// CHECK: msr dbgwvr11_el1, x12 // encoding: [0xcc,0x0b,0x10,0xd5] -// CHECK: msr dbgwvr12_el1, x12 // encoding: [0xcc,0x0c,0x10,0xd5] -// CHECK: msr dbgwvr13_el1, x12 // encoding: [0xcc,0x0d,0x10,0xd5] -// CHECK: msr dbgwvr14_el1, x12 // encoding: [0xcc,0x0e,0x10,0xd5] -// CHECK: msr dbgwvr15_el1, x12 // encoding: [0xcc,0x0f,0x10,0xd5] -// CHECK: msr dbgwcr0_el1, x12 // encoding: [0xec,0x00,0x10,0xd5] -// CHECK: msr dbgwcr1_el1, x12 // encoding: [0xec,0x01,0x10,0xd5] -// CHECK: msr dbgwcr2_el1, x12 // encoding: [0xec,0x02,0x10,0xd5] -// CHECK: msr dbgwcr3_el1, x12 // encoding: [0xec,0x03,0x10,0xd5] -// CHECK: msr dbgwcr4_el1, x12 // encoding: [0xec,0x04,0x10,0xd5] -// CHECK: msr dbgwcr5_el1, x12 // encoding: [0xec,0x05,0x10,0xd5] -// CHECK: msr dbgwcr6_el1, x12 // encoding: [0xec,0x06,0x10,0xd5] -// CHECK: msr dbgwcr7_el1, x12 // encoding: [0xec,0x07,0x10,0xd5] -// CHECK: msr dbgwcr8_el1, x12 // encoding: [0xec,0x08,0x10,0xd5] -// CHECK: msr dbgwcr9_el1, x12 // encoding: [0xec,0x09,0x10,0xd5] -// CHECK: msr dbgwcr10_el1, x12 // encoding: [0xec,0x0a,0x10,0xd5] -// CHECK: msr dbgwcr11_el1, x12 // encoding: [0xec,0x0b,0x10,0xd5] -// CHECK: msr dbgwcr12_el1, x12 // encoding: [0xec,0x0c,0x10,0xd5] -// CHECK: msr dbgwcr13_el1, x12 // encoding: [0xec,0x0d,0x10,0xd5] -// CHECK: msr dbgwcr14_el1, x12 // encoding: [0xec,0x0e,0x10,0xd5] -// CHECK: msr dbgwcr15_el1, x12 // encoding: [0xec,0x0f,0x10,0xd5] -// CHECK: msr teehbr32_el1, x12 // encoding: [0x0c,0x10,0x12,0xd5] -// CHECK: msr oslar_el1, x12 // encoding: [0x8c,0x10,0x10,0xd5] -// CHECK: msr osdlr_el1, x12 // encoding: [0x8c,0x13,0x10,0xd5] -// CHECK: msr dbgprcr_el1, x12 // encoding: [0x8c,0x14,0x10,0xd5] -// CHECK: msr dbgclaimset_el1, x12 // encoding: [0xcc,0x78,0x10,0xd5] -// CHECK: msr dbgclaimclr_el1, x12 // encoding: [0xcc,0x79,0x10,0xd5] -// CHECK: msr csselr_el1, x12 // encoding: [0x0c,0x00,0x1a,0xd5] -// CHECK: msr vpidr_el2, x12 // encoding: [0x0c,0x00,0x1c,0xd5] -// CHECK: msr vmpidr_el2, x12 // encoding: [0xac,0x00,0x1c,0xd5] -// CHECK: msr sctlr_el1, x12 // encoding: [0x0c,0x10,0x18,0xd5] -// CHECK: msr sctlr_el2, x12 // encoding: [0x0c,0x10,0x1c,0xd5] -// CHECK: msr sctlr_el3, x12 // encoding: [0x0c,0x10,0x1e,0xd5] -// CHECK: msr actlr_el1, x12 // encoding: [0x2c,0x10,0x18,0xd5] -// CHECK: msr actlr_el2, x12 // encoding: [0x2c,0x10,0x1c,0xd5] -// CHECK: msr actlr_el3, x12 // encoding: [0x2c,0x10,0x1e,0xd5] -// CHECK: msr cpacr_el1, x12 // encoding: [0x4c,0x10,0x18,0xd5] -// CHECK: msr hcr_el2, x12 // encoding: [0x0c,0x11,0x1c,0xd5] -// CHECK: msr scr_el3, x12 // encoding: [0x0c,0x11,0x1e,0xd5] -// CHECK: msr mdcr_el2, x12 // encoding: [0x2c,0x11,0x1c,0xd5] -// CHECK: msr sder32_el3, x12 // encoding: [0x2c,0x11,0x1e,0xd5] -// CHECK: msr cptr_el2, x12 // encoding: [0x4c,0x11,0x1c,0xd5] -// CHECK: msr cptr_el3, x12 // encoding: [0x4c,0x11,0x1e,0xd5] -// CHECK: msr hstr_el2, x12 // encoding: [0x6c,0x11,0x1c,0xd5] -// CHECK: msr hacr_el2, x12 // encoding: [0xec,0x11,0x1c,0xd5] -// CHECK: msr mdcr_el3, x12 // encoding: [0x2c,0x13,0x1e,0xd5] -// CHECK: msr ttbr0_el1, x12 // encoding: [0x0c,0x20,0x18,0xd5] -// CHECK: msr ttbr0_el2, x12 // encoding: [0x0c,0x20,0x1c,0xd5] -// CHECK: msr ttbr0_el3, x12 // encoding: [0x0c,0x20,0x1e,0xd5] -// CHECK: msr ttbr1_el1, x12 // encoding: [0x2c,0x20,0x18,0xd5] -// CHECK: msr tcr_el1, x12 // encoding: [0x4c,0x20,0x18,0xd5] -// CHECK: msr tcr_el2, x12 // encoding: [0x4c,0x20,0x1c,0xd5] -// CHECK: msr tcr_el3, x12 // encoding: [0x4c,0x20,0x1e,0xd5] -// CHECK: msr vttbr_el2, x12 // encoding: [0x0c,0x21,0x1c,0xd5] -// CHECK: msr vtcr_el2, x12 // encoding: [0x4c,0x21,0x1c,0xd5] -// CHECK: msr dacr32_el2, x12 // encoding: [0x0c,0x30,0x1c,0xd5] -// CHECK: msr spsr_el1, x12 // encoding: [0x0c,0x40,0x18,0xd5] -// CHECK: msr spsr_el2, x12 // encoding: [0x0c,0x40,0x1c,0xd5] -// CHECK: msr spsr_el3, x12 // encoding: [0x0c,0x40,0x1e,0xd5] -// CHECK: msr elr_el1, x12 // encoding: [0x2c,0x40,0x18,0xd5] -// CHECK: msr elr_el2, x12 // encoding: [0x2c,0x40,0x1c,0xd5] -// CHECK: msr elr_el3, x12 // encoding: [0x2c,0x40,0x1e,0xd5] -// CHECK: msr sp_el0, x12 // encoding: [0x0c,0x41,0x18,0xd5] -// CHECK: msr sp_el1, x12 // encoding: [0x0c,0x41,0x1c,0xd5] -// CHECK: msr sp_el2, x12 // encoding: [0x0c,0x41,0x1e,0xd5] -// CHECK: msr spsel, x12 // encoding: [0x0c,0x42,0x18,0xd5] -// CHECK: msr nzcv, x12 // encoding: [0x0c,0x42,0x1b,0xd5] -// CHECK: msr daif, x12 // encoding: [0x2c,0x42,0x1b,0xd5] -// CHECK: msr currentel, x12 // encoding: [0x4c,0x42,0x18,0xd5] -// CHECK: msr spsr_irq, x12 // encoding: [0x0c,0x43,0x1c,0xd5] -// CHECK: msr spsr_abt, x12 // encoding: [0x2c,0x43,0x1c,0xd5] -// CHECK: msr spsr_und, x12 // encoding: [0x4c,0x43,0x1c,0xd5] -// CHECK: msr spsr_fiq, x12 // encoding: [0x6c,0x43,0x1c,0xd5] -// CHECK: msr fpcr, x12 // encoding: [0x0c,0x44,0x1b,0xd5] -// CHECK: msr fpsr, x12 // encoding: [0x2c,0x44,0x1b,0xd5] -// CHECK: msr dspsr_el0, x12 // encoding: [0x0c,0x45,0x1b,0xd5] -// CHECK: msr dlr_el0, x12 // encoding: [0x2c,0x45,0x1b,0xd5] -// CHECK: msr ifsr32_el2, x12 // encoding: [0x2c,0x50,0x1c,0xd5] -// CHECK: msr afsr0_el1, x12 // encoding: [0x0c,0x51,0x18,0xd5] -// CHECK: msr afsr0_el2, x12 // encoding: [0x0c,0x51,0x1c,0xd5] -// CHECK: msr afsr0_el3, x12 // encoding: [0x0c,0x51,0x1e,0xd5] -// CHECK: msr afsr1_el1, x12 // encoding: [0x2c,0x51,0x18,0xd5] -// CHECK: msr afsr1_el2, x12 // encoding: [0x2c,0x51,0x1c,0xd5] -// CHECK: msr afsr1_el3, x12 // encoding: [0x2c,0x51,0x1e,0xd5] -// CHECK: msr esr_el1, x12 // encoding: [0x0c,0x52,0x18,0xd5] -// CHECK: msr esr_el2, x12 // encoding: [0x0c,0x52,0x1c,0xd5] -// CHECK: msr esr_el3, x12 // encoding: [0x0c,0x52,0x1e,0xd5] -// CHECK: msr fpexc32_el2, x12 // encoding: [0x0c,0x53,0x1c,0xd5] -// CHECK: msr far_el1, x12 // encoding: [0x0c,0x60,0x18,0xd5] -// CHECK: msr far_el2, x12 // encoding: [0x0c,0x60,0x1c,0xd5] -// CHECK: msr far_el3, x12 // encoding: [0x0c,0x60,0x1e,0xd5] -// CHECK: msr hpfar_el2, x12 // encoding: [0x8c,0x60,0x1c,0xd5] -// CHECK: msr par_el1, x12 // encoding: [0x0c,0x74,0x18,0xd5] -// CHECK: msr pmcr_el0, x12 // encoding: [0x0c,0x9c,0x1b,0xd5] -// CHECK: msr pmcntenset_el0, x12 // encoding: [0x2c,0x9c,0x1b,0xd5] -// CHECK: msr pmcntenclr_el0, x12 // encoding: [0x4c,0x9c,0x1b,0xd5] -// CHECK: msr pmovsclr_el0, x12 // encoding: [0x6c,0x9c,0x1b,0xd5] -// CHECK: msr pmselr_el0, x12 // encoding: [0xac,0x9c,0x1b,0xd5] -// CHECK: msr pmccntr_el0, x12 // encoding: [0x0c,0x9d,0x1b,0xd5] -// CHECK: msr pmxevtyper_el0, x12 // encoding: [0x2c,0x9d,0x1b,0xd5] -// CHECK: msr pmxevcntr_el0, x12 // encoding: [0x4c,0x9d,0x1b,0xd5] -// CHECK: msr pmuserenr_el0, x12 // encoding: [0x0c,0x9e,0x1b,0xd5] -// CHECK: msr pmintenset_el1, x12 // encoding: [0x2c,0x9e,0x18,0xd5] -// CHECK: msr pmintenclr_el1, x12 // encoding: [0x4c,0x9e,0x18,0xd5] -// CHECK: msr pmovsset_el0, x12 // encoding: [0x6c,0x9e,0x1b,0xd5] -// CHECK: msr mair_el1, x12 // encoding: [0x0c,0xa2,0x18,0xd5] -// CHECK: msr mair_el2, x12 // encoding: [0x0c,0xa2,0x1c,0xd5] -// CHECK: msr mair_el3, x12 // encoding: [0x0c,0xa2,0x1e,0xd5] -// CHECK: msr amair_el1, x12 // encoding: [0x0c,0xa3,0x18,0xd5] -// CHECK: msr amair_el2, x12 // encoding: [0x0c,0xa3,0x1c,0xd5] -// CHECK: msr amair_el3, x12 // encoding: [0x0c,0xa3,0x1e,0xd5] -// CHECK: msr vbar_el1, x12 // encoding: [0x0c,0xc0,0x18,0xd5] -// CHECK: msr vbar_el2, x12 // encoding: [0x0c,0xc0,0x1c,0xd5] -// CHECK: msr vbar_el3, x12 // encoding: [0x0c,0xc0,0x1e,0xd5] -// CHECK: msr rmr_el1, x12 // encoding: [0x4c,0xc0,0x18,0xd5] -// CHECK: msr rmr_el2, x12 // encoding: [0x4c,0xc0,0x1c,0xd5] -// CHECK: msr rmr_el3, x12 // encoding: [0x4c,0xc0,0x1e,0xd5] -// CHECK: msr contextidr_el1, x12 // encoding: [0x2c,0xd0,0x18,0xd5] -// CHECK: msr tpidr_el0, x12 // encoding: [0x4c,0xd0,0x1b,0xd5] -// CHECK: msr tpidr_el2, x12 // encoding: [0x4c,0xd0,0x1c,0xd5] -// CHECK: msr tpidr_el3, x12 // encoding: [0x4c,0xd0,0x1e,0xd5] -// CHECK: msr tpidrro_el0, x12 // encoding: [0x6c,0xd0,0x1b,0xd5] -// CHECK: msr tpidr_el1, x12 // encoding: [0x8c,0xd0,0x18,0xd5] -// CHECK: msr cntfrq_el0, x12 // encoding: [0x0c,0xe0,0x1b,0xd5] -// CHECK: msr cntvoff_el2, x12 // encoding: [0x6c,0xe0,0x1c,0xd5] -// CHECK: msr cntkctl_el1, x12 // encoding: [0x0c,0xe1,0x18,0xd5] -// CHECK: msr cnthctl_el2, x12 // encoding: [0x0c,0xe1,0x1c,0xd5] -// CHECK: msr cntp_tval_el0, x12 // encoding: [0x0c,0xe2,0x1b,0xd5] -// CHECK: msr cnthp_tval_el2, x12 // encoding: [0x0c,0xe2,0x1c,0xd5] -// CHECK: msr cntps_tval_el1, x12 // encoding: [0x0c,0xe2,0x1f,0xd5] -// CHECK: msr cntp_ctl_el0, x12 // encoding: [0x2c,0xe2,0x1b,0xd5] -// CHECK: msr cnthp_ctl_el2, x12 // encoding: [0x2c,0xe2,0x1c,0xd5] -// CHECK: msr cntps_ctl_el1, x12 // encoding: [0x2c,0xe2,0x1f,0xd5] -// CHECK: msr cntp_cval_el0, x12 // encoding: [0x4c,0xe2,0x1b,0xd5] -// CHECK: msr cnthp_cval_el2, x12 // encoding: [0x4c,0xe2,0x1c,0xd5] -// CHECK: msr cntps_cval_el1, x12 // encoding: [0x4c,0xe2,0x1f,0xd5] -// CHECK: msr cntv_tval_el0, x12 // encoding: [0x0c,0xe3,0x1b,0xd5] -// CHECK: msr cntv_ctl_el0, x12 // encoding: [0x2c,0xe3,0x1b,0xd5] -// CHECK: msr cntv_cval_el0, x12 // encoding: [0x4c,0xe3,0x1b,0xd5] -// CHECK: msr pmevcntr0_el0, x12 // encoding: [0x0c,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr1_el0, x12 // encoding: [0x2c,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr2_el0, x12 // encoding: [0x4c,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr3_el0, x12 // encoding: [0x6c,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr4_el0, x12 // encoding: [0x8c,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr5_el0, x12 // encoding: [0xac,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr6_el0, x12 // encoding: [0xcc,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr7_el0, x12 // encoding: [0xec,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr8_el0, x12 // encoding: [0x0c,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr9_el0, x12 // encoding: [0x2c,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr10_el0, x12 // encoding: [0x4c,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr11_el0, x12 // encoding: [0x6c,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr12_el0, x12 // encoding: [0x8c,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr13_el0, x12 // encoding: [0xac,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr14_el0, x12 // encoding: [0xcc,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr15_el0, x12 // encoding: [0xec,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr16_el0, x12 // encoding: [0x0c,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr17_el0, x12 // encoding: [0x2c,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr18_el0, x12 // encoding: [0x4c,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr19_el0, x12 // encoding: [0x6c,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr20_el0, x12 // encoding: [0x8c,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr21_el0, x12 // encoding: [0xac,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr22_el0, x12 // encoding: [0xcc,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr23_el0, x12 // encoding: [0xec,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr24_el0, x12 // encoding: [0x0c,0xeb,0x1b,0xd5] -// CHECK: msr pmevcntr25_el0, x12 // encoding: [0x2c,0xeb,0x1b,0xd5] -// CHECK: msr pmevcntr26_el0, x12 // encoding: [0x4c,0xeb,0x1b,0xd5] -// CHECK: msr pmevcntr27_el0, x12 // encoding: [0x6c,0xeb,0x1b,0xd5] -// CHECK: msr pmevcntr28_el0, x12 // encoding: [0x8c,0xeb,0x1b,0xd5] -// CHECK: msr pmevcntr29_el0, x12 // encoding: [0xac,0xeb,0x1b,0xd5] -// CHECK: msr pmevcntr30_el0, x12 // encoding: [0xcc,0xeb,0x1b,0xd5] -// CHECK: msr pmccfiltr_el0, x12 // encoding: [0xec,0xef,0x1b,0xd5] -// CHECK: msr pmevtyper0_el0, x12 // encoding: [0x0c,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper1_el0, x12 // encoding: [0x2c,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper2_el0, x12 // encoding: [0x4c,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper3_el0, x12 // encoding: [0x6c,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper4_el0, x12 // encoding: [0x8c,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper5_el0, x12 // encoding: [0xac,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper6_el0, x12 // encoding: [0xcc,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper7_el0, x12 // encoding: [0xec,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper8_el0, x12 // encoding: [0x0c,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper9_el0, x12 // encoding: [0x2c,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper10_el0, x12 // encoding: [0x4c,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper11_el0, x12 // encoding: [0x6c,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper12_el0, x12 // encoding: [0x8c,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper13_el0, x12 // encoding: [0xac,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper14_el0, x12 // encoding: [0xcc,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper15_el0, x12 // encoding: [0xec,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper16_el0, x12 // encoding: [0x0c,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper17_el0, x12 // encoding: [0x2c,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper18_el0, x12 // encoding: [0x4c,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper19_el0, x12 // encoding: [0x6c,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper20_el0, x12 // encoding: [0x8c,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper21_el0, x12 // encoding: [0xac,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper22_el0, x12 // encoding: [0xcc,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper23_el0, x12 // encoding: [0xec,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper24_el0, x12 // encoding: [0x0c,0xef,0x1b,0xd5] -// CHECK: msr pmevtyper25_el0, x12 // encoding: [0x2c,0xef,0x1b,0xd5] -// CHECK: msr pmevtyper26_el0, x12 // encoding: [0x4c,0xef,0x1b,0xd5] -// CHECK: msr pmevtyper27_el0, x12 // encoding: [0x6c,0xef,0x1b,0xd5] -// CHECK: msr pmevtyper28_el0, x12 // encoding: [0x8c,0xef,0x1b,0xd5] -// CHECK: msr pmevtyper29_el0, x12 // encoding: [0xac,0xef,0x1b,0xd5] -// CHECK: msr pmevtyper30_el0, x12 // encoding: [0xcc,0xef,0x1b,0xd5] +// CHECK: msr {{teecr32_el1|TEECR32_EL1}}, x12 // encoding: [0x0c,0x00,0x12,0xd5] +// CHECK: msr {{osdtrrx_el1|OSDTRRX_EL1}}, x12 // encoding: [0x4c,0x00,0x10,0xd5] +// CHECK: msr {{mdccint_el1|MDCCINT_EL1}}, x12 // encoding: [0x0c,0x02,0x10,0xd5] +// CHECK: msr {{mdscr_el1|MDSCR_EL1}}, x12 // encoding: [0x4c,0x02,0x10,0xd5] +// CHECK: msr {{osdtrtx_el1|OSDTRTX_EL1}}, x12 // encoding: [0x4c,0x03,0x10,0xd5] +// CHECK: msr {{dbgdtr_el0|DBGDTR_EL0}}, x12 // encoding: [0x0c,0x04,0x13,0xd5] +// CHECK: msr {{dbgdtrtx_el0|DBGDTRTX_EL0}}, x12 // encoding: [0x0c,0x05,0x13,0xd5] +// CHECK: msr {{oseccr_el1|OSECCR_EL1}}, x12 // encoding: [0x4c,0x06,0x10,0xd5] +// CHECK: msr {{dbgvcr32_el2|DBGVCR32_EL2}}, x12 // encoding: [0x0c,0x07,0x14,0xd5] +// CHECK: msr {{dbgbvr0_el1|DBGBVR0_EL1}}, x12 // encoding: [0x8c,0x00,0x10,0xd5] +// CHECK: msr {{dbgbvr1_el1|DBGBVR1_EL1}}, x12 // encoding: [0x8c,0x01,0x10,0xd5] +// CHECK: msr {{dbgbvr2_el1|DBGBVR2_EL1}}, x12 // encoding: [0x8c,0x02,0x10,0xd5] +// CHECK: msr {{dbgbvr3_el1|DBGBVR3_EL1}}, x12 // encoding: [0x8c,0x03,0x10,0xd5] +// CHECK: msr {{dbgbvr4_el1|DBGBVR4_EL1}}, x12 // encoding: [0x8c,0x04,0x10,0xd5] +// CHECK: msr {{dbgbvr5_el1|DBGBVR5_EL1}}, x12 // encoding: [0x8c,0x05,0x10,0xd5] +// CHECK: msr {{dbgbvr6_el1|DBGBVR6_EL1}}, x12 // encoding: [0x8c,0x06,0x10,0xd5] +// CHECK: msr {{dbgbvr7_el1|DBGBVR7_EL1}}, x12 // encoding: [0x8c,0x07,0x10,0xd5] +// CHECK: msr {{dbgbvr8_el1|DBGBVR8_EL1}}, x12 // encoding: [0x8c,0x08,0x10,0xd5] +// CHECK: msr {{dbgbvr9_el1|DBGBVR9_EL1}}, x12 // encoding: [0x8c,0x09,0x10,0xd5] +// CHECK: msr {{dbgbvr10_el1|DBGBVR10_EL1}}, x12 // encoding: [0x8c,0x0a,0x10,0xd5] +// CHECK: msr {{dbgbvr11_el1|DBGBVR11_EL1}}, x12 // encoding: [0x8c,0x0b,0x10,0xd5] +// CHECK: msr {{dbgbvr12_el1|DBGBVR12_EL1}}, x12 // encoding: [0x8c,0x0c,0x10,0xd5] +// CHECK: msr {{dbgbvr13_el1|DBGBVR13_EL1}}, x12 // encoding: [0x8c,0x0d,0x10,0xd5] +// CHECK: msr {{dbgbvr14_el1|DBGBVR14_EL1}}, x12 // encoding: [0x8c,0x0e,0x10,0xd5] +// CHECK: msr {{dbgbvr15_el1|DBGBVR15_EL1}}, x12 // encoding: [0x8c,0x0f,0x10,0xd5] +// CHECK: msr {{dbgbcr0_el1|DBGBCR0_EL1}}, x12 // encoding: [0xac,0x00,0x10,0xd5] +// CHECK: msr {{dbgbcr1_el1|DBGBCR1_EL1}}, x12 // encoding: [0xac,0x01,0x10,0xd5] +// CHECK: msr {{dbgbcr2_el1|DBGBCR2_EL1}}, x12 // encoding: [0xac,0x02,0x10,0xd5] +// CHECK: msr {{dbgbcr3_el1|DBGBCR3_EL1}}, x12 // encoding: [0xac,0x03,0x10,0xd5] +// CHECK: msr {{dbgbcr4_el1|DBGBCR4_EL1}}, x12 // encoding: [0xac,0x04,0x10,0xd5] +// CHECK: msr {{dbgbcr5_el1|DBGBCR5_EL1}}, x12 // encoding: [0xac,0x05,0x10,0xd5] +// CHECK: msr {{dbgbcr6_el1|DBGBCR6_EL1}}, x12 // encoding: [0xac,0x06,0x10,0xd5] +// CHECK: msr {{dbgbcr7_el1|DBGBCR7_EL1}}, x12 // encoding: [0xac,0x07,0x10,0xd5] +// CHECK: msr {{dbgbcr8_el1|DBGBCR8_EL1}}, x12 // encoding: [0xac,0x08,0x10,0xd5] +// CHECK: msr {{dbgbcr9_el1|DBGBCR9_EL1}}, x12 // encoding: [0xac,0x09,0x10,0xd5] +// CHECK: msr {{dbgbcr10_el1|DBGBCR10_EL1}}, x12 // encoding: [0xac,0x0a,0x10,0xd5] +// CHECK: msr {{dbgbcr11_el1|DBGBCR11_EL1}}, x12 // encoding: [0xac,0x0b,0x10,0xd5] +// CHECK: msr {{dbgbcr12_el1|DBGBCR12_EL1}}, x12 // encoding: [0xac,0x0c,0x10,0xd5] +// CHECK: msr {{dbgbcr13_el1|DBGBCR13_EL1}}, x12 // encoding: [0xac,0x0d,0x10,0xd5] +// CHECK: msr {{dbgbcr14_el1|DBGBCR14_EL1}}, x12 // encoding: [0xac,0x0e,0x10,0xd5] +// CHECK: msr {{dbgbcr15_el1|DBGBCR15_EL1}}, x12 // encoding: [0xac,0x0f,0x10,0xd5] +// CHECK: msr {{dbgwvr0_el1|DBGWVR0_EL1}}, x12 // encoding: [0xcc,0x00,0x10,0xd5] +// CHECK: msr {{dbgwvr1_el1|DBGWVR1_EL1}}, x12 // encoding: [0xcc,0x01,0x10,0xd5] +// CHECK: msr {{dbgwvr2_el1|DBGWVR2_EL1}}, x12 // encoding: [0xcc,0x02,0x10,0xd5] +// CHECK: msr {{dbgwvr3_el1|DBGWVR3_EL1}}, x12 // encoding: [0xcc,0x03,0x10,0xd5] +// CHECK: msr {{dbgwvr4_el1|DBGWVR4_EL1}}, x12 // encoding: [0xcc,0x04,0x10,0xd5] +// CHECK: msr {{dbgwvr5_el1|DBGWVR5_EL1}}, x12 // encoding: [0xcc,0x05,0x10,0xd5] +// CHECK: msr {{dbgwvr6_el1|DBGWVR6_EL1}}, x12 // encoding: [0xcc,0x06,0x10,0xd5] +// CHECK: msr {{dbgwvr7_el1|DBGWVR7_EL1}}, x12 // encoding: [0xcc,0x07,0x10,0xd5] +// CHECK: msr {{dbgwvr8_el1|DBGWVR8_EL1}}, x12 // encoding: [0xcc,0x08,0x10,0xd5] +// CHECK: msr {{dbgwvr9_el1|DBGWVR9_EL1}}, x12 // encoding: [0xcc,0x09,0x10,0xd5] +// CHECK: msr {{dbgwvr10_el1|DBGWVR10_EL1}}, x12 // encoding: [0xcc,0x0a,0x10,0xd5] +// CHECK: msr {{dbgwvr11_el1|DBGWVR11_EL1}}, x12 // encoding: [0xcc,0x0b,0x10,0xd5] +// CHECK: msr {{dbgwvr12_el1|DBGWVR12_EL1}}, x12 // encoding: [0xcc,0x0c,0x10,0xd5] +// CHECK: msr {{dbgwvr13_el1|DBGWVR13_EL1}}, x12 // encoding: [0xcc,0x0d,0x10,0xd5] +// CHECK: msr {{dbgwvr14_el1|DBGWVR14_EL1}}, x12 // encoding: [0xcc,0x0e,0x10,0xd5] +// CHECK: msr {{dbgwvr15_el1|DBGWVR15_EL1}}, x12 // encoding: [0xcc,0x0f,0x10,0xd5] +// CHECK: msr {{dbgwcr0_el1|DBGWCR0_EL1}}, x12 // encoding: [0xec,0x00,0x10,0xd5] +// CHECK: msr {{dbgwcr1_el1|DBGWCR1_EL1}}, x12 // encoding: [0xec,0x01,0x10,0xd5] +// CHECK: msr {{dbgwcr2_el1|DBGWCR2_EL1}}, x12 // encoding: [0xec,0x02,0x10,0xd5] +// CHECK: msr {{dbgwcr3_el1|DBGWCR3_EL1}}, x12 // encoding: [0xec,0x03,0x10,0xd5] +// CHECK: msr {{dbgwcr4_el1|DBGWCR4_EL1}}, x12 // encoding: [0xec,0x04,0x10,0xd5] +// CHECK: msr {{dbgwcr5_el1|DBGWCR5_EL1}}, x12 // encoding: [0xec,0x05,0x10,0xd5] +// CHECK: msr {{dbgwcr6_el1|DBGWCR6_EL1}}, x12 // encoding: [0xec,0x06,0x10,0xd5] +// CHECK: msr {{dbgwcr7_el1|DBGWCR7_EL1}}, x12 // encoding: [0xec,0x07,0x10,0xd5] +// CHECK: msr {{dbgwcr8_el1|DBGWCR8_EL1}}, x12 // encoding: [0xec,0x08,0x10,0xd5] +// CHECK: msr {{dbgwcr9_el1|DBGWCR9_EL1}}, x12 // encoding: [0xec,0x09,0x10,0xd5] +// CHECK: msr {{dbgwcr10_el1|DBGWCR10_EL1}}, x12 // encoding: [0xec,0x0a,0x10,0xd5] +// CHECK: msr {{dbgwcr11_el1|DBGWCR11_EL1}}, x12 // encoding: [0xec,0x0b,0x10,0xd5] +// CHECK: msr {{dbgwcr12_el1|DBGWCR12_EL1}}, x12 // encoding: [0xec,0x0c,0x10,0xd5] +// CHECK: msr {{dbgwcr13_el1|DBGWCR13_EL1}}, x12 // encoding: [0xec,0x0d,0x10,0xd5] +// CHECK: msr {{dbgwcr14_el1|DBGWCR14_EL1}}, x12 // encoding: [0xec,0x0e,0x10,0xd5] +// CHECK: msr {{dbgwcr15_el1|DBGWCR15_EL1}}, x12 // encoding: [0xec,0x0f,0x10,0xd5] +// CHECK: msr {{teehbr32_el1|TEEHBR32_EL1}}, x12 // encoding: [0x0c,0x10,0x12,0xd5] +// CHECK: msr {{oslar_el1|OSLAR_EL1}}, x12 // encoding: [0x8c,0x10,0x10,0xd5] +// CHECK: msr {{osdlr_el1|OSDLR_EL1}}, x12 // encoding: [0x8c,0x13,0x10,0xd5] +// CHECK: msr {{dbgprcr_el1|DBGPRCR_EL1}}, x12 // encoding: [0x8c,0x14,0x10,0xd5] +// CHECK: msr {{dbgclaimset_el1|DBGCLAIMSET_EL1}}, x12 // encoding: [0xcc,0x78,0x10,0xd5] +// CHECK: msr {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}, x12 // encoding: [0xcc,0x79,0x10,0xd5] +// CHECK: msr {{csselr_el1|CSSELR_EL1}}, x12 // encoding: [0x0c,0x00,0x1a,0xd5] +// CHECK: msr {{vpidr_el2|VPIDR_EL2}}, x12 // encoding: [0x0c,0x00,0x1c,0xd5] +// CHECK: msr {{vmpidr_el2|VMPIDR_EL2}}, x12 // encoding: [0xac,0x00,0x1c,0xd5] +// CHECK: msr {{sctlr_el1|SCTLR_EL1}}, x12 // encoding: [0x0c,0x10,0x18,0xd5] +// CHECK: msr {{sctlr_el2|SCTLR_EL2}}, x12 // encoding: [0x0c,0x10,0x1c,0xd5] +// CHECK: msr {{sctlr_el3|SCTLR_EL3}}, x12 // encoding: [0x0c,0x10,0x1e,0xd5] +// CHECK: msr {{actlr_el1|ACTLR_EL1}}, x12 // encoding: [0x2c,0x10,0x18,0xd5] +// CHECK: msr {{actlr_el2|ACTLR_EL2}}, x12 // encoding: [0x2c,0x10,0x1c,0xd5] +// CHECK: msr {{actlr_el3|ACTLR_EL3}}, x12 // encoding: [0x2c,0x10,0x1e,0xd5] +// CHECK: msr {{cpacr_el1|CPACR_EL1}}, x12 // encoding: [0x4c,0x10,0x18,0xd5] +// CHECK: msr {{hcr_el2|HCR_EL2}}, x12 // encoding: [0x0c,0x11,0x1c,0xd5] +// CHECK: msr {{scr_el3|SCR_EL3}}, x12 // encoding: [0x0c,0x11,0x1e,0xd5] +// CHECK: msr {{mdcr_el2|MDCR_EL2}}, x12 // encoding: [0x2c,0x11,0x1c,0xd5] +// CHECK: msr {{sder32_el3|SDER32_EL3}}, x12 // encoding: [0x2c,0x11,0x1e,0xd5] +// CHECK: msr {{cptr_el2|CPTR_EL2}}, x12 // encoding: [0x4c,0x11,0x1c,0xd5] +// CHECK: msr {{cptr_el3|CPTR_EL3}}, x12 // encoding: [0x4c,0x11,0x1e,0xd5] +// CHECK: msr {{hstr_el2|HSTR_EL2}}, x12 // encoding: [0x6c,0x11,0x1c,0xd5] +// CHECK: msr {{hacr_el2|HACR_EL2}}, x12 // encoding: [0xec,0x11,0x1c,0xd5] +// CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12 // encoding: [0x2c,0x13,0x1e,0xd5] +// CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12 // encoding: [0x0c,0x20,0x18,0xd5] +// CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12 // encoding: [0x0c,0x20,0x1c,0xd5] +// CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12 // encoding: [0x0c,0x20,0x1e,0xd5] +// CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12 // encoding: [0x2c,0x20,0x18,0xd5] +// CHECK: msr {{tcr_el1|TCR_EL1}}, x12 // encoding: [0x4c,0x20,0x18,0xd5] +// CHECK: msr {{tcr_el2|TCR_EL2}}, x12 // encoding: [0x4c,0x20,0x1c,0xd5] +// CHECK: msr {{tcr_el3|TCR_EL3}}, x12 // encoding: [0x4c,0x20,0x1e,0xd5] +// CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12 // encoding: [0x0c,0x21,0x1c,0xd5] +// CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12 // encoding: [0x4c,0x21,0x1c,0xd5] +// CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12 // encoding: [0x0c,0x30,0x1c,0xd5] +// CHECK: msr {{spsr_el1|SPSR_EL1}}, x12 // encoding: [0x0c,0x40,0x18,0xd5] +// CHECK: msr {{spsr_el2|SPSR_EL2}}, x12 // encoding: [0x0c,0x40,0x1c,0xd5] +// CHECK: msr {{spsr_el3|SPSR_EL3}}, x12 // encoding: [0x0c,0x40,0x1e,0xd5] +// CHECK: msr {{elr_el1|ELR_EL1}}, x12 // encoding: [0x2c,0x40,0x18,0xd5] +// CHECK: msr {{elr_el2|ELR_EL2}}, x12 // encoding: [0x2c,0x40,0x1c,0xd5] +// CHECK: msr {{elr_el3|ELR_EL3}}, x12 // encoding: [0x2c,0x40,0x1e,0xd5] +// CHECK: msr {{sp_el0|SP_EL0}}, x12 // encoding: [0x0c,0x41,0x18,0xd5] +// CHECK: msr {{sp_el1|SP_EL1}}, x12 // encoding: [0x0c,0x41,0x1c,0xd5] +// CHECK: msr {{sp_el2|SP_EL2}}, x12 // encoding: [0x0c,0x41,0x1e,0xd5] +// CHECK: msr {{spsel|SPSEL}}, x12 // encoding: [0x0c,0x42,0x18,0xd5] +// CHECK: msr {{nzcv|NZCV}}, x12 // encoding: [0x0c,0x42,0x1b,0xd5] +// CHECK: msr {{daif|DAIF}}, x12 // encoding: [0x2c,0x42,0x1b,0xd5] +// CHECK: msr {{currentel|CURRENTEL}}, x12 // encoding: [0x4c,0x42,0x18,0xd5] +// CHECK: msr {{spsr_irq|SPSR_IRQ}}, x12 // encoding: [0x0c,0x43,0x1c,0xd5] +// CHECK: msr {{spsr_abt|SPSR_ABT}}, x12 // encoding: [0x2c,0x43,0x1c,0xd5] +// CHECK: msr {{spsr_und|SPSR_UND}}, x12 // encoding: [0x4c,0x43,0x1c,0xd5] +// CHECK: msr {{spsr_fiq|SPSR_FIQ}}, x12 // encoding: [0x6c,0x43,0x1c,0xd5] +// CHECK: msr {{fpcr|FPCR}}, x12 // encoding: [0x0c,0x44,0x1b,0xd5] +// CHECK: msr {{fpsr|FPSR}}, x12 // encoding: [0x2c,0x44,0x1b,0xd5] +// CHECK: msr {{dspsr_el0|DSPSR_EL0}}, x12 // encoding: [0x0c,0x45,0x1b,0xd5] +// CHECK: msr {{dlr_el0|DLR_EL0}}, x12 // encoding: [0x2c,0x45,0x1b,0xd5] +// CHECK: msr {{ifsr32_el2|IFSR32_EL2}}, x12 // encoding: [0x2c,0x50,0x1c,0xd5] +// CHECK: msr {{afsr0_el1|AFSR0_EL1}}, x12 // encoding: [0x0c,0x51,0x18,0xd5] +// CHECK: msr {{afsr0_el2|AFSR0_EL2}}, x12 // encoding: [0x0c,0x51,0x1c,0xd5] +// CHECK: msr {{afsr0_el3|AFSR0_EL3}}, x12 // encoding: [0x0c,0x51,0x1e,0xd5] +// CHECK: msr {{afsr1_el1|AFSR1_EL1}}, x12 // encoding: [0x2c,0x51,0x18,0xd5] +// CHECK: msr {{afsr1_el2|AFSR1_EL2}}, x12 // encoding: [0x2c,0x51,0x1c,0xd5] +// CHECK: msr {{afsr1_el3|AFSR1_EL3}}, x12 // encoding: [0x2c,0x51,0x1e,0xd5] +// CHECK: msr {{esr_el1|ESR_EL1}}, x12 // encoding: [0x0c,0x52,0x18,0xd5] +// CHECK: msr {{esr_el2|ESR_EL2}}, x12 // encoding: [0x0c,0x52,0x1c,0xd5] +// CHECK: msr {{esr_el3|ESR_EL3}}, x12 // encoding: [0x0c,0x52,0x1e,0xd5] +// CHECK: msr {{fpexc32_el2|FPEXC32_EL2}}, x12 // encoding: [0x0c,0x53,0x1c,0xd5] +// CHECK: msr {{far_el1|FAR_EL1}}, x12 // encoding: [0x0c,0x60,0x18,0xd5] +// CHECK: msr {{far_el2|FAR_EL2}}, x12 // encoding: [0x0c,0x60,0x1c,0xd5] +// CHECK: msr {{far_el3|FAR_EL3}}, x12 // encoding: [0x0c,0x60,0x1e,0xd5] +// CHECK: msr {{hpfar_el2|HPFAR_EL2}}, x12 // encoding: [0x8c,0x60,0x1c,0xd5] +// CHECK: msr {{par_el1|PAR_EL1}}, x12 // encoding: [0x0c,0x74,0x18,0xd5] +// CHECK: msr {{pmcr_el0|PMCR_EL0}}, x12 // encoding: [0x0c,0x9c,0x1b,0xd5] +// CHECK: msr {{pmcntenset_el0|PMCNTENSET_EL0}}, x12 // encoding: [0x2c,0x9c,0x1b,0xd5] +// CHECK: msr {{pmcntenclr_el0|PMCNTENCLR_EL0}}, x12 // encoding: [0x4c,0x9c,0x1b,0xd5] +// CHECK: msr {{pmovsclr_el0|PMOVSCLR_EL0}}, x12 // encoding: [0x6c,0x9c,0x1b,0xd5] +// CHECK: msr {{pmselr_el0|PMSELR_EL0}}, x12 // encoding: [0xac,0x9c,0x1b,0xd5] +// CHECK: msr {{pmccntr_el0|PMCCNTR_EL0}}, x12 // encoding: [0x0c,0x9d,0x1b,0xd5] +// CHECK: msr {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12 // encoding: [0x2c,0x9d,0x1b,0xd5] +// CHECK: msr {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12 // encoding: [0x4c,0x9d,0x1b,0xd5] +// CHECK: msr {{pmuserenr_el0|PMUSERENR_EL0}}, x12 // encoding: [0x0c,0x9e,0x1b,0xd5] +// CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12 // encoding: [0x2c,0x9e,0x18,0xd5] +// CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12 // encoding: [0x4c,0x9e,0x18,0xd5] +// CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12 // encoding: [0x6c,0x9e,0x1b,0xd5] +// CHECK: msr {{mair_el1|MAIR_EL1}}, x12 // encoding: [0x0c,0xa2,0x18,0xd5] +// CHECK: msr {{mair_el2|MAIR_EL2}}, x12 // encoding: [0x0c,0xa2,0x1c,0xd5] +// CHECK: msr {{mair_el3|MAIR_EL3}}, x12 // encoding: [0x0c,0xa2,0x1e,0xd5] +// CHECK: msr {{amair_el1|AMAIR_EL1}}, x12 // encoding: [0x0c,0xa3,0x18,0xd5] +// CHECK: msr {{amair_el2|AMAIR_EL2}}, x12 // encoding: [0x0c,0xa3,0x1c,0xd5] +// CHECK: msr {{amair_el3|AMAIR_EL3}}, x12 // encoding: [0x0c,0xa3,0x1e,0xd5] +// CHECK: msr {{vbar_el1|VBAR_EL1}}, x12 // encoding: [0x0c,0xc0,0x18,0xd5] +// CHECK: msr {{vbar_el2|VBAR_EL2}}, x12 // encoding: [0x0c,0xc0,0x1c,0xd5] +// CHECK: msr {{vbar_el3|VBAR_EL3}}, x12 // encoding: [0x0c,0xc0,0x1e,0xd5] +// CHECK: msr {{rmr_el1|RMR_EL1}}, x12 // encoding: [0x4c,0xc0,0x18,0xd5] +// CHECK: msr {{rmr_el2|RMR_EL2}}, x12 // encoding: [0x4c,0xc0,0x1c,0xd5] +// CHECK: msr {{rmr_el3|RMR_EL3}}, x12 // encoding: [0x4c,0xc0,0x1e,0xd5] +// CHECK: msr {{contextidr_el1|CONTEXTIDR_EL1}}, x12 // encoding: [0x2c,0xd0,0x18,0xd5] +// CHECK: msr {{tpidr_el0|TPIDR_EL0}}, x12 // encoding: [0x4c,0xd0,0x1b,0xd5] +// CHECK: msr {{tpidr_el2|TPIDR_EL2}}, x12 // encoding: [0x4c,0xd0,0x1c,0xd5] +// CHECK: msr {{tpidr_el3|TPIDR_EL3}}, x12 // encoding: [0x4c,0xd0,0x1e,0xd5] +// CHECK: msr {{tpidrro_el0|TPIDRRO_EL0}}, x12 // encoding: [0x6c,0xd0,0x1b,0xd5] +// CHECK: msr {{tpidr_el1|TPIDR_EL1}}, x12 // encoding: [0x8c,0xd0,0x18,0xd5] +// CHECK: msr {{cntfrq_el0|CNTFRQ_EL0}}, x12 // encoding: [0x0c,0xe0,0x1b,0xd5] +// CHECK: msr {{cntvoff_el2|CNTVOFF_EL2}}, x12 // encoding: [0x6c,0xe0,0x1c,0xd5] +// CHECK: msr {{cntkctl_el1|CNTKCTL_EL1}}, x12 // encoding: [0x0c,0xe1,0x18,0xd5] +// CHECK: msr {{cnthctl_el2|CNTHCTL_EL2}}, x12 // encoding: [0x0c,0xe1,0x1c,0xd5] +// CHECK: msr {{cntp_tval_el0|CNTP_TVAL_EL0}}, x12 // encoding: [0x0c,0xe2,0x1b,0xd5] +// CHECK: msr {{cnthp_tval_el2|CNTHP_TVAL_EL2}}, x12 // encoding: [0x0c,0xe2,0x1c,0xd5] +// CHECK: msr {{cntps_tval_el1|CNTPS_TVAL_EL1}}, x12 // encoding: [0x0c,0xe2,0x1f,0xd5] +// CHECK: msr {{cntp_ctl_el0|CNTP_CTL_EL0}}, x12 // encoding: [0x2c,0xe2,0x1b,0xd5] +// CHECK: msr {{cnthp_ctl_el2|CNTHP_CTL_EL2}}, x12 // encoding: [0x2c,0xe2,0x1c,0xd5] +// CHECK: msr {{cntps_ctl_el1|CNTPS_CTL_EL1}}, x12 // encoding: [0x2c,0xe2,0x1f,0xd5] +// CHECK: msr {{cntp_cval_el0|CNTP_CVAL_EL0}}, x12 // encoding: [0x4c,0xe2,0x1b,0xd5] +// CHECK: msr {{cnthp_cval_el2|CNTHP_CVAL_EL2}}, x12 // encoding: [0x4c,0xe2,0x1c,0xd5] +// CHECK: msr {{cntps_cval_el1|CNTPS_CVAL_EL1}}, x12 // encoding: [0x4c,0xe2,0x1f,0xd5] +// CHECK: msr {{cntv_tval_el0|CNTV_TVAL_EL0}}, x12 // encoding: [0x0c,0xe3,0x1b,0xd5] +// CHECK: msr {{cntv_ctl_el0|CNTV_CTL_EL0}}, x12 // encoding: [0x2c,0xe3,0x1b,0xd5] +// CHECK: msr {{cntv_cval_el0|CNTV_CVAL_EL0}}, x12 // encoding: [0x4c,0xe3,0x1b,0xd5] +// CHECK: msr {{pmevcntr0_el0|PMEVCNTR0_EL0}}, x12 // encoding: [0x0c,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr1_el0|PMEVCNTR1_EL0}}, x12 // encoding: [0x2c,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr2_el0|PMEVCNTR2_EL0}}, x12 // encoding: [0x4c,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr3_el0|PMEVCNTR3_EL0}}, x12 // encoding: [0x6c,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr4_el0|PMEVCNTR4_EL0}}, x12 // encoding: [0x8c,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr5_el0|PMEVCNTR5_EL0}}, x12 // encoding: [0xac,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr6_el0|PMEVCNTR6_EL0}}, x12 // encoding: [0xcc,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr7_el0|PMEVCNTR7_EL0}}, x12 // encoding: [0xec,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr8_el0|PMEVCNTR8_EL0}}, x12 // encoding: [0x0c,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr9_el0|PMEVCNTR9_EL0}}, x12 // encoding: [0x2c,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr10_el0|PMEVCNTR10_EL0}}, x12 // encoding: [0x4c,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr11_el0|PMEVCNTR11_EL0}}, x12 // encoding: [0x6c,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr12_el0|PMEVCNTR12_EL0}}, x12 // encoding: [0x8c,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr13_el0|PMEVCNTR13_EL0}}, x12 // encoding: [0xac,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr14_el0|PMEVCNTR14_EL0}}, x12 // encoding: [0xcc,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr15_el0|PMEVCNTR15_EL0}}, x12 // encoding: [0xec,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr16_el0|PMEVCNTR16_EL0}}, x12 // encoding: [0x0c,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr17_el0|PMEVCNTR17_EL0}}, x12 // encoding: [0x2c,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr18_el0|PMEVCNTR18_EL0}}, x12 // encoding: [0x4c,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr19_el0|PMEVCNTR19_EL0}}, x12 // encoding: [0x6c,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr20_el0|PMEVCNTR20_EL0}}, x12 // encoding: [0x8c,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr21_el0|PMEVCNTR21_EL0}}, x12 // encoding: [0xac,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr22_el0|PMEVCNTR22_EL0}}, x12 // encoding: [0xcc,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr23_el0|PMEVCNTR23_EL0}}, x12 // encoding: [0xec,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr24_el0|PMEVCNTR24_EL0}}, x12 // encoding: [0x0c,0xeb,0x1b,0xd5] +// CHECK: msr {{pmevcntr25_el0|PMEVCNTR25_EL0}}, x12 // encoding: [0x2c,0xeb,0x1b,0xd5] +// CHECK: msr {{pmevcntr26_el0|PMEVCNTR26_EL0}}, x12 // encoding: [0x4c,0xeb,0x1b,0xd5] +// CHECK: msr {{pmevcntr27_el0|PMEVCNTR27_EL0}}, x12 // encoding: [0x6c,0xeb,0x1b,0xd5] +// CHECK: msr {{pmevcntr28_el0|PMEVCNTR28_EL0}}, x12 // encoding: [0x8c,0xeb,0x1b,0xd5] +// CHECK: msr {{pmevcntr29_el0|PMEVCNTR29_EL0}}, x12 // encoding: [0xac,0xeb,0x1b,0xd5] +// CHECK: msr {{pmevcntr30_el0|PMEVCNTR30_EL0}}, x12 // encoding: [0xcc,0xeb,0x1b,0xd5] +// CHECK: msr {{pmccfiltr_el0|PMCCFILTR_EL0}}, x12 // encoding: [0xec,0xef,0x1b,0xd5] +// CHECK: msr {{pmevtyper0_el0|PMEVTYPER0_EL0}}, x12 // encoding: [0x0c,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper1_el0|PMEVTYPER1_EL0}}, x12 // encoding: [0x2c,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper2_el0|PMEVTYPER2_EL0}}, x12 // encoding: [0x4c,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper3_el0|PMEVTYPER3_EL0}}, x12 // encoding: [0x6c,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper4_el0|PMEVTYPER4_EL0}}, x12 // encoding: [0x8c,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper5_el0|PMEVTYPER5_EL0}}, x12 // encoding: [0xac,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper6_el0|PMEVTYPER6_EL0}}, x12 // encoding: [0xcc,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper7_el0|PMEVTYPER7_EL0}}, x12 // encoding: [0xec,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper8_el0|PMEVTYPER8_EL0}}, x12 // encoding: [0x0c,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper9_el0|PMEVTYPER9_EL0}}, x12 // encoding: [0x2c,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper10_el0|PMEVTYPER10_EL0}}, x12 // encoding: [0x4c,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper11_el0|PMEVTYPER11_EL0}}, x12 // encoding: [0x6c,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper12_el0|PMEVTYPER12_EL0}}, x12 // encoding: [0x8c,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper13_el0|PMEVTYPER13_EL0}}, x12 // encoding: [0xac,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper14_el0|PMEVTYPER14_EL0}}, x12 // encoding: [0xcc,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper15_el0|PMEVTYPER15_EL0}}, x12 // encoding: [0xec,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper16_el0|PMEVTYPER16_EL0}}, x12 // encoding: [0x0c,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper17_el0|PMEVTYPER17_EL0}}, x12 // encoding: [0x2c,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper18_el0|PMEVTYPER18_EL0}}, x12 // encoding: [0x4c,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper19_el0|PMEVTYPER19_EL0}}, x12 // encoding: [0x6c,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper20_el0|PMEVTYPER20_EL0}}, x12 // encoding: [0x8c,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper21_el0|PMEVTYPER21_EL0}}, x12 // encoding: [0xac,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper22_el0|PMEVTYPER22_EL0}}, x12 // encoding: [0xcc,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper23_el0|PMEVTYPER23_EL0}}, x12 // encoding: [0xec,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper24_el0|PMEVTYPER24_EL0}}, x12 // encoding: [0x0c,0xef,0x1b,0xd5] +// CHECK: msr {{pmevtyper25_el0|PMEVTYPER25_EL0}}, x12 // encoding: [0x2c,0xef,0x1b,0xd5] +// CHECK: msr {{pmevtyper26_el0|PMEVTYPER26_EL0}}, x12 // encoding: [0x4c,0xef,0x1b,0xd5] +// CHECK: msr {{pmevtyper27_el0|PMEVTYPER27_EL0}}, x12 // encoding: [0x6c,0xef,0x1b,0xd5] +// CHECK: msr {{pmevtyper28_el0|PMEVTYPER28_EL0}}, x12 // encoding: [0x8c,0xef,0x1b,0xd5] +// CHECK: msr {{pmevtyper29_el0|PMEVTYPER29_EL0}}, x12 // encoding: [0xac,0xef,0x1b,0xd5] +// CHECK: msr {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12 // encoding: [0xcc,0xef,0x1b,0xd5] mrs x9, TEECR32_EL1 mrs x9, OSDTRRX_EL1 @@ -4497,315 +4464,315 @@ _func: mrs x9, PMEVTYPER28_EL0 mrs x9, PMEVTYPER29_EL0 mrs x9, PMEVTYPER30_EL0 -// CHECK: mrs x9, teecr32_el1 // encoding: [0x09,0x00,0x32,0xd5] -// CHECK: mrs x9, osdtrrx_el1 // encoding: [0x49,0x00,0x30,0xd5] -// CHECK: mrs x9, mdccsr_el0 // encoding: [0x09,0x01,0x33,0xd5] -// CHECK: mrs x9, mdccint_el1 // encoding: [0x09,0x02,0x30,0xd5] -// CHECK: mrs x9, mdscr_el1 // encoding: [0x49,0x02,0x30,0xd5] -// CHECK: mrs x9, osdtrtx_el1 // encoding: [0x49,0x03,0x30,0xd5] -// CHECK: mrs x9, dbgdtr_el0 // encoding: [0x09,0x04,0x33,0xd5] -// CHECK: mrs x9, dbgdtrrx_el0 // encoding: [0x09,0x05,0x33,0xd5] -// CHECK: mrs x9, oseccr_el1 // encoding: [0x49,0x06,0x30,0xd5] -// CHECK: mrs x9, dbgvcr32_el2 // encoding: [0x09,0x07,0x34,0xd5] -// CHECK: mrs x9, dbgbvr0_el1 // encoding: [0x89,0x00,0x30,0xd5] -// CHECK: mrs x9, dbgbvr1_el1 // encoding: [0x89,0x01,0x30,0xd5] -// CHECK: mrs x9, dbgbvr2_el1 // encoding: [0x89,0x02,0x30,0xd5] -// CHECK: mrs x9, dbgbvr3_el1 // encoding: [0x89,0x03,0x30,0xd5] -// CHECK: mrs x9, dbgbvr4_el1 // encoding: [0x89,0x04,0x30,0xd5] -// CHECK: mrs x9, dbgbvr5_el1 // encoding: [0x89,0x05,0x30,0xd5] -// CHECK: mrs x9, dbgbvr6_el1 // encoding: [0x89,0x06,0x30,0xd5] -// CHECK: mrs x9, dbgbvr7_el1 // encoding: [0x89,0x07,0x30,0xd5] -// CHECK: mrs x9, dbgbvr8_el1 // encoding: [0x89,0x08,0x30,0xd5] -// CHECK: mrs x9, dbgbvr9_el1 // encoding: [0x89,0x09,0x30,0xd5] -// CHECK: mrs x9, dbgbvr10_el1 // encoding: [0x89,0x0a,0x30,0xd5] -// CHECK: mrs x9, dbgbvr11_el1 // encoding: [0x89,0x0b,0x30,0xd5] -// CHECK: mrs x9, dbgbvr12_el1 // encoding: [0x89,0x0c,0x30,0xd5] -// CHECK: mrs x9, dbgbvr13_el1 // encoding: [0x89,0x0d,0x30,0xd5] -// CHECK: mrs x9, dbgbvr14_el1 // encoding: [0x89,0x0e,0x30,0xd5] -// CHECK: mrs x9, dbgbvr15_el1 // encoding: [0x89,0x0f,0x30,0xd5] -// CHECK: mrs x9, dbgbcr0_el1 // encoding: [0xa9,0x00,0x30,0xd5] -// CHECK: mrs x9, dbgbcr1_el1 // encoding: [0xa9,0x01,0x30,0xd5] -// CHECK: mrs x9, dbgbcr2_el1 // encoding: [0xa9,0x02,0x30,0xd5] -// CHECK: mrs x9, dbgbcr3_el1 // encoding: [0xa9,0x03,0x30,0xd5] -// CHECK: mrs x9, dbgbcr4_el1 // encoding: [0xa9,0x04,0x30,0xd5] -// CHECK: mrs x9, dbgbcr5_el1 // encoding: [0xa9,0x05,0x30,0xd5] -// CHECK: mrs x9, dbgbcr6_el1 // encoding: [0xa9,0x06,0x30,0xd5] -// CHECK: mrs x9, dbgbcr7_el1 // encoding: [0xa9,0x07,0x30,0xd5] -// CHECK: mrs x9, dbgbcr8_el1 // encoding: [0xa9,0x08,0x30,0xd5] -// CHECK: mrs x9, dbgbcr9_el1 // encoding: [0xa9,0x09,0x30,0xd5] -// CHECK: mrs x9, dbgbcr10_el1 // encoding: [0xa9,0x0a,0x30,0xd5] -// CHECK: mrs x9, dbgbcr11_el1 // encoding: [0xa9,0x0b,0x30,0xd5] -// CHECK: mrs x9, dbgbcr12_el1 // encoding: [0xa9,0x0c,0x30,0xd5] -// CHECK: mrs x9, dbgbcr13_el1 // encoding: [0xa9,0x0d,0x30,0xd5] -// CHECK: mrs x9, dbgbcr14_el1 // encoding: [0xa9,0x0e,0x30,0xd5] -// CHECK: mrs x9, dbgbcr15_el1 // encoding: [0xa9,0x0f,0x30,0xd5] -// CHECK: mrs x9, dbgwvr0_el1 // encoding: [0xc9,0x00,0x30,0xd5] -// CHECK: mrs x9, dbgwvr1_el1 // encoding: [0xc9,0x01,0x30,0xd5] -// CHECK: mrs x9, dbgwvr2_el1 // encoding: [0xc9,0x02,0x30,0xd5] -// CHECK: mrs x9, dbgwvr3_el1 // encoding: [0xc9,0x03,0x30,0xd5] -// CHECK: mrs x9, dbgwvr4_el1 // encoding: [0xc9,0x04,0x30,0xd5] -// CHECK: mrs x9, dbgwvr5_el1 // encoding: [0xc9,0x05,0x30,0xd5] -// CHECK: mrs x9, dbgwvr6_el1 // encoding: [0xc9,0x06,0x30,0xd5] -// CHECK: mrs x9, dbgwvr7_el1 // encoding: [0xc9,0x07,0x30,0xd5] -// CHECK: mrs x9, dbgwvr8_el1 // encoding: [0xc9,0x08,0x30,0xd5] -// CHECK: mrs x9, dbgwvr9_el1 // encoding: [0xc9,0x09,0x30,0xd5] -// CHECK: mrs x9, dbgwvr10_el1 // encoding: [0xc9,0x0a,0x30,0xd5] -// CHECK: mrs x9, dbgwvr11_el1 // encoding: [0xc9,0x0b,0x30,0xd5] -// CHECK: mrs x9, dbgwvr12_el1 // encoding: [0xc9,0x0c,0x30,0xd5] -// CHECK: mrs x9, dbgwvr13_el1 // encoding: [0xc9,0x0d,0x30,0xd5] -// CHECK: mrs x9, dbgwvr14_el1 // encoding: [0xc9,0x0e,0x30,0xd5] -// CHECK: mrs x9, dbgwvr15_el1 // encoding: [0xc9,0x0f,0x30,0xd5] -// CHECK: mrs x9, dbgwcr0_el1 // encoding: [0xe9,0x00,0x30,0xd5] -// CHECK: mrs x9, dbgwcr1_el1 // encoding: [0xe9,0x01,0x30,0xd5] -// CHECK: mrs x9, dbgwcr2_el1 // encoding: [0xe9,0x02,0x30,0xd5] -// CHECK: mrs x9, dbgwcr3_el1 // encoding: [0xe9,0x03,0x30,0xd5] -// CHECK: mrs x9, dbgwcr4_el1 // encoding: [0xe9,0x04,0x30,0xd5] -// CHECK: mrs x9, dbgwcr5_el1 // encoding: [0xe9,0x05,0x30,0xd5] -// CHECK: mrs x9, dbgwcr6_el1 // encoding: [0xe9,0x06,0x30,0xd5] -// CHECK: mrs x9, dbgwcr7_el1 // encoding: [0xe9,0x07,0x30,0xd5] -// CHECK: mrs x9, dbgwcr8_el1 // encoding: [0xe9,0x08,0x30,0xd5] -// CHECK: mrs x9, dbgwcr9_el1 // encoding: [0xe9,0x09,0x30,0xd5] -// CHECK: mrs x9, dbgwcr10_el1 // encoding: [0xe9,0x0a,0x30,0xd5] -// CHECK: mrs x9, dbgwcr11_el1 // encoding: [0xe9,0x0b,0x30,0xd5] -// CHECK: mrs x9, dbgwcr12_el1 // encoding: [0xe9,0x0c,0x30,0xd5] -// CHECK: mrs x9, dbgwcr13_el1 // encoding: [0xe9,0x0d,0x30,0xd5] -// CHECK: mrs x9, dbgwcr14_el1 // encoding: [0xe9,0x0e,0x30,0xd5] -// CHECK: mrs x9, dbgwcr15_el1 // encoding: [0xe9,0x0f,0x30,0xd5] -// CHECK: mrs x9, mdrar_el1 // encoding: [0x09,0x10,0x30,0xd5] -// CHECK: mrs x9, teehbr32_el1 // encoding: [0x09,0x10,0x32,0xd5] -// CHECK: mrs x9, oslsr_el1 // encoding: [0x89,0x11,0x30,0xd5] -// CHECK: mrs x9, osdlr_el1 // encoding: [0x89,0x13,0x30,0xd5] -// CHECK: mrs x9, dbgprcr_el1 // encoding: [0x89,0x14,0x30,0xd5] -// CHECK: mrs x9, dbgclaimset_el1 // encoding: [0xc9,0x78,0x30,0xd5] -// CHECK: mrs x9, dbgclaimclr_el1 // encoding: [0xc9,0x79,0x30,0xd5] -// CHECK: mrs x9, dbgauthstatus_el1 // encoding: [0xc9,0x7e,0x30,0xd5] -// CHECK: mrs x9, midr_el1 // encoding: [0x09,0x00,0x38,0xd5] -// CHECK: mrs x9, ccsidr_el1 // encoding: [0x09,0x00,0x39,0xd5] -// CHECK: mrs x9, csselr_el1 // encoding: [0x09,0x00,0x3a,0xd5] -// CHECK: mrs x9, vpidr_el2 // encoding: [0x09,0x00,0x3c,0xd5] -// CHECK: mrs x9, clidr_el1 // encoding: [0x29,0x00,0x39,0xd5] -// CHECK: mrs x9, ctr_el0 // encoding: [0x29,0x00,0x3b,0xd5] -// CHECK: mrs x9, mpidr_el1 // encoding: [0xa9,0x00,0x38,0xd5] -// CHECK: mrs x9, vmpidr_el2 // encoding: [0xa9,0x00,0x3c,0xd5] -// CHECK: mrs x9, revidr_el1 // encoding: [0xc9,0x00,0x38,0xd5] -// CHECK: mrs x9, aidr_el1 // encoding: [0xe9,0x00,0x39,0xd5] -// CHECK: mrs x9, dczid_el0 // encoding: [0xe9,0x00,0x3b,0xd5] -// CHECK: mrs x9, id_pfr0_el1 // encoding: [0x09,0x01,0x38,0xd5] -// CHECK: mrs x9, id_pfr1_el1 // encoding: [0x29,0x01,0x38,0xd5] -// CHECK: mrs x9, id_dfr0_el1 // encoding: [0x49,0x01,0x38,0xd5] -// CHECK: mrs x9, id_afr0_el1 // encoding: [0x69,0x01,0x38,0xd5] -// CHECK: mrs x9, id_mmfr0_el1 // encoding: [0x89,0x01,0x38,0xd5] -// CHECK: mrs x9, id_mmfr1_el1 // encoding: [0xa9,0x01,0x38,0xd5] -// CHECK: mrs x9, id_mmfr2_el1 // encoding: [0xc9,0x01,0x38,0xd5] -// CHECK: mrs x9, id_mmfr3_el1 // encoding: [0xe9,0x01,0x38,0xd5] -// CHECK: mrs x9, id_isar0_el1 // encoding: [0x09,0x02,0x38,0xd5] -// CHECK: mrs x9, id_isar1_el1 // encoding: [0x29,0x02,0x38,0xd5] -// CHECK: mrs x9, id_isar2_el1 // encoding: [0x49,0x02,0x38,0xd5] -// CHECK: mrs x9, id_isar3_el1 // encoding: [0x69,0x02,0x38,0xd5] -// CHECK: mrs x9, id_isar4_el1 // encoding: [0x89,0x02,0x38,0xd5] -// CHECK: mrs x9, id_isar5_el1 // encoding: [0xa9,0x02,0x38,0xd5] -// CHECK: mrs x9, mvfr0_el1 // encoding: [0x09,0x03,0x38,0xd5] -// CHECK: mrs x9, mvfr1_el1 // encoding: [0x29,0x03,0x38,0xd5] -// CHECK: mrs x9, mvfr2_el1 // encoding: [0x49,0x03,0x38,0xd5] -// CHECK: mrs x9, id_aa64pfr0_el1 // encoding: [0x09,0x04,0x38,0xd5] -// CHECK: mrs x9, id_aa64pfr1_el1 // encoding: [0x29,0x04,0x38,0xd5] -// CHECK: mrs x9, id_aa64dfr0_el1 // encoding: [0x09,0x05,0x38,0xd5] -// CHECK: mrs x9, id_aa64dfr1_el1 // encoding: [0x29,0x05,0x38,0xd5] -// CHECK: mrs x9, id_aa64afr0_el1 // encoding: [0x89,0x05,0x38,0xd5] -// CHECK: mrs x9, id_aa64afr1_el1 // encoding: [0xa9,0x05,0x38,0xd5] -// CHECK: mrs x9, id_aa64isar0_el1 // encoding: [0x09,0x06,0x38,0xd5] -// CHECK: mrs x9, id_aa64isar1_el1 // encoding: [0x29,0x06,0x38,0xd5] -// CHECK: mrs x9, id_aa64mmfr0_el1 // encoding: [0x09,0x07,0x38,0xd5] -// CHECK: mrs x9, id_aa64mmfr1_el1 // encoding: [0x29,0x07,0x38,0xd5] -// CHECK: mrs x9, sctlr_el1 // encoding: [0x09,0x10,0x38,0xd5] -// CHECK: mrs x9, sctlr_el2 // encoding: [0x09,0x10,0x3c,0xd5] -// CHECK: mrs x9, sctlr_el3 // encoding: [0x09,0x10,0x3e,0xd5] -// CHECK: mrs x9, actlr_el1 // encoding: [0x29,0x10,0x38,0xd5] -// CHECK: mrs x9, actlr_el2 // encoding: [0x29,0x10,0x3c,0xd5] -// CHECK: mrs x9, actlr_el3 // encoding: [0x29,0x10,0x3e,0xd5] -// CHECK: mrs x9, cpacr_el1 // encoding: [0x49,0x10,0x38,0xd5] -// CHECK: mrs x9, hcr_el2 // encoding: [0x09,0x11,0x3c,0xd5] -// CHECK: mrs x9, scr_el3 // encoding: [0x09,0x11,0x3e,0xd5] -// CHECK: mrs x9, mdcr_el2 // encoding: [0x29,0x11,0x3c,0xd5] -// CHECK: mrs x9, sder32_el3 // encoding: [0x29,0x11,0x3e,0xd5] -// CHECK: mrs x9, cptr_el2 // encoding: [0x49,0x11,0x3c,0xd5] -// CHECK: mrs x9, cptr_el3 // encoding: [0x49,0x11,0x3e,0xd5] -// CHECK: mrs x9, hstr_el2 // encoding: [0x69,0x11,0x3c,0xd5] -// CHECK: mrs x9, hacr_el2 // encoding: [0xe9,0x11,0x3c,0xd5] -// CHECK: mrs x9, mdcr_el3 // encoding: [0x29,0x13,0x3e,0xd5] -// CHECK: mrs x9, ttbr0_el1 // encoding: [0x09,0x20,0x38,0xd5] -// CHECK: mrs x9, ttbr0_el2 // encoding: [0x09,0x20,0x3c,0xd5] -// CHECK: mrs x9, ttbr0_el3 // encoding: [0x09,0x20,0x3e,0xd5] -// CHECK: mrs x9, ttbr1_el1 // encoding: [0x29,0x20,0x38,0xd5] -// CHECK: mrs x9, tcr_el1 // encoding: [0x49,0x20,0x38,0xd5] -// CHECK: mrs x9, tcr_el2 // encoding: [0x49,0x20,0x3c,0xd5] -// CHECK: mrs x9, tcr_el3 // encoding: [0x49,0x20,0x3e,0xd5] -// CHECK: mrs x9, vttbr_el2 // encoding: [0x09,0x21,0x3c,0xd5] -// CHECK: mrs x9, vtcr_el2 // encoding: [0x49,0x21,0x3c,0xd5] -// CHECK: mrs x9, dacr32_el2 // encoding: [0x09,0x30,0x3c,0xd5] -// CHECK: mrs x9, spsr_el1 // encoding: [0x09,0x40,0x38,0xd5] -// CHECK: mrs x9, spsr_el2 // encoding: [0x09,0x40,0x3c,0xd5] -// CHECK: mrs x9, spsr_el3 // encoding: [0x09,0x40,0x3e,0xd5] -// CHECK: mrs x9, elr_el1 // encoding: [0x29,0x40,0x38,0xd5] -// CHECK: mrs x9, elr_el2 // encoding: [0x29,0x40,0x3c,0xd5] -// CHECK: mrs x9, elr_el3 // encoding: [0x29,0x40,0x3e,0xd5] -// CHECK: mrs x9, sp_el0 // encoding: [0x09,0x41,0x38,0xd5] -// CHECK: mrs x9, sp_el1 // encoding: [0x09,0x41,0x3c,0xd5] -// CHECK: mrs x9, sp_el2 // encoding: [0x09,0x41,0x3e,0xd5] -// CHECK: mrs x9, spsel // encoding: [0x09,0x42,0x38,0xd5] -// CHECK: mrs x9, nzcv // encoding: [0x09,0x42,0x3b,0xd5] -// CHECK: mrs x9, daif // encoding: [0x29,0x42,0x3b,0xd5] -// CHECK: mrs x9, currentel // encoding: [0x49,0x42,0x38,0xd5] -// CHECK: mrs x9, spsr_irq // encoding: [0x09,0x43,0x3c,0xd5] -// CHECK: mrs x9, spsr_abt // encoding: [0x29,0x43,0x3c,0xd5] -// CHECK: mrs x9, spsr_und // encoding: [0x49,0x43,0x3c,0xd5] -// CHECK: mrs x9, spsr_fiq // encoding: [0x69,0x43,0x3c,0xd5] -// CHECK: mrs x9, fpcr // encoding: [0x09,0x44,0x3b,0xd5] -// CHECK: mrs x9, fpsr // encoding: [0x29,0x44,0x3b,0xd5] -// CHECK: mrs x9, dspsr_el0 // encoding: [0x09,0x45,0x3b,0xd5] -// CHECK: mrs x9, dlr_el0 // encoding: [0x29,0x45,0x3b,0xd5] -// CHECK: mrs x9, ifsr32_el2 // encoding: [0x29,0x50,0x3c,0xd5] -// CHECK: mrs x9, afsr0_el1 // encoding: [0x09,0x51,0x38,0xd5] -// CHECK: mrs x9, afsr0_el2 // encoding: [0x09,0x51,0x3c,0xd5] -// CHECK: mrs x9, afsr0_el3 // encoding: [0x09,0x51,0x3e,0xd5] -// CHECK: mrs x9, afsr1_el1 // encoding: [0x29,0x51,0x38,0xd5] -// CHECK: mrs x9, afsr1_el2 // encoding: [0x29,0x51,0x3c,0xd5] -// CHECK: mrs x9, afsr1_el3 // encoding: [0x29,0x51,0x3e,0xd5] -// CHECK: mrs x9, esr_el1 // encoding: [0x09,0x52,0x38,0xd5] -// CHECK: mrs x9, esr_el2 // encoding: [0x09,0x52,0x3c,0xd5] -// CHECK: mrs x9, esr_el3 // encoding: [0x09,0x52,0x3e,0xd5] -// CHECK: mrs x9, fpexc32_el2 // encoding: [0x09,0x53,0x3c,0xd5] -// CHECK: mrs x9, far_el1 // encoding: [0x09,0x60,0x38,0xd5] -// CHECK: mrs x9, far_el2 // encoding: [0x09,0x60,0x3c,0xd5] -// CHECK: mrs x9, far_el3 // encoding: [0x09,0x60,0x3e,0xd5] -// CHECK: mrs x9, hpfar_el2 // encoding: [0x89,0x60,0x3c,0xd5] -// CHECK: mrs x9, par_el1 // encoding: [0x09,0x74,0x38,0xd5] -// CHECK: mrs x9, pmcr_el0 // encoding: [0x09,0x9c,0x3b,0xd5] -// CHECK: mrs x9, pmcntenset_el0 // encoding: [0x29,0x9c,0x3b,0xd5] -// CHECK: mrs x9, pmcntenclr_el0 // encoding: [0x49,0x9c,0x3b,0xd5] -// CHECK: mrs x9, pmovsclr_el0 // encoding: [0x69,0x9c,0x3b,0xd5] -// CHECK: mrs x9, pmselr_el0 // encoding: [0xa9,0x9c,0x3b,0xd5] -// CHECK: mrs x9, pmceid0_el0 // encoding: [0xc9,0x9c,0x3b,0xd5] -// CHECK: mrs x9, pmceid1_el0 // encoding: [0xe9,0x9c,0x3b,0xd5] -// CHECK: mrs x9, pmccntr_el0 // encoding: [0x09,0x9d,0x3b,0xd5] -// CHECK: mrs x9, pmxevtyper_el0 // encoding: [0x29,0x9d,0x3b,0xd5] -// CHECK: mrs x9, pmxevcntr_el0 // encoding: [0x49,0x9d,0x3b,0xd5] -// CHECK: mrs x9, pmuserenr_el0 // encoding: [0x09,0x9e,0x3b,0xd5] -// CHECK: mrs x9, pmintenset_el1 // encoding: [0x29,0x9e,0x38,0xd5] -// CHECK: mrs x9, pmintenclr_el1 // encoding: [0x49,0x9e,0x38,0xd5] -// CHECK: mrs x9, pmovsset_el0 // encoding: [0x69,0x9e,0x3b,0xd5] -// CHECK: mrs x9, mair_el1 // encoding: [0x09,0xa2,0x38,0xd5] -// CHECK: mrs x9, mair_el2 // encoding: [0x09,0xa2,0x3c,0xd5] -// CHECK: mrs x9, mair_el3 // encoding: [0x09,0xa2,0x3e,0xd5] -// CHECK: mrs x9, amair_el1 // encoding: [0x09,0xa3,0x38,0xd5] -// CHECK: mrs x9, amair_el2 // encoding: [0x09,0xa3,0x3c,0xd5] -// CHECK: mrs x9, amair_el3 // encoding: [0x09,0xa3,0x3e,0xd5] -// CHECK: mrs x9, vbar_el1 // encoding: [0x09,0xc0,0x38,0xd5] -// CHECK: mrs x9, vbar_el2 // encoding: [0x09,0xc0,0x3c,0xd5] -// CHECK: mrs x9, vbar_el3 // encoding: [0x09,0xc0,0x3e,0xd5] -// CHECK: mrs x9, rvbar_el1 // encoding: [0x29,0xc0,0x38,0xd5] -// CHECK: mrs x9, rvbar_el2 // encoding: [0x29,0xc0,0x3c,0xd5] -// CHECK: mrs x9, rvbar_el3 // encoding: [0x29,0xc0,0x3e,0xd5] -// CHECK: mrs x9, rmr_el1 // encoding: [0x49,0xc0,0x38,0xd5] -// CHECK: mrs x9, rmr_el2 // encoding: [0x49,0xc0,0x3c,0xd5] -// CHECK: mrs x9, rmr_el3 // encoding: [0x49,0xc0,0x3e,0xd5] -// CHECK: mrs x9, isr_el1 // encoding: [0x09,0xc1,0x38,0xd5] -// CHECK: mrs x9, contextidr_el1 // encoding: [0x29,0xd0,0x38,0xd5] -// CHECK: mrs x9, tpidr_el0 // encoding: [0x49,0xd0,0x3b,0xd5] -// CHECK: mrs x9, tpidr_el2 // encoding: [0x49,0xd0,0x3c,0xd5] -// CHECK: mrs x9, tpidr_el3 // encoding: [0x49,0xd0,0x3e,0xd5] -// CHECK: mrs x9, tpidrro_el0 // encoding: [0x69,0xd0,0x3b,0xd5] -// CHECK: mrs x9, tpidr_el1 // encoding: [0x89,0xd0,0x38,0xd5] -// CHECK: mrs x9, cntfrq_el0 // encoding: [0x09,0xe0,0x3b,0xd5] -// CHECK: mrs x9, cntpct_el0 // encoding: [0x29,0xe0,0x3b,0xd5] -// CHECK: mrs x9, cntvct_el0 // encoding: [0x49,0xe0,0x3b,0xd5] -// CHECK: mrs x9, cntvoff_el2 // encoding: [0x69,0xe0,0x3c,0xd5] -// CHECK: mrs x9, cntkctl_el1 // encoding: [0x09,0xe1,0x38,0xd5] -// CHECK: mrs x9, cnthctl_el2 // encoding: [0x09,0xe1,0x3c,0xd5] -// CHECK: mrs x9, cntp_tval_el0 // encoding: [0x09,0xe2,0x3b,0xd5] -// CHECK: mrs x9, cnthp_tval_el2 // encoding: [0x09,0xe2,0x3c,0xd5] -// CHECK: mrs x9, cntps_tval_el1 // encoding: [0x09,0xe2,0x3f,0xd5] -// CHECK: mrs x9, cntp_ctl_el0 // encoding: [0x29,0xe2,0x3b,0xd5] -// CHECK: mrs x9, cnthp_ctl_el2 // encoding: [0x29,0xe2,0x3c,0xd5] -// CHECK: mrs x9, cntps_ctl_el1 // encoding: [0x29,0xe2,0x3f,0xd5] -// CHECK: mrs x9, cntp_cval_el0 // encoding: [0x49,0xe2,0x3b,0xd5] -// CHECK: mrs x9, cnthp_cval_el2 // encoding: [0x49,0xe2,0x3c,0xd5] -// CHECK: mrs x9, cntps_cval_el1 // encoding: [0x49,0xe2,0x3f,0xd5] -// CHECK: mrs x9, cntv_tval_el0 // encoding: [0x09,0xe3,0x3b,0xd5] -// CHECK: mrs x9, cntv_ctl_el0 // encoding: [0x29,0xe3,0x3b,0xd5] -// CHECK: mrs x9, cntv_cval_el0 // encoding: [0x49,0xe3,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr0_el0 // encoding: [0x09,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr1_el0 // encoding: [0x29,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr2_el0 // encoding: [0x49,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr3_el0 // encoding: [0x69,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr4_el0 // encoding: [0x89,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr5_el0 // encoding: [0xa9,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr6_el0 // encoding: [0xc9,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr7_el0 // encoding: [0xe9,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr8_el0 // encoding: [0x09,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr9_el0 // encoding: [0x29,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr10_el0 // encoding: [0x49,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr11_el0 // encoding: [0x69,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr12_el0 // encoding: [0x89,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr13_el0 // encoding: [0xa9,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr14_el0 // encoding: [0xc9,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr15_el0 // encoding: [0xe9,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr16_el0 // encoding: [0x09,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr17_el0 // encoding: [0x29,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr18_el0 // encoding: [0x49,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr19_el0 // encoding: [0x69,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr20_el0 // encoding: [0x89,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr21_el0 // encoding: [0xa9,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr22_el0 // encoding: [0xc9,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr23_el0 // encoding: [0xe9,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr24_el0 // encoding: [0x09,0xeb,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr25_el0 // encoding: [0x29,0xeb,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr26_el0 // encoding: [0x49,0xeb,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr27_el0 // encoding: [0x69,0xeb,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr28_el0 // encoding: [0x89,0xeb,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr29_el0 // encoding: [0xa9,0xeb,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr30_el0 // encoding: [0xc9,0xeb,0x3b,0xd5] -// CHECK: mrs x9, pmccfiltr_el0 // encoding: [0xe9,0xef,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper0_el0 // encoding: [0x09,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper1_el0 // encoding: [0x29,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper2_el0 // encoding: [0x49,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper3_el0 // encoding: [0x69,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper4_el0 // encoding: [0x89,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper5_el0 // encoding: [0xa9,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper6_el0 // encoding: [0xc9,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper7_el0 // encoding: [0xe9,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper8_el0 // encoding: [0x09,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper9_el0 // encoding: [0x29,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper10_el0 // encoding: [0x49,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper11_el0 // encoding: [0x69,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper12_el0 // encoding: [0x89,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper13_el0 // encoding: [0xa9,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper14_el0 // encoding: [0xc9,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper15_el0 // encoding: [0xe9,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper16_el0 // encoding: [0x09,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper17_el0 // encoding: [0x29,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper18_el0 // encoding: [0x49,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper19_el0 // encoding: [0x69,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper20_el0 // encoding: [0x89,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper21_el0 // encoding: [0xa9,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper22_el0 // encoding: [0xc9,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper23_el0 // encoding: [0xe9,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper24_el0 // encoding: [0x09,0xef,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper25_el0 // encoding: [0x29,0xef,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper26_el0 // encoding: [0x49,0xef,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper27_el0 // encoding: [0x69,0xef,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper28_el0 // encoding: [0x89,0xef,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper29_el0 // encoding: [0xa9,0xef,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper30_el0 // encoding: [0xc9,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{teecr32_el1|TEECR32_EL1}} // encoding: [0x09,0x00,0x32,0xd5] +// CHECK: mrs x9, {{osdtrrx_el1|OSDTRRX_EL1}} // encoding: [0x49,0x00,0x30,0xd5] +// CHECK: mrs x9, {{mdccsr_el0|MDCCSR_EL0}} // encoding: [0x09,0x01,0x33,0xd5] +// CHECK: mrs x9, {{mdccint_el1|MDCCINT_EL1}} // encoding: [0x09,0x02,0x30,0xd5] +// CHECK: mrs x9, {{mdscr_el1|MDSCR_EL1}} // encoding: [0x49,0x02,0x30,0xd5] +// CHECK: mrs x9, {{osdtrtx_el1|OSDTRTX_EL1}} // encoding: [0x49,0x03,0x30,0xd5] +// CHECK: mrs x9, {{dbgdtr_el0|DBGDTR_EL0}} // encoding: [0x09,0x04,0x33,0xd5] +// CHECK: mrs x9, {{dbgdtrrx_el0|DBGDTRRX_EL0}} // encoding: [0x09,0x05,0x33,0xd5] +// CHECK: mrs x9, {{oseccr_el1|OSECCR_EL1}} // encoding: [0x49,0x06,0x30,0xd5] +// CHECK: mrs x9, {{dbgvcr32_el2|DBGVCR32_EL2}} // encoding: [0x09,0x07,0x34,0xd5] +// CHECK: mrs x9, {{dbgbvr0_el1|DBGBVR0_EL1}} // encoding: [0x89,0x00,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr1_el1|DBGBVR1_EL1}} // encoding: [0x89,0x01,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr2_el1|DBGBVR2_EL1}} // encoding: [0x89,0x02,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr3_el1|DBGBVR3_EL1}} // encoding: [0x89,0x03,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr4_el1|DBGBVR4_EL1}} // encoding: [0x89,0x04,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr5_el1|DBGBVR5_EL1}} // encoding: [0x89,0x05,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr6_el1|DBGBVR6_EL1}} // encoding: [0x89,0x06,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr7_el1|DBGBVR7_EL1}} // encoding: [0x89,0x07,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr8_el1|DBGBVR8_EL1}} // encoding: [0x89,0x08,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr9_el1|DBGBVR9_EL1}} // encoding: [0x89,0x09,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr10_el1|DBGBVR10_EL1}} // encoding: [0x89,0x0a,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr11_el1|DBGBVR11_EL1}} // encoding: [0x89,0x0b,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr12_el1|DBGBVR12_EL1}} // encoding: [0x89,0x0c,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr13_el1|DBGBVR13_EL1}} // encoding: [0x89,0x0d,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr14_el1|DBGBVR14_EL1}} // encoding: [0x89,0x0e,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr15_el1|DBGBVR15_EL1}} // encoding: [0x89,0x0f,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr0_el1|DBGBCR0_EL1}} // encoding: [0xa9,0x00,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr1_el1|DBGBCR1_EL1}} // encoding: [0xa9,0x01,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr2_el1|DBGBCR2_EL1}} // encoding: [0xa9,0x02,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr3_el1|DBGBCR3_EL1}} // encoding: [0xa9,0x03,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr4_el1|DBGBCR4_EL1}} // encoding: [0xa9,0x04,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr5_el1|DBGBCR5_EL1}} // encoding: [0xa9,0x05,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr6_el1|DBGBCR6_EL1}} // encoding: [0xa9,0x06,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr7_el1|DBGBCR7_EL1}} // encoding: [0xa9,0x07,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr8_el1|DBGBCR8_EL1}} // encoding: [0xa9,0x08,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr9_el1|DBGBCR9_EL1}} // encoding: [0xa9,0x09,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr10_el1|DBGBCR10_EL1}} // encoding: [0xa9,0x0a,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr11_el1|DBGBCR11_EL1}} // encoding: [0xa9,0x0b,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr12_el1|DBGBCR12_EL1}} // encoding: [0xa9,0x0c,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr13_el1|DBGBCR13_EL1}} // encoding: [0xa9,0x0d,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr14_el1|DBGBCR14_EL1}} // encoding: [0xa9,0x0e,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr15_el1|DBGBCR15_EL1}} // encoding: [0xa9,0x0f,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr0_el1|DBGWVR0_EL1}} // encoding: [0xc9,0x00,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr1_el1|DBGWVR1_EL1}} // encoding: [0xc9,0x01,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr2_el1|DBGWVR2_EL1}} // encoding: [0xc9,0x02,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr3_el1|DBGWVR3_EL1}} // encoding: [0xc9,0x03,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr4_el1|DBGWVR4_EL1}} // encoding: [0xc9,0x04,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr5_el1|DBGWVR5_EL1}} // encoding: [0xc9,0x05,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr6_el1|DBGWVR6_EL1}} // encoding: [0xc9,0x06,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr7_el1|DBGWVR7_EL1}} // encoding: [0xc9,0x07,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr8_el1|DBGWVR8_EL1}} // encoding: [0xc9,0x08,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr9_el1|DBGWVR9_EL1}} // encoding: [0xc9,0x09,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr10_el1|DBGWVR10_EL1}} // encoding: [0xc9,0x0a,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr11_el1|DBGWVR11_EL1}} // encoding: [0xc9,0x0b,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr12_el1|DBGWVR12_EL1}} // encoding: [0xc9,0x0c,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr13_el1|DBGWVR13_EL1}} // encoding: [0xc9,0x0d,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr14_el1|DBGWVR14_EL1}} // encoding: [0xc9,0x0e,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr15_el1|DBGWVR15_EL1}} // encoding: [0xc9,0x0f,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr0_el1|DBGWCR0_EL1}} // encoding: [0xe9,0x00,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr1_el1|DBGWCR1_EL1}} // encoding: [0xe9,0x01,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr2_el1|DBGWCR2_EL1}} // encoding: [0xe9,0x02,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr3_el1|DBGWCR3_EL1}} // encoding: [0xe9,0x03,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr4_el1|DBGWCR4_EL1}} // encoding: [0xe9,0x04,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr5_el1|DBGWCR5_EL1}} // encoding: [0xe9,0x05,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr6_el1|DBGWCR6_EL1}} // encoding: [0xe9,0x06,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr7_el1|DBGWCR7_EL1}} // encoding: [0xe9,0x07,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr8_el1|DBGWCR8_EL1}} // encoding: [0xe9,0x08,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr9_el1|DBGWCR9_EL1}} // encoding: [0xe9,0x09,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr10_el1|DBGWCR10_EL1}} // encoding: [0xe9,0x0a,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr11_el1|DBGWCR11_EL1}} // encoding: [0xe9,0x0b,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr12_el1|DBGWCR12_EL1}} // encoding: [0xe9,0x0c,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr13_el1|DBGWCR13_EL1}} // encoding: [0xe9,0x0d,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr14_el1|DBGWCR14_EL1}} // encoding: [0xe9,0x0e,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr15_el1|DBGWCR15_EL1}} // encoding: [0xe9,0x0f,0x30,0xd5] +// CHECK: mrs x9, {{mdrar_el1|MDRAR_EL1}} // encoding: [0x09,0x10,0x30,0xd5] +// CHECK: mrs x9, {{teehbr32_el1|TEEHBR32_EL1}} // encoding: [0x09,0x10,0x32,0xd5] +// CHECK: mrs x9, {{oslsr_el1|OSLSR_EL1}} // encoding: [0x89,0x11,0x30,0xd5] +// CHECK: mrs x9, {{osdlr_el1|OSDLR_EL1}} // encoding: [0x89,0x13,0x30,0xd5] +// CHECK: mrs x9, {{dbgprcr_el1|DBGPRCR_EL1}} // encoding: [0x89,0x14,0x30,0xd5] +// CHECK: mrs x9, {{dbgclaimset_el1|DBGCLAIMSET_EL1}} // encoding: [0xc9,0x78,0x30,0xd5] +// CHECK: mrs x9, {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}} // encoding: [0xc9,0x79,0x30,0xd5] +// CHECK: mrs x9, {{dbgauthstatus_el1|DBGAUTHSTATUS_EL1}} // encoding: [0xc9,0x7e,0x30,0xd5] +// CHECK: mrs x9, {{midr_el1|MIDR_EL1}} // encoding: [0x09,0x00,0x38,0xd5] +// CHECK: mrs x9, {{ccsidr_el1|CCSIDR_EL1}} // encoding: [0x09,0x00,0x39,0xd5] +// CHECK: mrs x9, {{csselr_el1|CSSELR_EL1}} // encoding: [0x09,0x00,0x3a,0xd5] +// CHECK: mrs x9, {{vpidr_el2|VPIDR_EL2}} // encoding: [0x09,0x00,0x3c,0xd5] +// CHECK: mrs x9, {{clidr_el1|CLIDR_EL1}} // encoding: [0x29,0x00,0x39,0xd5] +// CHECK: mrs x9, {{ctr_el0|CTR_EL0}} // encoding: [0x29,0x00,0x3b,0xd5] +// CHECK: mrs x9, {{mpidr_el1|MPIDR_EL1}} // encoding: [0xa9,0x00,0x38,0xd5] +// CHECK: mrs x9, {{vmpidr_el2|VMPIDR_EL2}} // encoding: [0xa9,0x00,0x3c,0xd5] +// CHECK: mrs x9, {{revidr_el1|REVIDR_EL1}} // encoding: [0xc9,0x00,0x38,0xd5] +// CHECK: mrs x9, {{aidr_el1|AIDR_EL1}} // encoding: [0xe9,0x00,0x39,0xd5] +// CHECK: mrs x9, {{dczid_el0|DCZID_EL0}} // encoding: [0xe9,0x00,0x3b,0xd5] +// CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}} // encoding: [0x09,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} // encoding: [0x29,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} // encoding: [0x49,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} // encoding: [0x69,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} // encoding: [0x89,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} // encoding: [0xa9,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}} // encoding: [0xc9,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}} // encoding: [0xe9,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}} // encoding: [0x09,0x02,0x38,0xd5] +// CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}} // encoding: [0x29,0x02,0x38,0xd5] +// CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}} // encoding: [0x49,0x02,0x38,0xd5] +// CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}} // encoding: [0x69,0x02,0x38,0xd5] +// CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}} // encoding: [0x89,0x02,0x38,0xd5] +// CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}} // encoding: [0xa9,0x02,0x38,0xd5] +// CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}} // encoding: [0x09,0x03,0x38,0xd5] +// CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}} // encoding: [0x29,0x03,0x38,0xd5] +// CHECK: mrs x9, {{mvfr2_el1|MVFR2_EL1}} // encoding: [0x49,0x03,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64pfr0_el1|ID_AA64PFR0_EL1}} // encoding: [0x09,0x04,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64pfr1_el1|ID_AA64PFR1_EL1}} // encoding: [0x29,0x04,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64dfr0_el1|ID_AA64DFR0_EL1}} // encoding: [0x09,0x05,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64dfr1_el1|ID_AA64DFR1_EL1}} // encoding: [0x29,0x05,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64afr0_el1|ID_AA64AFR0_EL1}} // encoding: [0x89,0x05,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}} // encoding: [0xa9,0x05,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}} // encoding: [0x09,0x06,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}} // encoding: [0x29,0x06,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}} // encoding: [0x09,0x07,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}} // encoding: [0x29,0x07,0x38,0xd5] +// CHECK: mrs x9, {{sctlr_el1|SCTLR_EL1}} // encoding: [0x09,0x10,0x38,0xd5] +// CHECK: mrs x9, {{sctlr_el2|SCTLR_EL2}} // encoding: [0x09,0x10,0x3c,0xd5] +// CHECK: mrs x9, {{sctlr_el3|SCTLR_EL3}} // encoding: [0x09,0x10,0x3e,0xd5] +// CHECK: mrs x9, {{actlr_el1|ACTLR_EL1}} // encoding: [0x29,0x10,0x38,0xd5] +// CHECK: mrs x9, {{actlr_el2|ACTLR_EL2}} // encoding: [0x29,0x10,0x3c,0xd5] +// CHECK: mrs x9, {{actlr_el3|ACTLR_EL3}} // encoding: [0x29,0x10,0x3e,0xd5] +// CHECK: mrs x9, {{cpacr_el1|CPACR_EL1}} // encoding: [0x49,0x10,0x38,0xd5] +// CHECK: mrs x9, {{hcr_el2|HCR_EL2}} // encoding: [0x09,0x11,0x3c,0xd5] +// CHECK: mrs x9, {{scr_el3|SCR_EL3}} // encoding: [0x09,0x11,0x3e,0xd5] +// CHECK: mrs x9, {{mdcr_el2|MDCR_EL2}} // encoding: [0x29,0x11,0x3c,0xd5] +// CHECK: mrs x9, {{sder32_el3|SDER32_EL3}} // encoding: [0x29,0x11,0x3e,0xd5] +// CHECK: mrs x9, {{cptr_el2|CPTR_EL2}} // encoding: [0x49,0x11,0x3c,0xd5] +// CHECK: mrs x9, {{cptr_el3|CPTR_EL3}} // encoding: [0x49,0x11,0x3e,0xd5] +// CHECK: mrs x9, {{hstr_el2|HSTR_EL2}} // encoding: [0x69,0x11,0x3c,0xd5] +// CHECK: mrs x9, {{hacr_el2|HACR_EL2}} // encoding: [0xe9,0x11,0x3c,0xd5] +// CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}} // encoding: [0x29,0x13,0x3e,0xd5] +// CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}} // encoding: [0x09,0x20,0x38,0xd5] +// CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}} // encoding: [0x09,0x20,0x3c,0xd5] +// CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}} // encoding: [0x09,0x20,0x3e,0xd5] +// CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}} // encoding: [0x29,0x20,0x38,0xd5] +// CHECK: mrs x9, {{tcr_el1|TCR_EL1}} // encoding: [0x49,0x20,0x38,0xd5] +// CHECK: mrs x9, {{tcr_el2|TCR_EL2}} // encoding: [0x49,0x20,0x3c,0xd5] +// CHECK: mrs x9, {{tcr_el3|TCR_EL3}} // encoding: [0x49,0x20,0x3e,0xd5] +// CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}} // encoding: [0x09,0x21,0x3c,0xd5] +// CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}} // encoding: [0x49,0x21,0x3c,0xd5] +// CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}} // encoding: [0x09,0x30,0x3c,0xd5] +// CHECK: mrs x9, {{spsr_el1|SPSR_EL1}} // encoding: [0x09,0x40,0x38,0xd5] +// CHECK: mrs x9, {{spsr_el2|SPSR_EL2}} // encoding: [0x09,0x40,0x3c,0xd5] +// CHECK: mrs x9, {{spsr_el3|SPSR_EL3}} // encoding: [0x09,0x40,0x3e,0xd5] +// CHECK: mrs x9, {{elr_el1|ELR_EL1}} // encoding: [0x29,0x40,0x38,0xd5] +// CHECK: mrs x9, {{elr_el2|ELR_EL2}} // encoding: [0x29,0x40,0x3c,0xd5] +// CHECK: mrs x9, {{elr_el3|ELR_EL3}} // encoding: [0x29,0x40,0x3e,0xd5] +// CHECK: mrs x9, {{sp_el0|SP_EL0}} // encoding: [0x09,0x41,0x38,0xd5] +// CHECK: mrs x9, {{sp_el1|SP_EL1}} // encoding: [0x09,0x41,0x3c,0xd5] +// CHECK: mrs x9, {{sp_el2|SP_EL2}} // encoding: [0x09,0x41,0x3e,0xd5] +// CHECK: mrs x9, {{spsel|SPSEL}} // encoding: [0x09,0x42,0x38,0xd5] +// CHECK: mrs x9, {{nzcv|NZCV}} // encoding: [0x09,0x42,0x3b,0xd5] +// CHECK: mrs x9, {{daif|DAIF}} // encoding: [0x29,0x42,0x3b,0xd5] +// CHECK: mrs x9, {{currentel|CURRENTEL}} // encoding: [0x49,0x42,0x38,0xd5] +// CHECK: mrs x9, {{spsr_irq|SPSR_IRQ}} // encoding: [0x09,0x43,0x3c,0xd5] +// CHECK: mrs x9, {{spsr_abt|SPSR_ABT}} // encoding: [0x29,0x43,0x3c,0xd5] +// CHECK: mrs x9, {{spsr_und|SPSR_UND}} // encoding: [0x49,0x43,0x3c,0xd5] +// CHECK: mrs x9, {{spsr_fiq|SPSR_FIQ}} // encoding: [0x69,0x43,0x3c,0xd5] +// CHECK: mrs x9, {{fpcr|FPCR}} // encoding: [0x09,0x44,0x3b,0xd5] +// CHECK: mrs x9, {{fpsr|FPSR}} // encoding: [0x29,0x44,0x3b,0xd5] +// CHECK: mrs x9, {{dspsr_el0|DSPSR_EL0}} // encoding: [0x09,0x45,0x3b,0xd5] +// CHECK: mrs x9, {{dlr_el0|DLR_EL0}} // encoding: [0x29,0x45,0x3b,0xd5] +// CHECK: mrs x9, {{ifsr32_el2|IFSR32_EL2}} // encoding: [0x29,0x50,0x3c,0xd5] +// CHECK: mrs x9, {{afsr0_el1|AFSR0_EL1}} // encoding: [0x09,0x51,0x38,0xd5] +// CHECK: mrs x9, {{afsr0_el2|AFSR0_EL2}} // encoding: [0x09,0x51,0x3c,0xd5] +// CHECK: mrs x9, {{afsr0_el3|AFSR0_EL3}} // encoding: [0x09,0x51,0x3e,0xd5] +// CHECK: mrs x9, {{afsr1_el1|AFSR1_EL1}} // encoding: [0x29,0x51,0x38,0xd5] +// CHECK: mrs x9, {{afsr1_el2|AFSR1_EL2}} // encoding: [0x29,0x51,0x3c,0xd5] +// CHECK: mrs x9, {{afsr1_el3|AFSR1_EL3}} // encoding: [0x29,0x51,0x3e,0xd5] +// CHECK: mrs x9, {{esr_el1|ESR_EL1}} // encoding: [0x09,0x52,0x38,0xd5] +// CHECK: mrs x9, {{esr_el2|ESR_EL2}} // encoding: [0x09,0x52,0x3c,0xd5] +// CHECK: mrs x9, {{esr_el3|ESR_EL3}} // encoding: [0x09,0x52,0x3e,0xd5] +// CHECK: mrs x9, {{fpexc32_el2|FPEXC32_EL2}} // encoding: [0x09,0x53,0x3c,0xd5] +// CHECK: mrs x9, {{far_el1|FAR_EL1}} // encoding: [0x09,0x60,0x38,0xd5] +// CHECK: mrs x9, {{far_el2|FAR_EL2}} // encoding: [0x09,0x60,0x3c,0xd5] +// CHECK: mrs x9, {{far_el3|FAR_EL3}} // encoding: [0x09,0x60,0x3e,0xd5] +// CHECK: mrs x9, {{hpfar_el2|HPFAR_EL2}} // encoding: [0x89,0x60,0x3c,0xd5] +// CHECK: mrs x9, {{par_el1|PAR_EL1}} // encoding: [0x09,0x74,0x38,0xd5] +// CHECK: mrs x9, {{pmcr_el0|PMCR_EL0}} // encoding: [0x09,0x9c,0x3b,0xd5] +// CHECK: mrs x9, {{pmcntenset_el0|PMCNTENSET_EL0}} // encoding: [0x29,0x9c,0x3b,0xd5] +// CHECK: mrs x9, {{pmcntenclr_el0|PMCNTENCLR_EL0}} // encoding: [0x49,0x9c,0x3b,0xd5] +// CHECK: mrs x9, {{pmovsclr_el0|PMOVSCLR_EL0}} // encoding: [0x69,0x9c,0x3b,0xd5] +// CHECK: mrs x9, {{pmselr_el0|PMSELR_EL0}} // encoding: [0xa9,0x9c,0x3b,0xd5] +// CHECK: mrs x9, {{pmceid0_el0|PMCEID0_EL0}} // encoding: [0xc9,0x9c,0x3b,0xd5] +// CHECK: mrs x9, {{pmceid1_el0|PMCEID1_EL0}} // encoding: [0xe9,0x9c,0x3b,0xd5] +// CHECK: mrs x9, {{pmccntr_el0|PMCCNTR_EL0}} // encoding: [0x09,0x9d,0x3b,0xd5] +// CHECK: mrs x9, {{pmxevtyper_el0|PMXEVTYPER_EL0}} // encoding: [0x29,0x9d,0x3b,0xd5] +// CHECK: mrs x9, {{pmxevcntr_el0|PMXEVCNTR_EL0}} // encoding: [0x49,0x9d,0x3b,0xd5] +// CHECK: mrs x9, {{pmuserenr_el0|PMUSERENR_EL0}} // encoding: [0x09,0x9e,0x3b,0xd5] +// CHECK: mrs x9, {{pmintenset_el1|PMINTENSET_EL1}} // encoding: [0x29,0x9e,0x38,0xd5] +// CHECK: mrs x9, {{pmintenclr_el1|PMINTENCLR_EL1}} // encoding: [0x49,0x9e,0x38,0xd5] +// CHECK: mrs x9, {{pmovsset_el0|PMOVSSET_EL0}} // encoding: [0x69,0x9e,0x3b,0xd5] +// CHECK: mrs x9, {{mair_el1|MAIR_EL1}} // encoding: [0x09,0xa2,0x38,0xd5] +// CHECK: mrs x9, {{mair_el2|MAIR_EL2}} // encoding: [0x09,0xa2,0x3c,0xd5] +// CHECK: mrs x9, {{mair_el3|MAIR_EL3}} // encoding: [0x09,0xa2,0x3e,0xd5] +// CHECK: mrs x9, {{amair_el1|AMAIR_EL1}} // encoding: [0x09,0xa3,0x38,0xd5] +// CHECK: mrs x9, {{amair_el2|AMAIR_EL2}} // encoding: [0x09,0xa3,0x3c,0xd5] +// CHECK: mrs x9, {{amair_el3|AMAIR_EL3}} // encoding: [0x09,0xa3,0x3e,0xd5] +// CHECK: mrs x9, {{vbar_el1|VBAR_EL1}} // encoding: [0x09,0xc0,0x38,0xd5] +// CHECK: mrs x9, {{vbar_el2|VBAR_EL2}} // encoding: [0x09,0xc0,0x3c,0xd5] +// CHECK: mrs x9, {{vbar_el3|VBAR_EL3}} // encoding: [0x09,0xc0,0x3e,0xd5] +// CHECK: mrs x9, {{rvbar_el1|RVBAR_EL1}} // encoding: [0x29,0xc0,0x38,0xd5] +// CHECK: mrs x9, {{rvbar_el2|RVBAR_EL2}} // encoding: [0x29,0xc0,0x3c,0xd5] +// CHECK: mrs x9, {{rvbar_el3|RVBAR_EL3}} // encoding: [0x29,0xc0,0x3e,0xd5] +// CHECK: mrs x9, {{rmr_el1|RMR_EL1}} // encoding: [0x49,0xc0,0x38,0xd5] +// CHECK: mrs x9, {{rmr_el2|RMR_EL2}} // encoding: [0x49,0xc0,0x3c,0xd5] +// CHECK: mrs x9, {{rmr_el3|RMR_EL3}} // encoding: [0x49,0xc0,0x3e,0xd5] +// CHECK: mrs x9, {{isr_el1|ISR_EL1}} // encoding: [0x09,0xc1,0x38,0xd5] +// CHECK: mrs x9, {{contextidr_el1|CONTEXTIDR_EL1}} // encoding: [0x29,0xd0,0x38,0xd5] +// CHECK: mrs x9, {{tpidr_el0|TPIDR_EL0}} // encoding: [0x49,0xd0,0x3b,0xd5] +// CHECK: mrs x9, {{tpidr_el2|TPIDR_EL2}} // encoding: [0x49,0xd0,0x3c,0xd5] +// CHECK: mrs x9, {{tpidr_el3|TPIDR_EL3}} // encoding: [0x49,0xd0,0x3e,0xd5] +// CHECK: mrs x9, {{tpidrro_el0|TPIDRRO_EL0}} // encoding: [0x69,0xd0,0x3b,0xd5] +// CHECK: mrs x9, {{tpidr_el1|TPIDR_EL1}} // encoding: [0x89,0xd0,0x38,0xd5] +// CHECK: mrs x9, {{cntfrq_el0|CNTFRQ_EL0}} // encoding: [0x09,0xe0,0x3b,0xd5] +// CHECK: mrs x9, {{cntpct_el0|CNTPCT_EL0}} // encoding: [0x29,0xe0,0x3b,0xd5] +// CHECK: mrs x9, {{cntvct_el0|CNTVCT_EL0}} // encoding: [0x49,0xe0,0x3b,0xd5] +// CHECK: mrs x9, {{cntvoff_el2|CNTVOFF_EL2}} // encoding: [0x69,0xe0,0x3c,0xd5] +// CHECK: mrs x9, {{cntkctl_el1|CNTKCTL_EL1}} // encoding: [0x09,0xe1,0x38,0xd5] +// CHECK: mrs x9, {{cnthctl_el2|CNTHCTL_EL2}} // encoding: [0x09,0xe1,0x3c,0xd5] +// CHECK: mrs x9, {{cntp_tval_el0|CNTP_TVAL_EL0}} // encoding: [0x09,0xe2,0x3b,0xd5] +// CHECK: mrs x9, {{cnthp_tval_el2|CNTHP_TVAL_EL2}} // encoding: [0x09,0xe2,0x3c,0xd5] +// CHECK: mrs x9, {{cntps_tval_el1|CNTPS_TVAL_EL1}} // encoding: [0x09,0xe2,0x3f,0xd5] +// CHECK: mrs x9, {{cntp_ctl_el0|CNTP_CTL_EL0}} // encoding: [0x29,0xe2,0x3b,0xd5] +// CHECK: mrs x9, {{cnthp_ctl_el2|CNTHP_CTL_EL2}} // encoding: [0x29,0xe2,0x3c,0xd5] +// CHECK: mrs x9, {{cntps_ctl_el1|CNTPS_CTL_EL1}} // encoding: [0x29,0xe2,0x3f,0xd5] +// CHECK: mrs x9, {{cntp_cval_el0|CNTP_CVAL_EL0}} // encoding: [0x49,0xe2,0x3b,0xd5] +// CHECK: mrs x9, {{cnthp_cval_el2|CNTHP_CVAL_EL2}} // encoding: [0x49,0xe2,0x3c,0xd5] +// CHECK: mrs x9, {{cntps_cval_el1|CNTPS_CVAL_EL1}} // encoding: [0x49,0xe2,0x3f,0xd5] +// CHECK: mrs x9, {{cntv_tval_el0|CNTV_TVAL_EL0}} // encoding: [0x09,0xe3,0x3b,0xd5] +// CHECK: mrs x9, {{cntv_ctl_el0|CNTV_CTL_EL0}} // encoding: [0x29,0xe3,0x3b,0xd5] +// CHECK: mrs x9, {{cntv_cval_el0|CNTV_CVAL_EL0}} // encoding: [0x49,0xe3,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr0_el0|PMEVCNTR0_EL0}} // encoding: [0x09,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr1_el0|PMEVCNTR1_EL0}} // encoding: [0x29,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr2_el0|PMEVCNTR2_EL0}} // encoding: [0x49,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr3_el0|PMEVCNTR3_EL0}} // encoding: [0x69,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr4_el0|PMEVCNTR4_EL0}} // encoding: [0x89,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr5_el0|PMEVCNTR5_EL0}} // encoding: [0xa9,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr6_el0|PMEVCNTR6_EL0}} // encoding: [0xc9,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr7_el0|PMEVCNTR7_EL0}} // encoding: [0xe9,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr8_el0|PMEVCNTR8_EL0}} // encoding: [0x09,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr9_el0|PMEVCNTR9_EL0}} // encoding: [0x29,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr10_el0|PMEVCNTR10_EL0}} // encoding: [0x49,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr11_el0|PMEVCNTR11_EL0}} // encoding: [0x69,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr12_el0|PMEVCNTR12_EL0}} // encoding: [0x89,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr13_el0|PMEVCNTR13_EL0}} // encoding: [0xa9,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr14_el0|PMEVCNTR14_EL0}} // encoding: [0xc9,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr15_el0|PMEVCNTR15_EL0}} // encoding: [0xe9,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr16_el0|PMEVCNTR16_EL0}} // encoding: [0x09,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr17_el0|PMEVCNTR17_EL0}} // encoding: [0x29,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr18_el0|PMEVCNTR18_EL0}} // encoding: [0x49,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr19_el0|PMEVCNTR19_EL0}} // encoding: [0x69,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr20_el0|PMEVCNTR20_EL0}} // encoding: [0x89,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr21_el0|PMEVCNTR21_EL0}} // encoding: [0xa9,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr22_el0|PMEVCNTR22_EL0}} // encoding: [0xc9,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr23_el0|PMEVCNTR23_EL0}} // encoding: [0xe9,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr24_el0|PMEVCNTR24_EL0}} // encoding: [0x09,0xeb,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr25_el0|PMEVCNTR25_EL0}} // encoding: [0x29,0xeb,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr26_el0|PMEVCNTR26_EL0}} // encoding: [0x49,0xeb,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr27_el0|PMEVCNTR27_EL0}} // encoding: [0x69,0xeb,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr28_el0|PMEVCNTR28_EL0}} // encoding: [0x89,0xeb,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr29_el0|PMEVCNTR29_EL0}} // encoding: [0xa9,0xeb,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr30_el0|PMEVCNTR30_EL0}} // encoding: [0xc9,0xeb,0x3b,0xd5] +// CHECK: mrs x9, {{pmccfiltr_el0|PMCCFILTR_EL0}} // encoding: [0xe9,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper0_el0|PMEVTYPER0_EL0}} // encoding: [0x09,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper1_el0|PMEVTYPER1_EL0}} // encoding: [0x29,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper2_el0|PMEVTYPER2_EL0}} // encoding: [0x49,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper3_el0|PMEVTYPER3_EL0}} // encoding: [0x69,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper4_el0|PMEVTYPER4_EL0}} // encoding: [0x89,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper5_el0|PMEVTYPER5_EL0}} // encoding: [0xa9,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper6_el0|PMEVTYPER6_EL0}} // encoding: [0xc9,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper7_el0|PMEVTYPER7_EL0}} // encoding: [0xe9,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper8_el0|PMEVTYPER8_EL0}} // encoding: [0x09,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper9_el0|PMEVTYPER9_EL0}} // encoding: [0x29,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper10_el0|PMEVTYPER10_EL0}} // encoding: [0x49,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper11_el0|PMEVTYPER11_EL0}} // encoding: [0x69,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper12_el0|PMEVTYPER12_EL0}} // encoding: [0x89,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper13_el0|PMEVTYPER13_EL0}} // encoding: [0xa9,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper14_el0|PMEVTYPER14_EL0}} // encoding: [0xc9,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper15_el0|PMEVTYPER15_EL0}} // encoding: [0xe9,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper16_el0|PMEVTYPER16_EL0}} // encoding: [0x09,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper17_el0|PMEVTYPER17_EL0}} // encoding: [0x29,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper18_el0|PMEVTYPER18_EL0}} // encoding: [0x49,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper19_el0|PMEVTYPER19_EL0}} // encoding: [0x69,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper20_el0|PMEVTYPER20_EL0}} // encoding: [0x89,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper21_el0|PMEVTYPER21_EL0}} // encoding: [0xa9,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper22_el0|PMEVTYPER22_EL0}} // encoding: [0xc9,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper23_el0|PMEVTYPER23_EL0}} // encoding: [0xe9,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper24_el0|PMEVTYPER24_EL0}} // encoding: [0x09,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper25_el0|PMEVTYPER25_EL0}} // encoding: [0x29,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper26_el0|PMEVTYPER26_EL0}} // encoding: [0x49,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper27_el0|PMEVTYPER27_EL0}} // encoding: [0x69,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper28_el0|PMEVTYPER28_EL0}} // encoding: [0x89,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper29_el0|PMEVTYPER29_EL0}} // encoding: [0xa9,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper30_el0|PMEVTYPER30_EL0}} // encoding: [0xc9,0xef,0x3b,0xd5] mrs x12, s3_7_c15_c1_5 mrs x13, s3_2_c11_c15_7 msr s3_0_c15_c0_0, x12 msr s3_7_c11_c13_7, x5 -// CHECK: mrs x12, s3_7_c15_c1_5 // encoding: [0xac,0xf1,0x3f,0xd5] -// CHECK: mrs x13, s3_2_c11_c15_7 // encoding: [0xed,0xbf,0x3a,0xd5] -// CHECK: msr s3_0_c15_c0_0, x12 // encoding: [0x0c,0xf0,0x18,0xd5] -// CHECK: msr s3_7_c11_c13_7, x5 // encoding: [0xe5,0xbd,0x1f,0xd5] +// CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}} // encoding: [0xac,0xf1,0x3f,0xd5] +// CHECK: mrs x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}} // encoding: [0xed,0xbf,0x3a,0xd5] +// CHECK: msr {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12 // encoding: [0x0c,0xf0,0x18,0xd5] +// CHECK: msr {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5 // encoding: [0xe5,0xbd,0x1f,0xd5] //------------------------------------------------------------------------------ // Unconditional branch (immediate) @@ -4814,22 +4781,25 @@ _func: tbz x5, #0, somewhere tbz xzr, #63, elsewhere tbnz x5, #45, nowhere -// CHECK: tbz x5, #0, somewhere // encoding: [0x05'A',A,A,0x36'A'] -// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_a64_tstbr -// CHECK: tbz xzr, #63, elsewhere // encoding: [0x1f'A',A,0xf8'A',0xb6'A'] -// CHECK: // fixup A - offset: 0, value: elsewhere, kind: fixup_a64_tstbr -// CHECK: tbnz x5, #45, nowhere // encoding: [0x05'A',A,0x68'A',0xb7'A'] -// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_a64_tstbr + +// CHECK: tbz w5, #0, somewhere // encoding: [0bAAA00101,A,0b00000AAA,0x36] +// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_aarch64_pcrel_branch14 +// CHECK: tbz xzr, #63, elsewhere // encoding: [0bAAA11111,A,0b11111AAA,0xb6] +// CHECK: // fixup A - offset: 0, value: elsewhere, kind: fixup_aarch64_pcrel_branch14 +// CHECK: tbnz x5, #45, nowhere // encoding: [0bAAA00101,A,0b01101AAA,0xb7] +// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_aarch64_pcrel_branch14 + tbnz w3, #2, there tbnz wzr, #31, nowhere tbz w5, #12, anywhere -// CHECK: tbnz w3, #2, there // encoding: [0x03'A',A,0x10'A',0x37'A'] -// CHECK: // fixup A - offset: 0, value: there, kind: fixup_a64_tstbr -// CHECK: tbnz wzr, #31, nowhere // encoding: [0x1f'A',A,0xf8'A',0x37'A'] -// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_a64_tstbr -// CHECK: tbz w5, #12, anywhere // encoding: [0x05'A',A,0x60'A',0x36'A'] -// CHECK: // fixup A - offset: 0, value: anywhere, kind: fixup_a64_tstbr + +// CHECK: tbnz w3, #2, there // encoding: [0bAAA00011,A,0b00010AAA,0x37] +// CHECK: // fixup A - offset: 0, value: there, kind: fixup_aarch64_pcrel_branch14 +// CHECK: tbnz wzr, #31, nowhere // encoding: [0bAAA11111,A,0b11111AAA,0x37] +// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_aarch64_pcrel_branch14 +// CHECK: tbz w5, #12, anywhere // encoding: [0bAAA00101,A,0b01100AAA,0x36] +// CHECK: // fixup A - offset: 0, value: anywhere, kind: fixup_aarch64_pcrel_branch14 //------------------------------------------------------------------------------ // Unconditional branch (immediate) @@ -4837,10 +4807,11 @@ _func: b somewhere bl elsewhere -// CHECK: b somewhere // encoding: [A,A,A,0x14'A'] -// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_a64_uncondbr -// CHECK: bl elsewhere // encoding: [A,A,A,0x94'A'] -// CHECK: // fixup A - offset: 0, value: elsewhere, kind: fixup_a64_call + +// CHECK: b somewhere // encoding: [A,A,A,0b000101AA] +// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_aarch64_pcrel_branch26 +// CHECK: bl elsewhere // encoding: [A,A,A,0b100101AA] +// CHECK: // fixup A - offset: 0, value: elsewhere, kind: fixup_aarch64_pcrel_call26 b #4 bl #0 diff --git a/test/MC/AArch64/elf-globaladdress.ll b/test/MC/AArch64/elf-globaladdress.ll index bc43113..7d031e6 100644 --- a/test/MC/AArch64/elf-globaladdress.ll +++ b/test/MC/AArch64/elf-globaladdress.ll @@ -3,7 +3,7 @@ ; Also take it on a round-trip through llvm-mc to stretch assembly-parsing's legs: ;; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | \ -;; RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj -o - | \ +;; RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -o - | \ ;; RUN: llvm-readobj -h -r | FileCheck -check-prefix=OBJ %s @var8 = global i8 0 diff --git a/test/MC/AArch64/elf-reloc-addend.s b/test/MC/AArch64/elf-reloc-addend.s deleted file mode 100644 index 0e7e2ca..0000000 --- a/test/MC/AArch64/elf-reloc-addend.s +++ /dev/null @@ -1,8 +0,0 @@ -// RUN: llvm-mc -triple=aarch64-linux-gnu -filetype=obj -o - %s | llvm-objdump -triple=aarch64-linux-gnu -r - | FileCheck %s - - add x0, x4, #:lo12:sym -// CHECK: 0 R_AARCH64_ADD_ABS_LO12_NC sym - add x3, x5, #:lo12:sym+1 -// CHECK: 4 R_AARCH64_ADD_ABS_LO12_NC sym+1 - add x3, x5, #:lo12:sym-1 -// CHECK: 8 R_AARCH64_ADD_ABS_LO12_NC sym-1 diff --git a/test/MC/AArch64/gicv3-regs.s b/test/MC/AArch64/gicv3-regs.s index f777651..0f5742e 100644 --- a/test/MC/AArch64/gicv3-regs.s +++ b/test/MC/AArch64/gicv3-regs.s @@ -56,62 +56,62 @@ mrs x8, ich_lr13_el2 mrs x2, ich_lr14_el2 mrs x8, ich_lr15_el2 -// CHECK: mrs x8, icc_iar1_el1 // encoding: [0x08,0xcc,0x38,0xd5] -// CHECK: mrs x26, icc_iar0_el1 // encoding: [0x1a,0xc8,0x38,0xd5] -// CHECK: mrs x2, icc_hppir1_el1 // encoding: [0x42,0xcc,0x38,0xd5] -// CHECK: mrs x17, icc_hppir0_el1 // encoding: [0x51,0xc8,0x38,0xd5] -// CHECK: mrs x29, icc_rpr_el1 // encoding: [0x7d,0xcb,0x38,0xd5] -// CHECK: mrs x4, ich_vtr_el2 // encoding: [0x24,0xcb,0x3c,0xd5] -// CHECK: mrs x24, ich_eisr_el2 // encoding: [0x78,0xcb,0x3c,0xd5] -// CHECK: mrs x9, ich_elsr_el2 // encoding: [0xa9,0xcb,0x3c,0xd5] -// CHECK: mrs x24, icc_bpr1_el1 // encoding: [0x78,0xcc,0x38,0xd5] -// CHECK: mrs x14, icc_bpr0_el1 // encoding: [0x6e,0xc8,0x38,0xd5] -// CHECK: mrs x19, icc_pmr_el1 // encoding: [0x13,0x46,0x38,0xd5] -// CHECK: mrs x23, icc_ctlr_el1 // encoding: [0x97,0xcc,0x38,0xd5] -// CHECK: mrs x20, icc_ctlr_el3 // encoding: [0x94,0xcc,0x3e,0xd5] -// CHECK: mrs x28, icc_sre_el1 // encoding: [0xbc,0xcc,0x38,0xd5] -// CHECK: mrs x25, icc_sre_el2 // encoding: [0xb9,0xc9,0x3c,0xd5] -// CHECK: mrs x8, icc_sre_el3 // encoding: [0xa8,0xcc,0x3e,0xd5] -// CHECK: mrs x22, icc_igrpen0_el1 // encoding: [0xd6,0xcc,0x38,0xd5] -// CHECK: mrs x5, icc_igrpen1_el1 // encoding: [0xe5,0xcc,0x38,0xd5] -// CHECK: mrs x7, icc_igrpen1_el3 // encoding: [0xe7,0xcc,0x3e,0xd5] -// CHECK: mrs x22, icc_seien_el1 // encoding: [0x16,0xcd,0x38,0xd5] -// CHECK: mrs x4, icc_ap0r0_el1 // encoding: [0x84,0xc8,0x38,0xd5] -// CHECK: mrs x11, icc_ap0r1_el1 // encoding: [0xab,0xc8,0x38,0xd5] -// CHECK: mrs x27, icc_ap0r2_el1 // encoding: [0xdb,0xc8,0x38,0xd5] -// CHECK: mrs x21, icc_ap0r3_el1 // encoding: [0xf5,0xc8,0x38,0xd5] -// CHECK: mrs x2, icc_ap1r0_el1 // encoding: [0x02,0xc9,0x38,0xd5] -// CHECK: mrs x21, icc_ap1r1_el1 // encoding: [0x35,0xc9,0x38,0xd5] -// CHECK: mrs x10, icc_ap1r2_el1 // encoding: [0x4a,0xc9,0x38,0xd5] -// CHECK: mrs x27, icc_ap1r3_el1 // encoding: [0x7b,0xc9,0x38,0xd5] -// CHECK: mrs x20, ich_ap0r0_el2 // encoding: [0x14,0xc8,0x3c,0xd5] -// CHECK: mrs x21, ich_ap0r1_el2 // encoding: [0x35,0xc8,0x3c,0xd5] -// CHECK: mrs x5, ich_ap0r2_el2 // encoding: [0x45,0xc8,0x3c,0xd5] -// CHECK: mrs x4, ich_ap0r3_el2 // encoding: [0x64,0xc8,0x3c,0xd5] -// CHECK: mrs x15, ich_ap1r0_el2 // encoding: [0x0f,0xc9,0x3c,0xd5] -// CHECK: mrs x12, ich_ap1r1_el2 // encoding: [0x2c,0xc9,0x3c,0xd5] -// CHECK: mrs x27, ich_ap1r2_el2 // encoding: [0x5b,0xc9,0x3c,0xd5] -// CHECK: mrs x20, ich_ap1r3_el2 // encoding: [0x74,0xc9,0x3c,0xd5] -// CHECK: mrs x10, ich_hcr_el2 // encoding: [0x0a,0xcb,0x3c,0xd5] -// CHECK: mrs x27, ich_misr_el2 // encoding: [0x5b,0xcb,0x3c,0xd5] -// CHECK: mrs x6, ich_vmcr_el2 // encoding: [0xe6,0xcb,0x3c,0xd5] -// CHECK: mrs x19, ich_vseir_el2 // encoding: [0x93,0xc9,0x3c,0xd5] -// CHECK: mrs x3, ich_lr0_el2 // encoding: [0x03,0xcc,0x3c,0xd5] -// CHECK: mrs x1, ich_lr1_el2 // encoding: [0x21,0xcc,0x3c,0xd5] -// CHECK: mrs x22, ich_lr2_el2 // encoding: [0x56,0xcc,0x3c,0xd5] -// CHECK: mrs x21, ich_lr3_el2 // encoding: [0x75,0xcc,0x3c,0xd5] -// CHECK: mrs x6, ich_lr4_el2 // encoding: [0x86,0xcc,0x3c,0xd5] -// CHECK: mrs x10, ich_lr5_el2 // encoding: [0xaa,0xcc,0x3c,0xd5] -// CHECK: mrs x11, ich_lr6_el2 // encoding: [0xcb,0xcc,0x3c,0xd5] -// CHECK: mrs x12, ich_lr7_el2 // encoding: [0xec,0xcc,0x3c,0xd5] -// CHECK: mrs x0, ich_lr8_el2 // encoding: [0x00,0xcd,0x3c,0xd5] -// CHECK: mrs x21, ich_lr9_el2 // encoding: [0x35,0xcd,0x3c,0xd5] -// CHECK: mrs x13, ich_lr10_el2 // encoding: [0x4d,0xcd,0x3c,0xd5] -// CHECK: mrs x26, ich_lr11_el2 // encoding: [0x7a,0xcd,0x3c,0xd5] -// CHECK: mrs x1, ich_lr12_el2 // encoding: [0x81,0xcd,0x3c,0xd5] -// CHECK: mrs x8, ich_lr13_el2 // encoding: [0xa8,0xcd,0x3c,0xd5] -// CHECK: mrs x2, ich_lr14_el2 // encoding: [0xc2,0xcd,0x3c,0xd5] -// CHECK: mrs x8, ich_lr15_el2 // encoding: [0xe8,0xcd,0x3c,0xd5] +// CHECK: mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}} // encoding: [0x08,0xcc,0x38,0xd5] +// CHECK: mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}} // encoding: [0x1a,0xc8,0x38,0xd5] +// CHECK: mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}} // encoding: [0x42,0xcc,0x38,0xd5] +// CHECK: mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}} // encoding: [0x51,0xc8,0x38,0xd5] +// CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}} // encoding: [0x7d,0xcb,0x38,0xd5] +// CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}} // encoding: [0x24,0xcb,0x3c,0xd5] +// CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}} // encoding: [0x78,0xcb,0x3c,0xd5] +// CHECK: mrs x9, {{ich_elsr_el2|ICH_ELSR_EL2}} // encoding: [0xa9,0xcb,0x3c,0xd5] +// CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}} // encoding: [0x78,0xcc,0x38,0xd5] +// CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}} // encoding: [0x6e,0xc8,0x38,0xd5] +// CHECK: mrs x19, {{icc_pmr_el1|ICC_PMR_EL1}} // encoding: [0x13,0x46,0x38,0xd5] +// CHECK: mrs x23, {{icc_ctlr_el1|ICC_CTLR_EL1}} // encoding: [0x97,0xcc,0x38,0xd5] +// CHECK: mrs x20, {{icc_ctlr_el3|ICC_CTLR_EL3}} // encoding: [0x94,0xcc,0x3e,0xd5] +// CHECK: mrs x28, {{icc_sre_el1|ICC_SRE_EL1}} // encoding: [0xbc,0xcc,0x38,0xd5] +// CHECK: mrs x25, {{icc_sre_el2|ICC_SRE_EL2}} // encoding: [0xb9,0xc9,0x3c,0xd5] +// CHECK: mrs x8, {{icc_sre_el3|ICC_SRE_EL3}} // encoding: [0xa8,0xcc,0x3e,0xd5] +// CHECK: mrs x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}} // encoding: [0xd6,0xcc,0x38,0xd5] +// CHECK: mrs x5, {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}} // encoding: [0xe5,0xcc,0x38,0xd5] +// CHECK: mrs x7, {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}} // encoding: [0xe7,0xcc,0x3e,0xd5] +// CHECK: mrs x22, {{icc_seien_el1|ICC_SEIEN_EL1}} // encoding: [0x16,0xcd,0x38,0xd5] +// CHECK: mrs x4, {{icc_ap0r0_el1|ICC_AP0R0_EL1}} // encoding: [0x84,0xc8,0x38,0xd5] +// CHECK: mrs x11, {{icc_ap0r1_el1|ICC_AP0R1_EL1}} // encoding: [0xab,0xc8,0x38,0xd5] +// CHECK: mrs x27, {{icc_ap0r2_el1|ICC_AP0R2_EL1}} // encoding: [0xdb,0xc8,0x38,0xd5] +// CHECK: mrs x21, {{icc_ap0r3_el1|ICC_AP0R3_EL1}} // encoding: [0xf5,0xc8,0x38,0xd5] +// CHECK: mrs x2, {{icc_ap1r0_el1|ICC_AP1R0_EL1}} // encoding: [0x02,0xc9,0x38,0xd5] +// CHECK: mrs x21, {{icc_ap1r1_el1|ICC_AP1R1_EL1}} // encoding: [0x35,0xc9,0x38,0xd5] +// CHECK: mrs x10, {{icc_ap1r2_el1|ICC_AP1R2_EL1}} // encoding: [0x4a,0xc9,0x38,0xd5] +// CHECK: mrs x27, {{icc_ap1r3_el1|ICC_AP1R3_EL1}} // encoding: [0x7b,0xc9,0x38,0xd5] +// CHECK: mrs x20, {{ich_ap0r0_el2|ICH_AP0R0_EL2}} // encoding: [0x14,0xc8,0x3c,0xd5] +// CHECK: mrs x21, {{ich_ap0r1_el2|ICH_AP0R1_EL2}} // encoding: [0x35,0xc8,0x3c,0xd5] +// CHECK: mrs x5, {{ich_ap0r2_el2|ICH_AP0R2_EL2}} // encoding: [0x45,0xc8,0x3c,0xd5] +// CHECK: mrs x4, {{ich_ap0r3_el2|ICH_AP0R3_EL2}} // encoding: [0x64,0xc8,0x3c,0xd5] +// CHECK: mrs x15, {{ich_ap1r0_el2|ICH_AP1R0_EL2}} // encoding: [0x0f,0xc9,0x3c,0xd5] +// CHECK: mrs x12, {{ich_ap1r1_el2|ICH_AP1R1_EL2}} // encoding: [0x2c,0xc9,0x3c,0xd5] +// CHECK: mrs x27, {{ich_ap1r2_el2|ICH_AP1R2_EL2}} // encoding: [0x5b,0xc9,0x3c,0xd5] +// CHECK: mrs x20, {{ich_ap1r3_el2|ICH_AP1R3_EL2}} // encoding: [0x74,0xc9,0x3c,0xd5] +// CHECK: mrs x10, {{ich_hcr_el2|ICH_HCR_EL2}} // encoding: [0x0a,0xcb,0x3c,0xd5] +// CHECK: mrs x27, {{ich_misr_el2|ICH_MISR_EL2}} // encoding: [0x5b,0xcb,0x3c,0xd5] +// CHECK: mrs x6, {{ich_vmcr_el2|ICH_VMCR_EL2}} // encoding: [0xe6,0xcb,0x3c,0xd5] +// CHECK: mrs x19, {{ich_vseir_el2|ICH_VSEIR_EL2}} // encoding: [0x93,0xc9,0x3c,0xd5] +// CHECK: mrs x3, {{ich_lr0_el2|ICH_LR0_EL2}} // encoding: [0x03,0xcc,0x3c,0xd5] +// CHECK: mrs x1, {{ich_lr1_el2|ICH_LR1_EL2}} // encoding: [0x21,0xcc,0x3c,0xd5] +// CHECK: mrs x22, {{ich_lr2_el2|ICH_LR2_EL2}} // encoding: [0x56,0xcc,0x3c,0xd5] +// CHECK: mrs x21, {{ich_lr3_el2|ICH_LR3_EL2}} // encoding: [0x75,0xcc,0x3c,0xd5] +// CHECK: mrs x6, {{ich_lr4_el2|ICH_LR4_EL2}} // encoding: [0x86,0xcc,0x3c,0xd5] +// CHECK: mrs x10, {{ich_lr5_el2|ICH_LR5_EL2}} // encoding: [0xaa,0xcc,0x3c,0xd5] +// CHECK: mrs x11, {{ich_lr6_el2|ICH_LR6_EL2}} // encoding: [0xcb,0xcc,0x3c,0xd5] +// CHECK: mrs x12, {{ich_lr7_el2|ICH_LR7_EL2}} // encoding: [0xec,0xcc,0x3c,0xd5] +// CHECK: mrs x0, {{ich_lr8_el2|ICH_LR8_EL2}} // encoding: [0x00,0xcd,0x3c,0xd5] +// CHECK: mrs x21, {{ich_lr9_el2|ICH_LR9_EL2}} // encoding: [0x35,0xcd,0x3c,0xd5] +// CHECK: mrs x13, {{ich_lr10_el2|ICH_LR10_EL2}} // encoding: [0x4d,0xcd,0x3c,0xd5] +// CHECK: mrs x26, {{ich_lr11_el2|ICH_LR11_EL2}} // encoding: [0x7a,0xcd,0x3c,0xd5] +// CHECK: mrs x1, {{ich_lr12_el2|ICH_LR12_EL2}} // encoding: [0x81,0xcd,0x3c,0xd5] +// CHECK: mrs x8, {{ich_lr13_el2|ICH_LR13_EL2}} // encoding: [0xa8,0xcd,0x3c,0xd5] +// CHECK: mrs x2, {{ich_lr14_el2|ICH_LR14_EL2}} // encoding: [0xc2,0xcd,0x3c,0xd5] +// CHECK: mrs x8, {{ich_lr15_el2|ICH_LR15_EL2}} // encoding: [0xe8,0xcd,0x3c,0xd5] msr icc_eoir1_el1, x27 msr icc_eoir0_el1, x5 @@ -167,57 +167,57 @@ msr ich_lr13_el2, x2 msr ich_lr14_el2, x13 msr ich_lr15_el2, x27 -// CHECK: msr icc_eoir1_el1, x27 // encoding: [0x3b,0xcc,0x18,0xd5] -// CHECK: msr icc_eoir0_el1, x5 // encoding: [0x25,0xc8,0x18,0xd5] -// CHECK: msr icc_dir_el1, x13 // encoding: [0x2d,0xcb,0x18,0xd5] -// CHECK: msr icc_sgi1r_el1, x21 // encoding: [0xb5,0xcb,0x18,0xd5] -// CHECK: msr icc_asgi1r_el1, x25 // encoding: [0xd9,0xcb,0x18,0xd5] -// CHECK: msr icc_sgi0r_el1, x28 // encoding: [0xfc,0xcb,0x18,0xd5] -// CHECK: msr icc_bpr1_el1, x7 // encoding: [0x67,0xcc,0x18,0xd5] -// CHECK: msr icc_bpr0_el1, x9 // encoding: [0x69,0xc8,0x18,0xd5] -// CHECK: msr icc_pmr_el1, x29 // encoding: [0x1d,0x46,0x18,0xd5] -// CHECK: msr icc_ctlr_el1, x24 // encoding: [0x98,0xcc,0x18,0xd5] -// CHECK: msr icc_ctlr_el3, x0 // encoding: [0x80,0xcc,0x1e,0xd5] -// CHECK: msr icc_sre_el1, x2 // encoding: [0xa2,0xcc,0x18,0xd5] -// CHECK: msr icc_sre_el2, x5 // encoding: [0xa5,0xc9,0x1c,0xd5] -// CHECK: msr icc_sre_el3, x10 // encoding: [0xaa,0xcc,0x1e,0xd5] -// CHECK: msr icc_igrpen0_el1, x22 // encoding: [0xd6,0xcc,0x18,0xd5] -// CHECK: msr icc_igrpen1_el1, x11 // encoding: [0xeb,0xcc,0x18,0xd5] -// CHECK: msr icc_igrpen1_el3, x8 // encoding: [0xe8,0xcc,0x1e,0xd5] -// CHECK: msr icc_seien_el1, x4 // encoding: [0x04,0xcd,0x18,0xd5] -// CHECK: msr icc_ap0r0_el1, x27 // encoding: [0x9b,0xc8,0x18,0xd5] -// CHECK: msr icc_ap0r1_el1, x5 // encoding: [0xa5,0xc8,0x18,0xd5] -// CHECK: msr icc_ap0r2_el1, x20 // encoding: [0xd4,0xc8,0x18,0xd5] -// CHECK: msr icc_ap0r3_el1, x0 // encoding: [0xe0,0xc8,0x18,0xd5] -// CHECK: msr icc_ap1r0_el1, x2 // encoding: [0x02,0xc9,0x18,0xd5] -// CHECK: msr icc_ap1r1_el1, x29 // encoding: [0x3d,0xc9,0x18,0xd5] -// CHECK: msr icc_ap1r2_el1, x23 // encoding: [0x57,0xc9,0x18,0xd5] -// CHECK: msr icc_ap1r3_el1, x11 // encoding: [0x6b,0xc9,0x18,0xd5] -// CHECK: msr ich_ap0r0_el2, x2 // encoding: [0x02,0xc8,0x1c,0xd5] -// CHECK: msr ich_ap0r1_el2, x27 // encoding: [0x3b,0xc8,0x1c,0xd5] -// CHECK: msr ich_ap0r2_el2, x7 // encoding: [0x47,0xc8,0x1c,0xd5] -// CHECK: msr ich_ap0r3_el2, x1 // encoding: [0x61,0xc8,0x1c,0xd5] -// CHECK: msr ich_ap1r0_el2, x7 // encoding: [0x07,0xc9,0x1c,0xd5] -// CHECK: msr ich_ap1r1_el2, x12 // encoding: [0x2c,0xc9,0x1c,0xd5] -// CHECK: msr ich_ap1r2_el2, x14 // encoding: [0x4e,0xc9,0x1c,0xd5] -// CHECK: msr ich_ap1r3_el2, x13 // encoding: [0x6d,0xc9,0x1c,0xd5] -// CHECK: msr ich_hcr_el2, x1 // encoding: [0x01,0xcb,0x1c,0xd5] -// CHECK: msr ich_misr_el2, x10 // encoding: [0x4a,0xcb,0x1c,0xd5] -// CHECK: msr ich_vmcr_el2, x24 // encoding: [0xf8,0xcb,0x1c,0xd5] -// CHECK: msr ich_vseir_el2, x29 // encoding: [0x9d,0xc9,0x1c,0xd5] -// CHECK: msr ich_lr0_el2, x26 // encoding: [0x1a,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr1_el2, x9 // encoding: [0x29,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr2_el2, x18 // encoding: [0x52,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr3_el2, x26 // encoding: [0x7a,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr4_el2, x22 // encoding: [0x96,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr5_el2, x26 // encoding: [0xba,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr6_el2, x27 // encoding: [0xdb,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr7_el2, x8 // encoding: [0xe8,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr8_el2, x17 // encoding: [0x11,0xcd,0x1c,0xd5] -// CHECK: msr ich_lr9_el2, x19 // encoding: [0x33,0xcd,0x1c,0xd5] -// CHECK: msr ich_lr10_el2, x17 // encoding: [0x51,0xcd,0x1c,0xd5] -// CHECK: msr ich_lr11_el2, x5 // encoding: [0x65,0xcd,0x1c,0xd5] -// CHECK: msr ich_lr12_el2, x29 // encoding: [0x9d,0xcd,0x1c,0xd5] -// CHECK: msr ich_lr13_el2, x2 // encoding: [0xa2,0xcd,0x1c,0xd5] -// CHECK: msr ich_lr14_el2, x13 // encoding: [0xcd,0xcd,0x1c,0xd5] -// CHECK: msr ich_lr15_el2, x27 // encoding: [0xfb,0xcd,0x1c,0xd5] +// CHECK: msr {{icc_eoir1_el1|ICC_EOIR1_EL1}}, x27 // encoding: [0x3b,0xcc,0x18,0xd5] +// CHECK: msr {{icc_eoir0_el1|ICC_EOIR0_EL1}}, x5 // encoding: [0x25,0xc8,0x18,0xd5] +// CHECK: msr {{icc_dir_el1|ICC_DIR_EL1}}, x13 // encoding: [0x2d,0xcb,0x18,0xd5] +// CHECK: msr {{icc_sgi1r_el1|ICC_SGI1R_EL1}}, x21 // encoding: [0xb5,0xcb,0x18,0xd5] +// CHECK: msr {{icc_asgi1r_el1|ICC_ASGI1R_EL1}}, x25 // encoding: [0xd9,0xcb,0x18,0xd5] +// CHECK: msr {{icc_sgi0r_el1|ICC_SGI0R_EL1}}, x28 // encoding: [0xfc,0xcb,0x18,0xd5] +// CHECK: msr {{icc_bpr1_el1|ICC_BPR1_EL1}}, x7 // encoding: [0x67,0xcc,0x18,0xd5] +// CHECK: msr {{icc_bpr0_el1|ICC_BPR0_EL1}}, x9 // encoding: [0x69,0xc8,0x18,0xd5] +// CHECK: msr {{icc_pmr_el1|ICC_PMR_EL1}}, x29 // encoding: [0x1d,0x46,0x18,0xd5] +// CHECK: msr {{icc_ctlr_el1|ICC_CTLR_EL1}}, x24 // encoding: [0x98,0xcc,0x18,0xd5] +// CHECK: msr {{icc_ctlr_el3|ICC_CTLR_EL3}}, x0 // encoding: [0x80,0xcc,0x1e,0xd5] +// CHECK: msr {{icc_sre_el1|ICC_SRE_EL1}}, x2 // encoding: [0xa2,0xcc,0x18,0xd5] +// CHECK: msr {{icc_sre_el2|ICC_SRE_EL2}}, x5 // encoding: [0xa5,0xc9,0x1c,0xd5] +// CHECK: msr {{icc_sre_el3|ICC_SRE_EL3}}, x10 // encoding: [0xaa,0xcc,0x1e,0xd5] +// CHECK: msr {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22 // encoding: [0xd6,0xcc,0x18,0xd5] +// CHECK: msr {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x11 // encoding: [0xeb,0xcc,0x18,0xd5] +// CHECK: msr {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x8 // encoding: [0xe8,0xcc,0x1e,0xd5] +// CHECK: msr {{icc_seien_el1|ICC_SEIEN_EL1}}, x4 // encoding: [0x04,0xcd,0x18,0xd5] +// CHECK: msr {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x27 // encoding: [0x9b,0xc8,0x18,0xd5] +// CHECK: msr {{icc_ap0r1_el1|ICC_AP0R1_EL1}}, x5 // encoding: [0xa5,0xc8,0x18,0xd5] +// CHECK: msr {{icc_ap0r2_el1|ICC_AP0R2_EL1}}, x20 // encoding: [0xd4,0xc8,0x18,0xd5] +// CHECK: msr {{icc_ap0r3_el1|ICC_AP0R3_EL1}}, x0 // encoding: [0xe0,0xc8,0x18,0xd5] +// CHECK: msr {{icc_ap1r0_el1|ICC_AP1R0_EL1}}, x2 // encoding: [0x02,0xc9,0x18,0xd5] +// CHECK: msr {{icc_ap1r1_el1|ICC_AP1R1_EL1}}, x29 // encoding: [0x3d,0xc9,0x18,0xd5] +// CHECK: msr {{icc_ap1r2_el1|ICC_AP1R2_EL1}}, x23 // encoding: [0x57,0xc9,0x18,0xd5] +// CHECK: msr {{icc_ap1r3_el1|ICC_AP1R3_EL1}}, x11 // encoding: [0x6b,0xc9,0x18,0xd5] +// CHECK: msr {{ich_ap0r0_el2|ICH_AP0R0_EL2}}, x2 // encoding: [0x02,0xc8,0x1c,0xd5] +// CHECK: msr {{ich_ap0r1_el2|ICH_AP0R1_EL2}}, x27 // encoding: [0x3b,0xc8,0x1c,0xd5] +// CHECK: msr {{ich_ap0r2_el2|ICH_AP0R2_EL2}}, x7 // encoding: [0x47,0xc8,0x1c,0xd5] +// CHECK: msr {{ich_ap0r3_el2|ICH_AP0R3_EL2}}, x1 // encoding: [0x61,0xc8,0x1c,0xd5] +// CHECK: msr {{ich_ap1r0_el2|ICH_AP1R0_EL2}}, x7 // encoding: [0x07,0xc9,0x1c,0xd5] +// CHECK: msr {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x12 // encoding: [0x2c,0xc9,0x1c,0xd5] +// CHECK: msr {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14 // encoding: [0x4e,0xc9,0x1c,0xd5] +// CHECK: msr {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13 // encoding: [0x6d,0xc9,0x1c,0xd5] +// CHECK: msr {{ich_hcr_el2|ICH_HCR_EL2}}, x1 // encoding: [0x01,0xcb,0x1c,0xd5] +// CHECK: msr {{ich_misr_el2|ICH_MISR_EL2}}, x10 // encoding: [0x4a,0xcb,0x1c,0xd5] +// CHECK: msr {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24 // encoding: [0xf8,0xcb,0x1c,0xd5] +// CHECK: msr {{ich_vseir_el2|ICH_VSEIR_EL2}}, x29 // encoding: [0x9d,0xc9,0x1c,0xd5] +// CHECK: msr {{ich_lr0_el2|ICH_LR0_EL2}}, x26 // encoding: [0x1a,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr1_el2|ICH_LR1_EL2}}, x9 // encoding: [0x29,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr2_el2|ICH_LR2_EL2}}, x18 // encoding: [0x52,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr3_el2|ICH_LR3_EL2}}, x26 // encoding: [0x7a,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr4_el2|ICH_LR4_EL2}}, x22 // encoding: [0x96,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr5_el2|ICH_LR5_EL2}}, x26 // encoding: [0xba,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr6_el2|ICH_LR6_EL2}}, x27 // encoding: [0xdb,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr7_el2|ICH_LR7_EL2}}, x8 // encoding: [0xe8,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr8_el2|ICH_LR8_EL2}}, x17 // encoding: [0x11,0xcd,0x1c,0xd5] +// CHECK: msr {{ich_lr9_el2|ICH_LR9_EL2}}, x19 // encoding: [0x33,0xcd,0x1c,0xd5] +// CHECK: msr {{ich_lr10_el2|ICH_LR10_EL2}}, x17 // encoding: [0x51,0xcd,0x1c,0xd5] +// CHECK: msr {{ich_lr11_el2|ICH_LR11_EL2}}, x5 // encoding: [0x65,0xcd,0x1c,0xd5] +// CHECK: msr {{ich_lr12_el2|ICH_LR12_EL2}}, x29 // encoding: [0x9d,0xcd,0x1c,0xd5] +// CHECK: msr {{ich_lr13_el2|ICH_LR13_EL2}}, x2 // encoding: [0xa2,0xcd,0x1c,0xd5] +// CHECK: msr {{ich_lr14_el2|ICH_LR14_EL2}}, x13 // encoding: [0xcd,0xcd,0x1c,0xd5] +// CHECK: msr {{ich_lr15_el2|ICH_LR15_EL2}}, x27 // encoding: [0xfb,0xcd,0x1c,0xd5] diff --git a/test/MC/AArch64/lit.local.cfg b/test/MC/AArch64/lit.local.cfg index 75dba81..1be70c0 100644 --- a/test/MC/AArch64/lit.local.cfg +++ b/test/MC/AArch64/lit.local.cfg @@ -1,3 +1,3 @@ targets = set(config.root.targets_to_build.split()) -if not 'AArch64' in targets: - config.unsupported = True
\ No newline at end of file +if 'AArch64' not in targets: + config.unsupported = True diff --git a/test/MC/AArch64/neon-2velem.s b/test/MC/AArch64/neon-2velem.s index cde792a..04841d0 100644 --- a/test/MC/AArch64/neon-2velem.s +++ b/test/MC/AArch64/neon-2velem.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/test/MC/AArch64/neon-3vdiff.s b/test/MC/AArch64/neon-3vdiff.s index 3ff86bf..fc3215b 100644 --- a/test/MC/AArch64/neon-3vdiff.s +++ b/test/MC/AArch64/neon-3vdiff.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+crypto -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/test/MC/AArch64/neon-across.s b/test/MC/AArch64/neon-across.s index 8b1c2d4..60b766d 100644 --- a/test/MC/AArch64/neon-across.s +++ b/test/MC/AArch64/neon-across.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/test/MC/AArch64/neon-compare-instructions.s b/test/MC/AArch64/neon-compare-instructions.s index d4e3ef5..19cfaf1 100644 --- a/test/MC/AArch64/neon-compare-instructions.s +++ b/test/MC/AArch64/neon-compare-instructions.s @@ -255,13 +255,13 @@ cmeq v9.4s, v7.4s, #0 cmeq v3.2d, v31.2d, #0 -// CHECK: cmeq v0.8b, v15.8b, #0x0 // encoding: [0xe0,0x99,0x20,0x0e] -// CHECK: cmeq v1.16b, v31.16b, #0x0 // encoding: [0xe1,0x9b,0x20,0x4e] -// CHECK: cmeq v15.4h, v16.4h, #0x0 // encoding: [0x0f,0x9a,0x60,0x0e] -// CHECK: cmeq v5.8h, v6.8h, #0x0 // encoding: [0xc5,0x98,0x60,0x4e] -// CHECK: cmeq v29.2s, v27.2s, #0x0 // encoding: [0x7d,0x9b,0xa0,0x0e] -// CHECK: cmeq v9.4s, v7.4s, #0x0 // encoding: [0xe9,0x98,0xa0,0x4e] -// CHECK: cmeq v3.2d, v31.2d, #0x0 // encoding: [0xe3,0x9b,0xe0,0x4e] +// CHECK: cmeq v0.8b, v15.8b, #{{0x0|0}} // encoding: [0xe0,0x99,0x20,0x0e] +// CHECK: cmeq v1.16b, v31.16b, #{{0x0|0}} // encoding: [0xe1,0x9b,0x20,0x4e] +// CHECK: cmeq v15.4h, v16.4h, #{{0x0|0}} // encoding: [0x0f,0x9a,0x60,0x0e] +// CHECK: cmeq v5.8h, v6.8h, #{{0x0|0}} // encoding: [0xc5,0x98,0x60,0x4e] +// CHECK: cmeq v29.2s, v27.2s, #{{0x0|0}} // encoding: [0x7d,0x9b,0xa0,0x0e] +// CHECK: cmeq v9.4s, v7.4s, #{{0x0|0}} // encoding: [0xe9,0x98,0xa0,0x4e] +// CHECK: cmeq v3.2d, v31.2d, #{{0x0|0}} // encoding: [0xe3,0x9b,0xe0,0x4e] //---------------------------------------------------------------------- // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer) @@ -274,13 +274,13 @@ cmge v17.4s, v20.4s, #0 cmge v3.2d, v31.2d, #0 -// CHECK: cmge v0.8b, v15.8b, #0x0 // encoding: [0xe0,0x89,0x20,0x2e] -// CHECK: cmge v1.16b, v31.16b, #0x0 // encoding: [0xe1,0x8b,0x20,0x6e] -// CHECK: cmge v15.4h, v16.4h, #0x0 // encoding: [0x0f,0x8a,0x60,0x2e] -// CHECK: cmge v5.8h, v6.8h, #0x0 // encoding: [0xc5,0x88,0x60,0x6e] -// CHECK: cmge v29.2s, v27.2s, #0x0 // encoding: [0x7d,0x8b,0xa0,0x2e] -// CHECK: cmge v17.4s, v20.4s, #0x0 // encoding: [0x91,0x8a,0xa0,0x6e] -// CHECK: cmge v3.2d, v31.2d, #0x0 // encoding: [0xe3,0x8b,0xe0,0x6e] +// CHECK: cmge v0.8b, v15.8b, #{{0x0|0}} // encoding: [0xe0,0x89,0x20,0x2e] +// CHECK: cmge v1.16b, v31.16b, #{{0x0|0}} // encoding: [0xe1,0x8b,0x20,0x6e] +// CHECK: cmge v15.4h, v16.4h, #{{0x0|0}} // encoding: [0x0f,0x8a,0x60,0x2e] +// CHECK: cmge v5.8h, v6.8h, #{{0x0|0}} // encoding: [0xc5,0x88,0x60,0x6e] +// CHECK: cmge v29.2s, v27.2s, #{{0x0|0}} // encoding: [0x7d,0x8b,0xa0,0x2e] +// CHECK: cmge v17.4s, v20.4s, #{{0x0|0}} // encoding: [0x91,0x8a,0xa0,0x6e] +// CHECK: cmge v3.2d, v31.2d, #{{0x0|0}} // encoding: [0xe3,0x8b,0xe0,0x6e] //---------------------------------------------------------------------- // Vector Compare Mask Greater Than Zero (Signed Integer) @@ -294,13 +294,13 @@ cmgt v9.4s, v7.4s, #0 cmgt v3.2d, v31.2d, #0 -// CHECK: cmgt v0.8b, v15.8b, #0x0 // encoding: [0xe0,0x89,0x20,0x0e] -// CHECK: cmgt v1.16b, v31.16b, #0x0 // encoding: [0xe1,0x8b,0x20,0x4e] -// CHECK: cmgt v15.4h, v16.4h, #0x0 // encoding: [0x0f,0x8a,0x60,0x0e] -// CHECK: cmgt v5.8h, v6.8h, #0x0 // encoding: [0xc5,0x88,0x60,0x4e] -// CHECK: cmgt v29.2s, v27.2s, #0x0 // encoding: [0x7d,0x8b,0xa0,0x0e] -// CHECK: cmgt v9.4s, v7.4s, #0x0 // encoding: [0xe9,0x88,0xa0,0x4e] -// CHECK: cmgt v3.2d, v31.2d, #0x0 // encoding: [0xe3,0x8b,0xe0,0x4e] +// CHECK: cmgt v0.8b, v15.8b, #{{0x0|0}} // encoding: [0xe0,0x89,0x20,0x0e] +// CHECK: cmgt v1.16b, v31.16b, #{{0x0|0}} // encoding: [0xe1,0x8b,0x20,0x4e] +// CHECK: cmgt v15.4h, v16.4h, #{{0x0|0}} // encoding: [0x0f,0x8a,0x60,0x0e] +// CHECK: cmgt v5.8h, v6.8h, #{{0x0|0}} // encoding: [0xc5,0x88,0x60,0x4e] +// CHECK: cmgt v29.2s, v27.2s, #{{0x0|0}} // encoding: [0x7d,0x8b,0xa0,0x0e] +// CHECK: cmgt v9.4s, v7.4s, #{{0x0|0}} // encoding: [0xe9,0x88,0xa0,0x4e] +// CHECK: cmgt v3.2d, v31.2d, #{{0x0|0}} // encoding: [0xe3,0x8b,0xe0,0x4e] //---------------------------------------------------------------------- // Vector Compare Mask Less Than or Equal To Zero (Signed Integer) @@ -313,13 +313,13 @@ cmle v9.4s, v7.4s, #0 cmle v3.2d, v31.2d, #0 -// CHECK: cmle v0.8b, v15.8b, #0x0 // encoding: [0xe0,0x99,0x20,0x2e] -// CHECK: cmle v1.16b, v31.16b, #0x0 // encoding: [0xe1,0x9b,0x20,0x6e] -// CHECK: cmle v15.4h, v16.4h, #0x0 // encoding: [0x0f,0x9a,0x60,0x2e] -// CHECK: cmle v5.8h, v6.8h, #0x0 // encoding: [0xc5,0x98,0x60,0x6e] -// CHECK: cmle v29.2s, v27.2s, #0x0 // encoding: [0x7d,0x9b,0xa0,0x2e] -// CHECK: cmle v9.4s, v7.4s, #0x0 // encoding: [0xe9,0x98,0xa0,0x6e] -// CHECK: cmle v3.2d, v31.2d, #0x0 // encoding: [0xe3,0x9b,0xe0,0x6e] +// CHECK: cmle v0.8b, v15.8b, #{{0x0|0}} // encoding: [0xe0,0x99,0x20,0x2e] +// CHECK: cmle v1.16b, v31.16b, #{{0x0|0}} // encoding: [0xe1,0x9b,0x20,0x6e] +// CHECK: cmle v15.4h, v16.4h, #{{0x0|0}} // encoding: [0x0f,0x9a,0x60,0x2e] +// CHECK: cmle v5.8h, v6.8h, #{{0x0|0}} // encoding: [0xc5,0x98,0x60,0x6e] +// CHECK: cmle v29.2s, v27.2s, #{{0x0|0}} // encoding: [0x7d,0x9b,0xa0,0x2e] +// CHECK: cmle v9.4s, v7.4s, #{{0x0|0}} // encoding: [0xe9,0x98,0xa0,0x6e] +// CHECK: cmle v3.2d, v31.2d, #{{0x0|0}} // encoding: [0xe3,0x9b,0xe0,0x6e] //---------------------------------------------------------------------- // Vector Compare Mask Less Than Zero (Signed Integer) @@ -332,13 +332,13 @@ cmlt v9.4s, v7.4s, #0 cmlt v3.2d, v31.2d, #0 -// CHECK: cmlt v0.8b, v15.8b, #0x0 // encoding: [0xe0,0xa9,0x20,0x0e] -// CHECK: cmlt v1.16b, v31.16b, #0x0 // encoding: [0xe1,0xab,0x20,0x4e] -// CHECK: cmlt v15.4h, v16.4h, #0x0 // encoding: [0x0f,0xaa,0x60,0x0e] -// CHECK: cmlt v5.8h, v6.8h, #0x0 // encoding: [0xc5,0xa8,0x60,0x4e] -// CHECK: cmlt v29.2s, v27.2s, #0x0 // encoding: [0x7d,0xab,0xa0,0x0e] -// CHECK: cmlt v9.4s, v7.4s, #0x0 // encoding: [0xe9,0xa8,0xa0,0x4e] -// CHECK: cmlt v3.2d, v31.2d, #0x0 // encoding: [0xe3,0xab,0xe0,0x4e] +// CHECK: cmlt v0.8b, v15.8b, #{{0x0|0}} // encoding: [0xe0,0xa9,0x20,0x0e] +// CHECK: cmlt v1.16b, v31.16b, #{{0x0|0}} // encoding: [0xe1,0xab,0x20,0x4e] +// CHECK: cmlt v15.4h, v16.4h, #{{0x0|0}} // encoding: [0x0f,0xaa,0x60,0x0e] +// CHECK: cmlt v5.8h, v6.8h, #{{0x0|0}} // encoding: [0xc5,0xa8,0x60,0x4e] +// CHECK: cmlt v29.2s, v27.2s, #{{0x0|0}} // encoding: [0x7d,0xab,0xa0,0x0e] +// CHECK: cmlt v9.4s, v7.4s, #{{0x0|0}} // encoding: [0xe9,0xa8,0xa0,0x4e] +// CHECK: cmlt v3.2d, v31.2d, #{{0x0|0}} // encoding: [0xe3,0xab,0xe0,0x4e] //---------------------------------------------------------------------- // Vector Compare Mask Equal to Zero (Floating Point) diff --git a/test/MC/AArch64/neon-crypto.s b/test/MC/AArch64/neon-crypto.s index 2952dd5..ed1bf88 100644 --- a/test/MC/AArch64/neon-crypto.s +++ b/test/MC/AArch64/neon-crypto.s @@ -1,5 +1,5 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -mattr=+crypto -show-encoding < %s | FileCheck %s -// RUN: not llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s 2>&1 | FileCheck -check-prefix=CHECK-NO-CRYPTO %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -mattr=+crypto -show-encoding < %s | FileCheck %s +// RUN: not llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s 2>&1 | FileCheck -check-prefix=CHECK-NO-CRYPTO-ARM64 %s // Check that the assembler can handle the documented syntax for AArch64 @@ -13,6 +13,7 @@ aesimc v0.16b, v1.16b // CHECK-NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +// CHECK-NO-CRYPTO-ARM64: error: instruction requires: crypto // CHECK: aese v0.16b, v1.16b // encoding: [0x20,0x48,0x28,0x4e] // CHECK: aesd v0.16b, v1.16b // encoding: [0x20,0x58,0x28,0x4e] // CHECK: aesmc v0.16b, v1.16b // encoding: [0x20,0x68,0x28,0x4e] diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s index aa08857..fa1f3ca 100644 --- a/test/MC/AArch64/neon-diagnostics.s +++ b/test/MC/AArch64/neon-diagnostics.s @@ -587,10 +587,11 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmgt v0.2d, v31.2s, v16.2s // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected floating-point constant #0.0 or invalid register type + +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmgt v4.4s, v7.4s, v15.4h // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected floating-point constant #0.0 or invalid register type +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmlt v29.2d, v5.2d, v2.16b // CHECK-ERROR: ^ @@ -680,12 +681,15 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmeq v0.16b, v1.16b, #0.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate + + +// CHECK-ERROR: error: expected floating-point constant #0.0 // CHECK-ERROR: fcmeq v0.8b, v1.4h, #1.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmeq v0.8b, v1.4h, #1 // CHECK-ERROR: ^ + //---------------------------------------------------------------------- // Vector Compare Mask Greater Than or Equal to Zero (Floating Point) //---------------------------------------------------------------------- @@ -702,12 +706,15 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmge v3.8b, v8.2s, #0.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate + + +// CHECK-ERROR: error: expected floating-point constant #0.0 // CHECK-ERROR: fcmle v17.8h, v15.2d, #-1.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmle v17.8h, v15.2d, #2 // CHECK-ERROR: ^ + //---------------------------------------------------------------------- // Vector Compare Mask Greater Than Zero (Floating Point) //---------------------------------------------------------------------- @@ -723,10 +730,12 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmgt v4.4s, v7.4h, #0.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate + + +// CHECK-ERROR: error: expected floating-point constant #0.0 // CHECK-ERROR: fcmlt v29.2d, v5.2d, #255.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmlt v29.2d, v5.2d, #255 // CHECK-ERROR: ^ @@ -745,10 +754,12 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmge v3.8b, v8.2s, #0.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate + + +// CHECK-ERROR: error: expected floating-point constant #0.0 // CHECK-ERROR: fcmle v17.2d, v15.2d, #15.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmle v17.2d, v15.2d, #15 // CHECK-ERROR: ^ @@ -767,10 +778,12 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmgt v4.4s, v7.4h, #0.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate + + +// CHECK-ERROR: error: expected floating-point constant #0.0 // CHECK-ERROR: fcmlt v29.2d, v5.2d, #16.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmlt v29.2d, v5.2d, #2 // CHECK-ERROR: ^ @@ -1285,22 +1298,24 @@ shl v0.4s, v21.4s, #32 shl v0.2d, v1.2d, #64 -// CHECK-ERROR: error: expected comma before next operand + +// CHECK-ERROR: error: unexpected token in argument list // CHECK-ERROR: shl v0.4s, v15,2s, #3 // CHECK-ERROR: ^ + // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: shl v0.2d, v17.4s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: shl v0.8b, v31.8b, #-1 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: shl v0.8b, v31.8b, #8 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: shl v0.4s, v21.4s, #32 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: shl v0.2d, v1.2d, #64 // CHECK-ERROR: ^ @@ -1334,25 +1349,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ushll2 v1.4s, v25.4s, #7 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sshll v0.8h, v1.8b, #-1 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sshll v0.8h, v1.8b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: ushll v0.4s, v1.4h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: ushll v0.2d, v1.2s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sshll2 v0.8h, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: sshll2 v0.4s, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: ushll2 v0.2d, v1.4s, #33 // CHECK-ERROR: ^ @@ -1377,16 +1392,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sshr v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sshr v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sshr v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sshr v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: sshr v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1410,16 +1425,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ushr v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: ushr v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: ushr v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: ushr v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ushr v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1443,16 +1458,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ssra v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: ssra v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: ssra v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: ssra v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ssra v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1476,16 +1491,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: usra v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: usra v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: usra v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: usra v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: usra v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1509,16 +1524,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: srshr v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: srshr v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: srshr v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: srshr v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: srshr v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1542,16 +1557,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: urshr v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: urshr v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: urshr v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: urshr v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: urshr v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1575,16 +1590,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: srsra v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: srsra v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: srsra v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: srsra v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: srsra v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1608,16 +1623,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ursra v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: ursra v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: ursra v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: ursra v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ursra v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1641,16 +1656,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sri v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sri v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sri v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sri v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: sri v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1674,16 +1689,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sli v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sli v0.16b, v1.16b, #8 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: sli v0.8h, v1.8h, #16 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: sli v0.4s, v1.4s, #32 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: sli v0.2d, v1.2d, #64 // CHECK-ERROR: ^ @@ -1707,16 +1722,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqshlu v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sqshlu v0.16b, v1.16b, #8 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: sqshlu v0.8h, v1.8h, #16 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: sqshlu v0.4s, v1.4s, #32 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: sqshlu v0.2d, v1.2d, #64 // CHECK-ERROR: ^ @@ -1740,16 +1755,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqshl v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sqshl v0.16b, v1.16b, #8 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: sqshl v0.8h, v1.8h, #16 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: sqshl v0.4s, v1.4s, #32 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: sqshl v0.2d, v1.2d, #64 // CHECK-ERROR: ^ @@ -1773,16 +1788,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: uqshl v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: uqshl v0.16b, v1.16b, #8 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: uqshl v0.8h, v1.8h, #16 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: uqshl v0.4s, v1.4s, #32 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: uqshl v0.2d, v1.2d, #64 // CHECK-ERROR: ^ @@ -1805,13 +1820,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: shrn v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: shrn2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: shrn2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: shrn2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -1834,13 +1849,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqshrun v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqshrun2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqshrun2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqshrun2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -1863,13 +1878,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: rshrn v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: rshrn2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: rshrn2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: rshrn2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -1892,13 +1907,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqrshrun v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqrshrun2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqrshrun2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqrshrun2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -1921,13 +1936,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqshrn v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqshrn2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqshrn2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqshrn2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -1950,13 +1965,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: uqshrn v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: uqshrn2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: uqshrn2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: uqshrn2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -1979,13 +1994,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqrshrn v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqrshrn2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqrshrn2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqrshrn2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -2008,13 +2023,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: uqrshrn v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: uqrshrn2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: uqrshrn2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: uqrshrn2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -2037,13 +2052,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: scvtf v0.2d, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: ucvtf v0.2s, v1.2s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: ucvtf v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ucvtf v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -2066,13 +2081,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcvtzs v0.2d, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: fcvtzu v0.2s, v1.2s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: fcvtzu v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: fcvtzu v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -2616,9 +2631,11 @@ pmull2 v0.4s, v1.8h v2.8h pmull2 v0.2d, v1.4s, v2.4s -// CHECK-ERROR: error: expected comma before next operand + +// CHECK-ERROR: error: unexpected token in argument list // CHECK-ERROR: pmull2 v0.4s, v1.8h v2.8h // CHECK-ERROR: ^ + // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: pmull2 v0.2d, v1.4s, v2.4s // CHECK-ERROR: ^ @@ -2941,19 +2958,19 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: mla v0.2d, v1.2d, v16.d[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mla v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mla v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: mla v0.2h, v1.2h, v2.h[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mla v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mla v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -2975,19 +2992,19 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: mls v0.2d, v1.2d, v16.d[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mls v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mls v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: mls v0.2h, v1.2h, v2.h[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mls v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mls v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3012,22 +3029,22 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmla v0.8h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v3.4s, v8.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v3.4s, v8.4s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v0.2d, v1.2d, v2.d[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v0.2d, v1.2d, v22.d[2] // CHECK-ERROR: ^ @@ -3046,29 +3063,29 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmls v0.8h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v3.4s, v8.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v3.4s, v8.4s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v0.2d, v1.2d, v2.d[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v0.2d, v1.2d, v22.d[2] // CHECK-ERROR: ^ smlal v0.4h, v1.4h, v2.h[2] smlal v0.4s, v1.4h, v2.h[8] smlal v0.4s, v1.4h, v16.h[2] - smlal v0.2s, v1.2s, v2.s[4] + smlal v0.2s, v1.2s, v2.s[1] smlal v0.2d, v1.2s, v2.s[4] smlal v0.2d, v1.2s, v22.s[4] smlal2 v0.4h, v1.8h, v1.h[2] @@ -3081,25 +3098,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlal v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlal v0.4s, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout -// CHECK-ERROR: smlal v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlal v0.2s, v1.2s, v2.s[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlal2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3108,17 +3125,17 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlal2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ smlsl v0.4h, v1.4h, v2.h[2] smlsl v0.4s, v1.4h, v2.h[8] smlsl v0.4s, v1.4h, v16.h[2] - smlsl v0.2s, v1.2s, v2.s[4] + smlsl v0.2s, v1.2s, v2.s[1] smlsl v0.2d, v1.2s, v2.s[4] smlsl v0.2d, v1.2s, v22.s[4] smlsl2 v0.4h, v1.8h, v1.h[2] @@ -3131,25 +3148,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlsl v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlsl v0.4s, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout -// CHECK-ERROR: smlsl v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlsl v0.2s, v1.2s, v2.s[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlsl2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3158,17 +3175,17 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlsl2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ umlal v0.4h, v1.4h, v2.h[2] umlal v0.4s, v1.4h, v2.h[8] umlal v0.4s, v1.4h, v16.h[2] - umlal v0.2s, v1.2s, v2.s[4] + umlal v0.2s, v1.2s, v2.s[1] umlal v0.2d, v1.2s, v2.s[4] umlal v0.2d, v1.2s, v22.s[4] umlal2 v0.4h, v1.8h, v1.h[2] @@ -3181,25 +3198,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlal v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlal v0.4s, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout -// CHECK-ERROR: umlal v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlal v0.2s, v1.2s, v2.s[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlal2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3208,17 +3225,17 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlal2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ umlsl v0.4h, v1.4h, v2.h[2] umlsl v0.4s, v1.4h, v2.h[8] umlsl v0.4s, v1.4h, v16.h[2] - umlsl v0.2s, v1.2s, v2.s[4] + umlsl v0.2s, v1.2s, v2.s[3] umlsl v0.2d, v1.2s, v2.s[4] umlsl v0.2d, v1.2s, v22.s[4] umlsl2 v0.4h, v1.8h, v1.h[2] @@ -3231,25 +3248,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlsl v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlsl v0.4s, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout -// CHECK-ERROR: umlsl v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlsl v0.2s, v1.2s, v2.s[3] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlsl2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3258,17 +3275,17 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlsl2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ sqdmlal v0.4h, v1.4h, v2.h[2] sqdmlal v0.4s, v1.4h, v2.h[8] sqdmlal v0.4s, v1.4h, v16.h[2] - sqdmlal v0.2s, v1.2s, v2.s[4] + sqdmlal v0.2s, v1.2s, v2.s[3] sqdmlal v0.2d, v1.2s, v2.s[4] sqdmlal v0.2d, v1.2s, v22.s[4] sqdmlal2 v0.4h, v1.8h, v1.h[2] @@ -3281,25 +3298,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal v0.4s, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout -// CHECK-ERROR: sqdmlal v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal v0.2s, v1.2s, v2.s[3] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3308,17 +3325,17 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ sqdmlsl v0.4h, v1.4h, v2.h[2] sqdmlsl v0.4s, v1.4h, v2.h[8] sqdmlsl v0.4s, v1.4h, v16.h[2] - sqdmlsl v0.2s, v1.2s, v2.s[4] + sqdmlsl v0.2s, v1.2s, v2.s[3] sqdmlsl v0.2d, v1.2s, v2.s[4] sqdmlsl v0.2d, v1.2s, v22.s[4] sqdmlsl2 v0.4h, v1.8h, v1.h[2] @@ -3331,25 +3348,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl v0.4s, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout -// CHECK-ERROR: sqdmlsl v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl v0.2s, v1.2s, v2.s[3] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3358,10 +3375,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3375,28 +3392,28 @@ mul v0.4s, v1.4s, v22.s[4] mul v0.2d, v1.2d, v2.d[1] -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: mul v0.4h, v1.4h, v16.h[8] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: invalid operand for instruction // CHECK-ERROR: mul v0.8h, v1.8h, v16.h[8] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3414,22 +3431,22 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmul v0.4h, v1.4h, v2.h[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.2d, v1.2d, v2.d[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.2d, v1.2d, v22.d[2] // CHECK-ERROR: ^ @@ -3444,22 +3461,22 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmulx v0.4h, v1.4h, v2.h[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.2d, v1.2d, v2.d[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.2d, v1.2d, v22.d[2] // CHECK-ERROR: ^ @@ -3479,7 +3496,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smull v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3488,16 +3505,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smull v0.2s, v1.2s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smull2 v0.4h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull2 v0.4s, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3506,10 +3523,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smull2 v0.2s, v1.4s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull2 v0.2d, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3529,7 +3546,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umull v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3538,16 +3555,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umull v0.2s, v1.2s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umull2 v0.4h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull2 v0.4s, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3556,10 +3573,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umull2 v0.2s, v1.4s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull2 v0.2d, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3579,7 +3596,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3588,16 +3605,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull v0.2s, v1.2s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull2 v0.4h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull2 v0.4s, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3606,10 +3623,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull2 v0.2s, v1.4s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull2 v0.2d, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3623,28 +3640,28 @@ sqdmulh v0.4s, v1.4s, v22.s[4] sqdmulh v0.2d, v1.2d, v22.d[1] -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmulh v0.4h, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmulh v0.8h, v1.8h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3661,28 +3678,28 @@ sqrdmulh v0.4s, v1.4s, v22.s[4] sqrdmulh v0.2d, v1.2d, v22.d[1] -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqrdmulh v0.4h, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqrdmulh v0.8h, v1.8h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3900,13 +3917,13 @@ ld1 {v4}, [x0] ld1 {v32.16b}, [x0] ld1 {v15.8h}, [x32] -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: vector register expected // CHECK-ERROR: ld1 {x3}, [x2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld1 {v4}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: vector register expected // CHECK-ERROR: ld1 {v32.16b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3920,13 +3937,13 @@ ld1 {v1.8h-v1.8h}, [x0] ld1 {v15.8h-v17.4h}, [x15] ld1 {v0.8b-v2.8b, [x0] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: ld1 {v0.16b, v2.16b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: ld1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: '{' expected +// CHECK-ERROR: error: unexpected token in argument list // CHECK-ERROR: ld1 v0.8b, v1.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors @@ -3935,7 +3952,7 @@ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: ld1 {v1.8h-v1.8h}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld1 {v15.8h-v17.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: '}' expected @@ -3947,16 +3964,15 @@ ld2 {v15.4h, v16.4h, v17.4h}, [x32] ld2 {v15.8h-v16.4h}, [x15] ld2 {v0.2d-v2.2d}, [x0] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld2 {v15.8h, v16.4h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: ld2 {v0.8b, v2.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld2 {v15.4h, v16.4h, v17.4h}, [x32] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld2 {v15.8h-v16.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3968,16 +3984,16 @@ ld3 {v0.8b, v2.8b, v3.8b}, [x0] ld3 {v15.8h-v17.4h}, [x15] ld3 {v31.4s-v2.4s}, [sp] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld3 {v15.8h, v16.8h, v17.4h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: ld3 {v0.8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld3 {v15.8h-v17.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3989,16 +4005,16 @@ ld4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] ld4 {v15.8h-v18.4h}, [x15] ld4 {v31.2s-v1.2s}, [x31] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: ld4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: ld4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld4 {v15.8h-v18.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4009,13 +4025,13 @@ st1 {v4}, [x0] st1 {v32.16b}, [x0] st1 {v15.8h}, [x32] -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: vector register expected // CHECK-ERROR: st1 {x3}, [x2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st1 {v4}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: vector register expected // CHECK-ERROR: st1 {v32.16b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4029,13 +4045,13 @@ st1 {v1.8h-v1.8h}, [x0] st1 {v15.8h-v17.4h}, [x15] st1 {v0.8b-v2.8b, [x0] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: st1 {v0.16b, v2.16b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: st1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: '{' expected +// CHECK-ERROR: error: unexpected token in argument list // CHECK-ERROR: st1 v0.8b, v1.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors @@ -4044,7 +4060,7 @@ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: st1 {v1.8h-v1.8h}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st1 {v15.8h-v17.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: '}' expected @@ -4056,16 +4072,16 @@ st2 {v15.4h, v16.4h, v17.4h}, [x30] st2 {v15.8h-v16.4h}, [x15] st2 {v0.2d-v2.2d}, [x0] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st2 {v15.8h, v16.4h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: st2 {v0.8b, v2.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st2 {v15.4h, v16.4h, v17.4h}, [x30] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st2 {v15.8h-v16.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4077,16 +4093,16 @@ st3 {v0.8b, v2.8b, v3.8b}, [x0] st3 {v15.8h-v17.4h}, [x15] st3 {v31.4s-v2.4s}, [sp] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st3 {v15.8h, v16.8h, v17.4h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: st3 {v0.8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st3 {v15.8h-v17.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4098,16 +4114,16 @@ st4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] st4 {v15.8h-v18.4h}, [x15] st4 {v31.2s-v1.2s}, [x31] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: st4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: st4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st4 {v15.8h-v18.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4124,7 +4140,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld1 {v0.16b}, [x0], #8 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: invalid vector kind qualifier // CHECK-ERROR: ld1 {v0.8h, v1.16h}, [x0], x1 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4140,7 +4156,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld3 {v5.2s, v6.2s, v7.2s}, [x1], #48 // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 // CHECK-ERROR: ^ @@ -4150,7 +4166,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st1 {v0.16b}, [x0], #8 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: invalid vector kind qualifier // CHECK-ERROR: st1 {v0.8h, v1.16h}, [x0], x1 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4166,7 +4182,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st3 {v5.2s, v6.2s, v7.2s}, [x1], #48 // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 // CHECK-ERROR: ^ @@ -4178,16 +4194,16 @@ ld2r {v31.4s, v0.2s}, [sp] ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp] -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: vector register expected // CHECK-ERROR: ld1r {x1}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld2r {v31.4s, v0.2s}, [sp] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp] // CHECK-ERROR: ^ @@ -4199,16 +4215,16 @@ ld2 {v15.h, v16.h}[8], [x15] ld3 {v31.s, v0.s, v1.s}[-1], [sp] ld4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] -// CHECK-ERROR:: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: ld1 {v0.b}[16], [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: ld2 {v15.h, v16.h}[8], [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected lane number +// CHECK-ERROR: error: vector lane must be an integer in range // CHECK-ERROR: ld3 {v31.s, v0.s, v1.s}[-1], [sp] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: ld4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] // CHECK-ERROR: ^ @@ -4216,16 +4232,16 @@ st2 {v31.s, v0.s}[3], [8] st3 {v15.h, v16.h, v17.h}[-1], [x15] st4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] -// CHECK-ERROR:: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: st1 {v0.d}[16], [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st2 {v31.s, v0.s}[3], [8] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected lane number +// CHECK-ERROR: error: vector lane must be an integer in range // CHECK-ERROR: st3 {v15.h, v16.h, v17.h}[-1], [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: st4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] // CHECK-ERROR: ^ @@ -4264,7 +4280,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld2 {v15.h, v16.h}[0], [x15], #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld3 {v31.s, v0.s, v1.d}[0], [sp], x9 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4298,16 +4314,16 @@ ins v20.s[1], s30 ins v1.d[0], d7 -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: ins v2.b[16], w1 // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: ins v7.h[8], w14 // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: ins v20.s[5], w30 // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: ins v1.d[2], x7 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4334,19 +4350,19 @@ smov x14, v6.d[1] smov x20, v9.d[0] -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR smov w1, v0.b[16] // CHECK-ERROR ^ -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR smov w14, v6.h[8] // CHECK-ERROR ^ -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR smov x1, v0.b[16] // CHECK-ERROR ^ -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR smov x14, v6.h[8] // CHECK-ERROR ^ -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR smov x20, v9.s[5] // CHECK-ERROR ^ // CHECK-ERROR error: invalid operand for instruction @@ -4373,16 +4389,16 @@ umov s20, v9.s[2] umov d7, v18.d[1] -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR umov w1, v0.b[16] // CHECK-ERROR ^ -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR umov w14, v6.h[8] // CHECK-ERROR ^ -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR umov w20, v9.s[5] // CHECK-ERROR ^ -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR umov x7, v18.d[3] // CHECK-ERROR ^ // CHECK-ERROR error: invalid operand for instruction @@ -4798,7 +4814,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal s17, h27, s12 // CHECK-ERROR: ^ -// CHECK-ERROR: error: too few operands for instruction +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal d19, s24, d12 // CHECK-ERROR: ^ @@ -4812,7 +4828,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl s14, h12, s25 // CHECK-ERROR: ^ -// CHECK-ERROR: error: too few operands for instruction +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl d12, s23, d13 // CHECK-ERROR: ^ @@ -4826,7 +4842,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull s12, h22, s12 // CHECK-ERROR: ^ -// CHECK-ERROR: error: too few operands for instruction +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull d15, s22, d12 // CHECK-ERROR: ^ @@ -4890,7 +4906,7 @@ //---------------------------------------------------------------------- sshr d15, d16, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: sshr d15, d16, #99 // CHECK-ERROR: ^ @@ -4906,7 +4922,7 @@ ushr d10, d17, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ushr d10, d17, #99 // CHECK-ERROR: ^ @@ -4916,7 +4932,7 @@ srshr d19, d18, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: srshr d19, d18, #99 // CHECK-ERROR: ^ @@ -4926,7 +4942,7 @@ urshr d20, d23, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: urshr d20, d23, #99 // CHECK-ERROR: ^ @@ -4936,7 +4952,7 @@ ssra d18, d12, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ssra d18, d12, #99 // CHECK-ERROR: ^ @@ -4946,7 +4962,7 @@ usra d20, d13, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: usra d20, d13, #99 // CHECK-ERROR: ^ @@ -4956,7 +4972,7 @@ srsra d15, d11, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: srsra d15, d11, #99 // CHECK-ERROR: ^ @@ -4966,7 +4982,7 @@ ursra d18, d10, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ursra d18, d10, #99 // CHECK-ERROR: ^ @@ -4976,7 +4992,7 @@ shl d7, d10, #99 -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: shl d7, d10, #99 // CHECK-ERROR: ^ @@ -4995,16 +5011,16 @@ sqshl s14, s17, #99 sqshl d15, d16, #99 -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sqshl b11, b19, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: sqshl h13, h18, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: sqshl s14, s17, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: sqshl d15, d16, #99 // CHECK-ERROR: ^ @@ -5017,16 +5033,16 @@ uqshl s14, s19, #99 uqshl d15, d12, #99 -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: uqshl b18, b15, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: uqshl h11, h18, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: uqshl s14, s19, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: uqshl d15, d12, #99 // CHECK-ERROR: ^ @@ -5039,16 +5055,16 @@ sqshlu s16, s14, #99 sqshlu d11, d13, #99 -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sqshlu b15, b18, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: sqshlu h19, h17, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: sqshlu s16, s14, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: sqshlu d11, d13, #99 // CHECK-ERROR: ^ @@ -5058,7 +5074,7 @@ sri d10, d12, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: sri d10, d12, #99 // CHECK-ERROR: ^ @@ -5068,7 +5084,7 @@ sli d10, d14, #99 -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: sli d10, d14, #99 // CHECK-ERROR: ^ @@ -5080,13 +5096,13 @@ sqshrn h17, s10, #99 sqshrn s18, d10, #99 -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqshrn b10, h15, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqshrn h17, s10, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqshrn s18, d10, #99 // CHECK-ERROR: ^ @@ -5098,13 +5114,13 @@ uqshrn h10, s14, #99 uqshrn s10, d12, #99 -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: uqshrn b12, h10, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: uqshrn h10, s14, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: uqshrn s10, d12, #99 // CHECK-ERROR: ^ @@ -5116,13 +5132,13 @@ sqrshrn h15, s10, #99 sqrshrn s15, d12, #99 -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqrshrn b10, h13, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqrshrn h15, s10, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqrshrn s15, d12, #99 // CHECK-ERROR: ^ @@ -5134,13 +5150,13 @@ uqrshrn h12, s10, #99 uqrshrn s10, d10, #99 -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: uqrshrn b10, h12, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: uqrshrn h12, s10, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: uqrshrn s10, d10, #99 // CHECK-ERROR: ^ @@ -5152,13 +5168,13 @@ sqshrun h20, s14, #99 sqshrun s10, d15, #99 -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqshrun b15, h10, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqshrun h20, s14, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqshrun s10, d15, #99 // CHECK-ERROR: ^ @@ -5170,13 +5186,13 @@ sqrshrun h10, s13, #99 sqrshrun s22, d16, #99 -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqrshrun b17, h10, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqrshrun h10, s13, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqrshrun s22, d16, #99 // CHECK-ERROR: ^ @@ -5189,13 +5205,13 @@ scvtf d21, d12, #65 scvtf d21, s12, #31 -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: scvtf s22, s13, #0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: scvtf s22, s13, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: scvtf d21, d12, #65 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -5210,10 +5226,10 @@ ucvtf d21, d14, #65 ucvtf d21, s14, #64 -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: ucvtf s22, s13, #34 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ucvtf d21, d14, #65 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -6262,10 +6278,10 @@ fcvtzs d21, d12, #65 fcvtzs s21, d12, #1 -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: fcvtzs s21, s12, #0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: fcvtzs d21, d12, #65 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -6280,10 +6296,10 @@ fcvtzu d21, d12, #0 fcvtzu s21, d12, #1 -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: fcvtzu s21, s12, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: fcvtzu d21, d12, #0 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -6868,7 +6884,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmul h0, h1, v1.s[0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul s2, s29, v10.s[4] // CHECK-ERROR: ^ @@ -6887,7 +6903,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmulx h0, h1, v1.d[0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx d2, d29, v10.d[3] // CHECK-ERROR: ^ @@ -6906,7 +6922,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmla d30, s11, v1.d[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla s16, s22, v16.s[5] // CHECK-ERROR: ^ @@ -6925,7 +6941,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmls h7, h17, v26.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected lane number +// CHECK-ERROR: error: vector lane must be an integer in range [0, 1] // CHECK-ERROR: fmls d16, d22, v16.d[-1] // CHECK-ERROR: ^ @@ -6937,7 +6953,7 @@ sqdmlal s0, h0, v0.s[0] sqdmlal s8, s9, v14.s[1] // invalid lane - sqdmlal s4, s5, v1.s[5] + sqdmlal d4, s5, v1.s[5] // invalid vector index sqdmlal s0, h0, v17.h[0] @@ -6947,8 +6963,8 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal s8, s9, v14.s[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout -// CHECK-ERROR: sqdmlal s4, s5, v1.s[5] +// CHECK-ERROR: vector lane must be an integer in range +// CHECK-ERROR: sqdmlal d4, s5, v1.s[5] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal s0, h0, v17.h[0] @@ -6972,7 +6988,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl d1, h1, v13.s[0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl d1, s1, v13.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -6999,7 +7015,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull s1, s1, v4.s[0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull s12, h17, v9.h[9] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -7024,7 +7040,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmulh s25, s26, v27.h[3] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh s25, s26, v27.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -7049,7 +7065,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqrdmulh s5, h6, v7.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh h31, h30, v14.h[9] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -7081,16 +7097,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: dup d0, v17.s[3] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: dup d0, v17.d[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: dup s0, v1.s[7] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: dup h0, v31.h[16] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: dup b1, v3.b[16] // CHECK-ERROR: ^ diff --git a/test/MC/AArch64/neon-extract.s b/test/MC/AArch64/neon-extract.s index 2d58a75..1daa46d 100644 --- a/test/MC/AArch64/neon-extract.s +++ b/test/MC/AArch64/neon-extract.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 @@ -9,5 +9,5 @@ ext v0.8b, v1.8b, v2.8b, #0x3 ext v0.16b, v1.16b, v2.16b, #0x3 -// CHECK: ext v0.8b, v1.8b, v2.8b, #0x3 // encoding: [0x20,0x18,0x02,0x2e] -// CHECK: ext v0.16b, v1.16b, v2.16b, #0x3 // encoding: [0x20,0x18,0x02,0x6e] +// CHECK: ext v0.8b, v1.8b, v2.8b, #{{0x3|3}} // encoding: [0x20,0x18,0x02,0x2e] +// CHECK: ext v0.16b, v1.16b, v2.16b, #{{0x3|3}} // encoding: [0x20,0x18,0x02,0x6e] diff --git a/test/MC/AArch64/neon-mov.s b/test/MC/AArch64/neon-mov.s index c2ca803..567a5ec 100644 --- a/test/MC/AArch64/neon-mov.s +++ b/test/MC/AArch64/neon-mov.s @@ -20,19 +20,19 @@ movi v0.8h, #1 movi v0.8h, #1, lsl #8 -// CHECK: movi v0.2s, #0x1 // encoding: [0x20,0x04,0x00,0x0f] -// CHECK: movi v1.2s, #0x0 // encoding: [0x01,0x04,0x00,0x0f] -// CHECK: movi v15.2s, #0x1, lsl #8 // encoding: [0x2f,0x24,0x00,0x0f] -// CHECK: movi v16.2s, #0x1, lsl #16 // encoding: [0x30,0x44,0x00,0x0f] -// CHECK: movi v31.2s, #0x1, lsl #24 // encoding: [0x3f,0x64,0x00,0x0f] -// CHECK: movi v0.4s, #0x1 // encoding: [0x20,0x04,0x00,0x4f] -// CHECK: movi v0.4s, #0x1, lsl #8 // encoding: [0x20,0x24,0x00,0x4f] -// CHECK: movi v0.4s, #0x1, lsl #16 // encoding: [0x20,0x44,0x00,0x4f] -// CHECK: movi v0.4s, #0x1, lsl #24 // encoding: [0x20,0x64,0x00,0x4f] -// CHECK: movi v0.4h, #0x1 // encoding: [0x20,0x84,0x00,0x0f] -// CHECK: movi v0.4h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x0f] -// CHECK: movi v0.8h, #0x1 // encoding: [0x20,0x84,0x00,0x4f] -// CHECK: movi v0.8h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x4f] +// CHECK: movi v0.2s, #{{0x1|1}} // encoding: [0x20,0x04,0x00,0x0f] +// CHECK: movi v1.2s, #{{0x0|0}} // encoding: [0x01,0x04,0x00,0x0f] +// CHECK: movi v15.2s, #{{0x1|1}}, lsl #8 // encoding: [0x2f,0x24,0x00,0x0f] +// CHECK: movi v16.2s, #{{0x1|1}}, lsl #16 // encoding: [0x30,0x44,0x00,0x0f] +// CHECK: movi v31.2s, #{{0x1|1}}, lsl #24 // encoding: [0x3f,0x64,0x00,0x0f] +// CHECK: movi v0.4s, #{{0x1|1}} // encoding: [0x20,0x04,0x00,0x4f] +// CHECK: movi v0.4s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x24,0x00,0x4f] +// CHECK: movi v0.4s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x44,0x00,0x4f] +// CHECK: movi v0.4s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x64,0x00,0x4f] +// CHECK: movi v0.4h, #{{0x1|1}} // encoding: [0x20,0x84,0x00,0x0f] +// CHECK: movi v0.4h, #{{0x1|1}}, lsl #8 // encoding: [0x20,0xa4,0x00,0x0f] +// CHECK: movi v0.8h, #{{0x1|1}} // encoding: [0x20,0x84,0x00,0x4f] +// CHECK: movi v0.8h, #{{0x1|1}}, lsl #8 // encoding: [0x20,0xa4,0x00,0x4f] //---------------------------------------------------------------------- // Vector Move Inverted Immediate Shifted @@ -51,19 +51,19 @@ mvni v0.8h, #1 mvni v0.8h, #1, lsl #8 -// CHECK: mvni v0.2s, #0x1 // encoding: [0x20,0x04,0x00,0x2f] -// CHECK: mvni v1.2s, #0x0 // encoding: [0x01,0x04,0x00,0x2f] -// CHECK: mvni v0.2s, #0x1, lsl #8 // encoding: [0x20,0x24,0x00,0x2f] -// CHECK: mvni v0.2s, #0x1, lsl #16 // encoding: [0x20,0x44,0x00,0x2f] -// CHECK: mvni v0.2s, #0x1, lsl #24 // encoding: [0x20,0x64,0x00,0x2f] -// CHECK: mvni v0.4s, #0x1 // encoding: [0x20,0x04,0x00,0x6f] -// CHECK: mvni v15.4s, #0x1, lsl #8 // encoding: [0x2f,0x24,0x00,0x6f] -// CHECK: mvni v16.4s, #0x1, lsl #16 // encoding: [0x30,0x44,0x00,0x6f] -// CHECK: mvni v31.4s, #0x1, lsl #24 // encoding: [0x3f,0x64,0x00,0x6f] -// CHECK: mvni v0.4h, #0x1 // encoding: [0x20,0x84,0x00,0x2f] -// CHECK: mvni v0.4h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x2f] -// CHECK: mvni v0.8h, #0x1 // encoding: [0x20,0x84,0x00,0x6f] -// CHECK: mvni v0.8h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x6f] +// CHECK: mvni v0.2s, #{{0x1|1}} // encoding: [0x20,0x04,0x00,0x2f] +// CHECK: mvni v1.2s, #{{0x0|0}} // encoding: [0x01,0x04,0x00,0x2f] +// CHECK: mvni v0.2s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x24,0x00,0x2f] +// CHECK: mvni v0.2s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x44,0x00,0x2f] +// CHECK: mvni v0.2s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x64,0x00,0x2f] +// CHECK: mvni v0.4s, #{{0x1|1}} // encoding: [0x20,0x04,0x00,0x6f] +// CHECK: mvni v15.4s, #{{0x1|1}}, lsl #8 // encoding: [0x2f,0x24,0x00,0x6f] +// CHECK: mvni v16.4s, #{{0x1|1}}, lsl #16 // encoding: [0x30,0x44,0x00,0x6f] +// CHECK: mvni v31.4s, #{{0x1|1}}, lsl #24 // encoding: [0x3f,0x64,0x00,0x6f] +// CHECK: mvni v0.4h, #{{0x1|1}} // encoding: [0x20,0x84,0x00,0x2f] +// CHECK: mvni v0.4h, #{{0x1|1}}, lsl #8 // encoding: [0x20,0xa4,0x00,0x2f] +// CHECK: mvni v0.8h, #{{0x1|1}} // encoding: [0x20,0x84,0x00,0x6f] +// CHECK: mvni v0.8h, #{{0x1|1}}, lsl #8 // encoding: [0x20,0xa4,0x00,0x6f] //---------------------------------------------------------------------- // Vector Bitwise Bit Clear (AND NOT) - immediate @@ -82,19 +82,19 @@ bic v0.8h, #1 bic v31.8h, #1, lsl #8 -// CHECK: bic v0.2s, #0x1 // encoding: [0x20,0x14,0x00,0x2f] -// CHECK: bic v1.2s, #0x0 // encoding: [0x01,0x14,0x00,0x2f] -// CHECK: bic v0.2s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x2f] -// CHECK: bic v0.2s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x2f] -// CHECK: bic v0.2s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x2f] -// CHECK: bic v0.4s, #0x1 // encoding: [0x20,0x14,0x00,0x6f] -// CHECK: bic v0.4s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x6f] -// CHECK: bic v0.4s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x6f] -// CHECK: bic v0.4s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x6f] -// CHECK: bic v15.4h, #0x1 // encoding: [0x2f,0x94,0x00,0x2f] -// CHECK: bic v16.4h, #0x1, lsl #8 // encoding: [0x30,0xb4,0x00,0x2f] -// CHECK: bic v0.8h, #0x1 // encoding: [0x20,0x94,0x00,0x6f] -// CHECK: bic v31.8h, #0x1, lsl #8 // encoding: [0x3f,0xb4,0x00,0x6f] +// CHECK: bic v0.2s, #{{0x1|1}} // encoding: [0x20,0x14,0x00,0x2f] +// CHECK: bic v1.2s, #{{0x0|0}} // encoding: [0x01,0x14,0x00,0x2f] +// CHECK: bic v0.2s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x34,0x00,0x2f] +// CHECK: bic v0.2s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x54,0x00,0x2f] +// CHECK: bic v0.2s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x74,0x00,0x2f] +// CHECK: bic v0.4s, #{{0x1|1}} // encoding: [0x20,0x14,0x00,0x6f] +// CHECK: bic v0.4s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x34,0x00,0x6f] +// CHECK: bic v0.4s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x54,0x00,0x6f] +// CHECK: bic v0.4s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x74,0x00,0x6f] +// CHECK: bic v15.4h, #{{0x1|1}} // encoding: [0x2f,0x94,0x00,0x2f] +// CHECK: bic v16.4h, #{{0x1|1}}, lsl #8 // encoding: [0x30,0xb4,0x00,0x2f] +// CHECK: bic v0.8h, #{{0x1|1}} // encoding: [0x20,0x94,0x00,0x6f] +// CHECK: bic v31.8h, #{{0x1|1}}, lsl #8 // encoding: [0x3f,0xb4,0x00,0x6f] //---------------------------------------------------------------------- // Vector Bitwise OR - immedidate @@ -113,19 +113,19 @@ orr v0.8h, #1 orr v16.8h, #1, lsl #8 -// CHECK: orr v0.2s, #0x1 // encoding: [0x20,0x14,0x00,0x0f] -// CHECK: orr v1.2s, #0x0 // encoding: [0x01,0x14,0x00,0x0f] -// CHECK: orr v0.2s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x0f] -// CHECK: orr v0.2s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x0f] -// CHECK: orr v0.2s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x0f] -// CHECK: orr v0.4s, #0x1 // encoding: [0x20,0x14,0x00,0x4f] -// CHECK: orr v0.4s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x4f] -// CHECK: orr v0.4s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x4f] -// CHECK: orr v0.4s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x4f] -// CHECK: orr v31.4h, #0x1 // encoding: [0x3f,0x94,0x00,0x0f] -// CHECK: orr v15.4h, #0x1, lsl #8 // encoding: [0x2f,0xb4,0x00,0x0f] -// CHECK: orr v0.8h, #0x1 // encoding: [0x20,0x94,0x00,0x4f] -// CHECK: orr v16.8h, #0x1, lsl #8 // encoding: [0x30,0xb4,0x00,0x4f] +// CHECK: orr v0.2s, #{{0x1|1}} // encoding: [0x20,0x14,0x00,0x0f] +// CHECK: orr v1.2s, #{{0x0|0}} // encoding: [0x01,0x14,0x00,0x0f] +// CHECK: orr v0.2s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x34,0x00,0x0f] +// CHECK: orr v0.2s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x54,0x00,0x0f] +// CHECK: orr v0.2s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x74,0x00,0x0f] +// CHECK: orr v0.4s, #{{0x1|1}} // encoding: [0x20,0x14,0x00,0x4f] +// CHECK: orr v0.4s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x34,0x00,0x4f] +// CHECK: orr v0.4s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x54,0x00,0x4f] +// CHECK: orr v0.4s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x74,0x00,0x4f] +// CHECK: orr v31.4h, #{{0x1|1}} // encoding: [0x3f,0x94,0x00,0x0f] +// CHECK: orr v15.4h, #{{0x1|1}}, lsl #8 // encoding: [0x2f,0xb4,0x00,0x0f] +// CHECK: orr v0.8h, #{{0x1|1}} // encoding: [0x20,0x94,0x00,0x4f] +// CHECK: orr v16.8h, #{{0x1|1}}, lsl #8 // encoding: [0x30,0xb4,0x00,0x4f] //---------------------------------------------------------------------- // Vector Move Immediate Masked @@ -135,10 +135,10 @@ movi v0.4s, #1, msl #8 movi v31.4s, #1, msl #16 -// CHECK: movi v0.2s, #0x1, msl #8 // encoding: [0x20,0xc4,0x00,0x0f] -// CHECK: movi v1.2s, #0x1, msl #16 // encoding: [0x21,0xd4,0x00,0x0f] -// CHECK: movi v0.4s, #0x1, msl #8 // encoding: [0x20,0xc4,0x00,0x4f] -// CHECK: movi v31.4s, #0x1, msl #16 // encoding: [0x3f,0xd4,0x00,0x4f] +// CHECK: movi v0.2s, #{{0x1|1}}, msl #8 // encoding: [0x20,0xc4,0x00,0x0f] +// CHECK: movi v1.2s, #{{0x1|1}}, msl #16 // encoding: [0x21,0xd4,0x00,0x0f] +// CHECK: movi v0.4s, #{{0x1|1}}, msl #8 // encoding: [0x20,0xc4,0x00,0x4f] +// CHECK: movi v31.4s, #{{0x1|1}}, msl #16 // encoding: [0x3f,0xd4,0x00,0x4f] //---------------------------------------------------------------------- // Vector Move Inverted Immediate Masked @@ -148,10 +148,10 @@ mvni v31.4s, #0x1, msl #8 mvni v0.4s, #0x1, msl #16 -// CHECK: mvni v1.2s, #0x1, msl #8 // encoding: [0x21,0xc4,0x00,0x2f] -// CHECK: mvni v0.2s, #0x1, msl #16 // encoding: [0x20,0xd4,0x00,0x2f] -// CHECK: mvni v31.4s, #0x1, msl #8 // encoding: [0x3f,0xc4,0x00,0x6f] -// CHECK: mvni v0.4s, #0x1, msl #16 // encoding: [0x20,0xd4,0x00,0x6f] +// CHECK: mvni v1.2s, #{{0x1|1}}, msl #8 // encoding: [0x21,0xc4,0x00,0x2f] +// CHECK: mvni v0.2s, #{{0x1|1}}, msl #16 // encoding: [0x20,0xd4,0x00,0x2f] +// CHECK: mvni v31.4s, #{{0x1|1}}, msl #8 // encoding: [0x3f,0xc4,0x00,0x6f] +// CHECK: mvni v0.4s, #{{0x1|1}}, msl #16 // encoding: [0x20,0xd4,0x00,0x6f] //---------------------------------------------------------------------- // Vector Immediate - per byte @@ -161,10 +161,10 @@ movi v15.16b, #0xf movi v31.16b, #0x1f -// CHECK: movi v0.8b, #0x0 // encoding: [0x00,0xe4,0x00,0x0f] -// CHECK: movi v31.8b, #0xff // encoding: [0xff,0xe7,0x07,0x0f] -// CHECK: movi v15.16b, #0xf // encoding: [0xef,0xe5,0x00,0x4f] -// CHECK: movi v31.16b, #0x1f // encoding: [0xff,0xe7,0x00,0x4f] +// CHECK: movi v0.8b, #{{0x0|0}} // encoding: [0x00,0xe4,0x00,0x0f] +// CHECK: movi v31.8b, #{{0xff|255}} // encoding: [0xff,0xe7,0x07,0x0f] +// CHECK: movi v15.16b, #{{0xf|15}} // encoding: [0xef,0xe5,0x00,0x4f] +// CHECK: movi v31.16b, #{{0x1f|31}} // encoding: [0xff,0xe7,0x00,0x4f] //---------------------------------------------------------------------- // Vector Move Immediate - bytemask, per doubleword @@ -187,23 +187,22 @@ fmov v15.4s, #1.0 fmov v31.2d, #1.0 -// CHECK: fmov v1.2s, #1.00000000 // encoding: [0x01,0xf6,0x03,0x0f] -// CHECK: fmov v15.4s, #1.00000000 // encoding: [0x0f,0xf6,0x03,0x4f] -// CHECK: fmov v31.2d, #1.00000000 // encoding: [0x1f,0xf6,0x03,0x6f] +// CHECK: fmov v1.2s, #{{1.00000000|1.000000e\+00}} // encoding: [0x01,0xf6,0x03,0x0f] +// CHECK: fmov v15.4s, #{{1.00000000|1.000000e\+00}} // encoding: [0x0f,0xf6,0x03,0x4f] +// CHECK: fmov v31.2d, #{{1.00000000|1.000000e\+00}} // encoding: [0x1f,0xf6,0x03,0x6f] //---------------------------------------------------------------------- // Vector Move - register //---------------------------------------------------------------------- - // FIXME: these should all print with the "mov" syntax. mov v0.8b, v31.8b mov v15.16b, v16.16b orr v0.8b, v31.8b, v31.8b orr v15.16b, v16.16b, v16.16b -// CHECK: orr v0.8b, v31.8b, v31.8b // encoding: [0xe0,0x1f,0xbf,0x0e] -// CHECK: orr v15.16b, v16.16b, v16.16b // encoding: [0x0f,0x1e,0xb0,0x4e] -// CHECK: orr v0.8b, v31.8b, v31.8b // encoding: [0xe0,0x1f,0xbf,0x0e] -// CHECK: orr v15.16b, v16.16b, v16.16b // encoding: [0x0f,0x1e,0xb0,0x4e] +// CHECK: mov v0.8b, v31.8b // encoding: [0xe0,0x1f,0xbf,0x0e] +// CHECK: mov v15.16b, v16.16b // encoding: [0x0f,0x1e,0xb0,0x4e] +// CHECK: mov v0.8b, v31.8b // encoding: [0xe0,0x1f,0xbf,0x0e] +// CHECK: mov v15.16b, v16.16b // encoding: [0x0f,0x1e,0xb0,0x4e] diff --git a/test/MC/AArch64/neon-perm.s b/test/MC/AArch64/neon-perm.s index 20a4acde..4b28dd0 100644 --- a/test/MC/AArch64/neon-perm.s +++ b/test/MC/AArch64/neon-perm.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/test/MC/AArch64/neon-scalar-compare.s b/test/MC/AArch64/neon-scalar-compare.s index 55ade0e..28de46a 100644 --- a/test/MC/AArch64/neon-scalar-compare.s +++ b/test/MC/AArch64/neon-scalar-compare.s @@ -16,7 +16,7 @@ cmeq d20, d21, #0x0 -// CHECK: cmeq d20, d21, #0x0 // encoding: [0xb4,0x9a,0xe0,0x5e] +// CHECK: cmeq d20, d21, #{{0x0|0}} // encoding: [0xb4,0x9a,0xe0,0x5e] //---------------------------------------------------------------------- // Scalar Compare Unsigned Higher Or Same @@ -40,7 +40,7 @@ cmge d20, d21, #0x0 -// CHECK: cmge d20, d21, #0x0 // encoding: [0xb4,0x8a,0xe0,0x7e] +// CHECK: cmge d20, d21, #{{0x0|0}} // encoding: [0xb4,0x8a,0xe0,0x7e] //---------------------------------------------------------------------- // Scalar Compare Unsigned Higher @@ -63,7 +63,7 @@ cmgt d20, d21, #0x0 -// CHECK: cmgt d20, d21, #0x0 // encoding: [0xb4,0x8a,0xe0,0x5e] +// CHECK: cmgt d20, d21, #{{0x0|0}} // encoding: [0xb4,0x8a,0xe0,0x5e] //---------------------------------------------------------------------- // Scalar Compare Signed Less Than Or Equal To Zero @@ -71,7 +71,7 @@ cmle d20, d21, #0x0 -// CHECK: cmle d20, d21, #0x0 // encoding: [0xb4,0x9a,0xe0,0x7e] +// CHECK: cmle d20, d21, #{{0x0|0}} // encoding: [0xb4,0x9a,0xe0,0x7e] //---------------------------------------------------------------------- // Scalar Compare Less Than Zero @@ -79,7 +79,7 @@ cmlt d20, d21, #0x0 -// CHECK: cmlt d20, d21, #0x0 // encoding: [0xb4,0xaa,0xe0,0x5e] +// CHECK: cmlt d20, d21, #{{0x0|0}} // encoding: [0xb4,0xaa,0xe0,0x5e] //---------------------------------------------------------------------- // Scalar Compare Bitwise Test Bits diff --git a/test/MC/AArch64/neon-scalar-dup.s b/test/MC/AArch64/neon-scalar-dup.s index 77c638d..db11ea2 100644 --- a/test/MC/AArch64/neon-scalar-dup.s +++ b/test/MC/AArch64/neon-scalar-dup.s @@ -15,17 +15,17 @@ dup d3, v5.d[0] dup d6, v5.d[1] -// CHECK: dup b0, v0.b[15] // encoding: [0x00,0x04,0x1f,0x5e] -// CHECK: dup b1, v0.b[7] // encoding: [0x01,0x04,0x0f,0x5e] -// CHECK: dup b17, v0.b[0] // encoding: [0x11,0x04,0x01,0x5e] -// CHECK: dup h5, v31.h[7] // encoding: [0xe5,0x07,0x1e,0x5e] -// CHECK: dup h9, v1.h[4] // encoding: [0x29,0x04,0x12,0x5e] -// CHECK: dup h11, v17.h[0] // encoding: [0x2b,0x06,0x02,0x5e] -// CHECK: dup s2, v2.s[3] // encoding: [0x42,0x04,0x1c,0x5e] -// CHECK: dup s4, v21.s[0] // encoding: [0xa4,0x06,0x04,0x5e] -// CHECK: dup s31, v21.s[2] // encoding: [0xbf,0x06,0x14,0x5e] -// CHECK: dup d3, v5.d[0] // encoding: [0xa3,0x04,0x08,0x5e] -// CHECK: dup d6, v5.d[1] // encoding: [0xa6,0x04,0x18,0x5e] +// CHECK: {{dup|mov}} b0, v0.b[15] // encoding: [0x00,0x04,0x1f,0x5e] +// CHECK: {{dup|mov}} b1, v0.b[7] // encoding: [0x01,0x04,0x0f,0x5e] +// CHECK: {{dup|mov}} b17, v0.b[0] // encoding: [0x11,0x04,0x01,0x5e] +// CHECK: {{dup|mov}} h5, v31.h[7] // encoding: [0xe5,0x07,0x1e,0x5e] +// CHECK: {{dup|mov}} h9, v1.h[4] // encoding: [0x29,0x04,0x12,0x5e] +// CHECK: {{dup|mov}} h11, v17.h[0] // encoding: [0x2b,0x06,0x02,0x5e] +// CHECK: {{dup|mov}} s2, v2.s[3] // encoding: [0x42,0x04,0x1c,0x5e] +// CHECK: {{dup|mov}} s4, v21.s[0] // encoding: [0xa4,0x06,0x04,0x5e] +// CHECK: {{dup|mov}} s31, v21.s[2] // encoding: [0xbf,0x06,0x14,0x5e] +// CHECK: {{dup|mov}} d3, v5.d[0] // encoding: [0xa3,0x04,0x08,0x5e] +// CHECK: {{dup|mov}} d6, v5.d[1] // encoding: [0xa6,0x04,0x18,0x5e] //------------------------------------------------------------------------------ // Aliases for Duplicate element (scalar) @@ -42,14 +42,14 @@ mov d3, v5.d[0] mov d6, v5.d[1] -// CHECK: dup b0, v0.b[15] // encoding: [0x00,0x04,0x1f,0x5e] -// CHECK: dup b1, v0.b[7] // encoding: [0x01,0x04,0x0f,0x5e] -// CHECK: dup b17, v0.b[0] // encoding: [0x11,0x04,0x01,0x5e] -// CHECK: dup h5, v31.h[7] // encoding: [0xe5,0x07,0x1e,0x5e] -// CHECK: dup h9, v1.h[4] // encoding: [0x29,0x04,0x12,0x5e] -// CHECK: dup h11, v17.h[0] // encoding: [0x2b,0x06,0x02,0x5e] -// CHECK: dup s2, v2.s[3] // encoding: [0x42,0x04,0x1c,0x5e] -// CHECK: dup s4, v21.s[0] // encoding: [0xa4,0x06,0x04,0x5e] -// CHECK: dup s31, v21.s[2] // encoding: [0xbf,0x06,0x14,0x5e] -// CHECK: dup d3, v5.d[0] // encoding: [0xa3,0x04,0x08,0x5e] -// CHECK: dup d6, v5.d[1] // encoding: [0xa6,0x04,0x18,0x5e] +// CHECK: {{dup|mov}} b0, v0.b[15] // encoding: [0x00,0x04,0x1f,0x5e] +// CHECK: {{dup|mov}} b1, v0.b[7] // encoding: [0x01,0x04,0x0f,0x5e] +// CHECK: {{dup|mov}} b17, v0.b[0] // encoding: [0x11,0x04,0x01,0x5e] +// CHECK: {{dup|mov}} h5, v31.h[7] // encoding: [0xe5,0x07,0x1e,0x5e] +// CHECK: {{dup|mov}} h9, v1.h[4] // encoding: [0x29,0x04,0x12,0x5e] +// CHECK: {{dup|mov}} h11, v17.h[0] // encoding: [0x2b,0x06,0x02,0x5e] +// CHECK: {{dup|mov}} s2, v2.s[3] // encoding: [0x42,0x04,0x1c,0x5e] +// CHECK: {{dup|mov}} s4, v21.s[0] // encoding: [0xa4,0x06,0x04,0x5e] +// CHECK: {{dup|mov}} s31, v21.s[2] // encoding: [0xbf,0x06,0x14,0x5e] +// CHECK: {{dup|mov}} d3, v5.d[0] // encoding: [0xa3,0x04,0x08,0x5e] +// CHECK: {{dup|mov}} d6, v5.d[1] // encoding: [0xa6,0x04,0x18,0x5e] diff --git a/test/MC/AArch64/neon-simd-copy.s b/test/MC/AArch64/neon-simd-copy.s index f254d65..4837a4c 100644 --- a/test/MC/AArch64/neon-simd-copy.s +++ b/test/MC/AArch64/neon-simd-copy.s @@ -16,15 +16,15 @@ mov v20.s[0], w30 mov v1.d[1], x7 -// CHECK: ins v2.b[2], w1 // encoding: [0x22,0x1c,0x05,0x4e] -// CHECK: ins v7.h[7], w14 // encoding: [0xc7,0x1d,0x1e,0x4e] -// CHECK: ins v20.s[0], w30 // encoding: [0xd4,0x1f,0x04,0x4e] -// CHECK: ins v1.d[1], x7 // encoding: [0xe1,0x1c,0x18,0x4e] +// CHECK: {{mov|ins}} v2.b[2], w1 // encoding: [0x22,0x1c,0x05,0x4e] +// CHECK: {{mov|ins}} v7.h[7], w14 // encoding: [0xc7,0x1d,0x1e,0x4e] +// CHECK: {{mov|ins}} v20.s[0], w30 // encoding: [0xd4,0x1f,0x04,0x4e] +// CHECK: {{mov|ins}} v1.d[1], x7 // encoding: [0xe1,0x1c,0x18,0x4e] -// CHECK: ins v2.b[2], w1 // encoding: [0x22,0x1c,0x05,0x4e] -// CHECK: ins v7.h[7], w14 // encoding: [0xc7,0x1d,0x1e,0x4e] -// CHECK: ins v20.s[0], w30 // encoding: [0xd4,0x1f,0x04,0x4e] -// CHECK: ins v1.d[1], x7 // encoding: [0xe1,0x1c,0x18,0x4e] +// CHECK: {{mov|ins}} v2.b[2], w1 // encoding: [0x22,0x1c,0x05,0x4e] +// CHECK: {{mov|ins}} v7.h[7], w14 // encoding: [0xc7,0x1d,0x1e,0x4e] +// CHECK: {{mov|ins}} v20.s[0], w30 // encoding: [0xd4,0x1f,0x04,0x4e] +// CHECK: {{mov|ins}} v1.d[1], x7 // encoding: [0xe1,0x1c,0x18,0x4e] //------------------------------------------------------------------------------ @@ -54,13 +54,13 @@ mov w20, v9.s[2] mov x7, v18.d[1] -// CHECK: umov w1, v0.b[15] // encoding: [0x01,0x3c,0x1f,0x0e] -// CHECK: umov w14, v6.h[4] // encoding: [0xce,0x3c,0x12,0x0e] -// CHECK: umov w20, v9.s[2] // encoding: [0x34,0x3d,0x14,0x0e] -// CHECK: umov x7, v18.d[1] // encoding: [0x47,0x3e,0x18,0x4e] +// CHECK: {{mov|umov}} w1, v0.b[15] // encoding: [0x01,0x3c,0x1f,0x0e] +// CHECK: {{mov|umov}} w14, v6.h[4] // encoding: [0xce,0x3c,0x12,0x0e] +// CHECK: {{mov|umov}} w20, v9.s[2] // encoding: [0x34,0x3d,0x14,0x0e] +// CHECK: {{mov|umov}} x7, v18.d[1] // encoding: [0x47,0x3e,0x18,0x4e] -// CHECK: umov w20, v9.s[2] // encoding: [0x34,0x3d,0x14,0x0e] -// CHECK: umov x7, v18.d[1] // encoding: [0x47,0x3e,0x18,0x4e] +// CHECK: {{mov|umov}} w20, v9.s[2] // encoding: [0x34,0x3d,0x14,0x0e] +// CHECK: {{mov|umov}} x7, v18.d[1] // encoding: [0x47,0x3e,0x18,0x4e] //------------------------------------------------------------------------------ // Insert element (vector, from element) @@ -76,15 +76,15 @@ mov v15.s[3], v22.s[2] mov v0.d[0], v4.d[1] -// CHECK: ins v1.b[14], v3.b[6] // encoding: [0x61,0x34,0x1d,0x6e] -// CHECK: ins v6.h[7], v7.h[5] // encoding: [0xe6,0x54,0x1e,0x6e] -// CHECK: ins v15.s[3], v22.s[2] // encoding: [0xcf,0x46,0x1c,0x6e] -// CHECK: ins v0.d[0], v4.d[1] // encoding: [0x80,0x44,0x08,0x6e] +// CHECK: {{mov|ins}} v1.b[14], v3.b[6] // encoding: [0x61,0x34,0x1d,0x6e] +// CHECK: {{mov|ins}} v6.h[7], v7.h[5] // encoding: [0xe6,0x54,0x1e,0x6e] +// CHECK: {{mov|ins}} v15.s[3], v22.s[2] // encoding: [0xcf,0x46,0x1c,0x6e] +// CHECK: {{mov|ins}} v0.d[0], v4.d[1] // encoding: [0x80,0x44,0x08,0x6e] -// CHECK: ins v1.b[14], v3.b[6] // encoding: [0x61,0x34,0x1d,0x6e] -// CHECK: ins v6.h[7], v7.h[5] // encoding: [0xe6,0x54,0x1e,0x6e] -// CHECK: ins v15.s[3], v22.s[2] // encoding: [0xcf,0x46,0x1c,0x6e] -// CHECK: ins v0.d[0], v4.d[1] // encoding: [0x80,0x44,0x08,0x6e] +// CHECK: {{mov|ins}} v1.b[14], v3.b[6] // encoding: [0x61,0x34,0x1d,0x6e] +// CHECK: {{mov|ins}} v6.h[7], v7.h[5] // encoding: [0xe6,0x54,0x1e,0x6e] +// CHECK: {{mov|ins}} v15.s[3], v22.s[2] // encoding: [0xcf,0x46,0x1c,0x6e] +// CHECK: {{mov|ins}} v0.d[0], v4.d[1] // encoding: [0x80,0x44,0x08,0x6e] //------------------------------------------------------------------------------ // Duplicate to all lanes( vector, from element) @@ -97,13 +97,13 @@ dup v17.4s, v20.s[0] dup v5.2d, v1.d[1] -// CHECK: dup v1.8b, v2.b[2] // encoding: [0x41,0x04,0x05,0x0e] -// CHECK: dup v11.4h, v7.h[7] // encoding: [0xeb,0x04,0x1e,0x0e] -// CHECK: dup v17.2s, v20.s[0] // encoding: [0x91,0x06,0x04,0x0e] -// CHECK: dup v1.16b, v2.b[2] // encoding: [0x41,0x04,0x05,0x4e] -// CHECK: dup v11.8h, v7.h[7] // encoding: [0xeb,0x04,0x1e,0x4e] -// CHECK: dup v17.4s, v20.s[0] // encoding: [0x91,0x06,0x04,0x4e] -// CHECK: dup v5.2d, v1.d[1] // encoding: [0x25,0x04,0x18,0x4e] +// CHECK: {{mov|dup}} v1.8b, v2.b[2] // encoding: [0x41,0x04,0x05,0x0e] +// CHECK: {{mov|dup}} v11.4h, v7.h[7] // encoding: [0xeb,0x04,0x1e,0x0e] +// CHECK: {{mov|dup}} v17.2s, v20.s[0] // encoding: [0x91,0x06,0x04,0x0e] +// CHECK: {{mov|dup}} v1.16b, v2.b[2] // encoding: [0x41,0x04,0x05,0x4e] +// CHECK: {{mov|dup}} v11.8h, v7.h[7] // encoding: [0xeb,0x04,0x1e,0x4e] +// CHECK: {{mov|dup}} v17.4s, v20.s[0] // encoding: [0x91,0x06,0x04,0x4e] +// CHECK: {{mov|dup}} v5.2d, v1.d[1] // encoding: [0x25,0x04,0x18,0x4e] //------------------------------------------------------------------------------ // Duplicate to all lanes( vector, from main) @@ -116,13 +116,13 @@ dup v17.4s, w28 dup v5.2d, x0 -// CHECK: dup v1.8b, w1 // encoding: [0x21,0x0c,0x01,0x0e] -// CHECK: dup v11.4h, w14 // encoding: [0xcb,0x0d,0x02,0x0e] -// CHECK: dup v17.2s, w30 // encoding: [0xd1,0x0f,0x04,0x0e] -// CHECK: dup v1.16b, w2 // encoding: [0x41,0x0c,0x01,0x4e] -// CHECK: dup v11.8h, w16 // encoding: [0x0b,0x0e,0x02,0x4e] -// CHECK: dup v17.4s, w28 // encoding: [0x91,0x0f,0x04,0x4e] -// CHECK: dup v5.2d, x0 // encoding: [0x05,0x0c,0x08,0x4e] +// CHECK: {{mov|dup}} v1.8b, w1 // encoding: [0x21,0x0c,0x01,0x0e] +// CHECK: {{mov|dup}} v11.4h, w14 // encoding: [0xcb,0x0d,0x02,0x0e] +// CHECK: {{mov|dup}} v17.2s, w30 // encoding: [0xd1,0x0f,0x04,0x0e] +// CHECK: {{mov|dup}} v1.16b, w2 // encoding: [0x41,0x0c,0x01,0x4e] +// CHECK: {{mov|dup}} v11.8h, w16 // encoding: [0x0b,0x0e,0x02,0x4e] +// CHECK: {{mov|dup}} v17.4s, w28 // encoding: [0x91,0x0f,0x04,0x4e] +// CHECK: {{mov|dup}} v5.2d, x0 // encoding: [0x05,0x0c,0x08,0x4e] diff --git a/test/MC/AArch64/neon-simd-ldst-multi-elem.s b/test/MC/AArch64/neon-simd-ldst-multi-elem.s index 05fe4da..b8b3e72 100644 --- a/test/MC/AArch64/neon-simd-ldst-multi-elem.s +++ b/test/MC/AArch64/neon-simd-ldst-multi-elem.s @@ -1,463 +1,463 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 //------------------------------------------------------------------------------ // Store multiple 1-element structures from one register //------------------------------------------------------------------------------ - st1 {v0.16b}, [x0] - st1 {v15.8h}, [x15] - st1 {v31.4s}, [sp] - st1 {v0.2d}, [x0] - st1 {v0.8b}, [x0] - st1 {v15.4h}, [x15] - st1 {v31.2s}, [sp] - st1 {v0.1d}, [x0] -// CHECK: st1 {v0.16b}, [x0] // encoding: [0x00,0x70,0x00,0x4c] -// CHECK: st1 {v15.8h}, [x15] // encoding: [0xef,0x75,0x00,0x4c] -// CHECK: st1 {v31.4s}, [sp] // encoding: [0xff,0x7b,0x00,0x4c] -// CHECK: st1 {v0.2d}, [x0] // encoding: [0x00,0x7c,0x00,0x4c] -// CHECK: st1 {v0.8b}, [x0] // encoding: [0x00,0x70,0x00,0x0c] -// CHECK: st1 {v15.4h}, [x15] // encoding: [0xef,0x75,0x00,0x0c] -// CHECK: st1 {v31.2s}, [sp] // encoding: [0xff,0x7b,0x00,0x0c] -// CHECK: st1 {v0.1d}, [x0] // encoding: [0x00,0x7c,0x00,0x0c] + st1 { v0.16b }, [x0] + st1 { v15.8h }, [x15] + st1 { v31.4s }, [sp] + st1 { v0.2d }, [x0] + st1 { v0.8b }, [x0] + st1 { v15.4h }, [x15] + st1 { v31.2s }, [sp] + st1 { v0.1d }, [x0] +// CHECK: st1 { v0.16b }, [x0] // encoding: [0x00,0x70,0x00,0x4c] +// CHECK: st1 { v15.8h }, [x15] // encoding: [0xef,0x75,0x00,0x4c] +// CHECK: st1 { v31.4s }, [sp] // encoding: [0xff,0x7b,0x00,0x4c] +// CHECK: st1 { v0.2d }, [x0] // encoding: [0x00,0x7c,0x00,0x4c] +// CHECK: st1 { v0.8b }, [x0] // encoding: [0x00,0x70,0x00,0x0c] +// CHECK: st1 { v15.4h }, [x15] // encoding: [0xef,0x75,0x00,0x0c] +// CHECK: st1 { v31.2s }, [sp] // encoding: [0xff,0x7b,0x00,0x0c] +// CHECK: st1 { v0.1d }, [x0] // encoding: [0x00,0x7c,0x00,0x0c] //------------------------------------------------------------------------------ // Store multiple 1-element structures from two consecutive registers //------------------------------------------------------------------------------ - st1 {v0.16b, v1.16b}, [x0] - st1 {v15.8h, v16.8h}, [x15] - st1 {v31.4s, v0.4s}, [sp] - st1 {v0.2d, v1.2d}, [x0] - st1 {v0.8b, v1.8b}, [x0] - st1 {v15.4h, v16.4h}, [x15] - st1 {v31.2s, v0.2s}, [sp] - st1 {v0.1d, v1.1d}, [x0] -// CHECK: st1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x00,0x4c] -// CHECK: st1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x00,0x4c] -// CHECK: st1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x00,0x4c] -// CHECK: st1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x00,0x4c] -// CHECK: st1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x00,0x0c] -// CHECK: st1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x00,0x0c] -// CHECK: st1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x00,0x0c] -// CHECK: st1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x00,0x0c] + st1 { v0.16b, v1.16b }, [x0] + st1 { v15.8h, v16.8h }, [x15] + st1 { v31.4s, v0.4s }, [sp] + st1 { v0.2d, v1.2d }, [x0] + st1 { v0.8b, v1.8b }, [x0] + st1 { v15.4h, v16.4h }, [x15] + st1 { v31.2s, v0.2s }, [sp] + st1 { v0.1d, v1.1d }, [x0] +// CHECK: st1 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xa0,0x00,0x4c] +// CHECK: st1 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xa5,0x00,0x4c] +// CHECK: st1 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xab,0x00,0x4c] +// CHECK: st1 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xac,0x00,0x4c] +// CHECK: st1 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xa0,0x00,0x0c] +// CHECK: st1 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xa5,0x00,0x0c] +// CHECK: st1 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xab,0x00,0x0c] +// CHECK: st1 { v0.1d, v1.1d }, [x0] // encoding: [0x00,0xac,0x00,0x0c] - st1 {v0.16b-v1.16b}, [x0] - st1 {v15.8h-v16.8h}, [x15] - st1 {v31.4s-v0.4s}, [sp] - st1 {v0.2d-v1.2d}, [x0] - st1 {v0.8b-v1.8b}, [x0] - st1 {v15.4h-v16.4h}, [x15] - st1 {v31.2s-v0.2s}, [sp] - st1 {v0.1d-v1.1d}, [x0] -// CHECK: st1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x00,0x4c] -// CHECK: st1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x00,0x4c] -// CHECK: st1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x00,0x4c] -// CHECK: st1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x00,0x4c] -// CHECK: st1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x00,0x0c] -// CHECK: st1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x00,0x0c] -// CHECK: st1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x00,0x0c] -// CHECK: st1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x00,0x0c] + st1 { v0.16b-v1.16b }, [x0] + st1 { v15.8h-v16.8h }, [x15] + st1 { v31.4s-v0.4s }, [sp] + st1 { v0.2d-v1.2d }, [x0] + st1 { v0.8b-v1.8b }, [x0] + st1 { v15.4h-v16.4h }, [x15] + st1 { v31.2s-v0.2s }, [sp] + st1 { v0.1d-v1.1d }, [x0] +// CHECK: st1 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xa0,0x00,0x4c] +// CHECK: st1 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xa5,0x00,0x4c] +// CHECK: st1 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xab,0x00,0x4c] +// CHECK: st1 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xac,0x00,0x4c] +// CHECK: st1 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xa0,0x00,0x0c] +// CHECK: st1 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xa5,0x00,0x0c] +// CHECK: st1 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xab,0x00,0x0c] +// CHECK: st1 { v0.1d, v1.1d }, [x0] // encoding: [0x00,0xac,0x00,0x0c] //------------------------------------------------------------------------------ // Store multiple 1-element structures from three consecutive registers //------------------------------------------------------------------------------ - st1 {v0.16b, v1.16b, v2.16b}, [x0] - st1 {v15.8h, v16.8h, v17.8h}, [x15] - st1 {v31.4s, v0.4s, v1.4s}, [sp] - st1 {v0.2d, v1.2d, v2.2d}, [x0] - st1 {v0.8b, v1.8b, v2.8b}, [x0] - st1 {v15.4h, v16.4h, v17.4h}, [x15] - st1 {v31.2s, v0.2s, v1.2s}, [sp] - st1 {v0.1d, v1.1d, v2.1d}, [x0] -// CHECK: st1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x00,0x4c] -// CHECK: st1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x00,0x4c] -// CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x00,0x4c] -// CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x00,0x4c] -// CHECK: st1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x00,0x0c] -// CHECK: st1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x00,0x0c] -// CHECK: st1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x00,0x0c] -// CHECK: st1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x00,0x0c] + st1 { v0.16b, v1.16b, v2.16b }, [x0] + st1 { v15.8h, v16.8h, v17.8h }, [x15] + st1 { v31.4s, v0.4s, v1.4s }, [sp] + st1 { v0.2d, v1.2d, v2.2d }, [x0] + st1 { v0.8b, v1.8b, v2.8b }, [x0] + st1 { v15.4h, v16.4h, v17.4h }, [x15] + st1 { v31.2s, v0.2s, v1.2s }, [sp] + st1 { v0.1d, v1.1d, v2.1d }, [x0] +// CHECK: st1 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x60,0x00,0x4c] +// CHECK: st1 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x65,0x00,0x4c] +// CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x6b,0x00,0x4c] +// CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x6c,0x00,0x4c] +// CHECK: st1 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x60,0x00,0x0c] +// CHECK: st1 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x65,0x00,0x0c] +// CHECK: st1 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x6b,0x00,0x0c] +// CHECK: st1 { v0.1d, v1.1d, v2.1d }, [x0] // encoding: [0x00,0x6c,0x00,0x0c] - st1 {v0.16b-v2.16b}, [x0] - st1 {v15.8h-v17.8h}, [x15] - st1 {v31.4s-v1.4s}, [sp] - st1 {v0.2d-v2.2d}, [x0] - st1 {v0.8b-v2.8b}, [x0] - st1 {v15.4h-v17.4h}, [x15] - st1 {v31.2s-v1.2s}, [sp] - st1 {v0.1d-v2.1d}, [x0] -// CHECK: st1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x00,0x4c] -// CHECK: st1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x00,0x4c] -// CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x00,0x4c] -// CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x00,0x4c] -// CHECK: st1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x00,0x0c] -// CHECK: st1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x00,0x0c] -// CHECK: st1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x00,0x0c] -// CHECK: st1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x00,0x0c] + st1 { v0.16b-v2.16b }, [x0] + st1 { v15.8h-v17.8h }, [x15] + st1 { v31.4s-v1.4s }, [sp] + st1 { v0.2d-v2.2d }, [x0] + st1 { v0.8b-v2.8b }, [x0] + st1 { v15.4h-v17.4h }, [x15] + st1 { v31.2s-v1.2s }, [sp] + st1 { v0.1d-v2.1d }, [x0] +// CHECK: st1 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x60,0x00,0x4c] +// CHECK: st1 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x65,0x00,0x4c] +// CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x6b,0x00,0x4c] +// CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x6c,0x00,0x4c] +// CHECK: st1 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x60,0x00,0x0c] +// CHECK: st1 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x65,0x00,0x0c] +// CHECK: st1 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x6b,0x00,0x0c] +// CHECK: st1 { v0.1d, v1.1d, v2.1d }, [x0] // encoding: [0x00,0x6c,0x00,0x0c] //------------------------------------------------------------------------------ // Store multiple 1-element structures from four consecutive registers //------------------------------------------------------------------------------ - st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] - st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] - st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] - st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] - st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] - st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] - st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] - st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] -// CHECK: st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x00,0x4c] -// CHECK: st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x00,0x4c] -// CHECK: st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x00,0x4c] -// CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x00,0x4c] -// CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x00,0x0c] -// CHECK: st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x00,0x0c] -// CHECK: st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x00,0x0c] -// CHECK: st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x00,0x0c] + st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] + st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] + st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] + st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] + st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] + st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] + st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] + st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] +// CHECK: st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x20,0x00,0x4c] +// CHECK: st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x25,0x00,0x4c] +// CHECK: st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x2b,0x00,0x4c] +// CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x2c,0x00,0x4c] +// CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x20,0x00,0x0c] +// CHECK: st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x25,0x00,0x0c] +// CHECK: st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x2b,0x00,0x0c] +// CHECK: st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] // encoding: [0x00,0x2c,0x00,0x0c] - st1 {v0.16b-v3.16b}, [x0] - st1 {v15.8h-v18.8h}, [x15] - st1 {v31.4s-v2.4s}, [sp] - st1 {v0.2d-v3.2d}, [x0] - st1 {v0.8b-v3.8b}, [x0] - st1 {v15.4h-v18.4h}, [x15] - st1 {v31.2s-v2.2s}, [sp] - st1 {v0.1d-v3.1d}, [x0] -// CHECK: st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x00,0x4c] -// CHECK: st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x00,0x4c] -// CHECK: st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x00,0x4c] -// CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x00,0x4c] -// CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x00,0x0c] -// CHECK: st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x00,0x0c] -// CHECK: st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x00,0x0c] -// CHECK: st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x00,0x0c] + st1 { v0.16b-v3.16b }, [x0] + st1 { v15.8h-v18.8h }, [x15] + st1 { v31.4s-v2.4s }, [sp] + st1 { v0.2d-v3.2d }, [x0] + st1 { v0.8b-v3.8b }, [x0] + st1 { v15.4h-v18.4h }, [x15] + st1 { v31.2s-v2.2s }, [sp] + st1 { v0.1d-v3.1d }, [x0] +// CHECK: st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x20,0x00,0x4c] +// CHECK: st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x25,0x00,0x4c] +// CHECK: st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x2b,0x00,0x4c] +// CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x2c,0x00,0x4c] +// CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x20,0x00,0x0c] +// CHECK: st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x25,0x00,0x0c] +// CHECK: st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x2b,0x00,0x0c] +// CHECK: st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] // encoding: [0x00,0x2c,0x00,0x0c] //------------------------------------------------------------------------------ // Store multiple 2-element structures from two consecutive registers //------------------------------------------------------------------------------ - st2 {v0.16b, v1.16b}, [x0] - st2 {v15.8h, v16.8h}, [x15] - st2 {v31.4s, v0.4s}, [sp] - st2 {v0.2d, v1.2d}, [x0] - st2 {v0.8b, v1.8b}, [x0] - st2 {v15.4h, v16.4h}, [x15] - st2 {v31.2s, v0.2s}, [sp] -// CHECK: st2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x00,0x4c] -// CHECK: st2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x00,0x4c] -// CHECK: st2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x00,0x4c] -// CHECK: st2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x00,0x4c] -// CHECK: st2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x00,0x0c] -// CHECK: st2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x00,0x0c] -// CHECK: st2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x00,0x0c] + st2 { v0.16b, v1.16b }, [x0] + st2 { v15.8h, v16.8h }, [x15] + st2 { v31.4s, v0.4s }, [sp] + st2 { v0.2d, v1.2d }, [x0] + st2 { v0.8b, v1.8b }, [x0] + st2 { v15.4h, v16.4h }, [x15] + st2 { v31.2s, v0.2s }, [sp] +// CHECK: st2 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0x80,0x00,0x4c] +// CHECK: st2 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0x85,0x00,0x4c] +// CHECK: st2 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0x8b,0x00,0x4c] +// CHECK: st2 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0x8c,0x00,0x4c] +// CHECK: st2 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0x80,0x00,0x0c] +// CHECK: st2 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0x85,0x00,0x0c] +// CHECK: st2 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0x8b,0x00,0x0c] - st2 {v0.16b-v1.16b}, [x0] - st2 {v15.8h-v16.8h}, [x15] - st2 {v31.4s-v0.4s}, [sp] - st2 {v0.2d-v1.2d}, [x0] - st2 {v0.8b-v1.8b}, [x0] - st2 {v15.4h-v16.4h}, [x15] - st2 {v31.2s-v0.2s}, [sp] -// CHECK: st2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x00,0x4c] -// CHECK: st2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x00,0x4c] -// CHECK: st2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x00,0x4c] -// CHECK: st2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x00,0x4c] -// CHECK: st2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x00,0x0c] -// CHECK: st2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x00,0x0c] -// CHECK: st2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x00,0x0c] + st2 { v0.16b-v1.16b }, [x0] + st2 { v15.8h-v16.8h }, [x15] + st2 { v31.4s-v0.4s }, [sp] + st2 { v0.2d-v1.2d }, [x0] + st2 { v0.8b-v1.8b }, [x0] + st2 { v15.4h-v16.4h }, [x15] + st2 { v31.2s-v0.2s }, [sp] +// CHECK: st2 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0x80,0x00,0x4c] +// CHECK: st2 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0x85,0x00,0x4c] +// CHECK: st2 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0x8b,0x00,0x4c] +// CHECK: st2 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0x8c,0x00,0x4c] +// CHECK: st2 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0x80,0x00,0x0c] +// CHECK: st2 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0x85,0x00,0x0c] +// CHECK: st2 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0x8b,0x00,0x0c] //------------------------------------------------------------------------------ // Store multiple 3-element structures from three consecutive registers //------------------------------------------------------------------------------ - st3 {v0.16b, v1.16b, v2.16b}, [x0] - st3 {v15.8h, v16.8h, v17.8h}, [x15] - st3 {v31.4s, v0.4s, v1.4s}, [sp] - st3 {v0.2d, v1.2d, v2.2d}, [x0] - st3 {v0.8b, v1.8b, v2.8b}, [x0] - st3 {v15.4h, v16.4h, v17.4h}, [x15] - st3 {v31.2s, v0.2s, v1.2s}, [sp] -// CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x00,0x4c] -// CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x00,0x4c] -// CHECK: st3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x00,0x4c] -// CHECK: st3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x00,0x4c] -// CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x00,0x0c] -// CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x00,0x0c] -// CHECK: st3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x00,0x0c] + st3 { v0.16b, v1.16b, v2.16b }, [x0] + st3 { v15.8h, v16.8h, v17.8h }, [x15] + st3 { v31.4s, v0.4s, v1.4s }, [sp] + st3 { v0.2d, v1.2d, v2.2d }, [x0] + st3 { v0.8b, v1.8b, v2.8b }, [x0] + st3 { v15.4h, v16.4h, v17.4h }, [x15] + st3 { v31.2s, v0.2s, v1.2s }, [sp] +// CHECK: st3 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x40,0x00,0x4c] +// CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x45,0x00,0x4c] +// CHECK: st3 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x4b,0x00,0x4c] +// CHECK: st3 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x4c,0x00,0x4c] +// CHECK: st3 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x40,0x00,0x0c] +// CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x45,0x00,0x0c] +// CHECK: st3 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x4b,0x00,0x0c] - st3 {v0.16b-v2.16b}, [x0] - st3 {v15.8h-v17.8h}, [x15] - st3 {v31.4s-v1.4s}, [sp] - st3 {v0.2d-v2.2d}, [x0] - st3 {v0.8b-v2.8b}, [x0] - st3 {v15.4h-v17.4h}, [x15] - st3 {v31.2s-v1.2s}, [sp] -// CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x00,0x4c] -// CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x00,0x4c] -// CHECK: st3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x00,0x4c] -// CHECK: st3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x00,0x4c] -// CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x00,0x0c] -// CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x00,0x0c] -// CHECK: st3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x00,0x0c] + st3 { v0.16b-v2.16b }, [x0] + st3 { v15.8h-v17.8h }, [x15] + st3 { v31.4s-v1.4s }, [sp] + st3 { v0.2d-v2.2d }, [x0] + st3 { v0.8b-v2.8b }, [x0] + st3 { v15.4h-v17.4h }, [x15] + st3 { v31.2s-v1.2s }, [sp] +// CHECK: st3 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x40,0x00,0x4c] +// CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x45,0x00,0x4c] +// CHECK: st3 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x4b,0x00,0x4c] +// CHECK: st3 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x4c,0x00,0x4c] +// CHECK: st3 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x40,0x00,0x0c] +// CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x45,0x00,0x0c] +// CHECK: st3 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x4b,0x00,0x0c] //------------------------------------------------------------------------------ // Store multiple 4-element structures from four consecutive registers //------------------------------------------------------------------------------ - st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] - st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] - st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] - st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] - st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] - st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] - st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] -// CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x00,0x4c] -// CHECK: st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x00,0x4c] -// CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x00,0x4c] -// CHECK: st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x00,0x4c] -// CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x00,0x0c] -// CHECK: st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x00,0x0c] -// CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x00,0x0c] + st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] + st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] + st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] + st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] + st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] + st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] + st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] +// CHECK: st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x00,0x00,0x4c] +// CHECK: st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x05,0x00,0x4c] +// CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x0b,0x00,0x4c] +// CHECK: st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x0c,0x00,0x4c] +// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x00,0x0c] +// CHECK: st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x05,0x00,0x0c] +// CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x0b,0x00,0x0c] - st4 {v0.16b-v3.16b}, [x0] - st4 {v15.8h-v18.8h}, [x15] - st4 {v31.4s-v2.4s}, [sp] - st4 {v0.2d-v3.2d}, [x0] - st4 {v0.8b-v3.8b}, [x0] - st4 {v15.4h-v18.4h}, [x15] - st4 {v31.2s-v2.2s}, [sp] -// CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x00,0x4c] -// CHECK: st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x00,0x4c] -// CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x00,0x4c] -// CHECK: st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x00,0x4c] -// CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x00,0x0c] -// CHECK: st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x00,0x0c] -// CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x00,0x0c] + st4 { v0.16b-v3.16b }, [x0] + st4 { v15.8h-v18.8h }, [x15] + st4 { v31.4s-v2.4s }, [sp] + st4 { v0.2d-v3.2d }, [x0] + st4 { v0.8b-v3.8b }, [x0] + st4 { v15.4h-v18.4h }, [x15] + st4 { v31.2s-v2.2s }, [sp] +// CHECK: st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x00,0x00,0x4c] +// CHECK: st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x05,0x00,0x4c] +// CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x0b,0x00,0x4c] +// CHECK: st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x0c,0x00,0x4c] +// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x00,0x0c] +// CHECK: st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x05,0x00,0x0c] +// CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x0b,0x00,0x0c] //------------------------------------------------------------------------------ // Load multiple 1-element structures to one register //------------------------------------------------------------------------------ - ld1 {v0.16b}, [x0] - ld1 {v15.8h}, [x15] - ld1 {v31.4s}, [sp] - ld1 {v0.2d}, [x0] - ld1 {v0.8b}, [x0] - ld1 {v15.4h}, [x15] - ld1 {v31.2s}, [sp] - ld1 {v0.1d}, [x0] -// CHECK: ld1 {v0.16b}, [x0] // encoding: [0x00,0x70,0x40,0x4c] -// CHECK: ld1 {v15.8h}, [x15] // encoding: [0xef,0x75,0x40,0x4c] -// CHECK: ld1 {v31.4s}, [sp] // encoding: [0xff,0x7b,0x40,0x4c] -// CHECK: ld1 {v0.2d}, [x0] // encoding: [0x00,0x7c,0x40,0x4c] -// CHECK: ld1 {v0.8b}, [x0] // encoding: [0x00,0x70,0x40,0x0c] -// CHECK: ld1 {v15.4h}, [x15] // encoding: [0xef,0x75,0x40,0x0c] -// CHECK: ld1 {v31.2s}, [sp] // encoding: [0xff,0x7b,0x40,0x0c] -// CHECK: ld1 {v0.1d}, [x0] // encoding: [0x00,0x7c,0x40,0x0c] + ld1 { v0.16b }, [x0] + ld1 { v15.8h }, [x15] + ld1 { v31.4s }, [sp] + ld1 { v0.2d }, [x0] + ld1 { v0.8b }, [x0] + ld1 { v15.4h }, [x15] + ld1 { v31.2s }, [sp] + ld1 { v0.1d }, [x0] +// CHECK: ld1 { v0.16b }, [x0] // encoding: [0x00,0x70,0x40,0x4c] +// CHECK: ld1 { v15.8h }, [x15] // encoding: [0xef,0x75,0x40,0x4c] +// CHECK: ld1 { v31.4s }, [sp] // encoding: [0xff,0x7b,0x40,0x4c] +// CHECK: ld1 { v0.2d }, [x0] // encoding: [0x00,0x7c,0x40,0x4c] +// CHECK: ld1 { v0.8b }, [x0] // encoding: [0x00,0x70,0x40,0x0c] +// CHECK: ld1 { v15.4h }, [x15] // encoding: [0xef,0x75,0x40,0x0c] +// CHECK: ld1 { v31.2s }, [sp] // encoding: [0xff,0x7b,0x40,0x0c] +// CHECK: ld1 { v0.1d }, [x0] // encoding: [0x00,0x7c,0x40,0x0c] //------------------------------------------------------------------------------ // Load multiple 1-element structures to two consecutive registers //------------------------------------------------------------------------------ - ld1 {v0.16b, v1.16b}, [x0] - ld1 {v15.8h, v16.8h}, [x15] - ld1 {v31.4s, v0.4s}, [sp] - ld1 {v0.2d, v1.2d}, [x0] - ld1 {v0.8b, v1.8b}, [x0] - ld1 {v15.4h, v16.4h}, [x15] - ld1 {v31.2s, v0.2s}, [sp] - ld1 {v0.1d, v1.1d}, [x0] -// CHECK: ld1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x40,0x4c] -// CHECK: ld1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x40,0x4c] -// CHECK: ld1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x40,0x4c] -// CHECK: ld1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x40,0x4c] -// CHECK: ld1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x40,0x0c] -// CHECK: ld1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x40,0x0c] -// CHECK: ld1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x40,0x0c] -// CHECK: ld1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x40,0x0c] + ld1 { v0.16b, v1.16b }, [x0] + ld1 { v15.8h, v16.8h }, [x15] + ld1 { v31.4s, v0.4s }, [sp] + ld1 { v0.2d, v1.2d }, [x0] + ld1 { v0.8b, v1.8b }, [x0] + ld1 { v15.4h, v16.4h }, [x15] + ld1 { v31.2s, v0.2s }, [sp] + ld1 { v0.1d, v1.1d }, [x0] +// CHECK: ld1 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xa0,0x40,0x4c] +// CHECK: ld1 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xa5,0x40,0x4c] +// CHECK: ld1 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xab,0x40,0x4c] +// CHECK: ld1 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xac,0x40,0x4c] +// CHECK: ld1 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xa0,0x40,0x0c] +// CHECK: ld1 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xa5,0x40,0x0c] +// CHECK: ld1 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xab,0x40,0x0c] +// CHECK: ld1 { v0.1d, v1.1d }, [x0] // encoding: [0x00,0xac,0x40,0x0c] - ld1 {v0.16b-v1.16b}, [x0] - ld1 {v15.8h-v16.8h}, [x15] - ld1 {v31.4s-v0.4s}, [sp] - ld1 {v0.2d-v1.2d}, [x0] - ld1 {v0.8b-v1.8b}, [x0] - ld1 {v15.4h-v16.4h}, [x15] - ld1 {v31.2s-v0.2s}, [sp] - ld1 {v0.1d-v1.1d}, [x0] -// CHECK: ld1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x40,0x4c] -// CHECK: ld1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x40,0x4c] -// CHECK: ld1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x40,0x4c] -// CHECK: ld1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x40,0x4c] -// CHECK: ld1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x40,0x0c] -// CHECK: ld1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x40,0x0c] -// CHECK: ld1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x40,0x0c] -// CHECK: ld1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x40,0x0c] + ld1 { v0.16b-v1.16b }, [x0] + ld1 { v15.8h-v16.8h }, [x15] + ld1 { v31.4s-v0.4s }, [sp] + ld1 { v0.2d-v1.2d }, [x0] + ld1 { v0.8b-v1.8b }, [x0] + ld1 { v15.4h-v16.4h }, [x15] + ld1 { v31.2s-v0.2s }, [sp] + ld1 { v0.1d-v1.1d }, [x0] +// CHECK: ld1 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xa0,0x40,0x4c] +// CHECK: ld1 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xa5,0x40,0x4c] +// CHECK: ld1 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xab,0x40,0x4c] +// CHECK: ld1 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xac,0x40,0x4c] +// CHECK: ld1 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xa0,0x40,0x0c] +// CHECK: ld1 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xa5,0x40,0x0c] +// CHECK: ld1 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xab,0x40,0x0c] +// CHECK: ld1 { v0.1d, v1.1d }, [x0] // encoding: [0x00,0xac,0x40,0x0c] //------------------------------------------------------------------------------ // Load multiple 1-element structures to three consecutive registers //------------------------------------------------------------------------------ - ld1 {v0.16b, v1.16b, v2.16b}, [x0] - ld1 {v15.8h, v16.8h, v17.8h}, [x15] - ld1 {v31.4s, v0.4s, v1.4s}, [sp] - ld1 {v0.2d, v1.2d, v2.2d}, [x0] - ld1 {v0.8b, v1.8b, v2.8b}, [x0] - ld1 {v15.4h, v16.4h, v17.4h}, [x15] - ld1 {v31.2s, v0.2s, v1.2s}, [sp] - ld1 {v0.1d, v1.1d, v2.1d}, [x0] -// CHECK: ld1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x40,0x4c] -// CHECK: ld1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x40,0x4c] -// CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x40,0x4c] -// CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x40,0x4c] -// CHECK: ld1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x40,0x0c] -// CHECK: ld1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x40,0x0c] -// CHECK: ld1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x40,0x0c] -// CHECK: ld1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x40,0x0c] + ld1 { v0.16b, v1.16b, v2.16b }, [x0] + ld1 { v15.8h, v16.8h, v17.8h }, [x15] + ld1 { v31.4s, v0.4s, v1.4s }, [sp] + ld1 { v0.2d, v1.2d, v2.2d }, [x0] + ld1 { v0.8b, v1.8b, v2.8b }, [x0] + ld1 { v15.4h, v16.4h, v17.4h }, [x15] + ld1 { v31.2s, v0.2s, v1.2s }, [sp] + ld1 { v0.1d, v1.1d, v2.1d }, [x0] +// CHECK: ld1 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x60,0x40,0x4c] +// CHECK: ld1 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x65,0x40,0x4c] +// CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x6b,0x40,0x4c] +// CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x6c,0x40,0x4c] +// CHECK: ld1 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x60,0x40,0x0c] +// CHECK: ld1 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x65,0x40,0x0c] +// CHECK: ld1 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x6b,0x40,0x0c] +// CHECK: ld1 { v0.1d, v1.1d, v2.1d }, [x0] // encoding: [0x00,0x6c,0x40,0x0c] - ld1 {v0.16b-v2.16b}, [x0] - ld1 {v15.8h-v17.8h}, [x15] - ld1 {v31.4s-v1.4s}, [sp] - ld1 {v0.2d-v2.2d}, [x0] - ld1 {v0.8b-v2.8b}, [x0] - ld1 {v15.4h-v17.4h}, [x15] - ld1 {v31.2s-v1.2s}, [sp] - ld1 {v0.1d-v2.1d}, [x0] -// CHECK: ld1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x40,0x4c] -// CHECK: ld1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x40,0x4c] -// CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x40,0x4c] -// CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x40,0x4c] -// CHECK: ld1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x40,0x0c] -// CHECK: ld1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x40,0x0c] -// CHECK: ld1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x40,0x0c] -// CHECK: ld1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x40,0x0c] + ld1 { v0.16b-v2.16b }, [x0] + ld1 { v15.8h-v17.8h }, [x15] + ld1 { v31.4s-v1.4s }, [sp] + ld1 { v0.2d-v2.2d }, [x0] + ld1 { v0.8b-v2.8b }, [x0] + ld1 { v15.4h-v17.4h }, [x15] + ld1 { v31.2s-v1.2s }, [sp] + ld1 { v0.1d-v2.1d }, [x0] +// CHECK: ld1 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x60,0x40,0x4c] +// CHECK: ld1 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x65,0x40,0x4c] +// CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x6b,0x40,0x4c] +// CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x6c,0x40,0x4c] +// CHECK: ld1 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x60,0x40,0x0c] +// CHECK: ld1 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x65,0x40,0x0c] +// CHECK: ld1 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x6b,0x40,0x0c] +// CHECK: ld1 { v0.1d, v1.1d, v2.1d }, [x0] // encoding: [0x00,0x6c,0x40,0x0c] //------------------------------------------------------------------------------ // Load multiple 1-element structures to four consecutive registers //------------------------------------------------------------------------------ - ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] - ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] - ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] - ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] - ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] - ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] - ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] - ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] -// CHECK: ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x40,0x4c] -// CHECK: ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x40,0x4c] -// CHECK: ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x40,0x4c] -// CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x40,0x4c] -// CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x40,0x0c] -// CHECK: ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x40,0x0c] -// CHECK: ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x40,0x0c] -// CHECK: ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x40,0x0c] + ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] + ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] + ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] + ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] + ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] + ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] + ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] + ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] +// CHECK: ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x20,0x40,0x4c] +// CHECK: ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x25,0x40,0x4c] +// CHECK: ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x2b,0x40,0x4c] +// CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x2c,0x40,0x4c] +// CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x20,0x40,0x0c] +// CHECK: ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x25,0x40,0x0c] +// CHECK: ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x2b,0x40,0x0c] +// CHECK: ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] // encoding: [0x00,0x2c,0x40,0x0c] - ld1 {v0.16b-v3.16b}, [x0] - ld1 {v15.8h-v18.8h}, [x15] - ld1 {v31.4s-v2.4s}, [sp] - ld1 {v0.2d-v3.2d}, [x0] - ld1 {v0.8b-v3.8b}, [x0] - ld1 {v15.4h-v18.4h}, [x15] - ld1 {v31.2s-v2.2s}, [sp] - ld1 {v0.1d-v3.1d}, [x0] -// CHECK: ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x40,0x4c] -// CHECK: ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x40,0x4c] -// CHECK: ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x40,0x4c] -// CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x40,0x4c] -// CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x40,0x0c] -// CHECK: ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x40,0x0c] -// CHECK: ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x40,0x0c] -// CHECK: ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x40,0x0c] + ld1 { v0.16b-v3.16b }, [x0] + ld1 { v15.8h-v18.8h }, [x15] + ld1 { v31.4s-v2.4s }, [sp] + ld1 { v0.2d-v3.2d }, [x0] + ld1 { v0.8b-v3.8b }, [x0] + ld1 { v15.4h-v18.4h }, [x15] + ld1 { v31.2s-v2.2s }, [sp] + ld1 { v0.1d-v3.1d }, [x0] +// CHECK: ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x20,0x40,0x4c] +// CHECK: ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x25,0x40,0x4c] +// CHECK: ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x2b,0x40,0x4c] +// CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x2c,0x40,0x4c] +// CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x20,0x40,0x0c] +// CHECK: ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x25,0x40,0x0c] +// CHECK: ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x2b,0x40,0x0c] +// CHECK: ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] // encoding: [0x00,0x2c,0x40,0x0c] //------------------------------------------------------------------------------ // Load multiple 4-element structures to two consecutive registers //------------------------------------------------------------------------------ - ld2 {v0.16b, v1.16b}, [x0] - ld2 {v15.8h, v16.8h}, [x15] - ld2 {v31.4s, v0.4s}, [sp] - ld2 {v0.2d, v1.2d}, [x0] - ld2 {v0.8b, v1.8b}, [x0] - ld2 {v15.4h, v16.4h}, [x15] - ld2 {v31.2s, v0.2s}, [sp] -// CHECK: ld2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x40,0x4c] -// CHECK: ld2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x40,0x4c] -// CHECK: ld2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x40,0x4c] -// CHECK: ld2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x40,0x4c] -// CHECK: ld2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x40,0x0c] -// CHECK: ld2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x40,0x0c] -// CHECK: ld2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x40,0x0c] + ld2 { v0.16b, v1.16b }, [x0] + ld2 { v15.8h, v16.8h }, [x15] + ld2 { v31.4s, v0.4s }, [sp] + ld2 { v0.2d, v1.2d }, [x0] + ld2 { v0.8b, v1.8b }, [x0] + ld2 { v15.4h, v16.4h }, [x15] + ld2 { v31.2s, v0.2s }, [sp] +// CHECK: ld2 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0x80,0x40,0x4c] +// CHECK: ld2 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0x85,0x40,0x4c] +// CHECK: ld2 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0x8b,0x40,0x4c] +// CHECK: ld2 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0x8c,0x40,0x4c] +// CHECK: ld2 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0x80,0x40,0x0c] +// CHECK: ld2 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0x85,0x40,0x0c] +// CHECK: ld2 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0x8b,0x40,0x0c] - ld2 {v0.16b-v1.16b}, [x0] - ld2 {v15.8h-v16.8h}, [x15] - ld2 {v31.4s-v0.4s}, [sp] - ld2 {v0.2d-v1.2d}, [x0] - ld2 {v0.8b-v1.8b}, [x0] - ld2 {v15.4h-v16.4h}, [x15] - ld2 {v31.2s-v0.2s}, [sp] -// CHECK: ld2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x40,0x4c] -// CHECK: ld2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x40,0x4c] -// CHECK: ld2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x40,0x4c] -// CHECK: ld2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x40,0x4c] -// CHECK: ld2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x40,0x0c] -// CHECK: ld2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x40,0x0c] -// CHECK: ld2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x40,0x0c] + ld2 { v0.16b-v1.16b }, [x0] + ld2 { v15.8h-v16.8h }, [x15] + ld2 { v31.4s-v0.4s }, [sp] + ld2 { v0.2d-v1.2d }, [x0] + ld2 { v0.8b-v1.8b }, [x0] + ld2 { v15.4h-v16.4h }, [x15] + ld2 { v31.2s-v0.2s }, [sp] +// CHECK: ld2 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0x80,0x40,0x4c] +// CHECK: ld2 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0x85,0x40,0x4c] +// CHECK: ld2 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0x8b,0x40,0x4c] +// CHECK: ld2 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0x8c,0x40,0x4c] +// CHECK: ld2 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0x80,0x40,0x0c] +// CHECK: ld2 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0x85,0x40,0x0c] +// CHECK: ld2 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0x8b,0x40,0x0c] //------------------------------------------------------------------------------ // Load multiple 3-element structures to three consecutive registers //------------------------------------------------------------------------------ - ld3 {v0.16b, v1.16b, v2.16b}, [x0] - ld3 {v15.8h, v16.8h, v17.8h}, [x15] - ld3 {v31.4s, v0.4s, v1.4s}, [sp] - ld3 {v0.2d, v1.2d, v2.2d}, [x0] - ld3 {v0.8b, v1.8b, v2.8b}, [x0] - ld3 {v15.4h, v16.4h, v17.4h}, [x15] - ld3 {v31.2s, v0.2s, v1.2s}, [sp] -// CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x40,0x4c] -// CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x40,0x4c] -// CHECK: ld3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x40,0x4c] -// CHECK: ld3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x40,0x4c] -// CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x40,0x0c] -// CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x40,0x0c] -// CHECK: ld3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x40,0x0c] + ld3 { v0.16b, v1.16b, v2.16b }, [x0] + ld3 { v15.8h, v16.8h, v17.8h }, [x15] + ld3 { v31.4s, v0.4s, v1.4s }, [sp] + ld3 { v0.2d, v1.2d, v2.2d }, [x0] + ld3 { v0.8b, v1.8b, v2.8b }, [x0] + ld3 { v15.4h, v16.4h, v17.4h }, [x15] + ld3 { v31.2s, v0.2s, v1.2s }, [sp] +// CHECK: ld3 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x40,0x40,0x4c] +// CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x45,0x40,0x4c] +// CHECK: ld3 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x4b,0x40,0x4c] +// CHECK: ld3 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x4c,0x40,0x4c] +// CHECK: ld3 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x40,0x40,0x0c] +// CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x45,0x40,0x0c] +// CHECK: ld3 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x4b,0x40,0x0c] - ld3 {v0.16b-v2.16b}, [x0] - ld3 {v15.8h-v17.8h}, [x15] - ld3 {v31.4s-v1.4s}, [sp] - ld3 {v0.2d-v2.2d}, [x0] - ld3 {v0.8b-v2.8b}, [x0] - ld3 {v15.4h-v17.4h}, [x15] - ld3 {v31.2s-v1.2s}, [sp] -// CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x40,0x4c] -// CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x40,0x4c] -// CHECK: ld3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x40,0x4c] -// CHECK: ld3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x40,0x4c] -// CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x40,0x0c] -// CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x40,0x0c] -// CHECK: ld3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x40,0x0c] + ld3 { v0.16b-v2.16b }, [x0] + ld3 { v15.8h-v17.8h }, [x15] + ld3 { v31.4s-v1.4s }, [sp] + ld3 { v0.2d-v2.2d }, [x0] + ld3 { v0.8b-v2.8b }, [x0] + ld3 { v15.4h-v17.4h }, [x15] + ld3 { v31.2s-v1.2s }, [sp] +// CHECK: ld3 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x40,0x40,0x4c] +// CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x45,0x40,0x4c] +// CHECK: ld3 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x4b,0x40,0x4c] +// CHECK: ld3 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x4c,0x40,0x4c] +// CHECK: ld3 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x40,0x40,0x0c] +// CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x45,0x40,0x0c] +// CHECK: ld3 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x4b,0x40,0x0c] //------------------------------------------------------------------------------ // Load multiple 4-element structures to four consecutive registers //------------------------------------------------------------------------------ - ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] - ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] - ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] - ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] - ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] - ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] - ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] -// CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x40,0x4c] -// CHECK: ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x40,0x4c] -// CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x40,0x4c] -// CHECK: ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x40,0x4c] -// CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x40,0x0c] -// CHECK: ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x40,0x0c] -// CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x40,0x0c] + ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] + ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] + ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] + ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] + ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] + ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] + ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] +// CHECK: ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x00,0x40,0x4c] +// CHECK: ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x05,0x40,0x4c] +// CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x0b,0x40,0x4c] +// CHECK: ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x0c,0x40,0x4c] +// CHECK: ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x40,0x0c] +// CHECK: ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x05,0x40,0x0c] +// CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x0b,0x40,0x0c] - ld4 {v0.16b-v3.16b}, [x0] - ld4 {v15.8h-v18.8h}, [x15] - ld4 {v31.4s-v2.4s}, [sp] - ld4 {v0.2d-v3.2d}, [x0] - ld4 {v0.8b-v3.8b}, [x0] - ld4 {v15.4h-v18.4h}, [x15] - ld4 {v31.2s-v2.2s}, [sp] -// CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x40,0x4c] -// CHECK: ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x40,0x4c] -// CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x40,0x4c] -// CHECK: ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x40,0x4c] -// CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x40,0x0c] -// CHECK: ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x40,0x0c] -// CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x40,0x0c] + ld4 { v0.16b-v3.16b }, [x0] + ld4 { v15.8h-v18.8h }, [x15] + ld4 { v31.4s-v2.4s }, [sp] + ld4 { v0.2d-v3.2d }, [x0] + ld4 { v0.8b-v3.8b }, [x0] + ld4 { v15.4h-v18.4h }, [x15] + ld4 { v31.2s-v2.2s }, [sp] +// CHECK: ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x00,0x40,0x4c] +// CHECK: ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x05,0x40,0x4c] +// CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x0b,0x40,0x4c] +// CHECK: ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x0c,0x40,0x4c] +// CHECK: ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x40,0x0c] +// CHECK: ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x05,0x40,0x0c] +// CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x0b,0x40,0x0c] diff --git a/test/MC/AArch64/neon-simd-ldst-one-elem.s b/test/MC/AArch64/neon-simd-ldst-one-elem.s index 140d752..4febf6d 100644 --- a/test/MC/AArch64/neon-simd-ldst-one-elem.s +++ b/test/MC/AArch64/neon-simd-ldst-one-elem.s @@ -1,325 +1,325 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 //------------------------------------------------------------------------------ // Load single 1-element structure to all lanes of 1 register //------------------------------------------------------------------------------ - ld1r {v0.16b}, [x0] - ld1r {v15.8h}, [x15] - ld1r {v31.4s}, [sp] - ld1r {v0.2d}, [x0] - ld1r {v0.8b}, [x0] - ld1r {v15.4h}, [x15] - ld1r {v31.2s}, [sp] - ld1r {v0.1d}, [x0] -// CHECK: ld1r {v0.16b}, [x0] // encoding: [0x00,0xc0,0x40,0x4d] -// CHECK: ld1r {v15.8h}, [x15] // encoding: [0xef,0xc5,0x40,0x4d] -// CHECK: ld1r {v31.4s}, [sp] // encoding: [0xff,0xcb,0x40,0x4d] -// CHECK: ld1r {v0.2d}, [x0] // encoding: [0x00,0xcc,0x40,0x4d] -// CHECK: ld1r {v0.8b}, [x0] // encoding: [0x00,0xc0,0x40,0x0d] -// CHECK: ld1r {v15.4h}, [x15] // encoding: [0xef,0xc5,0x40,0x0d] -// CHECK: ld1r {v31.2s}, [sp] // encoding: [0xff,0xcb,0x40,0x0d] -// CHECK: ld1r {v0.1d}, [x0] // encoding: [0x00,0xcc,0x40,0x0d] + ld1r { v0.16b }, [x0] + ld1r { v15.8h }, [x15] + ld1r { v31.4s }, [sp] + ld1r { v0.2d }, [x0] + ld1r { v0.8b }, [x0] + ld1r { v15.4h }, [x15] + ld1r { v31.2s }, [sp] + ld1r { v0.1d }, [x0] +// CHECK: ld1r { v0.16b }, [x0] // encoding: [0x00,0xc0,0x40,0x4d] +// CHECK: ld1r { v15.8h }, [x15] // encoding: [0xef,0xc5,0x40,0x4d] +// CHECK: ld1r { v31.4s }, [sp] // encoding: [0xff,0xcb,0x40,0x4d] +// CHECK: ld1r { v0.2d }, [x0] // encoding: [0x00,0xcc,0x40,0x4d] +// CHECK: ld1r { v0.8b }, [x0] // encoding: [0x00,0xc0,0x40,0x0d] +// CHECK: ld1r { v15.4h }, [x15] // encoding: [0xef,0xc5,0x40,0x0d] +// CHECK: ld1r { v31.2s }, [sp] // encoding: [0xff,0xcb,0x40,0x0d] +// CHECK: ld1r { v0.1d }, [x0] // encoding: [0x00,0xcc,0x40,0x0d] //------------------------------------------------------------------------------ // Load single N-element structure to all lanes of N consecutive // registers (N = 2,3,4) //------------------------------------------------------------------------------ - ld2r {v0.16b, v1.16b}, [x0] - ld2r {v15.8h, v16.8h}, [x15] - ld2r {v31.4s, v0.4s}, [sp] - ld2r {v0.2d, v1.2d}, [x0] - ld2r {v0.8b, v1.8b}, [x0] - ld2r {v15.4h, v16.4h}, [x15] - ld2r {v31.2s, v0.2s}, [sp] - ld2r {v31.1d, v0.1d}, [sp] -// CHECK: ld2r {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xc0,0x60,0x4d] -// CHECK: ld2r {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xc5,0x60,0x4d] -// CHECK: ld2r {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xcb,0x60,0x4d] -// CHECK: ld2r {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xcc,0x60,0x4d] -// CHECK: ld2r {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xc0,0x60,0x0d] -// CHECK: ld2r {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xc5,0x60,0x0d] -// CHECK: ld2r {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xcb,0x60,0x0d] -// CHECK: ld2r {v31.1d, v0.1d}, [sp] // encoding: [0xff,0xcf,0x60,0x0d] + ld2r { v0.16b, v1.16b }, [x0] + ld2r { v15.8h, v16.8h }, [x15] + ld2r { v31.4s, v0.4s }, [sp] + ld2r { v0.2d, v1.2d }, [x0] + ld2r { v0.8b, v1.8b }, [x0] + ld2r { v15.4h, v16.4h }, [x15] + ld2r { v31.2s, v0.2s }, [sp] + ld2r { v31.1d, v0.1d }, [sp] +// CHECK: ld2r { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xc0,0x60,0x4d] +// CHECK: ld2r { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xc5,0x60,0x4d] +// CHECK: ld2r { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xcb,0x60,0x4d] +// CHECK: ld2r { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xcc,0x60,0x4d] +// CHECK: ld2r { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xc0,0x60,0x0d] +// CHECK: ld2r { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xc5,0x60,0x0d] +// CHECK: ld2r { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xcb,0x60,0x0d] +// CHECK: ld2r { v31.1d, v0.1d }, [sp] // encoding: [0xff,0xcf,0x60,0x0d] - ld3r {v0.16b, v1.16b, v2.16b}, [x0] - ld3r {v15.8h, v16.8h, v17.8h}, [x15] - ld3r {v31.4s, v0.4s, v1.4s}, [sp] - ld3r {v0.2d, v1.2d, v2.2d}, [x0] - ld3r {v0.8b, v1.8b, v2.8b}, [x0] - ld3r {v15.4h, v16.4h, v17.4h}, [x15] - ld3r {v31.2s, v0.2s, v1.2s}, [sp] - ld3r {v31.1d, v0.1d, v1.1d}, [sp] -// CHECK: ld3r {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0xe0,0x40,0x4d] -// CHECK: ld3r {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0xe5,0x40,0x4d] -// CHECK: ld3r {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0xeb,0x40,0x4d] -// CHECK: ld3r {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0xec,0x40,0x4d] -// CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0xe0,0x40,0x0d] -// CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0xe5,0x40,0x0d] -// CHECK: ld3r {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0xeb,0x40,0x0d] -// CHECK: ld3r {v31.1d, v0.1d, v1.1d}, [sp] // encoding: [0xff,0xef,0x40,0x0d] + ld3r { v0.16b, v1.16b, v2.16b }, [x0] + ld3r { v15.8h, v16.8h, v17.8h }, [x15] + ld3r { v31.4s, v0.4s, v1.4s }, [sp] + ld3r { v0.2d, v1.2d, v2.2d }, [x0] + ld3r { v0.8b, v1.8b, v2.8b }, [x0] + ld3r { v15.4h, v16.4h, v17.4h }, [x15] + ld3r { v31.2s, v0.2s, v1.2s }, [sp] + ld3r { v31.1d, v0.1d, v1.1d }, [sp] +// CHECK: ld3r { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0xe0,0x40,0x4d] +// CHECK: ld3r { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0xe5,0x40,0x4d] +// CHECK: ld3r { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0xeb,0x40,0x4d] +// CHECK: ld3r { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0xec,0x40,0x4d] +// CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0xe0,0x40,0x0d] +// CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0xe5,0x40,0x0d] +// CHECK: ld3r { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0xeb,0x40,0x0d] +// CHECK: ld3r { v31.1d, v0.1d, v1.1d }, [sp] // encoding: [0xff,0xef,0x40,0x0d] - ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] - ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] - ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] - ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] - ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] - ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] - ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] - ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] -// CHECK: ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0xe0,0x60,0x4d] -// CHECK: ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0xe5,0x60,0x4d] -// CHECK: ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0xeb,0x60,0x4d] -// CHECK: ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0xec,0x60,0x4d] -// CHECK: ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0xe0,0x60,0x0d] -// CHECK: ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0xe5,0x60,0x0d] -// CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0xeb,0x60,0x0d] -// CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] // encoding: [0xff,0xef,0x60,0x0d] + ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] + ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] + ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] + ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] + ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] + ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] + ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] + ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp] +// CHECK: ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0xe0,0x60,0x4d] +// CHECK: ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0xe5,0x60,0x4d] +// CHECK: ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0xeb,0x60,0x4d] +// CHECK: ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0xec,0x60,0x4d] +// CHECK: ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0xe0,0x60,0x0d] +// CHECK: ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0xe5,0x60,0x0d] +// CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0xeb,0x60,0x0d] +// CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp] // encoding: [0xff,0xef,0x60,0x0d] //------------------------------------------------------------------------------ // Load single 1-element structure to one lane of 1 register. //------------------------------------------------------------------------------ - ld1 {v0.b}[9], [x0] - ld1 {v15.h}[7], [x15] - ld1 {v31.s}[3], [sp] - ld1 {v0.d}[1], [x0] -// CHECK: ld1 {v0.b}[9], [x0] // encoding: [0x00,0x04,0x40,0x4d] -// CHECK: ld1 {v15.h}[7], [x15] // encoding: [0xef,0x59,0x40,0x4d] -// CHECK: ld1 {v31.s}[3], [sp] // encoding: [0xff,0x93,0x40,0x4d] -// CHECK: ld1 {v0.d}[1], [x0] // encoding: [0x00,0x84,0x40,0x4d] + ld1 { v0.b }[9], [x0] + ld1 { v15.h }[7], [x15] + ld1 { v31.s }[3], [sp] + ld1 { v0.d }[1], [x0] +// CHECK: ld1 { v0.b }[9], [x0] // encoding: [0x00,0x04,0x40,0x4d] +// CHECK: ld1 { v15.h }[7], [x15] // encoding: [0xef,0x59,0x40,0x4d] +// CHECK: ld1 { v31.s }[3], [sp] // encoding: [0xff,0x93,0x40,0x4d] +// CHECK: ld1 { v0.d }[1], [x0] // encoding: [0x00,0x84,0x40,0x4d] //------------------------------------------------------------------------------ // Load single N-element structure to one lane of N consecutive registers // (N = 2,3,4) //------------------------------------------------------------------------------ - ld2 {v0.b, v1.b}[9], [x0] - ld2 {v15.h, v16.h}[7], [x15] - ld2 {v31.s, v0.s}[3], [sp] - ld2 {v0.d, v1.d}[1], [x0] -// CHECK: ld2 {v0.b, v1.b}[9], [x0] // encoding: [0x00,0x04,0x60,0x4d] -// CHECK: ld2 {v15.h, v16.h}[7], [x15] // encoding: [0xef,0x59,0x60,0x4d] -// CHECK: ld2 {v31.s, v0.s}[3], [sp] // encoding: [0xff,0x93,0x60,0x4d] -// CHECK: ld2 {v0.d, v1.d}[1], [x0] // encoding: [0x00,0x84,0x60,0x4d] + ld2 { v0.b, v1.b }[9], [x0] + ld2 { v15.h, v16.h }[7], [x15] + ld2 { v31.s, v0.s }[3], [sp] + ld2 { v0.d, v1.d }[1], [x0] +// CHECK: ld2 { v0.b, v1.b }[9], [x0] // encoding: [0x00,0x04,0x60,0x4d] +// CHECK: ld2 { v15.h, v16.h }[7], [x15] // encoding: [0xef,0x59,0x60,0x4d] +// CHECK: ld2 { v31.s, v0.s }[3], [sp] // encoding: [0xff,0x93,0x60,0x4d] +// CHECK: ld2 { v0.d, v1.d }[1], [x0] // encoding: [0x00,0x84,0x60,0x4d] - ld3 {v0.b, v1.b, v2.b}[9], [x0] - ld3 {v15.h, v16.h, v17.h}[7], [x15] - ld3 {v31.s, v0.s, v1.s}[3], [sp] - ld3 {v0.d, v1.d, v2.d}[1], [x0] -// CHECK: ld3 {v0.b, v1.b, v2.b}[9], [x0] // encoding: [0x00,0x24,0x40,0x4d] -// CHECK: ld3 {v15.h, v16.h, v17.h}[7], [x15] // encoding: [0xef,0x79,0x40,0x4d] -// CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp] // encoding: [0xff,0xb3,0x40,0x4d] -// CHECK: ld3 {v0.d, v1.d, v2.d}[1], [x0] // encoding: [0x00,0xa4,0x40,0x4d] + ld3 { v0.b, v1.b, v2.b }[9], [x0] + ld3 { v15.h, v16.h, v17.h }[7], [x15] + ld3 { v31.s, v0.s, v1.s }[3], [sp] + ld3 { v0.d, v1.d, v2.d }[1], [x0] +// CHECK: ld3 { v0.b, v1.b, v2.b }[9], [x0] // encoding: [0x00,0x24,0x40,0x4d] +// CHECK: ld3 { v15.h, v16.h, v17.h }[7], [x15] // encoding: [0xef,0x79,0x40,0x4d] +// CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp] // encoding: [0xff,0xb3,0x40,0x4d] +// CHECK: ld3 { v0.d, v1.d, v2.d }[1], [x0] // encoding: [0x00,0xa4,0x40,0x4d] - ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] - ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] - ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] - ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] -// CHECK: ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] // encoding: [0x00,0x24,0x60,0x4d] -// CHECK: ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] // encoding: [0xef,0x79,0x60,0x4d] -// CHECK: ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] // encoding: [0xff,0xb3,0x60,0x4d] -// CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] // encoding: [0x00,0xa4,0x60,0x4d] + ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] + ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15] + ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp] + ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] +// CHECK: ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] // encoding: [0x00,0x24,0x60,0x4d] +// CHECK: ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15] // encoding: [0xef,0x79,0x60,0x4d] +// CHECK: ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp] // encoding: [0xff,0xb3,0x60,0x4d] +// CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] // encoding: [0x00,0xa4,0x60,0x4d] //------------------------------------------------------------------------------ // Store single 1-element structure from one lane of 1 register. //------------------------------------------------------------------------------ - st1 {v0.b}[9], [x0] - st1 {v15.h}[7], [x15] - st1 {v31.s}[3], [sp] - st1 {v0.d}[1], [x0] -// CHECK: st1 {v0.b}[9], [x0] // encoding: [0x00,0x04,0x00,0x4d] -// CHECK: st1 {v15.h}[7], [x15] // encoding: [0xef,0x59,0x00,0x4d] -// CHECK: st1 {v31.s}[3], [sp] // encoding: [0xff,0x93,0x00,0x4d] -// CHECK: st1 {v0.d}[1], [x0] // encoding: [0x00,0x84,0x00,0x4d] + st1 { v0.b }[9], [x0] + st1 { v15.h }[7], [x15] + st1 { v31.s }[3], [sp] + st1 { v0.d }[1], [x0] +// CHECK: st1 { v0.b }[9], [x0] // encoding: [0x00,0x04,0x00,0x4d] +// CHECK: st1 { v15.h }[7], [x15] // encoding: [0xef,0x59,0x00,0x4d] +// CHECK: st1 { v31.s }[3], [sp] // encoding: [0xff,0x93,0x00,0x4d] +// CHECK: st1 { v0.d }[1], [x0] // encoding: [0x00,0x84,0x00,0x4d] //------------------------------------------------------------------------------ // Store single N-element structure from one lane of N consecutive registers // (N = 2,3,4) //------------------------------------------------------------------------------ - st2 {v0.b, v1.b}[9], [x0] - st2 {v15.h, v16.h}[7], [x15] - st2 {v31.s, v0.s}[3], [sp] - st2 {v0.d, v1.d}[1], [x0] -// CHECK: st2 {v0.b, v1.b}[9], [x0] // encoding: [0x00,0x04,0x20,0x4d] -// CHECK: st2 {v15.h, v16.h}[7], [x15] // encoding: [0xef,0x59,0x20,0x4d] -// CHECK: st2 {v31.s, v0.s}[3], [sp] // encoding: [0xff,0x93,0x20,0x4d] -// CHECK: st2 {v0.d, v1.d}[1], [x0] // encoding: [0x00,0x84,0x20,0x4d] + st2 { v0.b, v1.b }[9], [x0] + st2 { v15.h, v16.h }[7], [x15] + st2 { v31.s, v0.s }[3], [sp] + st2 { v0.d, v1.d }[1], [x0] +// CHECK: st2 { v0.b, v1.b }[9], [x0] // encoding: [0x00,0x04,0x20,0x4d] +// CHECK: st2 { v15.h, v16.h }[7], [x15] // encoding: [0xef,0x59,0x20,0x4d] +// CHECK: st2 { v31.s, v0.s }[3], [sp] // encoding: [0xff,0x93,0x20,0x4d] +// CHECK: st2 { v0.d, v1.d }[1], [x0] // encoding: [0x00,0x84,0x20,0x4d] - st3 {v0.b, v1.b, v2.b}[9], [x0] - st3 {v15.h, v16.h, v17.h}[7], [x15] - st3 {v31.s, v0.s, v1.s}[3], [sp] - st3 {v0.d, v1.d, v2.d}[1], [x0] -// CHECK: st3 {v0.b, v1.b, v2.b}[9], [x0] // encoding: [0x00,0x24,0x00,0x4d] -// CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15] // encoding: [0xef,0x79,0x00,0x4d] -// CHECK: st3 {v31.s, v0.s, v1.s}[3], [sp] // encoding: [0xff,0xb3,0x00,0x4d] -// CHECK: st3 {v0.d, v1.d, v2.d}[1], [x0] // encoding: [0x00,0xa4,0x00,0x4d] + st3 { v0.b, v1.b, v2.b }[9], [x0] + st3 { v15.h, v16.h, v17.h }[7], [x15] + st3 { v31.s, v0.s, v1.s }[3], [sp] + st3 { v0.d, v1.d, v2.d }[1], [x0] +// CHECK: st3 { v0.b, v1.b, v2.b }[9], [x0] // encoding: [0x00,0x24,0x00,0x4d] +// CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15] // encoding: [0xef,0x79,0x00,0x4d] +// CHECK: st3 { v31.s, v0.s, v1.s }[3], [sp] // encoding: [0xff,0xb3,0x00,0x4d] +// CHECK: st3 { v0.d, v1.d, v2.d }[1], [x0] // encoding: [0x00,0xa4,0x00,0x4d] - st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] - st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] - st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] - st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] -// CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] // encoding: [0x00,0x24,0x20,0x4d] -// CHECK: st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] // encoding: [0xef,0x79,0x20,0x4d] -// CHECK: st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] // encoding: [0xff,0xb3,0x20,0x4d] -// CHECK: st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] // encoding: [0x00,0xa4,0x20,0x4d] + st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] + st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15] + st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp] + st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] +// CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] // encoding: [0x00,0x24,0x20,0x4d] +// CHECK: st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15] // encoding: [0xef,0x79,0x20,0x4d] +// CHECK: st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp] // encoding: [0xff,0xb3,0x20,0x4d] +// CHECK: st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] // encoding: [0x00,0xa4,0x20,0x4d] //------------------------------------------------------------------------------ // Post-index oad single 1-element structure to all lanes of 1 register //------------------------------------------------------------------------------ - ld1r {v0.16b}, [x0], #1 - ld1r {v15.8h}, [x15], #2 - ld1r {v31.4s}, [sp], #4 - ld1r {v0.2d}, [x0], #8 - ld1r {v0.8b}, [x0], x0 - ld1r {v15.4h}, [x15], x1 - ld1r {v31.2s}, [sp], x2 - ld1r {v0.1d}, [x0], x3 -// CHECK: ld1r {v0.16b}, [x0], #1 // encoding: [0x00,0xc0,0xdf,0x4d] -// CHECK: ld1r {v15.8h}, [x15], #2 // encoding: [0xef,0xc5,0xdf,0x4d] -// CHECK: ld1r {v31.4s}, [sp], #4 // encoding: [0xff,0xcb,0xdf,0x4d] -// CHECK: ld1r {v0.2d}, [x0], #8 // encoding: [0x00,0xcc,0xdf,0x4d] -// CHECK: ld1r {v0.8b}, [x0], x0 // encoding: [0x00,0xc0,0xc0,0x0d] -// CHECK: ld1r {v15.4h}, [x15], x1 // encoding: [0xef,0xc5,0xc1,0x0d] -// CHECK: ld1r {v31.2s}, [sp], x2 // encoding: [0xff,0xcb,0xc2,0x0d] -// CHECK: ld1r {v0.1d}, [x0], x3 // encoding: [0x00,0xcc,0xc3,0x0d] + ld1r { v0.16b }, [x0], #1 + ld1r { v15.8h }, [x15], #2 + ld1r { v31.4s }, [sp], #4 + ld1r { v0.2d }, [x0], #8 + ld1r { v0.8b }, [x0], x0 + ld1r { v15.4h }, [x15], x1 + ld1r { v31.2s }, [sp], x2 + ld1r { v0.1d }, [x0], x3 +// CHECK: ld1r { v0.16b }, [x0], #1 // encoding: [0x00,0xc0,0xdf,0x4d] +// CHECK: ld1r { v15.8h }, [x15], #2 // encoding: [0xef,0xc5,0xdf,0x4d] +// CHECK: ld1r { v31.4s }, [sp], #4 // encoding: [0xff,0xcb,0xdf,0x4d] +// CHECK: ld1r { v0.2d }, [x0], #8 // encoding: [0x00,0xcc,0xdf,0x4d] +// CHECK: ld1r { v0.8b }, [x0], x0 // encoding: [0x00,0xc0,0xc0,0x0d] +// CHECK: ld1r { v15.4h }, [x15], x1 // encoding: [0xef,0xc5,0xc1,0x0d] +// CHECK: ld1r { v31.2s }, [sp], x2 // encoding: [0xff,0xcb,0xc2,0x0d] +// CHECK: ld1r { v0.1d }, [x0], x3 // encoding: [0x00,0xcc,0xc3,0x0d] //------------------------------------------------------------------------------ // Post-index load single N-element structure to all lanes of N consecutive // registers (N = 2,3,4) //------------------------------------------------------------------------------ - ld2r {v0.16b, v1.16b}, [x0], #2 - ld2r {v15.8h, v16.8h}, [x15], #4 - ld2r {v31.4s, v0.4s}, [sp], #8 - ld2r {v0.2d, v1.2d}, [x0], #16 - ld2r {v0.8b, v1.8b}, [x0], x6 - ld2r {v15.4h, v16.4h}, [x15], x7 - ld2r {v31.2s, v0.2s}, [sp], x9 - ld2r {v31.1d, v0.1d}, [x0], x5 -// CHECK: ld2r {v0.16b, v1.16b}, [x0], #2 // encoding: [0x00,0xc0,0xff,0x4d] -// CHECK: ld2r {v15.8h, v16.8h}, [x15], #4 // encoding: [0xef,0xc5,0xff,0x4d] -// CHECK: ld2r {v31.4s, v0.4s}, [sp], #8 // encoding: [0xff,0xcb,0xff,0x4d] -// CHECK: ld2r {v0.2d, v1.2d}, [x0], #16 // encoding: [0x00,0xcc,0xff,0x4d] -// CHECK: ld2r {v0.8b, v1.8b}, [x0], x6 // encoding: [0x00,0xc0,0xe6,0x0d] -// CHECK: ld2r {v15.4h, v16.4h}, [x15], x7 // encoding: [0xef,0xc5,0xe7,0x0d] -// CHECK: ld2r {v31.2s, v0.2s}, [sp], x9 // encoding: [0xff,0xcb,0xe9,0x0d] -// CHECK: ld2r {v31.1d, v0.1d}, [x0], x5 // encoding: [0x1f,0xcc,0xe5,0x0d] + ld2r { v0.16b, v1.16b }, [x0], #2 + ld2r { v15.8h, v16.8h }, [x15], #4 + ld2r { v31.4s, v0.4s }, [sp], #8 + ld2r { v0.2d, v1.2d }, [x0], #16 + ld2r { v0.8b, v1.8b }, [x0], x6 + ld2r { v15.4h, v16.4h }, [x15], x7 + ld2r { v31.2s, v0.2s }, [sp], x9 + ld2r { v31.1d, v0.1d }, [x0], x5 +// CHECK: ld2r { v0.16b, v1.16b }, [x0], #2 // encoding: [0x00,0xc0,0xff,0x4d] +// CHECK: ld2r { v15.8h, v16.8h }, [x15], #4 // encoding: [0xef,0xc5,0xff,0x4d] +// CHECK: ld2r { v31.4s, v0.4s }, [sp], #8 // encoding: [0xff,0xcb,0xff,0x4d] +// CHECK: ld2r { v0.2d, v1.2d }, [x0], #16 // encoding: [0x00,0xcc,0xff,0x4d] +// CHECK: ld2r { v0.8b, v1.8b }, [x0], x6 // encoding: [0x00,0xc0,0xe6,0x0d] +// CHECK: ld2r { v15.4h, v16.4h }, [x15], x7 // encoding: [0xef,0xc5,0xe7,0x0d] +// CHECK: ld2r { v31.2s, v0.2s }, [sp], x9 // encoding: [0xff,0xcb,0xe9,0x0d] +// CHECK: ld2r { v31.1d, v0.1d }, [x0], x5 // encoding: [0x1f,0xcc,0xe5,0x0d] - ld3r {v0.16b, v1.16b, v2.16b}, [x0], x9 - ld3r {v15.8h, v16.8h, v17.8h}, [x15], x6 - ld3r {v31.4s, v0.4s, v1.4s}, [sp], x7 - ld3r {v0.2d, v1.2d, v2.2d}, [x0], x5 - ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 - ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 - ld3r {v31.2s, v0.2s, v1.2s}, [sp], #12 - ld3r {v31.1d, v0.1d, v1.1d}, [sp], #24 -// CHECK: ld3r {v0.16b, v1.16b, v2.16b}, [x0], x9 // encoding: [0x00,0xe0,0xc9,0x4d] -// CHECK: ld3r {v15.8h, v16.8h, v17.8h}, [x15], x6 // encoding: [0xef,0xe5,0xc6,0x4d] -// CHECK: ld3r {v31.4s, v0.4s, v1.4s}, [sp], x7 // encoding: [0xff,0xeb,0xc7,0x4d] -// CHECK: ld3r {v0.2d, v1.2d, v2.2d}, [x0], x5 // encoding: [0x00,0xec,0xc5,0x4d] -// CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 // encoding: [0x00,0xe0,0xdf,0x0d] -// CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 // encoding: [0xef,0xe5,0xdf,0x0d] -// CHECK: ld3r {v31.2s, v0.2s, v1.2s}, [sp], #12 // encoding: [0xff,0xeb,0xdf,0x0d] -// CHECK: ld3r {v31.1d, v0.1d, v1.1d}, [sp], #24 // encoding: [0xff,0xef,0xdf,0x0d] + ld3r { v0.16b, v1.16b, v2.16b }, [x0], x9 + ld3r { v15.8h, v16.8h, v17.8h }, [x15], x6 + ld3r { v31.4s, v0.4s, v1.4s }, [sp], x7 + ld3r { v0.2d, v1.2d, v2.2d }, [x0], x5 + ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 + ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6 + ld3r { v31.2s, v0.2s, v1.2s }, [sp], #12 + ld3r { v31.1d, v0.1d, v1.1d }, [sp], #24 +// CHECK: ld3r { v0.16b, v1.16b, v2.16b }, [x0], x9 // encoding: [0x00,0xe0,0xc9,0x4d] +// CHECK: ld3r { v15.8h, v16.8h, v17.8h }, [x15], x6 // encoding: [0xef,0xe5,0xc6,0x4d] +// CHECK: ld3r { v31.4s, v0.4s, v1.4s }, [sp], x7 // encoding: [0xff,0xeb,0xc7,0x4d] +// CHECK: ld3r { v0.2d, v1.2d, v2.2d }, [x0], x5 // encoding: [0x00,0xec,0xc5,0x4d] +// CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 // encoding: [0x00,0xe0,0xdf,0x0d] +// CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6 // encoding: [0xef,0xe5,0xdf,0x0d] +// CHECK: ld3r { v31.2s, v0.2s, v1.2s }, [sp], #12 // encoding: [0xff,0xeb,0xdf,0x0d] +// CHECK: ld3r { v31.1d, v0.1d, v1.1d }, [sp], #24 // encoding: [0xff,0xef,0xdf,0x0d] - ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], #4 - ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], #8 - ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #16 - ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #32 - ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x5 - ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x9 - ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 - ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 -// CHECK: ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], #4 // encoding: [0x00,0xe0,0xff,0x4d] -// CHECK: ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], #8 // encoding: [0xef,0xe5,0xff,0x4d] -// CHECK: ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #16 // encoding: [0xff,0xeb,0xff,0x4d] -// CHECK: ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #32 // encoding: [0x00,0xec,0xff,0x4d] -// CHECK: ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x5 // encoding: [0x00,0xe0,0xe5,0x0d] -// CHECK: ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x9 // encoding: [0xef,0xe5,0xe9,0x0d] -// CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 // encoding: [0xff,0xeb,0xfe,0x0d] -// CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 // encoding: [0xff,0xef,0xe7,0x0d] + ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], #4 + ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], #8 + ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #16 + ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #32 + ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x5 + ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x9 + ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30 + ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7 +// CHECK: ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], #4 // encoding: [0x00,0xe0,0xff,0x4d] +// CHECK: ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], #8 // encoding: [0xef,0xe5,0xff,0x4d] +// CHECK: ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #16 // encoding: [0xff,0xeb,0xff,0x4d] +// CHECK: ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #32 // encoding: [0x00,0xec,0xff,0x4d] +// CHECK: ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x5 // encoding: [0x00,0xe0,0xe5,0x0d] +// CHECK: ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x9 // encoding: [0xef,0xe5,0xe9,0x0d] +// CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30 // encoding: [0xff,0xeb,0xfe,0x0d] +// CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7 // encoding: [0xff,0xef,0xe7,0x0d] //------------------------------------------------------------------------------ // Post-index load single 1-element structure to one lane of 1 register. //------------------------------------------------------------------------------ - ld1 {v0.b}[9], [x0], #1 - ld1 {v15.h}[7], [x15], x9 - ld1 {v31.s}[3], [sp], x6 - ld1 {v0.d}[1], [x0], #8 -// CHECK: ld1 {v0.b}[9], [x0], #1 // encoding: [0x00,0x04,0xdf,0x4d] -// CHECK: ld1 {v15.h}[7], [x15], x9 // encoding: [0xef,0x59,0xc9,0x4d] -// CHECK: ld1 {v31.s}[3], [sp], x6 // encoding: [0xff,0x93,0xc6,0x4d] -// CHECK: ld1 {v0.d}[1], [x0], #8 // encoding: [0x00,0x84,0xdf,0x4d] + ld1 { v0.b }[9], [x0], #1 + ld1 { v15.h }[7], [x15], x9 + ld1 { v31.s }[3], [sp], x6 + ld1 { v0.d }[1], [x0], #8 +// CHECK: ld1 { v0.b }[9], [x0], #1 // encoding: [0x00,0x04,0xdf,0x4d] +// CHECK: ld1 { v15.h }[7], [x15], x9 // encoding: [0xef,0x59,0xc9,0x4d] +// CHECK: ld1 { v31.s }[3], [sp], x6 // encoding: [0xff,0x93,0xc6,0x4d] +// CHECK: ld1 { v0.d }[1], [x0], #8 // encoding: [0x00,0x84,0xdf,0x4d] //------------------------------------------------------------------------------ // Post-index load single N-element structure to one lane of N consecutive // registers (N = 2,3,4) //------------------------------------------------------------------------------ - ld2 {v0.b, v1.b}[9], [x0], x3 - ld2 {v15.h, v16.h}[7], [x15], #4 - ld2 {v31.s, v0.s}[3], [sp], #8 - ld2 {v0.d, v1.d}[1], [x0], x0 -// CHECK: ld2 {v0.b, v1.b}[9], [x0], x3 // encoding: [0x00,0x04,0xe3,0x4d] -// CHECK: ld2 {v15.h, v16.h}[7], [x15], #4 // encoding: [0xef,0x59,0xff,0x4d] -// CHECK: ld2 {v31.s, v0.s}[3], [sp], #8 // encoding: [0xff,0x93,0xff,0x4d] -// CHECK: ld2 {v0.d, v1.d}[1], [x0], x0 // encoding: [0x00,0x84,0xe0,0x4d] + ld2 { v0.b, v1.b }[9], [x0], x3 + ld2 { v15.h, v16.h }[7], [x15], #4 + ld2 { v31.s, v0.s }[3], [sp], #8 + ld2 { v0.d, v1.d }[1], [x0], x0 +// CHECK: ld2 { v0.b, v1.b }[9], [x0], x3 // encoding: [0x00,0x04,0xe3,0x4d] +// CHECK: ld2 { v15.h, v16.h }[7], [x15], #4 // encoding: [0xef,0x59,0xff,0x4d] +// CHECK: ld2 { v31.s, v0.s }[3], [sp], #8 // encoding: [0xff,0x93,0xff,0x4d] +// CHECK: ld2 { v0.d, v1.d }[1], [x0], x0 // encoding: [0x00,0x84,0xe0,0x4d] - ld3 {v0.b, v1.b, v2.b}[9], [x0], #3 - ld3 {v15.h, v16.h, v17.h}[7], [x15], #6 - ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 - ld3 {v0.d, v1.d, v2.d}[1], [x0], x6 -// CHECK: ld3 {v0.b, v1.b, v2.b}[9], [x0], #3 // encoding: [0x00,0x24,0xdf,0x4d] -// CHECK: ld3 {v15.h, v16.h, v17.h}[7], [x15], #6 // encoding: [0xef,0x79,0xdf,0x4d] -// CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 // encoding: [0xff,0xb3,0xc3,0x4d] -// CHECK: ld3 {v0.d, v1.d, v2.d}[1], [x0], x6 // encoding: [0x00,0xa4,0xc6,0x4d] + ld3 { v0.b, v1.b, v2.b }[9], [x0], #3 + ld3 { v15.h, v16.h, v17.h }[7], [x15], #6 + ld3 { v31.s, v0.s, v1.s }[3], [sp], x3 + ld3 { v0.d, v1.d, v2.d }[1], [x0], x6 +// CHECK: ld3 { v0.b, v1.b, v2.b }[9], [x0], #3 // encoding: [0x00,0x24,0xdf,0x4d] +// CHECK: ld3 { v15.h, v16.h, v17.h }[7], [x15], #6 // encoding: [0xef,0x79,0xdf,0x4d] +// CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp], x3 // encoding: [0xff,0xb3,0xc3,0x4d] +// CHECK: ld3 { v0.d, v1.d, v2.d }[1], [x0], x6 // encoding: [0x00,0xa4,0xc6,0x4d] - ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 - ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 - ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 - ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 -// CHECK: ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 // encoding: [0x00,0x24,0xe5,0x4d] -// CHECK: ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 // encoding: [0xef,0x79,0xe7,0x4d] -// CHECK: ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 // encoding: [0xff,0xb3,0xff,0x4d] -// CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 // encoding: [0x00,0xa4,0xff,0x4d] + ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 + ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7 + ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16 + ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 +// CHECK: ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 // encoding: [0x00,0x24,0xe5,0x4d] +// CHECK: ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7 // encoding: [0xef,0x79,0xe7,0x4d] +// CHECK: ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16 // encoding: [0xff,0xb3,0xff,0x4d] +// CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 // encoding: [0x00,0xa4,0xff,0x4d] //------------------------------------------------------------------------------ // Post-index store single 1-element structure from one lane of 1 register. //------------------------------------------------------------------------------ - st1 {v0.b}[9], [x0], #1 - st1 {v15.h}[7], [x15], x9 - st1 {v31.s}[3], [sp], x6 - st1 {v0.d}[1], [x0], #8 -// CHECK: st1 {v0.b}[9], [x0], #1 // encoding: [0x00,0x04,0x9f,0x4d] -// CHECK: st1 {v15.h}[7], [x15], x9 // encoding: [0xef,0x59,0x89,0x4d] -// CHECK: st1 {v31.s}[3], [sp], x6 // encoding: [0xff,0x93,0x86,0x4d] -// CHECK: st1 {v0.d}[1], [x0], #8 // encoding: [0x00,0x84,0x9f,0x4d] + st1 { v0.b }[9], [x0], #1 + st1 { v15.h }[7], [x15], x9 + st1 { v31.s }[3], [sp], x6 + st1 { v0.d }[1], [x0], #8 +// CHECK: st1 { v0.b }[9], [x0], #1 // encoding: [0x00,0x04,0x9f,0x4d] +// CHECK: st1 { v15.h }[7], [x15], x9 // encoding: [0xef,0x59,0x89,0x4d] +// CHECK: st1 { v31.s }[3], [sp], x6 // encoding: [0xff,0x93,0x86,0x4d] +// CHECK: st1 { v0.d }[1], [x0], #8 // encoding: [0x00,0x84,0x9f,0x4d] //------------------------------------------------------------------------------ // Post-index store single N-element structure from one lane of N consecutive // registers (N = 2,3,4) //------------------------------------------------------------------------------ - st2 {v0.b, v1.b}[9], [x0], x3 - st2 {v15.h, v16.h}[7], [x15], #4 - st2 {v31.s, v0.s}[3], [sp], #8 - st2 {v0.d, v1.d}[1], [x0], x0 -// CHECK: st2 {v0.b, v1.b}[9], [x0], x3 // encoding: [0x00,0x04,0xa3,0x4d] -// CHECK: st2 {v15.h, v16.h}[7], [x15], #4 // encoding: [0xef,0x59,0xbf,0x4d] -// CHECK: st2 {v31.s, v0.s}[3], [sp], #8 // encoding: [0xff,0x93,0xbf,0x4d] -// CHECK: st2 {v0.d, v1.d}[1], [x0], x0 // encoding: [0x00,0x84,0xa0,0x4d] + st2 { v0.b, v1.b }[9], [x0], x3 + st2 { v15.h, v16.h }[7], [x15], #4 + st2 { v31.s, v0.s }[3], [sp], #8 + st2 { v0.d, v1.d }[1], [x0], x0 +// CHECK: st2 { v0.b, v1.b }[9], [x0], x3 // encoding: [0x00,0x04,0xa3,0x4d] +// CHECK: st2 { v15.h, v16.h }[7], [x15], #4 // encoding: [0xef,0x59,0xbf,0x4d] +// CHECK: st2 { v31.s, v0.s }[3], [sp], #8 // encoding: [0xff,0x93,0xbf,0x4d] +// CHECK: st2 { v0.d, v1.d }[1], [x0], x0 // encoding: [0x00,0x84,0xa0,0x4d] - st3 {v0.b, v1.b, v2.b}[9], [x0], #3 - st3 {v15.h, v16.h, v17.h}[7], [x15], #6 - st3 {v31.s, v0.s, v1.s}[3], [sp], x3 - st3 {v0.d, v1.d, v2.d}[1], [x0], x6 -// CHECK: st3 {v0.b, v1.b, v2.b}[9], [x0], #3 // encoding: [0x00,0x24,0x9f,0x4d] -// CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6 // encoding: [0xef,0x79,0x9f,0x4d] -// CHECK: st3 {v31.s, v0.s, v1.s}[3], [sp], x3 // encoding: [0xff,0xb3,0x83,0x4d] -// CHECK: st3 {v0.d, v1.d, v2.d}[1], [x0], x6 // encoding: [0x00,0xa4,0x86,0x4d] + st3 { v0.b, v1.b, v2.b }[9], [x0], #3 + st3 { v15.h, v16.h, v17.h }[7], [x15], #6 + st3 { v31.s, v0.s, v1.s }[3], [sp], x3 + st3 { v0.d, v1.d, v2.d }[1], [x0], x6 +// CHECK: st3 { v0.b, v1.b, v2.b }[9], [x0], #3 // encoding: [0x00,0x24,0x9f,0x4d] +// CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15], #6 // encoding: [0xef,0x79,0x9f,0x4d] +// CHECK: st3 { v31.s, v0.s, v1.s }[3], [sp], x3 // encoding: [0xff,0xb3,0x83,0x4d] +// CHECK: st3 { v0.d, v1.d, v2.d }[1], [x0], x6 // encoding: [0x00,0xa4,0x86,0x4d] - st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 - st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 - st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 - st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 -// CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 // encoding: [0x00,0x24,0xa5,0x4d] -// CHECK: st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 // encoding: [0xef,0x79,0xa7,0x4d] -// CHECK: st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 // encoding: [0xff,0xb3,0xbf,0x4d] -// CHECK: st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 // encoding: [0x00,0xa4,0xbf,0x4d] + st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 + st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7 + st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16 + st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 +// CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 // encoding: [0x00,0x24,0xa5,0x4d] +// CHECK: st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7 // encoding: [0xef,0x79,0xa7,0x4d] +// CHECK: st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16 // encoding: [0xff,0xb3,0xbf,0x4d] +// CHECK: st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 // encoding: [0x00,0xa4,0xbf,0x4d] diff --git a/test/MC/AArch64/neon-simd-misc.s b/test/MC/AArch64/neon-simd-misc.s index 9e0f9c5..6d1aafd 100644 --- a/test/MC/AArch64/neon-simd-misc.s +++ b/test/MC/AArch64/neon-simd-misc.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 @@ -281,8 +281,8 @@ not v0.16b, v31.16b not v1.8b, v9.8b -// CHECK: not v0.16b, v31.16b // encoding: [0xe0,0x5b,0x20,0x6e] -// CHECK: not v1.8b, v9.8b // encoding: [0x21,0x59,0x20,0x2e] +// CHECK: {{mvn|not}} v0.16b, v31.16b // encoding: [0xe0,0x5b,0x20,0x6e] +// CHECK: {{mvn|not}} v1.8b, v9.8b // encoding: [0x21,0x59,0x20,0x2e] //------------------------------------------------------------------------------ // Bitwise reverse diff --git a/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s b/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s index 8dc271e..c57a122 100644 --- a/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s +++ b/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s @@ -1,389 +1,389 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 //------------------------------------------------------------------------------ // Load multiple 1-element structures from one register (post-index) //------------------------------------------------------------------------------ - ld1 {v0.16b}, [x0], x1 - ld1 {v15.8h}, [x15], x2 - ld1 {v31.4s}, [sp], #16 - ld1 {v0.2d}, [x0], #16 - ld1 {v0.8b}, [x0], x2 - ld1 {v15.4h}, [x15], x3 - ld1 {v31.2s}, [sp], #8 - ld1 {v0.1d}, [x0], #8 -// CHECK: ld1 {v0.16b}, [x0], x1 + ld1 { v0.16b }, [x0], x1 + ld1 { v15.8h }, [x15], x2 + ld1 { v31.4s }, [sp], #16 + ld1 { v0.2d }, [x0], #16 + ld1 { v0.8b }, [x0], x2 + ld1 { v15.4h }, [x15], x3 + ld1 { v31.2s }, [sp], #8 + ld1 { v0.1d }, [x0], #8 +// CHECK: ld1 { v0.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x70,0xc1,0x4c] -// CHECK: ld1 {v15.8h}, [x15], x2 +// CHECK: ld1 { v15.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x75,0xc2,0x4c] -// CHECK: ld1 {v31.4s}, [sp], #16 +// CHECK: ld1 { v31.4s }, [sp], #16 // CHECK: // encoding: [0xff,0x7b,0xdf,0x4c] -// CHECK: ld1 {v0.2d}, [x0], #16 +// CHECK: ld1 { v0.2d }, [x0], #16 // CHECK: // encoding: [0x00,0x7c,0xdf,0x4c] -// CHECK: ld1 {v0.8b}, [x0], x2 +// CHECK: ld1 { v0.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x70,0xc2,0x0c] -// CHECK: ld1 {v15.4h}, [x15], x3 +// CHECK: ld1 { v15.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x75,0xc3,0x0c] -// CHECK: ld1 {v31.2s}, [sp], #8 +// CHECK: ld1 { v31.2s }, [sp], #8 // CHECK: // encoding: [0xff,0x7b,0xdf,0x0c] -// CHECK: ld1 {v0.1d}, [x0], #8 +// CHECK: ld1 { v0.1d }, [x0], #8 // CHECK: // encoding: [0x00,0x7c,0xdf,0x0c] //------------------------------------------------------------------------------ // Load multiple 1-element structures from two consecutive registers // (post-index) //------------------------------------------------------------------------------ - ld1 {v0.16b, v1.16b}, [x0], x1 - ld1 {v15.8h, v16.8h}, [x15], x2 - ld1 {v31.4s, v0.4s}, [sp], #32 - ld1 {v0.2d, v1.2d}, [x0], #32 - ld1 {v0.8b, v1.8b}, [x0], x2 - ld1 {v15.4h, v16.4h}, [x15], x3 - ld1 {v31.2s, v0.2s}, [sp], #16 - ld1 {v0.1d, v1.1d}, [x0], #16 -// CHECK: ld1 {v0.16b, v1.16b}, [x0], x1 + ld1 { v0.16b, v1.16b }, [x0], x1 + ld1 { v15.8h, v16.8h }, [x15], x2 + ld1 { v31.4s, v0.4s }, [sp], #32 + ld1 { v0.2d, v1.2d }, [x0], #32 + ld1 { v0.8b, v1.8b }, [x0], x2 + ld1 { v15.4h, v16.4h }, [x15], x3 + ld1 { v31.2s, v0.2s }, [sp], #16 + ld1 { v0.1d, v1.1d }, [x0], #16 +// CHECK: ld1 { v0.16b, v1.16b }, [x0], x1 // CHECK: // encoding: [0x00,0xa0,0xc1,0x4c] -// CHECK: ld1 {v15.8h, v16.8h}, [x15], x2 +// CHECK: ld1 { v15.8h, v16.8h }, [x15], x2 // CHECK: // encoding: [0xef,0xa5,0xc2,0x4c] -// CHECK: ld1 {v31.4s, v0.4s}, [sp], #32 +// CHECK: ld1 { v31.4s, v0.4s }, [sp], #32 // CHECK: // encoding: [0xff,0xab,0xdf,0x4c] -// CHECK: ld1 {v0.2d, v1.2d}, [x0], #32 +// CHECK: ld1 { v0.2d, v1.2d }, [x0], #32 // CHECK: // encoding: [0x00,0xac,0xdf,0x4c] -// CHECK: ld1 {v0.8b, v1.8b}, [x0], x2 +// CHECK: ld1 { v0.8b, v1.8b }, [x0], x2 // CHECK: // encoding: [0x00,0xa0,0xc2,0x0c] -// CHECK: ld1 {v15.4h, v16.4h}, [x15], x3 +// CHECK: ld1 { v15.4h, v16.4h }, [x15], x3 // CHECK: // encoding: [0xef,0xa5,0xc3,0x0c] -// CHECK: ld1 {v31.2s, v0.2s}, [sp], #16 +// CHECK: ld1 { v31.2s, v0.2s }, [sp], #16 // CHECK: // encoding: [0xff,0xab,0xdf,0x0c] -// CHECK: ld1 {v0.1d, v1.1d}, [x0], #16 +// CHECK: ld1 { v0.1d, v1.1d }, [x0], #16 // CHECK: // encoding: [0x00,0xac,0xdf,0x0c] //------------------------------------------------------------------------------ // Load multiple 1-element structures from three consecutive registers // (post-index) //------------------------------------------------------------------------------ - ld1 {v0.16b, v1.16b, v2.16b}, [x0], x1 - ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2 - ld1 {v31.4s, v0.4s, v1.4s}, [sp], #48 - ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 - ld1 {v0.8b, v1.8b, v2.8b}, [x0], x2 - ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3 - ld1 {v31.2s, v0.2s, v1.2s}, [sp], #24 - ld1 {v0.1d, v1.1d, v2.1d}, [x0], #24 -// CHECK: ld1 {v0.16b, v1.16b, v2.16b}, [x0], x1 + ld1 { v0.16b, v1.16b, v2.16b }, [x0], x1 + ld1 { v15.8h, v16.8h, v17.8h }, [x15], x2 + ld1 { v31.4s, v0.4s, v1.4s }, [sp], #48 + ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48 + ld1 { v0.8b, v1.8b, v2.8b }, [x0], x2 + ld1 { v15.4h, v16.4h, v17.4h }, [x15], x3 + ld1 { v31.2s, v0.2s, v1.2s }, [sp], #24 + ld1 { v0.1d, v1.1d, v2.1d }, [x0], #24 +// CHECK: ld1 { v0.16b, v1.16b, v2.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x60,0xc1,0x4c] -// CHECK: ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: ld1 { v15.8h, v16.8h, v17.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x65,0xc2,0x4c] -// CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp], #48 // CHECK: // encoding: [0xff,0x6b,0xdf,0x4c] -// CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48 // CHECK: // encoding: [0x00,0x6c,0xdf,0x4c] -// CHECK: ld1 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: ld1 { v0.8b, v1.8b, v2.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x60,0xc2,0x0c] -// CHECK: ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: ld1 { v15.4h, v16.4h, v17.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x65,0xc3,0x0c] -// CHECK: ld1 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: ld1 { v31.2s, v0.2s, v1.2s }, [sp], #24 // CHECK: // encoding: [0xff,0x6b,0xdf,0x0c] -// CHECK: ld1 {v0.1d, v1.1d, v2.1d}, [x0], #24 +// CHECK: ld1 { v0.1d, v1.1d, v2.1d }, [x0], #24 // CHECK: // encoding: [0x00,0x6c,0xdf,0x0c] //------------------------------------------------------------------------------ // Load multiple 1-element structures from four consecutive registers // (post-index) //------------------------------------------------------------------------------ - ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 - ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 - ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 - ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 - ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 - ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 - ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 - ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 -// CHECK: ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 + ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 + ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 + ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 + ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 + ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 + ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 + ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32 +// CHECK: ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x20,0xc1,0x4c] -// CHECK: ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x25,0xc2,0x4c] -// CHECK: ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 // CHECK: // encoding: [0xff,0x2b,0xdf,0x4c] -// CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 // CHECK: // encoding: [0x00,0x2c,0xdf,0x4c] -// CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 // CHECK: // encoding: [0x00,0x20,0xc3,0x0c] -// CHECK: ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 // CHECK: // encoding: [0xef,0x25,0xc4,0x0c] -// CHECK: ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 // CHECK: // encoding: [0xff,0x2b,0xdf,0x0c] -// CHECK: ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 +// CHECK: ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32 // CHECK: // encoding: [0x00,0x2c,0xdf,0x0c] //------------------------------------------------------------------------------ // Load multiple 2-element structures from two consecutive registers // (post-index) //------------------------------------------------------------------------------ - ld2 {v0.16b, v1.16b}, [x0], x1 - ld2 {v15.8h, v16.8h}, [x15], x2 - ld2 {v31.4s, v0.4s}, [sp], #32 - ld2 {v0.2d, v1.2d}, [x0], #32 - ld2 {v0.8b, v1.8b}, [x0], x2 - ld2 {v15.4h, v16.4h}, [x15], x3 - ld2 {v31.2s, v0.2s}, [sp], #16 -// CHECK: ld2 {v0.16b, v1.16b}, [x0], x1 + ld2 { v0.16b, v1.16b }, [x0], x1 + ld2 { v15.8h, v16.8h }, [x15], x2 + ld2 { v31.4s, v0.4s }, [sp], #32 + ld2 { v0.2d, v1.2d }, [x0], #32 + ld2 { v0.8b, v1.8b }, [x0], x2 + ld2 { v15.4h, v16.4h }, [x15], x3 + ld2 { v31.2s, v0.2s }, [sp], #16 +// CHECK: ld2 { v0.16b, v1.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x80,0xc1,0x4c] -// CHECK: ld2 {v15.8h, v16.8h}, [x15], x2 +// CHECK: ld2 { v15.8h, v16.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x85,0xc2,0x4c] -// CHECK: ld2 {v31.4s, v0.4s}, [sp], #32 +// CHECK: ld2 { v31.4s, v0.4s }, [sp], #32 // CHECK: // encoding: [0xff,0x8b,0xdf,0x4c] -// CHECK: ld2 {v0.2d, v1.2d}, [x0], #32 +// CHECK: ld2 { v0.2d, v1.2d }, [x0], #32 // CHECK: // encoding: [0x00,0x8c,0xdf,0x4c] -// CHECK: ld2 {v0.8b, v1.8b}, [x0], x2 +// CHECK: ld2 { v0.8b, v1.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x80,0xc2,0x0c] -// CHECK: ld2 {v15.4h, v16.4h}, [x15], x3 +// CHECK: ld2 { v15.4h, v16.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x85,0xc3,0x0c] -// CHECK: ld2 {v31.2s, v0.2s}, [sp], #16 +// CHECK: ld2 { v31.2s, v0.2s }, [sp], #16 // CHECK: // encoding: [0xff,0x8b,0xdf,0x0c] //------------------------------------------------------------------------------ // Load multiple 3-element structures from three consecutive registers // (post-index) //------------------------------------------------------------------------------ - ld3 {v0.16b, v1.16b, v2.16b}, [x0], x1 - ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 - ld3 {v31.4s, v0.4s, v1.4s}, [sp], #48 - ld3 {v0.2d, v1.2d, v2.2d}, [x0], #48 - ld3 {v0.8b, v1.8b, v2.8b}, [x0], x2 - ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3 - ld3 {v31.2s, v0.2s, v1.2s}, [sp], #24 -// CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0], x1 + ld3 { v0.16b, v1.16b, v2.16b }, [x0], x1 + ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2 + ld3 { v31.4s, v0.4s, v1.4s }, [sp], #48 + ld3 { v0.2d, v1.2d, v2.2d }, [x0], #48 + ld3 { v0.8b, v1.8b, v2.8b }, [x0], x2 + ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3 + ld3 { v31.2s, v0.2s, v1.2s }, [sp], #24 +// CHECK: ld3 { v0.16b, v1.16b, v2.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x40,0xc1,0x4c] -// CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x45,0xc2,0x4c] -// CHECK: ld3 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: ld3 { v31.4s, v0.4s, v1.4s }, [sp], #48 // CHECK: // encoding: [0xff,0x4b,0xdf,0x4c] -// CHECK: ld3 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: ld3 { v0.2d, v1.2d, v2.2d }, [x0], #48 // CHECK: // encoding: [0x00,0x4c,0xdf,0x4c] -// CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: ld3 { v0.8b, v1.8b, v2.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x40,0xc2,0x0c] -// CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x45,0xc3,0x0c] -// CHECK: ld3 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: ld3 { v31.2s, v0.2s, v1.2s }, [sp], #24 // CHECK: // encoding: [0xff,0x4b,0xdf,0x0c] //------------------------------------------------------------------------------ // Load multiple 4-element structures from four consecutive registers // (post-index) //------------------------------------------------------------------------------ - ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 - ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 - ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 - ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 - ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 - ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 - ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 -// CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 + ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 + ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 + ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 + ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 + ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 + ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 +// CHECK: ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x00,0xc1,0x4c] -// CHECK: ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x05,0xc2,0x4c] -// CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 // CHECK: // encoding: [0xff,0x0b,0xdf,0x4c] -// CHECK: ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 // CHECK: // encoding: [0x00,0x0c,0xdf,0x4c] -// CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 // CHECK: // encoding: [0x00,0x00,0xc3,0x0c] -// CHECK: ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 // CHECK: // encoding: [0xef,0x05,0xc4,0x0c] -// CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 // CHECK: // encoding: [0xff,0x0b,0xdf,0x0c] //------------------------------------------------------------------------------ // Store multiple 1-element structures from one register (post-index) //------------------------------------------------------------------------------ - st1 {v0.16b}, [x0], x1 - st1 {v15.8h}, [x15], x2 - st1 {v31.4s}, [sp], #16 - st1 {v0.2d}, [x0], #16 - st1 {v0.8b}, [x0], x2 - st1 {v15.4h}, [x15], x3 - st1 {v31.2s}, [sp], #8 - st1 {v0.1d}, [x0], #8 -// CHECK: st1 {v0.16b}, [x0], x1 + st1 { v0.16b }, [x0], x1 + st1 { v15.8h }, [x15], x2 + st1 { v31.4s }, [sp], #16 + st1 { v0.2d }, [x0], #16 + st1 { v0.8b }, [x0], x2 + st1 { v15.4h }, [x15], x3 + st1 { v31.2s }, [sp], #8 + st1 { v0.1d }, [x0], #8 +// CHECK: st1 { v0.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x70,0x81,0x4c] -// CHECK: st1 {v15.8h}, [x15], x2 +// CHECK: st1 { v15.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x75,0x82,0x4c] -// CHECK: st1 {v31.4s}, [sp], #16 +// CHECK: st1 { v31.4s }, [sp], #16 // CHECK: // encoding: [0xff,0x7b,0x9f,0x4c] -// CHECK: st1 {v0.2d}, [x0], #16 +// CHECK: st1 { v0.2d }, [x0], #16 // CHECK: // encoding: [0x00,0x7c,0x9f,0x4c] -// CHECK: st1 {v0.8b}, [x0], x2 +// CHECK: st1 { v0.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x70,0x82,0x0c] -// CHECK: st1 {v15.4h}, [x15], x3 +// CHECK: st1 { v15.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x75,0x83,0x0c] -// CHECK: st1 {v31.2s}, [sp], #8 +// CHECK: st1 { v31.2s }, [sp], #8 // CHECK: // encoding: [0xff,0x7b,0x9f,0x0c] -// CHECK: st1 {v0.1d}, [x0], #8 +// CHECK: st1 { v0.1d }, [x0], #8 // CHECK: // encoding: [0x00,0x7c,0x9f,0x0c] //------------------------------------------------------------------------------ // Store multiple 1-element structures from two consecutive registers // (post-index) //------------------------------------------------------------------------------ - st1 {v0.16b, v1.16b}, [x0], x1 - st1 {v15.8h, v16.8h}, [x15], x2 - st1 {v31.4s, v0.4s}, [sp], #32 - st1 {v0.2d, v1.2d}, [x0], #32 - st1 {v0.8b, v1.8b}, [x0], x2 - st1 {v15.4h, v16.4h}, [x15], x3 - st1 {v31.2s, v0.2s}, [sp], #16 - st1 {v0.1d, v1.1d}, [x0], #16 -// CHECK: st1 {v0.16b, v1.16b}, [x0], x1 + st1 { v0.16b, v1.16b }, [x0], x1 + st1 { v15.8h, v16.8h }, [x15], x2 + st1 { v31.4s, v0.4s }, [sp], #32 + st1 { v0.2d, v1.2d }, [x0], #32 + st1 { v0.8b, v1.8b }, [x0], x2 + st1 { v15.4h, v16.4h }, [x15], x3 + st1 { v31.2s, v0.2s }, [sp], #16 + st1 { v0.1d, v1.1d }, [x0], #16 +// CHECK: st1 { v0.16b, v1.16b }, [x0], x1 // CHECK: // encoding: [0x00,0xa0,0x81,0x4c] -// CHECK: st1 {v15.8h, v16.8h}, [x15], x2 +// CHECK: st1 { v15.8h, v16.8h }, [x15], x2 // CHECK: // encoding: [0xef,0xa5,0x82,0x4c] -// CHECK: st1 {v31.4s, v0.4s}, [sp], #32 +// CHECK: st1 { v31.4s, v0.4s }, [sp], #32 // CHECK: // encoding: [0xff,0xab,0x9f,0x4c] -// CHECK: st1 {v0.2d, v1.2d}, [x0], #32 +// CHECK: st1 { v0.2d, v1.2d }, [x0], #32 // CHECK: // encoding: [0x00,0xac,0x9f,0x4c] -// CHECK: st1 {v0.8b, v1.8b}, [x0], x2 +// CHECK: st1 { v0.8b, v1.8b }, [x0], x2 // CHECK: // encoding: [0x00,0xa0,0x82,0x0c] -// CHECK: st1 {v15.4h, v16.4h}, [x15], x3 +// CHECK: st1 { v15.4h, v16.4h }, [x15], x3 // CHECK: // encoding: [0xef,0xa5,0x83,0x0c] -// CHECK: st1 {v31.2s, v0.2s}, [sp], #16 +// CHECK: st1 { v31.2s, v0.2s }, [sp], #16 // CHECK: // encoding: [0xff,0xab,0x9f,0x0c] -// CHECK: st1 {v0.1d, v1.1d}, [x0], #16 +// CHECK: st1 { v0.1d, v1.1d }, [x0], #16 // CHECK: // encoding: [0x00,0xac,0x9f,0x0c] //------------------------------------------------------------------------------ // Store multiple 1-element structures from three consecutive registers // (post-index) //------------------------------------------------------------------------------ - st1 {v0.16b, v1.16b, v2.16b}, [x0], x1 - st1 {v15.8h, v16.8h, v17.8h}, [x15], x2 - st1 {v31.4s, v0.4s, v1.4s}, [sp], #48 - st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 - st1 {v0.8b, v1.8b, v2.8b}, [x0], x2 - st1 {v15.4h, v16.4h, v17.4h}, [x15], x3 - st1 {v31.2s, v0.2s, v1.2s}, [sp], #24 - st1 {v0.1d, v1.1d, v2.1d}, [x0], #24 -// CHECK: st1 {v0.16b, v1.16b, v2.16b}, [x0], x1 + st1 { v0.16b, v1.16b, v2.16b }, [x0], x1 + st1 { v15.8h, v16.8h, v17.8h }, [x15], x2 + st1 { v31.4s, v0.4s, v1.4s }, [sp], #48 + st1 { v0.2d, v1.2d, v2.2d }, [x0], #48 + st1 { v0.8b, v1.8b, v2.8b }, [x0], x2 + st1 { v15.4h, v16.4h, v17.4h }, [x15], x3 + st1 { v31.2s, v0.2s, v1.2s }, [sp], #24 + st1 { v0.1d, v1.1d, v2.1d }, [x0], #24 +// CHECK: st1 { v0.16b, v1.16b, v2.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x60,0x81,0x4c] -// CHECK: st1 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: st1 { v15.8h, v16.8h, v17.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x65,0x82,0x4c] -// CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp], #48 // CHECK: // encoding: [0xff,0x6b,0x9f,0x4c] -// CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0], #48 // CHECK: // encoding: [0x00,0x6c,0x9f,0x4c] -// CHECK: st1 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: st1 { v0.8b, v1.8b, v2.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x60,0x82,0x0c] -// CHECK: st1 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: st1 { v15.4h, v16.4h, v17.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x65,0x83,0x0c] -// CHECK: st1 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: st1 { v31.2s, v0.2s, v1.2s }, [sp], #24 // CHECK: // encoding: [0xff,0x6b,0x9f,0x0c] -// CHECK: st1 {v0.1d, v1.1d, v2.1d}, [x0], #24 +// CHECK: st1 { v0.1d, v1.1d, v2.1d }, [x0], #24 // CHECK: // encoding: [0x00,0x6c,0x9f,0x0c] //------------------------------------------------------------------------------ // Store multiple 1-element structures from four consecutive registers // (post-index) //------------------------------------------------------------------------------ - st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 - st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 - st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 - st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 - st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 - st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 - st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 - st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 -// CHECK: st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 + st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 + st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 + st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 + st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 + st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 + st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 + st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32 +// CHECK: st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x20,0x81,0x4c] -// CHECK: st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x25,0x82,0x4c] -// CHECK: st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 // CHECK: // encoding: [0xff,0x2b,0x9f,0x4c] -// CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 // CHECK: // encoding: [0x00,0x2c,0x9f,0x4c] -// CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 // CHECK: // encoding: [0x00,0x20,0x83,0x0c] -// CHECK: st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 // CHECK: // encoding: [0xef,0x25,0x84,0x0c] -// CHECK: st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 // CHECK: // encoding: [0xff,0x2b,0x9f,0x0c] -// CHECK: st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 +// CHECK: st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32 // CHECK: // encoding: [0x00,0x2c,0x9f,0x0c] //------------------------------------------------------------------------------ // Store multiple 2-element structures from two consecutive registers // (post-index) //------------------------------------------------------------------------------ - st2 {v0.16b, v1.16b}, [x0], x1 - st2 {v15.8h, v16.8h}, [x15], x2 - st2 {v31.4s, v0.4s}, [sp], #32 - st2 {v0.2d, v1.2d}, [x0], #32 - st2 {v0.8b, v1.8b}, [x0], x2 - st2 {v15.4h, v16.4h}, [x15], x3 - st2 {v31.2s, v0.2s}, [sp], #16 -// CHECK: st2 {v0.16b, v1.16b}, [x0], x1 + st2 { v0.16b, v1.16b }, [x0], x1 + st2 { v15.8h, v16.8h }, [x15], x2 + st2 { v31.4s, v0.4s }, [sp], #32 + st2 { v0.2d, v1.2d }, [x0], #32 + st2 { v0.8b, v1.8b }, [x0], x2 + st2 { v15.4h, v16.4h }, [x15], x3 + st2 { v31.2s, v0.2s }, [sp], #16 +// CHECK: st2 { v0.16b, v1.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x80,0x81,0x4c] -// CHECK: st2 {v15.8h, v16.8h}, [x15], x2 +// CHECK: st2 { v15.8h, v16.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x85,0x82,0x4c] -// CHECK: st2 {v31.4s, v0.4s}, [sp], #32 +// CHECK: st2 { v31.4s, v0.4s }, [sp], #32 // CHECK: // encoding: [0xff,0x8b,0x9f,0x4c] -// CHECK: st2 {v0.2d, v1.2d}, [x0], #32 +// CHECK: st2 { v0.2d, v1.2d }, [x0], #32 // CHECK: // encoding: [0x00,0x8c,0x9f,0x4c] -// CHECK: st2 {v0.8b, v1.8b}, [x0], x2 +// CHECK: st2 { v0.8b, v1.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x80,0x82,0x0c] -// CHECK: st2 {v15.4h, v16.4h}, [x15], x3 +// CHECK: st2 { v15.4h, v16.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x85,0x83,0x0c] -// CHECK: st2 {v31.2s, v0.2s}, [sp], #16 +// CHECK: st2 { v31.2s, v0.2s }, [sp], #16 // CHECK: // encoding: [0xff,0x8b,0x9f,0x0c] //------------------------------------------------------------------------------ // Store multiple 3-element structures from three consecutive registers // (post-index) //------------------------------------------------------------------------------ - st3 {v0.16b, v1.16b, v2.16b}, [x0], x1 - st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 - st3 {v31.4s, v0.4s, v1.4s}, [sp], #48 - st3 {v0.2d, v1.2d, v2.2d}, [x0], #48 - st3 {v0.8b, v1.8b, v2.8b}, [x0], x2 - st3 {v15.4h, v16.4h, v17.4h}, [x15], x3 - st3 {v31.2s, v0.2s, v1.2s}, [sp], #24 -// CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0], x1 + st3 { v0.16b, v1.16b, v2.16b }, [x0], x1 + st3 { v15.8h, v16.8h, v17.8h }, [x15], x2 + st3 { v31.4s, v0.4s, v1.4s }, [sp], #48 + st3 { v0.2d, v1.2d, v2.2d }, [x0], #48 + st3 { v0.8b, v1.8b, v2.8b }, [x0], x2 + st3 { v15.4h, v16.4h, v17.4h }, [x15], x3 + st3 { v31.2s, v0.2s, v1.2s }, [sp], #24 +// CHECK: st3 { v0.16b, v1.16b, v2.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x40,0x81,0x4c] -// CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x45,0x82,0x4c] -// CHECK: st3 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: st3 { v31.4s, v0.4s, v1.4s }, [sp], #48 // CHECK: // encoding: [0xff,0x4b,0x9f,0x4c] -// CHECK: st3 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: st3 { v0.2d, v1.2d, v2.2d }, [x0], #48 // CHECK: // encoding: [0x00,0x4c,0x9f,0x4c] -// CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: st3 { v0.8b, v1.8b, v2.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x40,0x82,0x0c] -// CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x45,0x83,0x0c] -// CHECK: st3 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: st3 { v31.2s, v0.2s, v1.2s }, [sp], #24 // CHECK: // encoding: [0xff,0x4b,0x9f,0x0c] //------------------------------------------------------------------------------ // Store multiple 4-element structures from four consecutive registers // (post-index) //------------------------------------------------------------------------------ - st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 - st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 - st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 - st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 - st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 - st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 - st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 -// CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 + st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 + st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 + st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 + st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 + st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 + st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 +// CHECK: st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x00,0x81,0x4c] -// CHECK: st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x05,0x82,0x4c] -// CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 // CHECK: // encoding: [0xff,0x0b,0x9f,0x4c] -// CHECK: st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 // CHECK: // encoding: [0x00,0x0c,0x9f,0x4c] -// CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 // CHECK: // encoding: [0x00,0x00,0x83,0x0c] -// CHECK: st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 // CHECK: // encoding: [0xef,0x05,0x84,0x0c] -// CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 // CHECK: // encoding: [0xff,0x0b,0x9f,0x0c] diff --git a/test/MC/AArch64/neon-tbl.s b/test/MC/AArch64/neon-tbl.s index ff3e86b..bb39fa9 100644 --- a/test/MC/AArch64/neon-tbl.s +++ b/test/MC/AArch64/neon-tbl.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 @@ -6,51 +6,50 @@ // Instructions across vector registers //------------------------------------------------------------------------------ - tbl v0.8b, {v1.16b}, v2.8b - tbl v0.8b, {v1.16b, v2.16b}, v2.8b - tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b - tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b - tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b - -// CHECK: tbl v0.8b, {v1.16b}, v2.8b // encoding: [0x20,0x00,0x02,0x0e] -// CHECK: tbl v0.8b, {v1.16b, v2.16b}, v2.8b // encoding: [0x20,0x20,0x02,0x0e] -// CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // encoding: [0x20,0x40,0x02,0x0e] -// CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b // encoding: [0x20,0x60,0x02,0x0e] -// CHECK: tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b // encoding: [0xe0,0x63,0x02,0x0e] - - tbl v0.16b, {v1.16b}, v2.16b - tbl v0.16b, {v1.16b, v2.16b}, v2.16b - tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b - tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b - tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b - -// CHECK: tbl v0.16b, {v1.16b}, v2.16b // encoding: [0x20,0x00,0x02,0x4e] -// CHECK: tbl v0.16b, {v1.16b, v2.16b}, v2.16b // encoding: [0x20,0x20,0x02,0x4e] -// CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b // encoding: [0x20,0x40,0x02,0x4e] -// CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b // encoding: [0x20,0x60,0x02,0x4e] -// CHECK: tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b // encoding: [0xc0,0x63,0x02,0x4e] - - tbx v0.8b, {v1.16b}, v2.8b - tbx v0.8b, {v1.16b, v2.16b}, v2.8b - tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b - tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b - tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b - -// CHECK: tbx v0.8b, {v1.16b}, v2.8b // encoding: [0x20,0x10,0x02,0x0e] -// CHECK: tbx v0.8b, {v1.16b, v2.16b}, v2.8b // encoding: [0x20,0x30,0x02,0x0e] -// CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // encoding: [0x20,0x50,0x02,0x0e] -// CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b // encoding: [0x20,0x70,0x02,0x0e] -// CHECK: tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b // encoding: [0xe0,0x73,0x02,0x0e] - - tbx v0.16b, {v1.16b}, v2.16b - tbx v0.16b, {v1.16b, v2.16b}, v2.16b - tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b - tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b - tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b - -// CHECK: tbx v0.16b, {v1.16b}, v2.16b // encoding: [0x20,0x10,0x02,0x4e] -// CHECK: tbx v0.16b, {v1.16b, v2.16b}, v2.16b // encoding: [0x20,0x30,0x02,0x4e] -// CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b // encoding: [0x20,0x50,0x02,0x4e] -// CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b // encoding: [0x20,0x70,0x02,0x4e] -// CHECK: tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b // encoding: [0xc0,0x73,0x02,0x4e] - + tbl v0.8b, { v1.16b }, v2.8b + tbl v0.8b, { v1.16b, v2.16b }, v2.8b + tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b + tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b + tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b + +// CHECK: tbl v0.8b, { v1.16b }, v2.8b // encoding: [0x20,0x00,0x02,0x0e] +// CHECK: tbl v0.8b, { v1.16b, v2.16b }, v2.8b // encoding: [0x20,0x20,0x02,0x0e] +// CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b // encoding: [0x20,0x40,0x02,0x0e] +// CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b // encoding: [0x20,0x60,0x02,0x0e] +// CHECK: tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b // encoding: [0xe0,0x63,0x02,0x0e] + + tbl v0.16b, { v1.16b }, v2.16b + tbl v0.16b, { v1.16b, v2.16b }, v2.16b + tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b + tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b + tbl v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b + +// CHECK: tbl v0.16b, { v1.16b }, v2.16b // encoding: [0x20,0x00,0x02,0x4e] +// CHECK: tbl v0.16b, { v1.16b, v2.16b }, v2.16b // encoding: [0x20,0x20,0x02,0x4e] +// CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b // encoding: [0x20,0x40,0x02,0x4e] +// CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b // encoding: [0x20,0x60,0x02,0x4e] +// CHECK: tbl v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b // encoding: [0xc0,0x63,0x02,0x4e] + + tbx v0.8b, { v1.16b }, v2.8b + tbx v0.8b, { v1.16b, v2.16b }, v2.8b + tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b + tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b + tbx v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b + +// CHECK: tbx v0.8b, { v1.16b }, v2.8b // encoding: [0x20,0x10,0x02,0x0e] +// CHECK: tbx v0.8b, { v1.16b, v2.16b }, v2.8b // encoding: [0x20,0x30,0x02,0x0e] +// CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b // encoding: [0x20,0x50,0x02,0x0e] +// CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b // encoding: [0x20,0x70,0x02,0x0e] +// CHECK: tbx v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b // encoding: [0xe0,0x73,0x02,0x0e] + + tbx v0.16b, { v1.16b }, v2.16b + tbx v0.16b, { v1.16b, v2.16b }, v2.16b + tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b + tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b + tbx v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b + +// CHECK: tbx v0.16b, { v1.16b }, v2.16b // encoding: [0x20,0x10,0x02,0x4e] +// CHECK: tbx v0.16b, { v1.16b, v2.16b }, v2.16b // encoding: [0x20,0x30,0x02,0x4e] +// CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b // encoding: [0x20,0x50,0x02,0x4e] +// CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b // encoding: [0x20,0x70,0x02,0x4e] +// CHECK: tbx v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b // encoding: [0xc0,0x73,0x02,0x4e] diff --git a/test/MC/AArch64/noneon-diagnostics.s b/test/MC/AArch64/noneon-diagnostics.s index ea786c0..60a5fd2 100644 --- a/test/MC/AArch64/noneon-diagnostics.s +++ b/test/MC/AArch64/noneon-diagnostics.s @@ -4,25 +4,26 @@ fmla v3.4s, v12.4s, v17.4s fmla v1.2d, v30.2d, v20.2d fmla v9.2s, v9.2s, v0.2s -// CHECK-ERROR: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR: error: instruction requires: neon // CHECK-ERROR-NEXT: fmla v3.4s, v12.4s, v17.4s // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR-NEXT: error: instruction requires: neon // CHECK-ERROR-NEXT: fmla v1.2d, v30.2d, v20.2d // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR-NEXT: error: instruction requires: neon // CHECK-ERROR-NEXT: fmla v9.2s, v9.2s, v0.2s // CHECK-ERROR-NEXT: ^ fmls v3.4s, v12.4s, v17.4s fmls v1.2d, v30.2d, v20.2d fmls v9.2s, v9.2s, v0.2s -// CHECK-ERROR: error: instruction requires a CPU feature not currently enabled + +// CHECK-ERROR: error: instruction requires: neon // CHECK-ERROR-NEXT: fmls v3.4s, v12.4s, v17.4s // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR-NEXT: error: instruction requires: neon // CHECK-ERROR-NEXT: fmls v1.2d, v30.2d, v20.2d // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR-NEXT: error: instruction requires: neon // CHECK-ERROR-NEXT: fmls v9.2s, v9.2s, v0.2s // CHECK-ERROR-NEXT: ^ diff --git a/test/MC/AArch64/optional-hash.s b/test/MC/AArch64/optional-hash.s index 54b6fb3..3922b5b 100644 --- a/test/MC/AArch64/optional-hash.s +++ b/test/MC/AArch64/optional-hash.s @@ -1,6 +1,6 @@ // PR18929 // RUN: llvm-mc < %s -triple=aarch64-linux-gnueabi -mattr=+fp-armv8,+neon -filetype=obj -o - \ -// RUN: | llvm-objdump --disassemble -arch=aarch64 -mattr=+fp-armv8,+neon - | FileCheck %s +// RUN: | llvm-objdump --disassemble -arch=arm64 -mattr=+fp-armv8,+neon - | FileCheck %s .text // CHECK: cmp w0, #123 diff --git a/test/MC/AArch64/tls-relocs.s b/test/MC/AArch64/tls-relocs.s index f99cb41..ebf0216 100644 --- a/test/MC/AArch64/tls-relocs.s +++ b/test/MC/AArch64/tls-relocs.s @@ -7,14 +7,15 @@ movn x2, #:dtprel_g2:var movz x3, #:dtprel_g2:var movn x4, #:dtprel_g2:var -// CHECK: movz x1, #:dtprel_g2:var // encoding: [0x01'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 -// CHECK: movn x2, #:dtprel_g2:var // encoding: [0x02'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 -// CHECK: movz x3, #:dtprel_g2:var // encoding: [0x03'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 -// CHECK: movn x4, #:dtprel_g2:var // encoding: [0x04'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 + +// CHECK: movz x1, #:dtprel_g2:var // encoding: [0bAAA00001,A,0b110AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw +// CHECK: movn x2, #:dtprel_g2:var // encoding: [0bAAA00010,A,0b110AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw +// CHECK: movz x3, #:dtprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw +// CHECK: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw // CHECK-ELF: Relocations [ // CHECK-ELF-NEXT: Section (2) .rela.text { @@ -28,14 +29,15 @@ movn x6, #:dtprel_g1:var movz w7, #:dtprel_g1:var movn w8, #:dtprel_g1:var -// CHECK: movz x5, #:dtprel_g1:var // encoding: [0x05'A',A,0xa0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 -// CHECK: movn x6, #:dtprel_g1:var // encoding: [0x06'A',A,0xa0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 -// CHECK: movz w7, #:dtprel_g1:var // encoding: [0x07'A',A,0xa0'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 -// CHECK: movn w8, #:dtprel_g1:var // encoding: [0x08'A',A,0xa0'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 + +// CHECK: movz x5, #:dtprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movz w7, #:dtprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movn w8, #:dtprel_g1:var // encoding: [0bAAA01000,A,0b101AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x10 R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] // CHECK-ELF-NEXT: 0x14 R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] @@ -45,10 +47,11 @@ movk x9, #:dtprel_g1_nc:var movk w10, #:dtprel_g1_nc:var -// CHECK: movk x9, #:dtprel_g1_nc:var // encoding: [0x09'A',A,0xa0'A',0xf2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_a64_movw_dtprel_g1_nc -// CHECK: movk w10, #:dtprel_g1_nc:var // encoding: [0x0a'A',A,0xa0'A',0x72'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_a64_movw_dtprel_g1_nc + +// CHECK: movk x9, #:dtprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2] +// CHECK: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_aarch64_movw +// CHECK: movk w10, #:dtprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72] +// CHECK: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x20 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]] // CHECK-ELF-NEXT: 0x24 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]] @@ -58,13 +61,15 @@ movn x12, #:dtprel_g0:var movz w13, #:dtprel_g0:var movn w14, #:dtprel_g0:var -// CHECK: movz x11, #:dtprel_g0:var // encoding: [0x0b'A',A,0x80'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0 -// CHECK: movn x12, #:dtprel_g0:var // encoding: [0x0c'A',A,0x80'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0 -// CHECK: movz w13, #:dtprel_g0:var // encoding: [0x0d'A',A,0x80'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0 -// CHECK: movn w14, #:dtprel_g0:var // encoding: [0x0e'A',A,0x80'A',0x12'A'] + +// CHECK: movz x11, #:dtprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movn x12, #:dtprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movz w13, #:dtprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movn w14, #:dtprel_g0:var // encoding: [0bAAA01110,A,0b100AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x28 R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] // CHECK-ELF-NEXT: 0x2C R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] @@ -74,10 +79,11 @@ movk x15, #:dtprel_g0_nc:var movk w16, #:dtprel_g0_nc:var -// CHECK: movk x15, #:dtprel_g0_nc:var // encoding: [0x0f'A',A,0x80'A',0xf2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_a64_movw_dtprel_g0_nc -// CHECK: movk w16, #:dtprel_g0_nc:var // encoding: [0x10'A',A,0x80'A',0x72'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_a64_movw_dtprel_g0_nc + +// CHECK: movk x15, #:dtprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2] +// CHECK: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw +// CHECK: movk w16, #:dtprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72] +// CHECK: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x38 R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]] // CHECK-ELF-NEXT: 0x3C R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]] @@ -85,10 +91,11 @@ add x17, x18, #:dtprel_hi12:var, lsl #12 add w19, w20, #:dtprel_hi12:var, lsl #12 -// CHECK: add x17, x18, #:dtprel_hi12:var, lsl #12 // encoding: [0x51'A',0x02'A',0x40'A',0x91'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_a64_add_dtprel_hi12 -// CHECK: add w19, w20, #:dtprel_hi12:var, lsl #12 // encoding: [0x93'A',0x02'A',0x40'A',0x11'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_a64_add_dtprel_hi12 + +// CHECK: add x17, x18, :dtprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_aarch64_add_imm12 +// CHECK: add w19, w20, :dtprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b00AAAAAA,0x11] +// CHECK: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: 0x40 R_AARCH64_TLSLD_ADD_DTPREL_HI12 [[VARSYM]] // CHECK-ELF-NEXT: 0x44 R_AARCH64_TLSLD_ADD_DTPREL_HI12 [[VARSYM]] @@ -96,10 +103,11 @@ add x21, x22, #:dtprel_lo12:var add w23, w24, #:dtprel_lo12:var -// CHECK: add x21, x22, #:dtprel_lo12:var // encoding: [0xd5'A',0x02'A',A,0x91'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_add_dtprel_lo12 -// CHECK: add w23, w24, #:dtprel_lo12:var // encoding: [0x17'A',0x03'A',A,0x11'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_add_dtprel_lo12 + +// CHECK: add x21, x22, :dtprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_add_imm12 +// CHECK: add w23, w24, :dtprel_lo12:var // encoding: [0x17,0bAAAAAA11,0b00AAAAAA,0x11] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: 0x48 R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0x4C R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]] @@ -107,10 +115,11 @@ add x25, x26, #:dtprel_lo12_nc:var add w27, w28, #:dtprel_lo12_nc:var -// CHECK: add x25, x26, #:dtprel_lo12_nc:var // encoding: [0x59'A',0x03'A',A,0x91'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_add_dtprel_lo12_nc -// CHECK: add w27, w28, #:dtprel_lo12_nc:var // encoding: [0x9b'A',0x03'A',A,0x11'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_add_dtprel_lo12_nc + +// CHECK: add x25, x26, :dtprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_add_imm12 +// CHECK: add w27, w28, :dtprel_lo12_nc:var // encoding: [0x9b,0bAAAAAA11,0b00AAAAAA,0x11] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: 0x50 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]] // CHECK-ELF-NEXT: 0x54 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]] @@ -118,10 +127,11 @@ ldrb w29, [x30, #:dtprel_lo12:var] ldrsb x29, [x28, #:dtprel_lo12_nc:var] -// CHECK: ldrb w29, [x30, #:dtprel_lo12:var] // encoding: [0xdd'A',0x03'A',0x40'A',0x39'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst8_dtprel_lo12 -// CHECK: ldrsb x29, [x28, #:dtprel_lo12_nc:var] // encoding: [0x9d'A',0x03'A',0x80'A',0x39'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst8_dtprel_lo12_nc + +// CHECK: ldrb w29, [x30, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1 +// CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1 // CHECK-ELF-NEXT: 0x58 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0x5C R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC [[VARSYM]] @@ -129,10 +139,11 @@ strh w27, [x26, #:dtprel_lo12:var] ldrsh x25, [x24, #:dtprel_lo12_nc:var] -// CHECK: strh w27, [x26, #:dtprel_lo12:var] // encoding: [0x5b'A',0x03'A',A,0x79'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst16_dtprel_lo12 -// CHECK: ldrsh x25, [x24, #:dtprel_lo12_nc:var] // encoding: [0x19'A',0x03'A',0x80'A',0x79'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst16_dtprel_lo12_n + +// CHECK: strh w27, [x26, :dtprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2 +// CHECK: ldrsh x25, [x24, :dtprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2 // CHECK-ELF-NEXT: 0x60 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0x64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC [[VARSYM]] @@ -140,10 +151,11 @@ ldr w23, [x22, #:dtprel_lo12:var] ldrsw x21, [x20, #:dtprel_lo12_nc:var] -// CHECK: ldr w23, [x22, #:dtprel_lo12:var] // encoding: [0xd7'A',0x02'A',0x40'A',0xb9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst32_dtprel_lo12 -// CHECK: ldrsw x21, [x20, #:dtprel_lo12_nc:var] // encoding: [0x95'A',0x02'A',0x80'A',0xb9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst32_dtprel_lo12_n + +// CHECK: ldr w23, [x22, :dtprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4 +// CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4 // CHECK-ELF-NEXT: 0x68 R_AARCH64_TLSLD_LDST32_DTPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0x6C R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC [[VARSYM]] @@ -151,11 +163,11 @@ ldr x19, [x18, #:dtprel_lo12:var] str x17, [x16, #:dtprel_lo12_nc:var] -// CHECK: ldr x19, [x18, #:dtprel_lo12:var] // encoding: [0x53'A',0x02'A',0x40'A',0xf9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst64_dtprel_lo12 -// CHECK: str x17, [x16, #:dtprel_lo12_nc:var] // encoding: [0x11'A',0x02'A',A,0xf9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst64_dtprel_lo12_nc +// CHECK: ldr x19, [x18, :dtprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: str x17, [x16, :dtprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8 // CHECK-ELF-NEXT: 0x70 R_AARCH64_TLSLD_LDST64_DTPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0x74 R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC [[VARSYM]] @@ -164,10 +176,11 @@ // TLS initial-exec forms movz x15, #:gottprel_g1:var movz w14, #:gottprel_g1:var -// CHECK: movz x15, #:gottprel_g1:var // encoding: [0x0f'A',A,0xa0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_a64_movw_gottprel_g1 -// CHECK: movz w14, #:gottprel_g1:var // encoding: [0x0e'A',A,0xa0'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_a64_movw_gottprel_g1 + +// CHECK: movz x15, #:gottprel_g1:var // encoding: [0bAAA01111,A,0b101AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movz w14, #:gottprel_g1:var // encoding: [0bAAA01110,A,0b101AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x78 R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM]] // CHECK-ELF-NEXT: 0x7C R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM]] @@ -175,10 +188,11 @@ movk x13, #:gottprel_g0_nc:var movk w12, #:gottprel_g0_nc:var -// CHECK: movk x13, #:gottprel_g0_nc:var // encoding: [0x0d'A',A,0x80'A',0xf2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_a64_movw_gottprel_g0_nc -// CHECK: movk w12, #:gottprel_g0_nc:var // encoding: [0x0c'A',A,0x80'A',0x72'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_a64_movw_gottprel_g0_nc + +// CHECK: movk x13, #:gottprel_g0_nc:var // encoding: [0bAAA01101,A,0b100AAAAA,0xf2] +// CHECK: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_aarch64_movw +// CHECK: movk w12, #:gottprel_g0_nc:var // encoding: [0bAAA01100,A,0b100AAAAA,0x72] +// CHECK: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x80 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]] // CHECK-ELF-NEXT: 0x84 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]] @@ -187,12 +201,13 @@ adrp x11, :gottprel:var ldr x10, [x0, #:gottprel_lo12:var] ldr x9, :gottprel:var + // CHECK: adrp x11, :gottprel:var // encoding: [0x0b'A',A,A,0x90'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_a64_adr_gottprel_page -// CHECK: ldr x10, [x0, #:gottprel_lo12:var] // encoding: [0x0a'A',A,0x40'A',0xf9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_a64_ld64_gottprel_lo12_nc -// CHECK: ldr x9, :gottprel:var // encoding: [0x09'A',A,A,0x58'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_a64_ld_gottprel_prel19 +// CHECK: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_pcrel_adrp_imm21 +// CHECK: ldr x10, [x0, :gottprel_lo12:var] // encoding: [0x0a,0bAAAAAA00,0b01AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: ldr x9, :gottprel:var // encoding: [0bAAA01001,A,A,0x58] +// CHECK: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_ldr_pcrel_imm19 // CHECK-ELF-NEXT: 0x88 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 [[VARSYM]] // CHECK-ELF-NEXT: 0x8C R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC [[VARSYM]] @@ -202,10 +217,11 @@ // TLS local-exec forms movz x3, #:tprel_g2:var movn x4, #:tprel_g2:var -// CHECK: movz x3, #:tprel_g2:var // encoding: [0x03'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_a64_movw_tprel_g2 -// CHECK: movn x4, #:tprel_g2:var // encoding: [0x04'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_a64_movw_tprel_g2 + +// CHECK: movz x3, #:tprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_aarch64_movw +// CHECK: movn x4, #:tprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x94 R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]] // CHECK-ELF-NEXT: 0x98 R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]] @@ -215,14 +231,15 @@ movn x6, #:tprel_g1:var movz w7, #:tprel_g1:var movn w8, #:tprel_g1:var -// CHECK: movz x5, #:tprel_g1:var // encoding: [0x05'A',A,0xa0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 -// CHECK: movn x6, #:tprel_g1:var // encoding: [0x06'A',A,0xa0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 -// CHECK: movz w7, #:tprel_g1:var // encoding: [0x07'A',A,0xa0'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 -// CHECK: movn w8, #:tprel_g1:var // encoding: [0x08'A',A,0xa0'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 + +// CHECK: movz x5, #:tprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movn x6, #:tprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movz w7, #:tprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movn w8, #:tprel_g1:var // encoding: [0bAAA01000,A,0b101AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x9C R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]] // CHECK-ELF-NEXT: 0xA0 R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]] @@ -232,10 +249,11 @@ movk x9, #:tprel_g1_nc:var movk w10, #:tprel_g1_nc:var -// CHECK: movk x9, #:tprel_g1_nc:var // encoding: [0x09'A',A,0xa0'A',0xf2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_a64_movw_tprel_g1_nc -// CHECK: movk w10, #:tprel_g1_nc:var // encoding: [0x0a'A',A,0xa0'A',0x72'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_a64_movw_tprel_g1_nc + +// CHECK: movk x9, #:tprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2] +// CHECK: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_aarch64_movw +// CHECK: movk w10, #:tprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72] +// CHECK: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0xAC R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]] // CHECK-ELF-NEXT: 0xB0 R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]] @@ -245,14 +263,15 @@ movn x12, #:tprel_g0:var movz w13, #:tprel_g0:var movn w14, #:tprel_g0:var -// CHECK: movz x11, #:tprel_g0:var // encoding: [0x0b'A',A,0x80'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 -// CHECK: movn x12, #:tprel_g0:var // encoding: [0x0c'A',A,0x80'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 -// CHECK: movz w13, #:tprel_g0:var // encoding: [0x0d'A',A,0x80'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 -// CHECK: movn w14, #:tprel_g0:var // encoding: [0x0e'A',A,0x80'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 + +// CHECK: movz x11, #:tprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movn x12, #:tprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movz w13, #:tprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movn w14, #:tprel_g0:var // encoding: [0bAAA01110,A,0b100AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0xB4 R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]] // CHECK-ELF-NEXT: 0xB8 R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]] @@ -262,10 +281,11 @@ movk x15, #:tprel_g0_nc:var movk w16, #:tprel_g0_nc:var -// CHECK: movk x15, #:tprel_g0_nc:var // encoding: [0x0f'A',A,0x80'A',0xf2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_a64_movw_tprel_g0_nc -// CHECK: movk w16, #:tprel_g0_nc:var // encoding: [0x10'A',A,0x80'A',0x72'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_a64_movw_tprel_g0_nc + +// CHECK: movk x15, #:tprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2] +// CHECK: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw +// CHECK: movk w16, #:tprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72] +// CHECK: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0xC4 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]] // CHECK-ELF-NEXT: 0xC8 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]] @@ -273,10 +293,11 @@ add x17, x18, #:tprel_hi12:var, lsl #12 add w19, w20, #:tprel_hi12:var, lsl #12 -// CHECK: add x17, x18, #:tprel_hi12:var, lsl #12 // encoding: [0x51'A',0x02'A',0x40'A',0x91'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_a64_add_tprel_hi12 -// CHECK: add w19, w20, #:tprel_hi12:var, lsl #12 // encoding: [0x93'A',0x02'A',0x40'A',0x11'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_a64_add_tprel_hi12 + +// CHECK: add x17, x18, :tprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_aarch64_add_imm12 +// CHECK: add w19, w20, :tprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b00AAAAAA,0x11] +// CHECK: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: 0xCC R_AARCH64_TLSLE_ADD_TPREL_HI12 [[VARSYM]] // CHECK-ELF-NEXT: 0xD0 R_AARCH64_TLSLE_ADD_TPREL_HI12 [[VARSYM]] @@ -284,10 +305,11 @@ add x21, x22, #:tprel_lo12:var add w23, w24, #:tprel_lo12:var -// CHECK: add x21, x22, #:tprel_lo12:var // encoding: [0xd5'A',0x02'A',A,0x91'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_add_tprel_lo12 -// CHECK: add w23, w24, #:tprel_lo12:var // encoding: [0x17'A',0x03'A',A,0x11'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_add_tprel_lo12 + +// CHECK: add x21, x22, :tprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_add_imm12 +// CHECK: add w23, w24, :tprel_lo12:var // encoding: [0x17,0bAAAAAA11,0b00AAAAAA,0x11] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: 0xD4 R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0xD8 R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]] @@ -295,10 +317,11 @@ add x25, x26, #:tprel_lo12_nc:var add w27, w28, #:tprel_lo12_nc:var -// CHECK: add x25, x26, #:tprel_lo12_nc:var // encoding: [0x59'A',0x03'A',A,0x91'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_add_tprel_lo12_nc -// CHECK: add w27, w28, #:tprel_lo12_nc:var // encoding: [0x9b'A',0x03'A',A,0x11'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_add_tprel_lo12_nc + +// CHECK: add x25, x26, :tprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_add_imm12 +// CHECK: add w27, w28, :tprel_lo12_nc:var // encoding: [0x9b,0bAAAAAA11,0b00AAAAAA,0x11] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: 0xDC R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]] // CHECK-ELF-NEXT: 0xE0 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]] @@ -306,10 +329,11 @@ ldrb w29, [x30, #:tprel_lo12:var] ldrsb x29, [x28, #:tprel_lo12_nc:var] -// CHECK: ldrb w29, [x30, #:tprel_lo12:var] // encoding: [0xdd'A',0x03'A',0x40'A',0x39'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst8_tprel_lo12 -// CHECK: ldrsb x29, [x28, #:tprel_lo12_nc:var] // encoding: [0x9d'A',0x03'A',0x80'A',0x39'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst8_tprel_lo12_nc + +// CHECK: ldrb w29, [x30, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1 +// CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1 // CHECK-ELF-NEXT: 0xE4 R_AARCH64_TLSLE_LDST8_TPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0xE8 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC [[VARSYM]] @@ -317,10 +341,11 @@ strh w27, [x26, #:tprel_lo12:var] ldrsh x25, [x24, #:tprel_lo12_nc:var] -// CHECK: strh w27, [x26, #:tprel_lo12:var] // encoding: [0x5b'A',0x03'A',A,0x79'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst16_tprel_lo12 -// CHECK: ldrsh x25, [x24, #:tprel_lo12_nc:var] // encoding: [0x19'A',0x03'A',0x80'A',0x79'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst16_tprel_lo12_n + +// CHECK: strh w27, [x26, :tprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2 +// CHECK: ldrsh x25, [x24, :tprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2 // CHECK-ELF-NEXT: 0xEC R_AARCH64_TLSLE_LDST16_TPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0xF0 R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC [[VARSYM]] @@ -328,20 +353,22 @@ ldr w23, [x22, #:tprel_lo12:var] ldrsw x21, [x20, #:tprel_lo12_nc:var] -// CHECK: ldr w23, [x22, #:tprel_lo12:var] // encoding: [0xd7'A',0x02'A',0x40'A',0xb9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst32_tprel_lo12 -// CHECK: ldrsw x21, [x20, #:tprel_lo12_nc:var] // encoding: [0x95'A',0x02'A',0x80'A',0xb9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst32_tprel_lo12_n + +// CHECK: ldr w23, [x22, :tprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4 +// CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4 // CHECK-ELF-NEXT: 0xF4 R_AARCH64_TLSLE_LDST32_TPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0xF8 R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC [[VARSYM]] ldr x19, [x18, #:tprel_lo12:var] str x17, [x16, #:tprel_lo12_nc:var] -// CHECK: ldr x19, [x18, #:tprel_lo12:var] // encoding: [0x53'A',0x02'A',0x40'A',0xf9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst64_tprel_lo12 -// CHECK: str x17, [x16, #:tprel_lo12_nc:var] // encoding: [0x11'A',0x02'A',A,0xf9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst64_tprel_lo12_nc + +// CHECK: ldr x19, [x18, :tprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: str x17, [x16, :tprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8 // CHECK-ELF-NEXT: 0xFC R_AARCH64_TLSLE_LDST64_TPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0x100 R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC [[VARSYM]] @@ -353,16 +380,16 @@ .tlsdesccall var blr x3 + // CHECK: adrp x8, :tlsdesc:var // encoding: [0x08'A',A,A,0x90'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_a64_tlsdesc_adr_page -// CHECK: ldr x7, [x6, #:tlsdesc_lo12:var] // encoding: [0xc7'A',A,0x40'A',0xf9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_a64_tlsdesc_ld64_lo12_nc -// CHECK: add x5, x4, #:tlsdesc_lo12:var // encoding: [0x85'A',A,A,0x91'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_a64_tlsdesc_add_lo12_nc +// CHECK: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_aarch64_pcrel_adrp_imm21 +// CHECK: ldr x7, [x6, :tlsdesc_lo12:var] // encoding: [0xc7,0bAAAAAA00,0b01AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: add x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_add_imm12 // CHECK: .tlsdesccall var // encoding: [] -// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_a64_tlsdesc_call -// CHECK: blr x3 // encoding: [0x60,0x00,0x3f,0xd6] - +// CHECK: // fixup A - offset: 0, value: var, kind: fixup_aarch64_tlsdesc_call +// CHECK: blr x3 // encoding: [0x60,0x00,0x3f,0xd6] // CHECK-ELF-NEXT: 0x104 R_AARCH64_TLSDESC_ADR_PAGE [[VARSYM]] // CHECK-ELF-NEXT: 0x108 R_AARCH64_TLSDESC_LD64_LO12_NC [[VARSYM]] @@ -374,7 +401,7 @@ // CHECK-ELF: Symbols [ // CHECK-ELF: Symbol { -// CHECK-ELF: Name: var (6) +// CHECK-ELF: Name: var // CHECK-ELF-NEXT: Value: // CHECK-ELF-NEXT: Size: // CHECK-ELF-NEXT: Binding: Global diff --git a/test/MC/AArch64/trace-regs.s b/test/MC/AArch64/trace-regs.s index f9ab4c9..92f16cd 100644 --- a/test/MC/AArch64/trace-regs.s +++ b/test/MC/AArch64/trace-regs.s @@ -1,4 +1,5 @@ // RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s + mrs x8, trcstatr mrs x9, trcidr8 mrs x11, trcidr9 @@ -207,214 +208,214 @@ mrs x22, trcitctrl mrs x23, trcclaimset mrs x14, trcclaimclr -// CHECK: mrs x8, trcstatr // encoding: [0x08,0x03,0x31,0xd5] -// CHECK: mrs x9, trcidr8 // encoding: [0xc9,0x00,0x31,0xd5] -// CHECK: mrs x11, trcidr9 // encoding: [0xcb,0x01,0x31,0xd5] -// CHECK: mrs x25, trcidr10 // encoding: [0xd9,0x02,0x31,0xd5] -// CHECK: mrs x7, trcidr11 // encoding: [0xc7,0x03,0x31,0xd5] -// CHECK: mrs x7, trcidr12 // encoding: [0xc7,0x04,0x31,0xd5] -// CHECK: mrs x6, trcidr13 // encoding: [0xc6,0x05,0x31,0xd5] -// CHECK: mrs x27, trcidr0 // encoding: [0xfb,0x08,0x31,0xd5] -// CHECK: mrs x29, trcidr1 // encoding: [0xfd,0x09,0x31,0xd5] -// CHECK: mrs x4, trcidr2 // encoding: [0xe4,0x0a,0x31,0xd5] -// CHECK: mrs x8, trcidr3 // encoding: [0xe8,0x0b,0x31,0xd5] -// CHECK: mrs x15, trcidr4 // encoding: [0xef,0x0c,0x31,0xd5] -// CHECK: mrs x20, trcidr5 // encoding: [0xf4,0x0d,0x31,0xd5] -// CHECK: mrs x6, trcidr6 // encoding: [0xe6,0x0e,0x31,0xd5] -// CHECK: mrs x6, trcidr7 // encoding: [0xe6,0x0f,0x31,0xd5] -// CHECK: mrs x24, trcoslsr // encoding: [0x98,0x11,0x31,0xd5] -// CHECK: mrs x18, trcpdsr // encoding: [0x92,0x15,0x31,0xd5] -// CHECK: mrs x28, trcdevaff0 // encoding: [0xdc,0x7a,0x31,0xd5] -// CHECK: mrs x5, trcdevaff1 // encoding: [0xc5,0x7b,0x31,0xd5] -// CHECK: mrs x5, trclsr // encoding: [0xc5,0x7d,0x31,0xd5] -// CHECK: mrs x11, trcauthstatus // encoding: [0xcb,0x7e,0x31,0xd5] -// CHECK: mrs x13, trcdevarch // encoding: [0xcd,0x7f,0x31,0xd5] -// CHECK: mrs x18, trcdevid // encoding: [0xf2,0x72,0x31,0xd5] -// CHECK: mrs x22, trcdevtype // encoding: [0xf6,0x73,0x31,0xd5] -// CHECK: mrs x14, trcpidr4 // encoding: [0xee,0x74,0x31,0xd5] -// CHECK: mrs x5, trcpidr5 // encoding: [0xe5,0x75,0x31,0xd5] -// CHECK: mrs x5, trcpidr6 // encoding: [0xe5,0x76,0x31,0xd5] -// CHECK: mrs x9, trcpidr7 // encoding: [0xe9,0x77,0x31,0xd5] -// CHECK: mrs x15, trcpidr0 // encoding: [0xef,0x78,0x31,0xd5] -// CHECK: mrs x6, trcpidr1 // encoding: [0xe6,0x79,0x31,0xd5] -// CHECK: mrs x11, trcpidr2 // encoding: [0xeb,0x7a,0x31,0xd5] -// CHECK: mrs x20, trcpidr3 // encoding: [0xf4,0x7b,0x31,0xd5] -// CHECK: mrs x17, trccidr0 // encoding: [0xf1,0x7c,0x31,0xd5] -// CHECK: mrs x2, trccidr1 // encoding: [0xe2,0x7d,0x31,0xd5] -// CHECK: mrs x20, trccidr2 // encoding: [0xf4,0x7e,0x31,0xd5] -// CHECK: mrs x4, trccidr3 // encoding: [0xe4,0x7f,0x31,0xd5] -// CHECK: mrs x11, trcprgctlr // encoding: [0x0b,0x01,0x31,0xd5] -// CHECK: mrs x23, trcprocselr // encoding: [0x17,0x02,0x31,0xd5] -// CHECK: mrs x13, trcconfigr // encoding: [0x0d,0x04,0x31,0xd5] -// CHECK: mrs x23, trcauxctlr // encoding: [0x17,0x06,0x31,0xd5] -// CHECK: mrs x9, trceventctl0r // encoding: [0x09,0x08,0x31,0xd5] -// CHECK: mrs x16, trceventctl1r // encoding: [0x10,0x09,0x31,0xd5] -// CHECK: mrs x4, trcstallctlr // encoding: [0x04,0x0b,0x31,0xd5] -// CHECK: mrs x14, trctsctlr // encoding: [0x0e,0x0c,0x31,0xd5] -// CHECK: mrs x24, trcsyncpr // encoding: [0x18,0x0d,0x31,0xd5] -// CHECK: mrs x28, trcccctlr // encoding: [0x1c,0x0e,0x31,0xd5] -// CHECK: mrs x15, trcbbctlr // encoding: [0x0f,0x0f,0x31,0xd5] -// CHECK: mrs x1, trctraceidr // encoding: [0x21,0x00,0x31,0xd5] -// CHECK: mrs x20, trcqctlr // encoding: [0x34,0x01,0x31,0xd5] -// CHECK: mrs x2, trcvictlr // encoding: [0x42,0x00,0x31,0xd5] -// CHECK: mrs x12, trcviiectlr // encoding: [0x4c,0x01,0x31,0xd5] -// CHECK: mrs x16, trcvissctlr // encoding: [0x50,0x02,0x31,0xd5] -// CHECK: mrs x8, trcvipcssctlr // encoding: [0x48,0x03,0x31,0xd5] -// CHECK: mrs x27, trcvdctlr // encoding: [0x5b,0x08,0x31,0xd5] -// CHECK: mrs x9, trcvdsacctlr // encoding: [0x49,0x09,0x31,0xd5] -// CHECK: mrs x0, trcvdarcctlr // encoding: [0x40,0x0a,0x31,0xd5] -// CHECK: mrs x13, trcseqevr0 // encoding: [0x8d,0x00,0x31,0xd5] -// CHECK: mrs x11, trcseqevr1 // encoding: [0x8b,0x01,0x31,0xd5] -// CHECK: mrs x26, trcseqevr2 // encoding: [0x9a,0x02,0x31,0xd5] -// CHECK: mrs x14, trcseqrstevr // encoding: [0x8e,0x06,0x31,0xd5] -// CHECK: mrs x4, trcseqstr // encoding: [0x84,0x07,0x31,0xd5] -// CHECK: mrs x17, trcextinselr // encoding: [0x91,0x08,0x31,0xd5] -// CHECK: mrs x21, trccntrldvr0 // encoding: [0xb5,0x00,0x31,0xd5] -// CHECK: mrs x10, trccntrldvr1 // encoding: [0xaa,0x01,0x31,0xd5] -// CHECK: mrs x20, trccntrldvr2 // encoding: [0xb4,0x02,0x31,0xd5] -// CHECK: mrs x5, trccntrldvr3 // encoding: [0xa5,0x03,0x31,0xd5] -// CHECK: mrs x17, trccntctlr0 // encoding: [0xb1,0x04,0x31,0xd5] -// CHECK: mrs x1, trccntctlr1 // encoding: [0xa1,0x05,0x31,0xd5] -// CHECK: mrs x17, trccntctlr2 // encoding: [0xb1,0x06,0x31,0xd5] -// CHECK: mrs x6, trccntctlr3 // encoding: [0xa6,0x07,0x31,0xd5] -// CHECK: mrs x28, trccntvr0 // encoding: [0xbc,0x08,0x31,0xd5] -// CHECK: mrs x23, trccntvr1 // encoding: [0xb7,0x09,0x31,0xd5] -// CHECK: mrs x9, trccntvr2 // encoding: [0xa9,0x0a,0x31,0xd5] -// CHECK: mrs x6, trccntvr3 // encoding: [0xa6,0x0b,0x31,0xd5] -// CHECK: mrs x24, trcimspec0 // encoding: [0xf8,0x00,0x31,0xd5] -// CHECK: mrs x24, trcimspec1 // encoding: [0xf8,0x01,0x31,0xd5] -// CHECK: mrs x15, trcimspec2 // encoding: [0xef,0x02,0x31,0xd5] -// CHECK: mrs x10, trcimspec3 // encoding: [0xea,0x03,0x31,0xd5] -// CHECK: mrs x29, trcimspec4 // encoding: [0xfd,0x04,0x31,0xd5] -// CHECK: mrs x18, trcimspec5 // encoding: [0xf2,0x05,0x31,0xd5] -// CHECK: mrs x29, trcimspec6 // encoding: [0xfd,0x06,0x31,0xd5] -// CHECK: mrs x2, trcimspec7 // encoding: [0xe2,0x07,0x31,0xd5] -// CHECK: mrs x8, trcrsctlr2 // encoding: [0x08,0x12,0x31,0xd5] -// CHECK: mrs x0, trcrsctlr3 // encoding: [0x00,0x13,0x31,0xd5] -// CHECK: mrs x12, trcrsctlr4 // encoding: [0x0c,0x14,0x31,0xd5] -// CHECK: mrs x26, trcrsctlr5 // encoding: [0x1a,0x15,0x31,0xd5] -// CHECK: mrs x29, trcrsctlr6 // encoding: [0x1d,0x16,0x31,0xd5] -// CHECK: mrs x17, trcrsctlr7 // encoding: [0x11,0x17,0x31,0xd5] -// CHECK: mrs x0, trcrsctlr8 // encoding: [0x00,0x18,0x31,0xd5] -// CHECK: mrs x1, trcrsctlr9 // encoding: [0x01,0x19,0x31,0xd5] -// CHECK: mrs x17, trcrsctlr10 // encoding: [0x11,0x1a,0x31,0xd5] -// CHECK: mrs x21, trcrsctlr11 // encoding: [0x15,0x1b,0x31,0xd5] -// CHECK: mrs x1, trcrsctlr12 // encoding: [0x01,0x1c,0x31,0xd5] -// CHECK: mrs x8, trcrsctlr13 // encoding: [0x08,0x1d,0x31,0xd5] -// CHECK: mrs x24, trcrsctlr14 // encoding: [0x18,0x1e,0x31,0xd5] -// CHECK: mrs x0, trcrsctlr15 // encoding: [0x00,0x1f,0x31,0xd5] -// CHECK: mrs x2, trcrsctlr16 // encoding: [0x22,0x10,0x31,0xd5] -// CHECK: mrs x29, trcrsctlr17 // encoding: [0x3d,0x11,0x31,0xd5] -// CHECK: mrs x22, trcrsctlr18 // encoding: [0x36,0x12,0x31,0xd5] -// CHECK: mrs x6, trcrsctlr19 // encoding: [0x26,0x13,0x31,0xd5] -// CHECK: mrs x26, trcrsctlr20 // encoding: [0x3a,0x14,0x31,0xd5] -// CHECK: mrs x26, trcrsctlr21 // encoding: [0x3a,0x15,0x31,0xd5] -// CHECK: mrs x4, trcrsctlr22 // encoding: [0x24,0x16,0x31,0xd5] -// CHECK: mrs x12, trcrsctlr23 // encoding: [0x2c,0x17,0x31,0xd5] -// CHECK: mrs x1, trcrsctlr24 // encoding: [0x21,0x18,0x31,0xd5] -// CHECK: mrs x0, trcrsctlr25 // encoding: [0x20,0x19,0x31,0xd5] -// CHECK: mrs x17, trcrsctlr26 // encoding: [0x31,0x1a,0x31,0xd5] -// CHECK: mrs x8, trcrsctlr27 // encoding: [0x28,0x1b,0x31,0xd5] -// CHECK: mrs x10, trcrsctlr28 // encoding: [0x2a,0x1c,0x31,0xd5] -// CHECK: mrs x25, trcrsctlr29 // encoding: [0x39,0x1d,0x31,0xd5] -// CHECK: mrs x12, trcrsctlr30 // encoding: [0x2c,0x1e,0x31,0xd5] -// CHECK: mrs x11, trcrsctlr31 // encoding: [0x2b,0x1f,0x31,0xd5] -// CHECK: mrs x18, trcssccr0 // encoding: [0x52,0x10,0x31,0xd5] -// CHECK: mrs x12, trcssccr1 // encoding: [0x4c,0x11,0x31,0xd5] -// CHECK: mrs x3, trcssccr2 // encoding: [0x43,0x12,0x31,0xd5] -// CHECK: mrs x2, trcssccr3 // encoding: [0x42,0x13,0x31,0xd5] -// CHECK: mrs x21, trcssccr4 // encoding: [0x55,0x14,0x31,0xd5] -// CHECK: mrs x10, trcssccr5 // encoding: [0x4a,0x15,0x31,0xd5] -// CHECK: mrs x22, trcssccr6 // encoding: [0x56,0x16,0x31,0xd5] -// CHECK: mrs x23, trcssccr7 // encoding: [0x57,0x17,0x31,0xd5] -// CHECK: mrs x23, trcsscsr0 // encoding: [0x57,0x18,0x31,0xd5] -// CHECK: mrs x19, trcsscsr1 // encoding: [0x53,0x19,0x31,0xd5] -// CHECK: mrs x25, trcsscsr2 // encoding: [0x59,0x1a,0x31,0xd5] -// CHECK: mrs x17, trcsscsr3 // encoding: [0x51,0x1b,0x31,0xd5] -// CHECK: mrs x19, trcsscsr4 // encoding: [0x53,0x1c,0x31,0xd5] -// CHECK: mrs x11, trcsscsr5 // encoding: [0x4b,0x1d,0x31,0xd5] -// CHECK: mrs x5, trcsscsr6 // encoding: [0x45,0x1e,0x31,0xd5] -// CHECK: mrs x9, trcsscsr7 // encoding: [0x49,0x1f,0x31,0xd5] -// CHECK: mrs x1, trcsspcicr0 // encoding: [0x61,0x10,0x31,0xd5] -// CHECK: mrs x12, trcsspcicr1 // encoding: [0x6c,0x11,0x31,0xd5] -// CHECK: mrs x21, trcsspcicr2 // encoding: [0x75,0x12,0x31,0xd5] -// CHECK: mrs x11, trcsspcicr3 // encoding: [0x6b,0x13,0x31,0xd5] -// CHECK: mrs x3, trcsspcicr4 // encoding: [0x63,0x14,0x31,0xd5] -// CHECK: mrs x9, trcsspcicr5 // encoding: [0x69,0x15,0x31,0xd5] -// CHECK: mrs x5, trcsspcicr6 // encoding: [0x65,0x16,0x31,0xd5] -// CHECK: mrs x2, trcsspcicr7 // encoding: [0x62,0x17,0x31,0xd5] -// CHECK: mrs x26, trcpdcr // encoding: [0x9a,0x14,0x31,0xd5] -// CHECK: mrs x8, trcacvr0 // encoding: [0x08,0x20,0x31,0xd5] -// CHECK: mrs x15, trcacvr1 // encoding: [0x0f,0x22,0x31,0xd5] -// CHECK: mrs x19, trcacvr2 // encoding: [0x13,0x24,0x31,0xd5] -// CHECK: mrs x8, trcacvr3 // encoding: [0x08,0x26,0x31,0xd5] -// CHECK: mrs x28, trcacvr4 // encoding: [0x1c,0x28,0x31,0xd5] -// CHECK: mrs x3, trcacvr5 // encoding: [0x03,0x2a,0x31,0xd5] -// CHECK: mrs x25, trcacvr6 // encoding: [0x19,0x2c,0x31,0xd5] -// CHECK: mrs x24, trcacvr7 // encoding: [0x18,0x2e,0x31,0xd5] -// CHECK: mrs x6, trcacvr8 // encoding: [0x26,0x20,0x31,0xd5] -// CHECK: mrs x3, trcacvr9 // encoding: [0x23,0x22,0x31,0xd5] -// CHECK: mrs x24, trcacvr10 // encoding: [0x38,0x24,0x31,0xd5] -// CHECK: mrs x3, trcacvr11 // encoding: [0x23,0x26,0x31,0xd5] -// CHECK: mrs x12, trcacvr12 // encoding: [0x2c,0x28,0x31,0xd5] -// CHECK: mrs x9, trcacvr13 // encoding: [0x29,0x2a,0x31,0xd5] -// CHECK: mrs x14, trcacvr14 // encoding: [0x2e,0x2c,0x31,0xd5] -// CHECK: mrs x3, trcacvr15 // encoding: [0x23,0x2e,0x31,0xd5] -// CHECK: mrs x21, trcacatr0 // encoding: [0x55,0x20,0x31,0xd5] -// CHECK: mrs x26, trcacatr1 // encoding: [0x5a,0x22,0x31,0xd5] -// CHECK: mrs x8, trcacatr2 // encoding: [0x48,0x24,0x31,0xd5] -// CHECK: mrs x22, trcacatr3 // encoding: [0x56,0x26,0x31,0xd5] -// CHECK: mrs x6, trcacatr4 // encoding: [0x46,0x28,0x31,0xd5] -// CHECK: mrs x29, trcacatr5 // encoding: [0x5d,0x2a,0x31,0xd5] -// CHECK: mrs x5, trcacatr6 // encoding: [0x45,0x2c,0x31,0xd5] -// CHECK: mrs x18, trcacatr7 // encoding: [0x52,0x2e,0x31,0xd5] -// CHECK: mrs x2, trcacatr8 // encoding: [0x62,0x20,0x31,0xd5] -// CHECK: mrs x19, trcacatr9 // encoding: [0x73,0x22,0x31,0xd5] -// CHECK: mrs x13, trcacatr10 // encoding: [0x6d,0x24,0x31,0xd5] -// CHECK: mrs x25, trcacatr11 // encoding: [0x79,0x26,0x31,0xd5] -// CHECK: mrs x18, trcacatr12 // encoding: [0x72,0x28,0x31,0xd5] -// CHECK: mrs x29, trcacatr13 // encoding: [0x7d,0x2a,0x31,0xd5] -// CHECK: mrs x9, trcacatr14 // encoding: [0x69,0x2c,0x31,0xd5] -// CHECK: mrs x18, trcacatr15 // encoding: [0x72,0x2e,0x31,0xd5] -// CHECK: mrs x29, trcdvcvr0 // encoding: [0x9d,0x20,0x31,0xd5] -// CHECK: mrs x15, trcdvcvr1 // encoding: [0x8f,0x24,0x31,0xd5] -// CHECK: mrs x15, trcdvcvr2 // encoding: [0x8f,0x28,0x31,0xd5] -// CHECK: mrs x15, trcdvcvr3 // encoding: [0x8f,0x2c,0x31,0xd5] -// CHECK: mrs x19, trcdvcvr4 // encoding: [0xb3,0x20,0x31,0xd5] -// CHECK: mrs x22, trcdvcvr5 // encoding: [0xb6,0x24,0x31,0xd5] -// CHECK: mrs x27, trcdvcvr6 // encoding: [0xbb,0x28,0x31,0xd5] -// CHECK: mrs x1, trcdvcvr7 // encoding: [0xa1,0x2c,0x31,0xd5] -// CHECK: mrs x29, trcdvcmr0 // encoding: [0xdd,0x20,0x31,0xd5] -// CHECK: mrs x9, trcdvcmr1 // encoding: [0xc9,0x24,0x31,0xd5] -// CHECK: mrs x1, trcdvcmr2 // encoding: [0xc1,0x28,0x31,0xd5] -// CHECK: mrs x2, trcdvcmr3 // encoding: [0xc2,0x2c,0x31,0xd5] -// CHECK: mrs x5, trcdvcmr4 // encoding: [0xe5,0x20,0x31,0xd5] -// CHECK: mrs x21, trcdvcmr5 // encoding: [0xf5,0x24,0x31,0xd5] -// CHECK: mrs x5, trcdvcmr6 // encoding: [0xe5,0x28,0x31,0xd5] -// CHECK: mrs x1, trcdvcmr7 // encoding: [0xe1,0x2c,0x31,0xd5] -// CHECK: mrs x21, trccidcvr0 // encoding: [0x15,0x30,0x31,0xd5] -// CHECK: mrs x24, trccidcvr1 // encoding: [0x18,0x32,0x31,0xd5] -// CHECK: mrs x24, trccidcvr2 // encoding: [0x18,0x34,0x31,0xd5] -// CHECK: mrs x12, trccidcvr3 // encoding: [0x0c,0x36,0x31,0xd5] -// CHECK: mrs x10, trccidcvr4 // encoding: [0x0a,0x38,0x31,0xd5] -// CHECK: mrs x9, trccidcvr5 // encoding: [0x09,0x3a,0x31,0xd5] -// CHECK: mrs x6, trccidcvr6 // encoding: [0x06,0x3c,0x31,0xd5] -// CHECK: mrs x20, trccidcvr7 // encoding: [0x14,0x3e,0x31,0xd5] -// CHECK: mrs x20, trcvmidcvr0 // encoding: [0x34,0x30,0x31,0xd5] -// CHECK: mrs x20, trcvmidcvr1 // encoding: [0x34,0x32,0x31,0xd5] -// CHECK: mrs x26, trcvmidcvr2 // encoding: [0x3a,0x34,0x31,0xd5] -// CHECK: mrs x1, trcvmidcvr3 // encoding: [0x21,0x36,0x31,0xd5] -// CHECK: mrs x14, trcvmidcvr4 // encoding: [0x2e,0x38,0x31,0xd5] -// CHECK: mrs x27, trcvmidcvr5 // encoding: [0x3b,0x3a,0x31,0xd5] -// CHECK: mrs x29, trcvmidcvr6 // encoding: [0x3d,0x3c,0x31,0xd5] -// CHECK: mrs x17, trcvmidcvr7 // encoding: [0x31,0x3e,0x31,0xd5] -// CHECK: mrs x10, trccidcctlr0 // encoding: [0x4a,0x30,0x31,0xd5] -// CHECK: mrs x4, trccidcctlr1 // encoding: [0x44,0x31,0x31,0xd5] -// CHECK: mrs x9, trcvmidcctlr0 // encoding: [0x49,0x32,0x31,0xd5] -// CHECK: mrs x11, trcvmidcctlr1 // encoding: [0x4b,0x33,0x31,0xd5] -// CHECK: mrs x22, trcitctrl // encoding: [0x96,0x70,0x31,0xd5] -// CHECK: mrs x23, trcclaimset // encoding: [0xd7,0x78,0x31,0xd5] -// CHECK: mrs x14, trcclaimclr // encoding: [0xce,0x79,0x31,0xd5] +// CHECK: mrs x8, {{trcstatr|TRCSTATR}} // encoding: [0x08,0x03,0x31,0xd5] +// CHECK: mrs x9, {{trcidr8|TRCIDR8}} // encoding: [0xc9,0x00,0x31,0xd5] +// CHECK: mrs x11, {{trcidr9|TRCIDR9}} // encoding: [0xcb,0x01,0x31,0xd5] +// CHECK: mrs x25, {{trcidr10|TRCIDR10}} // encoding: [0xd9,0x02,0x31,0xd5] +// CHECK: mrs x7, {{trcidr11|TRCIDR11}} // encoding: [0xc7,0x03,0x31,0xd5] +// CHECK: mrs x7, {{trcidr12|TRCIDR12}} // encoding: [0xc7,0x04,0x31,0xd5] +// CHECK: mrs x6, {{trcidr13|TRCIDR13}} // encoding: [0xc6,0x05,0x31,0xd5] +// CHECK: mrs x27, {{trcidr0|TRCIDR0}} // encoding: [0xfb,0x08,0x31,0xd5] +// CHECK: mrs x29, {{trcidr1|TRCIDR1}} // encoding: [0xfd,0x09,0x31,0xd5] +// CHECK: mrs x4, {{trcidr2|TRCIDR2}} // encoding: [0xe4,0x0a,0x31,0xd5] +// CHECK: mrs x8, {{trcidr3|TRCIDR3}} // encoding: [0xe8,0x0b,0x31,0xd5] +// CHECK: mrs x15, {{trcidr4|TRCIDR4}} // encoding: [0xef,0x0c,0x31,0xd5] +// CHECK: mrs x20, {{trcidr5|TRCIDR5}} // encoding: [0xf4,0x0d,0x31,0xd5] +// CHECK: mrs x6, {{trcidr6|TRCIDR6}} // encoding: [0xe6,0x0e,0x31,0xd5] +// CHECK: mrs x6, {{trcidr7|TRCIDR7}} // encoding: [0xe6,0x0f,0x31,0xd5] +// CHECK: mrs x24, {{trcoslsr|TRCOSLSR}} // encoding: [0x98,0x11,0x31,0xd5] +// CHECK: mrs x18, {{trcpdsr|TRCPDSR}} // encoding: [0x92,0x15,0x31,0xd5] +// CHECK: mrs x28, {{trcdevaff0|TRCDEVAFF0}} // encoding: [0xdc,0x7a,0x31,0xd5] +// CHECK: mrs x5, {{trcdevaff1|TRCDEVAFF1}} // encoding: [0xc5,0x7b,0x31,0xd5] +// CHECK: mrs x5, {{trclsr|TRCLSR}} // encoding: [0xc5,0x7d,0x31,0xd5] +// CHECK: mrs x11, {{trcauthstatus|TRCAUTHSTATUS}} // encoding: [0xcb,0x7e,0x31,0xd5] +// CHECK: mrs x13, {{trcdevarch|TRCDEVARCH}} // encoding: [0xcd,0x7f,0x31,0xd5] +// CHECK: mrs x18, {{trcdevid|TRCDEVID}} // encoding: [0xf2,0x72,0x31,0xd5] +// CHECK: mrs x22, {{trcdevtype|TRCDEVTYPE}} // encoding: [0xf6,0x73,0x31,0xd5] +// CHECK: mrs x14, {{trcpidr4|TRCPIDR4}} // encoding: [0xee,0x74,0x31,0xd5] +// CHECK: mrs x5, {{trcpidr5|TRCPIDR5}} // encoding: [0xe5,0x75,0x31,0xd5] +// CHECK: mrs x5, {{trcpidr6|TRCPIDR6}} // encoding: [0xe5,0x76,0x31,0xd5] +// CHECK: mrs x9, {{trcpidr7|TRCPIDR7}} // encoding: [0xe9,0x77,0x31,0xd5] +// CHECK: mrs x15, {{trcpidr0|TRCPIDR0}} // encoding: [0xef,0x78,0x31,0xd5] +// CHECK: mrs x6, {{trcpidr1|TRCPIDR1}} // encoding: [0xe6,0x79,0x31,0xd5] +// CHECK: mrs x11, {{trcpidr2|TRCPIDR2}} // encoding: [0xeb,0x7a,0x31,0xd5] +// CHECK: mrs x20, {{trcpidr3|TRCPIDR3}} // encoding: [0xf4,0x7b,0x31,0xd5] +// CHECK: mrs x17, {{trccidr0|TRCCIDR0}} // encoding: [0xf1,0x7c,0x31,0xd5] +// CHECK: mrs x2, {{trccidr1|TRCCIDR1}} // encoding: [0xe2,0x7d,0x31,0xd5] +// CHECK: mrs x20, {{trccidr2|TRCCIDR2}} // encoding: [0xf4,0x7e,0x31,0xd5] +// CHECK: mrs x4, {{trccidr3|TRCCIDR3}} // encoding: [0xe4,0x7f,0x31,0xd5] +// CHECK: mrs x11, {{trcprgctlr|TRCPRGCTLR}} // encoding: [0x0b,0x01,0x31,0xd5] +// CHECK: mrs x23, {{trcprocselr|TRCPROCSELR}} // encoding: [0x17,0x02,0x31,0xd5] +// CHECK: mrs x13, {{trcconfigr|TRCCONFIGR}} // encoding: [0x0d,0x04,0x31,0xd5] +// CHECK: mrs x23, {{trcauxctlr|TRCAUXCTLR}} // encoding: [0x17,0x06,0x31,0xd5] +// CHECK: mrs x9, {{trceventctl0r|TRCEVENTCTL0R}} // encoding: [0x09,0x08,0x31,0xd5] +// CHECK: mrs x16, {{trceventctl1r|TRCEVENTCTL1R}} // encoding: [0x10,0x09,0x31,0xd5] +// CHECK: mrs x4, {{trcstallctlr|TRCSTALLCTLR}} // encoding: [0x04,0x0b,0x31,0xd5] +// CHECK: mrs x14, {{trctsctlr|TRCTSCTLR}} // encoding: [0x0e,0x0c,0x31,0xd5] +// CHECK: mrs x24, {{trcsyncpr|TRCSYNCPR}} // encoding: [0x18,0x0d,0x31,0xd5] +// CHECK: mrs x28, {{trcccctlr|TRCCCCTLR}} // encoding: [0x1c,0x0e,0x31,0xd5] +// CHECK: mrs x15, {{trcbbctlr|TRCBBCTLR}} // encoding: [0x0f,0x0f,0x31,0xd5] +// CHECK: mrs x1, {{trctraceidr|TRCTRACEIDR}} // encoding: [0x21,0x00,0x31,0xd5] +// CHECK: mrs x20, {{trcqctlr|TRCQCTLR}} // encoding: [0x34,0x01,0x31,0xd5] +// CHECK: mrs x2, {{trcvictlr|TRCVICTLR}} // encoding: [0x42,0x00,0x31,0xd5] +// CHECK: mrs x12, {{trcviiectlr|TRCVIIECTLR}} // encoding: [0x4c,0x01,0x31,0xd5] +// CHECK: mrs x16, {{trcvissctlr|TRCVISSCTLR}} // encoding: [0x50,0x02,0x31,0xd5] +// CHECK: mrs x8, {{trcvipcssctlr|TRCVIPCSSCTLR}} // encoding: [0x48,0x03,0x31,0xd5] +// CHECK: mrs x27, {{trcvdctlr|TRCVDCTLR}} // encoding: [0x5b,0x08,0x31,0xd5] +// CHECK: mrs x9, {{trcvdsacctlr|TRCVDSACCTLR}} // encoding: [0x49,0x09,0x31,0xd5] +// CHECK: mrs x0, {{trcvdarcctlr|TRCVDARCCTLR}} // encoding: [0x40,0x0a,0x31,0xd5] +// CHECK: mrs x13, {{trcseqevr0|TRCSEQEVR0}} // encoding: [0x8d,0x00,0x31,0xd5] +// CHECK: mrs x11, {{trcseqevr1|TRCSEQEVR1}} // encoding: [0x8b,0x01,0x31,0xd5] +// CHECK: mrs x26, {{trcseqevr2|TRCSEQEVR2}} // encoding: [0x9a,0x02,0x31,0xd5] +// CHECK: mrs x14, {{trcseqrstevr|TRCSEQRSTEVR}} // encoding: [0x8e,0x06,0x31,0xd5] +// CHECK: mrs x4, {{trcseqstr|TRCSEQSTR}} // encoding: [0x84,0x07,0x31,0xd5] +// CHECK: mrs x17, {{trcextinselr|TRCEXTINSELR}} // encoding: [0x91,0x08,0x31,0xd5] +// CHECK: mrs x21, {{trccntrldvr0|TRCCNTRLDVR0}} // encoding: [0xb5,0x00,0x31,0xd5] +// CHECK: mrs x10, {{trccntrldvr1|TRCCNTRLDVR1}} // encoding: [0xaa,0x01,0x31,0xd5] +// CHECK: mrs x20, {{trccntrldvr2|TRCCNTRLDVR2}} // encoding: [0xb4,0x02,0x31,0xd5] +// CHECK: mrs x5, {{trccntrldvr3|TRCCNTRLDVR3}} // encoding: [0xa5,0x03,0x31,0xd5] +// CHECK: mrs x17, {{trccntctlr0|TRCCNTCTLR0}} // encoding: [0xb1,0x04,0x31,0xd5] +// CHECK: mrs x1, {{trccntctlr1|TRCCNTCTLR1}} // encoding: [0xa1,0x05,0x31,0xd5] +// CHECK: mrs x17, {{trccntctlr2|TRCCNTCTLR2}} // encoding: [0xb1,0x06,0x31,0xd5] +// CHECK: mrs x6, {{trccntctlr3|TRCCNTCTLR3}} // encoding: [0xa6,0x07,0x31,0xd5] +// CHECK: mrs x28, {{trccntvr0|TRCCNTVR0}} // encoding: [0xbc,0x08,0x31,0xd5] +// CHECK: mrs x23, {{trccntvr1|TRCCNTVR1}} // encoding: [0xb7,0x09,0x31,0xd5] +// CHECK: mrs x9, {{trccntvr2|TRCCNTVR2}} // encoding: [0xa9,0x0a,0x31,0xd5] +// CHECK: mrs x6, {{trccntvr3|TRCCNTVR3}} // encoding: [0xa6,0x0b,0x31,0xd5] +// CHECK: mrs x24, {{trcimspec0|TRCIMSPEC0}} // encoding: [0xf8,0x00,0x31,0xd5] +// CHECK: mrs x24, {{trcimspec1|TRCIMSPEC1}} // encoding: [0xf8,0x01,0x31,0xd5] +// CHECK: mrs x15, {{trcimspec2|TRCIMSPEC2}} // encoding: [0xef,0x02,0x31,0xd5] +// CHECK: mrs x10, {{trcimspec3|TRCIMSPEC3}} // encoding: [0xea,0x03,0x31,0xd5] +// CHECK: mrs x29, {{trcimspec4|TRCIMSPEC4}} // encoding: [0xfd,0x04,0x31,0xd5] +// CHECK: mrs x18, {{trcimspec5|TRCIMSPEC5}} // encoding: [0xf2,0x05,0x31,0xd5] +// CHECK: mrs x29, {{trcimspec6|TRCIMSPEC6}} // encoding: [0xfd,0x06,0x31,0xd5] +// CHECK: mrs x2, {{trcimspec7|TRCIMSPEC7}} // encoding: [0xe2,0x07,0x31,0xd5] +// CHECK: mrs x8, {{trcrsctlr2|TRCRSCTLR2}} // encoding: [0x08,0x12,0x31,0xd5] +// CHECK: mrs x0, {{trcrsctlr3|TRCRSCTLR3}} // encoding: [0x00,0x13,0x31,0xd5] +// CHECK: mrs x12, {{trcrsctlr4|TRCRSCTLR4}} // encoding: [0x0c,0x14,0x31,0xd5] +// CHECK: mrs x26, {{trcrsctlr5|TRCRSCTLR5}} // encoding: [0x1a,0x15,0x31,0xd5] +// CHECK: mrs x29, {{trcrsctlr6|TRCRSCTLR6}} // encoding: [0x1d,0x16,0x31,0xd5] +// CHECK: mrs x17, {{trcrsctlr7|TRCRSCTLR7}} // encoding: [0x11,0x17,0x31,0xd5] +// CHECK: mrs x0, {{trcrsctlr8|TRCRSCTLR8}} // encoding: [0x00,0x18,0x31,0xd5] +// CHECK: mrs x1, {{trcrsctlr9|TRCRSCTLR9}} // encoding: [0x01,0x19,0x31,0xd5] +// CHECK: mrs x17, {{trcrsctlr10|TRCRSCTLR10}} // encoding: [0x11,0x1a,0x31,0xd5] +// CHECK: mrs x21, {{trcrsctlr11|TRCRSCTLR11}} // encoding: [0x15,0x1b,0x31,0xd5] +// CHECK: mrs x1, {{trcrsctlr12|TRCRSCTLR12}} // encoding: [0x01,0x1c,0x31,0xd5] +// CHECK: mrs x8, {{trcrsctlr13|TRCRSCTLR13}} // encoding: [0x08,0x1d,0x31,0xd5] +// CHECK: mrs x24, {{trcrsctlr14|TRCRSCTLR14}} // encoding: [0x18,0x1e,0x31,0xd5] +// CHECK: mrs x0, {{trcrsctlr15|TRCRSCTLR15}} // encoding: [0x00,0x1f,0x31,0xd5] +// CHECK: mrs x2, {{trcrsctlr16|TRCRSCTLR16}} // encoding: [0x22,0x10,0x31,0xd5] +// CHECK: mrs x29, {{trcrsctlr17|TRCRSCTLR17}} // encoding: [0x3d,0x11,0x31,0xd5] +// CHECK: mrs x22, {{trcrsctlr18|TRCRSCTLR18}} // encoding: [0x36,0x12,0x31,0xd5] +// CHECK: mrs x6, {{trcrsctlr19|TRCRSCTLR19}} // encoding: [0x26,0x13,0x31,0xd5] +// CHECK: mrs x26, {{trcrsctlr20|TRCRSCTLR20}} // encoding: [0x3a,0x14,0x31,0xd5] +// CHECK: mrs x26, {{trcrsctlr21|TRCRSCTLR21}} // encoding: [0x3a,0x15,0x31,0xd5] +// CHECK: mrs x4, {{trcrsctlr22|TRCRSCTLR22}} // encoding: [0x24,0x16,0x31,0xd5] +// CHECK: mrs x12, {{trcrsctlr23|TRCRSCTLR23}} // encoding: [0x2c,0x17,0x31,0xd5] +// CHECK: mrs x1, {{trcrsctlr24|TRCRSCTLR24}} // encoding: [0x21,0x18,0x31,0xd5] +// CHECK: mrs x0, {{trcrsctlr25|TRCRSCTLR25}} // encoding: [0x20,0x19,0x31,0xd5] +// CHECK: mrs x17, {{trcrsctlr26|TRCRSCTLR26}} // encoding: [0x31,0x1a,0x31,0xd5] +// CHECK: mrs x8, {{trcrsctlr27|TRCRSCTLR27}} // encoding: [0x28,0x1b,0x31,0xd5] +// CHECK: mrs x10, {{trcrsctlr28|TRCRSCTLR28}} // encoding: [0x2a,0x1c,0x31,0xd5] +// CHECK: mrs x25, {{trcrsctlr29|TRCRSCTLR29}} // encoding: [0x39,0x1d,0x31,0xd5] +// CHECK: mrs x12, {{trcrsctlr30|TRCRSCTLR30}} // encoding: [0x2c,0x1e,0x31,0xd5] +// CHECK: mrs x11, {{trcrsctlr31|TRCRSCTLR31}} // encoding: [0x2b,0x1f,0x31,0xd5] +// CHECK: mrs x18, {{trcssccr0|TRCSSCCR0}} // encoding: [0x52,0x10,0x31,0xd5] +// CHECK: mrs x12, {{trcssccr1|TRCSSCCR1}} // encoding: [0x4c,0x11,0x31,0xd5] +// CHECK: mrs x3, {{trcssccr2|TRCSSCCR2}} // encoding: [0x43,0x12,0x31,0xd5] +// CHECK: mrs x2, {{trcssccr3|TRCSSCCR3}} // encoding: [0x42,0x13,0x31,0xd5] +// CHECK: mrs x21, {{trcssccr4|TRCSSCCR4}} // encoding: [0x55,0x14,0x31,0xd5] +// CHECK: mrs x10, {{trcssccr5|TRCSSCCR5}} // encoding: [0x4a,0x15,0x31,0xd5] +// CHECK: mrs x22, {{trcssccr6|TRCSSCCR6}} // encoding: [0x56,0x16,0x31,0xd5] +// CHECK: mrs x23, {{trcssccr7|TRCSSCCR7}} // encoding: [0x57,0x17,0x31,0xd5] +// CHECK: mrs x23, {{trcsscsr0|TRCSSCSR0}} // encoding: [0x57,0x18,0x31,0xd5] +// CHECK: mrs x19, {{trcsscsr1|TRCSSCSR1}} // encoding: [0x53,0x19,0x31,0xd5] +// CHECK: mrs x25, {{trcsscsr2|TRCSSCSR2}} // encoding: [0x59,0x1a,0x31,0xd5] +// CHECK: mrs x17, {{trcsscsr3|TRCSSCSR3}} // encoding: [0x51,0x1b,0x31,0xd5] +// CHECK: mrs x19, {{trcsscsr4|TRCSSCSR4}} // encoding: [0x53,0x1c,0x31,0xd5] +// CHECK: mrs x11, {{trcsscsr5|TRCSSCSR5}} // encoding: [0x4b,0x1d,0x31,0xd5] +// CHECK: mrs x5, {{trcsscsr6|TRCSSCSR6}} // encoding: [0x45,0x1e,0x31,0xd5] +// CHECK: mrs x9, {{trcsscsr7|TRCSSCSR7}} // encoding: [0x49,0x1f,0x31,0xd5] +// CHECK: mrs x1, {{trcsspcicr0|TRCSSPCICR0}} // encoding: [0x61,0x10,0x31,0xd5] +// CHECK: mrs x12, {{trcsspcicr1|TRCSSPCICR1}} // encoding: [0x6c,0x11,0x31,0xd5] +// CHECK: mrs x21, {{trcsspcicr2|TRCSSPCICR2}} // encoding: [0x75,0x12,0x31,0xd5] +// CHECK: mrs x11, {{trcsspcicr3|TRCSSPCICR3}} // encoding: [0x6b,0x13,0x31,0xd5] +// CHECK: mrs x3, {{trcsspcicr4|TRCSSPCICR4}} // encoding: [0x63,0x14,0x31,0xd5] +// CHECK: mrs x9, {{trcsspcicr5|TRCSSPCICR5}} // encoding: [0x69,0x15,0x31,0xd5] +// CHECK: mrs x5, {{trcsspcicr6|TRCSSPCICR6}} // encoding: [0x65,0x16,0x31,0xd5] +// CHECK: mrs x2, {{trcsspcicr7|TRCSSPCICR7}} // encoding: [0x62,0x17,0x31,0xd5] +// CHECK: mrs x26, {{trcpdcr|TRCPDCR}} // encoding: [0x9a,0x14,0x31,0xd5] +// CHECK: mrs x8, {{trcacvr0|TRCACVR0}} // encoding: [0x08,0x20,0x31,0xd5] +// CHECK: mrs x15, {{trcacvr1|TRCACVR1}} // encoding: [0x0f,0x22,0x31,0xd5] +// CHECK: mrs x19, {{trcacvr2|TRCACVR2}} // encoding: [0x13,0x24,0x31,0xd5] +// CHECK: mrs x8, {{trcacvr3|TRCACVR3}} // encoding: [0x08,0x26,0x31,0xd5] +// CHECK: mrs x28, {{trcacvr4|TRCACVR4}} // encoding: [0x1c,0x28,0x31,0xd5] +// CHECK: mrs x3, {{trcacvr5|TRCACVR5}} // encoding: [0x03,0x2a,0x31,0xd5] +// CHECK: mrs x25, {{trcacvr6|TRCACVR6}} // encoding: [0x19,0x2c,0x31,0xd5] +// CHECK: mrs x24, {{trcacvr7|TRCACVR7}} // encoding: [0x18,0x2e,0x31,0xd5] +// CHECK: mrs x6, {{trcacvr8|TRCACVR8}} // encoding: [0x26,0x20,0x31,0xd5] +// CHECK: mrs x3, {{trcacvr9|TRCACVR9}} // encoding: [0x23,0x22,0x31,0xd5] +// CHECK: mrs x24, {{trcacvr10|TRCACVR10}} // encoding: [0x38,0x24,0x31,0xd5] +// CHECK: mrs x3, {{trcacvr11|TRCACVR11}} // encoding: [0x23,0x26,0x31,0xd5] +// CHECK: mrs x12, {{trcacvr12|TRCACVR12}} // encoding: [0x2c,0x28,0x31,0xd5] +// CHECK: mrs x9, {{trcacvr13|TRCACVR13}} // encoding: [0x29,0x2a,0x31,0xd5] +// CHECK: mrs x14, {{trcacvr14|TRCACVR14}} // encoding: [0x2e,0x2c,0x31,0xd5] +// CHECK: mrs x3, {{trcacvr15|TRCACVR15}} // encoding: [0x23,0x2e,0x31,0xd5] +// CHECK: mrs x21, {{trcacatr0|TRCACATR0}} // encoding: [0x55,0x20,0x31,0xd5] +// CHECK: mrs x26, {{trcacatr1|TRCACATR1}} // encoding: [0x5a,0x22,0x31,0xd5] +// CHECK: mrs x8, {{trcacatr2|TRCACATR2}} // encoding: [0x48,0x24,0x31,0xd5] +// CHECK: mrs x22, {{trcacatr3|TRCACATR3}} // encoding: [0x56,0x26,0x31,0xd5] +// CHECK: mrs x6, {{trcacatr4|TRCACATR4}} // encoding: [0x46,0x28,0x31,0xd5] +// CHECK: mrs x29, {{trcacatr5|TRCACATR5}} // encoding: [0x5d,0x2a,0x31,0xd5] +// CHECK: mrs x5, {{trcacatr6|TRCACATR6}} // encoding: [0x45,0x2c,0x31,0xd5] +// CHECK: mrs x18, {{trcacatr7|TRCACATR7}} // encoding: [0x52,0x2e,0x31,0xd5] +// CHECK: mrs x2, {{trcacatr8|TRCACATR8}} // encoding: [0x62,0x20,0x31,0xd5] +// CHECK: mrs x19, {{trcacatr9|TRCACATR9}} // encoding: [0x73,0x22,0x31,0xd5] +// CHECK: mrs x13, {{trcacatr10|TRCACATR10}} // encoding: [0x6d,0x24,0x31,0xd5] +// CHECK: mrs x25, {{trcacatr11|TRCACATR11}} // encoding: [0x79,0x26,0x31,0xd5] +// CHECK: mrs x18, {{trcacatr12|TRCACATR12}} // encoding: [0x72,0x28,0x31,0xd5] +// CHECK: mrs x29, {{trcacatr13|TRCACATR13}} // encoding: [0x7d,0x2a,0x31,0xd5] +// CHECK: mrs x9, {{trcacatr14|TRCACATR14}} // encoding: [0x69,0x2c,0x31,0xd5] +// CHECK: mrs x18, {{trcacatr15|TRCACATR15}} // encoding: [0x72,0x2e,0x31,0xd5] +// CHECK: mrs x29, {{trcdvcvr0|TRCDVCVR0}} // encoding: [0x9d,0x20,0x31,0xd5] +// CHECK: mrs x15, {{trcdvcvr1|TRCDVCVR1}} // encoding: [0x8f,0x24,0x31,0xd5] +// CHECK: mrs x15, {{trcdvcvr2|TRCDVCVR2}} // encoding: [0x8f,0x28,0x31,0xd5] +// CHECK: mrs x15, {{trcdvcvr3|TRCDVCVR3}} // encoding: [0x8f,0x2c,0x31,0xd5] +// CHECK: mrs x19, {{trcdvcvr4|TRCDVCVR4}} // encoding: [0xb3,0x20,0x31,0xd5] +// CHECK: mrs x22, {{trcdvcvr5|TRCDVCVR5}} // encoding: [0xb6,0x24,0x31,0xd5] +// CHECK: mrs x27, {{trcdvcvr6|TRCDVCVR6}} // encoding: [0xbb,0x28,0x31,0xd5] +// CHECK: mrs x1, {{trcdvcvr7|TRCDVCVR7}} // encoding: [0xa1,0x2c,0x31,0xd5] +// CHECK: mrs x29, {{trcdvcmr0|TRCDVCMR0}} // encoding: [0xdd,0x20,0x31,0xd5] +// CHECK: mrs x9, {{trcdvcmr1|TRCDVCMR1}} // encoding: [0xc9,0x24,0x31,0xd5] +// CHECK: mrs x1, {{trcdvcmr2|TRCDVCMR2}} // encoding: [0xc1,0x28,0x31,0xd5] +// CHECK: mrs x2, {{trcdvcmr3|TRCDVCMR3}} // encoding: [0xc2,0x2c,0x31,0xd5] +// CHECK: mrs x5, {{trcdvcmr4|TRCDVCMR4}} // encoding: [0xe5,0x20,0x31,0xd5] +// CHECK: mrs x21, {{trcdvcmr5|TRCDVCMR5}} // encoding: [0xf5,0x24,0x31,0xd5] +// CHECK: mrs x5, {{trcdvcmr6|TRCDVCMR6}} // encoding: [0xe5,0x28,0x31,0xd5] +// CHECK: mrs x1, {{trcdvcmr7|TRCDVCMR7}} // encoding: [0xe1,0x2c,0x31,0xd5] +// CHECK: mrs x21, {{trccidcvr0|TRCCIDCVR0}} // encoding: [0x15,0x30,0x31,0xd5] +// CHECK: mrs x24, {{trccidcvr1|TRCCIDCVR1}} // encoding: [0x18,0x32,0x31,0xd5] +// CHECK: mrs x24, {{trccidcvr2|TRCCIDCVR2}} // encoding: [0x18,0x34,0x31,0xd5] +// CHECK: mrs x12, {{trccidcvr3|TRCCIDCVR3}} // encoding: [0x0c,0x36,0x31,0xd5] +// CHECK: mrs x10, {{trccidcvr4|TRCCIDCVR4}} // encoding: [0x0a,0x38,0x31,0xd5] +// CHECK: mrs x9, {{trccidcvr5|TRCCIDCVR5}} // encoding: [0x09,0x3a,0x31,0xd5] +// CHECK: mrs x6, {{trccidcvr6|TRCCIDCVR6}} // encoding: [0x06,0x3c,0x31,0xd5] +// CHECK: mrs x20, {{trccidcvr7|TRCCIDCVR7}} // encoding: [0x14,0x3e,0x31,0xd5] +// CHECK: mrs x20, {{trcvmidcvr0|TRCVMIDCVR0}} // encoding: [0x34,0x30,0x31,0xd5] +// CHECK: mrs x20, {{trcvmidcvr1|TRCVMIDCVR1}} // encoding: [0x34,0x32,0x31,0xd5] +// CHECK: mrs x26, {{trcvmidcvr2|TRCVMIDCVR2}} // encoding: [0x3a,0x34,0x31,0xd5] +// CHECK: mrs x1, {{trcvmidcvr3|TRCVMIDCVR3}} // encoding: [0x21,0x36,0x31,0xd5] +// CHECK: mrs x14, {{trcvmidcvr4|TRCVMIDCVR4}} // encoding: [0x2e,0x38,0x31,0xd5] +// CHECK: mrs x27, {{trcvmidcvr5|TRCVMIDCVR5}} // encoding: [0x3b,0x3a,0x31,0xd5] +// CHECK: mrs x29, {{trcvmidcvr6|TRCVMIDCVR6}} // encoding: [0x3d,0x3c,0x31,0xd5] +// CHECK: mrs x17, {{trcvmidcvr7|TRCVMIDCVR7}} // encoding: [0x31,0x3e,0x31,0xd5] +// CHECK: mrs x10, {{trccidcctlr0|TRCCIDCCTLR0}} // encoding: [0x4a,0x30,0x31,0xd5] +// CHECK: mrs x4, {{trccidcctlr1|TRCCIDCCTLR1}} // encoding: [0x44,0x31,0x31,0xd5] +// CHECK: mrs x9, {{trcvmidcctlr0|TRCVMIDCCTLR0}} // encoding: [0x49,0x32,0x31,0xd5] +// CHECK: mrs x11, {{trcvmidcctlr1|TRCVMIDCCTLR1}} // encoding: [0x4b,0x33,0x31,0xd5] +// CHECK: mrs x22, {{trcitctrl|TRCITCTRL}} // encoding: [0x96,0x70,0x31,0xd5] +// CHECK: mrs x23, {{trcclaimset|TRCCLAIMSET}} // encoding: [0xd7,0x78,0x31,0xd5] +// CHECK: mrs x14, {{trcclaimclr|TRCCLAIMCLR}} // encoding: [0xce,0x79,0x31,0xd5] msr trcoslar, x28 msr trclar, x14 @@ -590,177 +591,177 @@ msr trcitctrl, x1 msr trcclaimset, x7 msr trcclaimclr, x29 -// CHECK: msr trcoslar, x28 // encoding: [0x9c,0x10,0x11,0xd5] -// CHECK: msr trclar, x14 // encoding: [0xce,0x7c,0x11,0xd5] -// CHECK: msr trcprgctlr, x10 // encoding: [0x0a,0x01,0x11,0xd5] -// CHECK: msr trcprocselr, x27 // encoding: [0x1b,0x02,0x11,0xd5] -// CHECK: msr trcconfigr, x24 // encoding: [0x18,0x04,0x11,0xd5] -// CHECK: msr trcauxctlr, x8 // encoding: [0x08,0x06,0x11,0xd5] -// CHECK: msr trceventctl0r, x16 // encoding: [0x10,0x08,0x11,0xd5] -// CHECK: msr trceventctl1r, x27 // encoding: [0x1b,0x09,0x11,0xd5] -// CHECK: msr trcstallctlr, x26 // encoding: [0x1a,0x0b,0x11,0xd5] -// CHECK: msr trctsctlr, x0 // encoding: [0x00,0x0c,0x11,0xd5] -// CHECK: msr trcsyncpr, x14 // encoding: [0x0e,0x0d,0x11,0xd5] -// CHECK: msr trcccctlr, x8 // encoding: [0x08,0x0e,0x11,0xd5] -// CHECK: msr trcbbctlr, x6 // encoding: [0x06,0x0f,0x11,0xd5] -// CHECK: msr trctraceidr, x23 // encoding: [0x37,0x00,0x11,0xd5] -// CHECK: msr trcqctlr, x5 // encoding: [0x25,0x01,0x11,0xd5] -// CHECK: msr trcvictlr, x0 // encoding: [0x40,0x00,0x11,0xd5] -// CHECK: msr trcviiectlr, x0 // encoding: [0x40,0x01,0x11,0xd5] -// CHECK: msr trcvissctlr, x1 // encoding: [0x41,0x02,0x11,0xd5] -// CHECK: msr trcvipcssctlr, x0 // encoding: [0x40,0x03,0x11,0xd5] -// CHECK: msr trcvdctlr, x7 // encoding: [0x47,0x08,0x11,0xd5] -// CHECK: msr trcvdsacctlr, x18 // encoding: [0x52,0x09,0x11,0xd5] -// CHECK: msr trcvdarcctlr, x24 // encoding: [0x58,0x0a,0x11,0xd5] -// CHECK: msr trcseqevr0, x28 // encoding: [0x9c,0x00,0x11,0xd5] -// CHECK: msr trcseqevr1, x21 // encoding: [0x95,0x01,0x11,0xd5] -// CHECK: msr trcseqevr2, x16 // encoding: [0x90,0x02,0x11,0xd5] -// CHECK: msr trcseqrstevr, x16 // encoding: [0x90,0x06,0x11,0xd5] -// CHECK: msr trcseqstr, x25 // encoding: [0x99,0x07,0x11,0xd5] -// CHECK: msr trcextinselr, x29 // encoding: [0x9d,0x08,0x11,0xd5] -// CHECK: msr trccntrldvr0, x20 // encoding: [0xb4,0x00,0x11,0xd5] -// CHECK: msr trccntrldvr1, x20 // encoding: [0xb4,0x01,0x11,0xd5] -// CHECK: msr trccntrldvr2, x22 // encoding: [0xb6,0x02,0x11,0xd5] -// CHECK: msr trccntrldvr3, x12 // encoding: [0xac,0x03,0x11,0xd5] -// CHECK: msr trccntctlr0, x20 // encoding: [0xb4,0x04,0x11,0xd5] -// CHECK: msr trccntctlr1, x4 // encoding: [0xa4,0x05,0x11,0xd5] -// CHECK: msr trccntctlr2, x8 // encoding: [0xa8,0x06,0x11,0xd5] -// CHECK: msr trccntctlr3, x16 // encoding: [0xb0,0x07,0x11,0xd5] -// CHECK: msr trccntvr0, x5 // encoding: [0xa5,0x08,0x11,0xd5] -// CHECK: msr trccntvr1, x27 // encoding: [0xbb,0x09,0x11,0xd5] -// CHECK: msr trccntvr2, x21 // encoding: [0xb5,0x0a,0x11,0xd5] -// CHECK: msr trccntvr3, x8 // encoding: [0xa8,0x0b,0x11,0xd5] -// CHECK: msr trcimspec0, x6 // encoding: [0xe6,0x00,0x11,0xd5] -// CHECK: msr trcimspec1, x27 // encoding: [0xfb,0x01,0x11,0xd5] -// CHECK: msr trcimspec2, x23 // encoding: [0xf7,0x02,0x11,0xd5] -// CHECK: msr trcimspec3, x15 // encoding: [0xef,0x03,0x11,0xd5] -// CHECK: msr trcimspec4, x13 // encoding: [0xed,0x04,0x11,0xd5] -// CHECK: msr trcimspec5, x25 // encoding: [0xf9,0x05,0x11,0xd5] -// CHECK: msr trcimspec6, x19 // encoding: [0xf3,0x06,0x11,0xd5] -// CHECK: msr trcimspec7, x27 // encoding: [0xfb,0x07,0x11,0xd5] -// CHECK: msr trcrsctlr2, x4 // encoding: [0x04,0x12,0x11,0xd5] -// CHECK: msr trcrsctlr3, x0 // encoding: [0x00,0x13,0x11,0xd5] -// CHECK: msr trcrsctlr4, x21 // encoding: [0x15,0x14,0x11,0xd5] -// CHECK: msr trcrsctlr5, x8 // encoding: [0x08,0x15,0x11,0xd5] -// CHECK: msr trcrsctlr6, x20 // encoding: [0x14,0x16,0x11,0xd5] -// CHECK: msr trcrsctlr7, x11 // encoding: [0x0b,0x17,0x11,0xd5] -// CHECK: msr trcrsctlr8, x18 // encoding: [0x12,0x18,0x11,0xd5] -// CHECK: msr trcrsctlr9, x24 // encoding: [0x18,0x19,0x11,0xd5] -// CHECK: msr trcrsctlr10, x15 // encoding: [0x0f,0x1a,0x11,0xd5] -// CHECK: msr trcrsctlr11, x21 // encoding: [0x15,0x1b,0x11,0xd5] -// CHECK: msr trcrsctlr12, x4 // encoding: [0x04,0x1c,0x11,0xd5] -// CHECK: msr trcrsctlr13, x28 // encoding: [0x1c,0x1d,0x11,0xd5] -// CHECK: msr trcrsctlr14, x3 // encoding: [0x03,0x1e,0x11,0xd5] -// CHECK: msr trcrsctlr15, x20 // encoding: [0x14,0x1f,0x11,0xd5] -// CHECK: msr trcrsctlr16, x12 // encoding: [0x2c,0x10,0x11,0xd5] -// CHECK: msr trcrsctlr17, x17 // encoding: [0x31,0x11,0x11,0xd5] -// CHECK: msr trcrsctlr18, x10 // encoding: [0x2a,0x12,0x11,0xd5] -// CHECK: msr trcrsctlr19, x11 // encoding: [0x2b,0x13,0x11,0xd5] -// CHECK: msr trcrsctlr20, x3 // encoding: [0x23,0x14,0x11,0xd5] -// CHECK: msr trcrsctlr21, x18 // encoding: [0x32,0x15,0x11,0xd5] -// CHECK: msr trcrsctlr22, x26 // encoding: [0x3a,0x16,0x11,0xd5] -// CHECK: msr trcrsctlr23, x5 // encoding: [0x25,0x17,0x11,0xd5] -// CHECK: msr trcrsctlr24, x25 // encoding: [0x39,0x18,0x11,0xd5] -// CHECK: msr trcrsctlr25, x5 // encoding: [0x25,0x19,0x11,0xd5] -// CHECK: msr trcrsctlr26, x4 // encoding: [0x24,0x1a,0x11,0xd5] -// CHECK: msr trcrsctlr27, x20 // encoding: [0x34,0x1b,0x11,0xd5] -// CHECK: msr trcrsctlr28, x5 // encoding: [0x25,0x1c,0x11,0xd5] -// CHECK: msr trcrsctlr29, x10 // encoding: [0x2a,0x1d,0x11,0xd5] -// CHECK: msr trcrsctlr30, x24 // encoding: [0x38,0x1e,0x11,0xd5] -// CHECK: msr trcrsctlr31, x20 // encoding: [0x34,0x1f,0x11,0xd5] -// CHECK: msr trcssccr0, x23 // encoding: [0x57,0x10,0x11,0xd5] -// CHECK: msr trcssccr1, x27 // encoding: [0x5b,0x11,0x11,0xd5] -// CHECK: msr trcssccr2, x27 // encoding: [0x5b,0x12,0x11,0xd5] -// CHECK: msr trcssccr3, x6 // encoding: [0x46,0x13,0x11,0xd5] -// CHECK: msr trcssccr4, x3 // encoding: [0x43,0x14,0x11,0xd5] -// CHECK: msr trcssccr5, x12 // encoding: [0x4c,0x15,0x11,0xd5] -// CHECK: msr trcssccr6, x7 // encoding: [0x47,0x16,0x11,0xd5] -// CHECK: msr trcssccr7, x6 // encoding: [0x46,0x17,0x11,0xd5] -// CHECK: msr trcsscsr0, x20 // encoding: [0x54,0x18,0x11,0xd5] -// CHECK: msr trcsscsr1, x17 // encoding: [0x51,0x19,0x11,0xd5] -// CHECK: msr trcsscsr2, x11 // encoding: [0x4b,0x1a,0x11,0xd5] -// CHECK: msr trcsscsr3, x4 // encoding: [0x44,0x1b,0x11,0xd5] -// CHECK: msr trcsscsr4, x14 // encoding: [0x4e,0x1c,0x11,0xd5] -// CHECK: msr trcsscsr5, x22 // encoding: [0x56,0x1d,0x11,0xd5] -// CHECK: msr trcsscsr6, x3 // encoding: [0x43,0x1e,0x11,0xd5] -// CHECK: msr trcsscsr7, x11 // encoding: [0x4b,0x1f,0x11,0xd5] -// CHECK: msr trcsspcicr0, x2 // encoding: [0x62,0x10,0x11,0xd5] -// CHECK: msr trcsspcicr1, x3 // encoding: [0x63,0x11,0x11,0xd5] -// CHECK: msr trcsspcicr2, x5 // encoding: [0x65,0x12,0x11,0xd5] -// CHECK: msr trcsspcicr3, x7 // encoding: [0x67,0x13,0x11,0xd5] -// CHECK: msr trcsspcicr4, x11 // encoding: [0x6b,0x14,0x11,0xd5] -// CHECK: msr trcsspcicr5, x13 // encoding: [0x6d,0x15,0x11,0xd5] -// CHECK: msr trcsspcicr6, x17 // encoding: [0x71,0x16,0x11,0xd5] -// CHECK: msr trcsspcicr7, x23 // encoding: [0x77,0x17,0x11,0xd5] -// CHECK: msr trcpdcr, x3 // encoding: [0x83,0x14,0x11,0xd5] -// CHECK: msr trcacvr0, x6 // encoding: [0x06,0x20,0x11,0xd5] -// CHECK: msr trcacvr1, x20 // encoding: [0x14,0x22,0x11,0xd5] -// CHECK: msr trcacvr2, x25 // encoding: [0x19,0x24,0x11,0xd5] -// CHECK: msr trcacvr3, x1 // encoding: [0x01,0x26,0x11,0xd5] -// CHECK: msr trcacvr4, x28 // encoding: [0x1c,0x28,0x11,0xd5] -// CHECK: msr trcacvr5, x15 // encoding: [0x0f,0x2a,0x11,0xd5] -// CHECK: msr trcacvr6, x25 // encoding: [0x19,0x2c,0x11,0xd5] -// CHECK: msr trcacvr7, x12 // encoding: [0x0c,0x2e,0x11,0xd5] -// CHECK: msr trcacvr8, x5 // encoding: [0x25,0x20,0x11,0xd5] -// CHECK: msr trcacvr9, x25 // encoding: [0x39,0x22,0x11,0xd5] -// CHECK: msr trcacvr10, x13 // encoding: [0x2d,0x24,0x11,0xd5] -// CHECK: msr trcacvr11, x10 // encoding: [0x2a,0x26,0x11,0xd5] -// CHECK: msr trcacvr12, x19 // encoding: [0x33,0x28,0x11,0xd5] -// CHECK: msr trcacvr13, x10 // encoding: [0x2a,0x2a,0x11,0xd5] -// CHECK: msr trcacvr14, x19 // encoding: [0x33,0x2c,0x11,0xd5] -// CHECK: msr trcacvr15, x2 // encoding: [0x22,0x2e,0x11,0xd5] -// CHECK: msr trcacatr0, x15 // encoding: [0x4f,0x20,0x11,0xd5] -// CHECK: msr trcacatr1, x13 // encoding: [0x4d,0x22,0x11,0xd5] -// CHECK: msr trcacatr2, x8 // encoding: [0x48,0x24,0x11,0xd5] -// CHECK: msr trcacatr3, x1 // encoding: [0x41,0x26,0x11,0xd5] -// CHECK: msr trcacatr4, x11 // encoding: [0x4b,0x28,0x11,0xd5] -// CHECK: msr trcacatr5, x8 // encoding: [0x48,0x2a,0x11,0xd5] -// CHECK: msr trcacatr6, x24 // encoding: [0x58,0x2c,0x11,0xd5] -// CHECK: msr trcacatr7, x6 // encoding: [0x46,0x2e,0x11,0xd5] -// CHECK: msr trcacatr8, x23 // encoding: [0x77,0x20,0x11,0xd5] -// CHECK: msr trcacatr9, x5 // encoding: [0x65,0x22,0x11,0xd5] -// CHECK: msr trcacatr10, x11 // encoding: [0x6b,0x24,0x11,0xd5] -// CHECK: msr trcacatr11, x11 // encoding: [0x6b,0x26,0x11,0xd5] -// CHECK: msr trcacatr12, x3 // encoding: [0x63,0x28,0x11,0xd5] -// CHECK: msr trcacatr13, x28 // encoding: [0x7c,0x2a,0x11,0xd5] -// CHECK: msr trcacatr14, x25 // encoding: [0x79,0x2c,0x11,0xd5] -// CHECK: msr trcacatr15, x4 // encoding: [0x64,0x2e,0x11,0xd5] -// CHECK: msr trcdvcvr0, x6 // encoding: [0x86,0x20,0x11,0xd5] -// CHECK: msr trcdvcvr1, x3 // encoding: [0x83,0x24,0x11,0xd5] -// CHECK: msr trcdvcvr2, x5 // encoding: [0x85,0x28,0x11,0xd5] -// CHECK: msr trcdvcvr3, x11 // encoding: [0x8b,0x2c,0x11,0xd5] -// CHECK: msr trcdvcvr4, x9 // encoding: [0xa9,0x20,0x11,0xd5] -// CHECK: msr trcdvcvr5, x14 // encoding: [0xae,0x24,0x11,0xd5] -// CHECK: msr trcdvcvr6, x10 // encoding: [0xaa,0x28,0x11,0xd5] -// CHECK: msr trcdvcvr7, x12 // encoding: [0xac,0x2c,0x11,0xd5] -// CHECK: msr trcdvcmr0, x8 // encoding: [0xc8,0x20,0x11,0xd5] -// CHECK: msr trcdvcmr1, x8 // encoding: [0xc8,0x24,0x11,0xd5] -// CHECK: msr trcdvcmr2, x22 // encoding: [0xd6,0x28,0x11,0xd5] -// CHECK: msr trcdvcmr3, x22 // encoding: [0xd6,0x2c,0x11,0xd5] -// CHECK: msr trcdvcmr4, x5 // encoding: [0xe5,0x20,0x11,0xd5] -// CHECK: msr trcdvcmr5, x16 // encoding: [0xf0,0x24,0x11,0xd5] -// CHECK: msr trcdvcmr6, x27 // encoding: [0xfb,0x28,0x11,0xd5] -// CHECK: msr trcdvcmr7, x21 // encoding: [0xf5,0x2c,0x11,0xd5] -// CHECK: msr trccidcvr0, x8 // encoding: [0x08,0x30,0x11,0xd5] -// CHECK: msr trccidcvr1, x6 // encoding: [0x06,0x32,0x11,0xd5] -// CHECK: msr trccidcvr2, x9 // encoding: [0x09,0x34,0x11,0xd5] -// CHECK: msr trccidcvr3, x8 // encoding: [0x08,0x36,0x11,0xd5] -// CHECK: msr trccidcvr4, x3 // encoding: [0x03,0x38,0x11,0xd5] -// CHECK: msr trccidcvr5, x21 // encoding: [0x15,0x3a,0x11,0xd5] -// CHECK: msr trccidcvr6, x12 // encoding: [0x0c,0x3c,0x11,0xd5] -// CHECK: msr trccidcvr7, x7 // encoding: [0x07,0x3e,0x11,0xd5] -// CHECK: msr trcvmidcvr0, x4 // encoding: [0x24,0x30,0x11,0xd5] -// CHECK: msr trcvmidcvr1, x3 // encoding: [0x23,0x32,0x11,0xd5] -// CHECK: msr trcvmidcvr2, x9 // encoding: [0x29,0x34,0x11,0xd5] -// CHECK: msr trcvmidcvr3, x17 // encoding: [0x31,0x36,0x11,0xd5] -// CHECK: msr trcvmidcvr4, x14 // encoding: [0x2e,0x38,0x11,0xd5] -// CHECK: msr trcvmidcvr5, x12 // encoding: [0x2c,0x3a,0x11,0xd5] -// CHECK: msr trcvmidcvr6, x10 // encoding: [0x2a,0x3c,0x11,0xd5] -// CHECK: msr trcvmidcvr7, x3 // encoding: [0x23,0x3e,0x11,0xd5] -// CHECK: msr trccidcctlr0, x14 // encoding: [0x4e,0x30,0x11,0xd5] -// CHECK: msr trccidcctlr1, x22 // encoding: [0x56,0x31,0x11,0xd5] -// CHECK: msr trcvmidcctlr0, x8 // encoding: [0x48,0x32,0x11,0xd5] -// CHECK: msr trcvmidcctlr1, x15 // encoding: [0x4f,0x33,0x11,0xd5] -// CHECK: msr trcitctrl, x1 // encoding: [0x81,0x70,0x11,0xd5] -// CHECK: msr trcclaimset, x7 // encoding: [0xc7,0x78,0x11,0xd5] -// CHECK: msr trcclaimclr, x29 // encoding: [0xdd,0x79,0x11,0xd5] +// CHECK: msr {{trcoslar|TRCOSLAR}}, x28 // encoding: [0x9c,0x10,0x11,0xd5] +// CHECK: msr {{trclar|TRCLAR}}, x14 // encoding: [0xce,0x7c,0x11,0xd5] +// CHECK: msr {{trcprgctlr|TRCPRGCTLR}}, x10 // encoding: [0x0a,0x01,0x11,0xd5] +// CHECK: msr {{trcprocselr|TRCPROCSELR}}, x27 // encoding: [0x1b,0x02,0x11,0xd5] +// CHECK: msr {{trcconfigr|TRCCONFIGR}}, x24 // encoding: [0x18,0x04,0x11,0xd5] +// CHECK: msr {{trcauxctlr|TRCAUXCTLR}}, x8 // encoding: [0x08,0x06,0x11,0xd5] +// CHECK: msr {{trceventctl0r|TRCEVENTCTL0R}}, x16 // encoding: [0x10,0x08,0x11,0xd5] +// CHECK: msr {{trceventctl1r|TRCEVENTCTL1R}}, x27 // encoding: [0x1b,0x09,0x11,0xd5] +// CHECK: msr {{trcstallctlr|TRCSTALLCTLR}}, x26 // encoding: [0x1a,0x0b,0x11,0xd5] +// CHECK: msr {{trctsctlr|TRCTSCTLR}}, x0 // encoding: [0x00,0x0c,0x11,0xd5] +// CHECK: msr {{trcsyncpr|TRCSYNCPR}}, x14 // encoding: [0x0e,0x0d,0x11,0xd5] +// CHECK: msr {{trcccctlr|TRCCCCTLR}}, x8 // encoding: [0x08,0x0e,0x11,0xd5] +// CHECK: msr {{trcbbctlr|TRCBBCTLR}}, x6 // encoding: [0x06,0x0f,0x11,0xd5] +// CHECK: msr {{trctraceidr|TRCTRACEIDR}}, x23 // encoding: [0x37,0x00,0x11,0xd5] +// CHECK: msr {{trcqctlr|TRCQCTLR}}, x5 // encoding: [0x25,0x01,0x11,0xd5] +// CHECK: msr {{trcvictlr|TRCVICTLR}}, x0 // encoding: [0x40,0x00,0x11,0xd5] +// CHECK: msr {{trcviiectlr|TRCVIIECTLR}}, x0 // encoding: [0x40,0x01,0x11,0xd5] +// CHECK: msr {{trcvissctlr|TRCVISSCTLR}}, x1 // encoding: [0x41,0x02,0x11,0xd5] +// CHECK: msr {{trcvipcssctlr|TRCVIPCSSCTLR}}, x0 // encoding: [0x40,0x03,0x11,0xd5] +// CHECK: msr {{trcvdctlr|TRCVDCTLR}}, x7 // encoding: [0x47,0x08,0x11,0xd5] +// CHECK: msr {{trcvdsacctlr|TRCVDSACCTLR}}, x18 // encoding: [0x52,0x09,0x11,0xd5] +// CHECK: msr {{trcvdarcctlr|TRCVDARCCTLR}}, x24 // encoding: [0x58,0x0a,0x11,0xd5] +// CHECK: msr {{trcseqevr0|TRCSEQEVR0}}, x28 // encoding: [0x9c,0x00,0x11,0xd5] +// CHECK: msr {{trcseqevr1|TRCSEQEVR1}}, x21 // encoding: [0x95,0x01,0x11,0xd5] +// CHECK: msr {{trcseqevr2|TRCSEQEVR2}}, x16 // encoding: [0x90,0x02,0x11,0xd5] +// CHECK: msr {{trcseqrstevr|TRCSEQRSTEVR}}, x16 // encoding: [0x90,0x06,0x11,0xd5] +// CHECK: msr {{trcseqstr|TRCSEQSTR}}, x25 // encoding: [0x99,0x07,0x11,0xd5] +// CHECK: msr {{trcextinselr|TRCEXTINSELR}}, x29 // encoding: [0x9d,0x08,0x11,0xd5] +// CHECK: msr {{trccntrldvr0|TRCCNTRLDVR0}}, x20 // encoding: [0xb4,0x00,0x11,0xd5] +// CHECK: msr {{trccntrldvr1|TRCCNTRLDVR1}}, x20 // encoding: [0xb4,0x01,0x11,0xd5] +// CHECK: msr {{trccntrldvr2|TRCCNTRLDVR2}}, x22 // encoding: [0xb6,0x02,0x11,0xd5] +// CHECK: msr {{trccntrldvr3|TRCCNTRLDVR3}}, x12 // encoding: [0xac,0x03,0x11,0xd5] +// CHECK: msr {{trccntctlr0|TRCCNTCTLR0}}, x20 // encoding: [0xb4,0x04,0x11,0xd5] +// CHECK: msr {{trccntctlr1|TRCCNTCTLR1}}, x4 // encoding: [0xa4,0x05,0x11,0xd5] +// CHECK: msr {{trccntctlr2|TRCCNTCTLR2}}, x8 // encoding: [0xa8,0x06,0x11,0xd5] +// CHECK: msr {{trccntctlr3|TRCCNTCTLR3}}, x16 // encoding: [0xb0,0x07,0x11,0xd5] +// CHECK: msr {{trccntvr0|TRCCNTVR0}}, x5 // encoding: [0xa5,0x08,0x11,0xd5] +// CHECK: msr {{trccntvr1|TRCCNTVR1}}, x27 // encoding: [0xbb,0x09,0x11,0xd5] +// CHECK: msr {{trccntvr2|TRCCNTVR2}}, x21 // encoding: [0xb5,0x0a,0x11,0xd5] +// CHECK: msr {{trccntvr3|TRCCNTVR3}}, x8 // encoding: [0xa8,0x0b,0x11,0xd5] +// CHECK: msr {{trcimspec0|TRCIMSPEC0}}, x6 // encoding: [0xe6,0x00,0x11,0xd5] +// CHECK: msr {{trcimspec1|TRCIMSPEC1}}, x27 // encoding: [0xfb,0x01,0x11,0xd5] +// CHECK: msr {{trcimspec2|TRCIMSPEC2}}, x23 // encoding: [0xf7,0x02,0x11,0xd5] +// CHECK: msr {{trcimspec3|TRCIMSPEC3}}, x15 // encoding: [0xef,0x03,0x11,0xd5] +// CHECK: msr {{trcimspec4|TRCIMSPEC4}}, x13 // encoding: [0xed,0x04,0x11,0xd5] +// CHECK: msr {{trcimspec5|TRCIMSPEC5}}, x25 // encoding: [0xf9,0x05,0x11,0xd5] +// CHECK: msr {{trcimspec6|TRCIMSPEC6}}, x19 // encoding: [0xf3,0x06,0x11,0xd5] +// CHECK: msr {{trcimspec7|TRCIMSPEC7}}, x27 // encoding: [0xfb,0x07,0x11,0xd5] +// CHECK: msr {{trcrsctlr2|TRCRSCTLR2}}, x4 // encoding: [0x04,0x12,0x11,0xd5] +// CHECK: msr {{trcrsctlr3|TRCRSCTLR3}}, x0 // encoding: [0x00,0x13,0x11,0xd5] +// CHECK: msr {{trcrsctlr4|TRCRSCTLR4}}, x21 // encoding: [0x15,0x14,0x11,0xd5] +// CHECK: msr {{trcrsctlr5|TRCRSCTLR5}}, x8 // encoding: [0x08,0x15,0x11,0xd5] +// CHECK: msr {{trcrsctlr6|TRCRSCTLR6}}, x20 // encoding: [0x14,0x16,0x11,0xd5] +// CHECK: msr {{trcrsctlr7|TRCRSCTLR7}}, x11 // encoding: [0x0b,0x17,0x11,0xd5] +// CHECK: msr {{trcrsctlr8|TRCRSCTLR8}}, x18 // encoding: [0x12,0x18,0x11,0xd5] +// CHECK: msr {{trcrsctlr9|TRCRSCTLR9}}, x24 // encoding: [0x18,0x19,0x11,0xd5] +// CHECK: msr {{trcrsctlr10|TRCRSCTLR10}}, x15 // encoding: [0x0f,0x1a,0x11,0xd5] +// CHECK: msr {{trcrsctlr11|TRCRSCTLR11}}, x21 // encoding: [0x15,0x1b,0x11,0xd5] +// CHECK: msr {{trcrsctlr12|TRCRSCTLR12}}, x4 // encoding: [0x04,0x1c,0x11,0xd5] +// CHECK: msr {{trcrsctlr13|TRCRSCTLR13}}, x28 // encoding: [0x1c,0x1d,0x11,0xd5] +// CHECK: msr {{trcrsctlr14|TRCRSCTLR14}}, x3 // encoding: [0x03,0x1e,0x11,0xd5] +// CHECK: msr {{trcrsctlr15|TRCRSCTLR15}}, x20 // encoding: [0x14,0x1f,0x11,0xd5] +// CHECK: msr {{trcrsctlr16|TRCRSCTLR16}}, x12 // encoding: [0x2c,0x10,0x11,0xd5] +// CHECK: msr {{trcrsctlr17|TRCRSCTLR17}}, x17 // encoding: [0x31,0x11,0x11,0xd5] +// CHECK: msr {{trcrsctlr18|TRCRSCTLR18}}, x10 // encoding: [0x2a,0x12,0x11,0xd5] +// CHECK: msr {{trcrsctlr19|TRCRSCTLR19}}, x11 // encoding: [0x2b,0x13,0x11,0xd5] +// CHECK: msr {{trcrsctlr20|TRCRSCTLR20}}, x3 // encoding: [0x23,0x14,0x11,0xd5] +// CHECK: msr {{trcrsctlr21|TRCRSCTLR21}}, x18 // encoding: [0x32,0x15,0x11,0xd5] +// CHECK: msr {{trcrsctlr22|TRCRSCTLR22}}, x26 // encoding: [0x3a,0x16,0x11,0xd5] +// CHECK: msr {{trcrsctlr23|TRCRSCTLR23}}, x5 // encoding: [0x25,0x17,0x11,0xd5] +// CHECK: msr {{trcrsctlr24|TRCRSCTLR24}}, x25 // encoding: [0x39,0x18,0x11,0xd5] +// CHECK: msr {{trcrsctlr25|TRCRSCTLR25}}, x5 // encoding: [0x25,0x19,0x11,0xd5] +// CHECK: msr {{trcrsctlr26|TRCRSCTLR26}}, x4 // encoding: [0x24,0x1a,0x11,0xd5] +// CHECK: msr {{trcrsctlr27|TRCRSCTLR27}}, x20 // encoding: [0x34,0x1b,0x11,0xd5] +// CHECK: msr {{trcrsctlr28|TRCRSCTLR28}}, x5 // encoding: [0x25,0x1c,0x11,0xd5] +// CHECK: msr {{trcrsctlr29|TRCRSCTLR29}}, x10 // encoding: [0x2a,0x1d,0x11,0xd5] +// CHECK: msr {{trcrsctlr30|TRCRSCTLR30}}, x24 // encoding: [0x38,0x1e,0x11,0xd5] +// CHECK: msr {{trcrsctlr31|TRCRSCTLR31}}, x20 // encoding: [0x34,0x1f,0x11,0xd5] +// CHECK: msr {{trcssccr0|TRCSSCCR0}}, x23 // encoding: [0x57,0x10,0x11,0xd5] +// CHECK: msr {{trcssccr1|TRCSSCCR1}}, x27 // encoding: [0x5b,0x11,0x11,0xd5] +// CHECK: msr {{trcssccr2|TRCSSCCR2}}, x27 // encoding: [0x5b,0x12,0x11,0xd5] +// CHECK: msr {{trcssccr3|TRCSSCCR3}}, x6 // encoding: [0x46,0x13,0x11,0xd5] +// CHECK: msr {{trcssccr4|TRCSSCCR4}}, x3 // encoding: [0x43,0x14,0x11,0xd5] +// CHECK: msr {{trcssccr5|TRCSSCCR5}}, x12 // encoding: [0x4c,0x15,0x11,0xd5] +// CHECK: msr {{trcssccr6|TRCSSCCR6}}, x7 // encoding: [0x47,0x16,0x11,0xd5] +// CHECK: msr {{trcssccr7|TRCSSCCR7}}, x6 // encoding: [0x46,0x17,0x11,0xd5] +// CHECK: msr {{trcsscsr0|TRCSSCSR0}}, x20 // encoding: [0x54,0x18,0x11,0xd5] +// CHECK: msr {{trcsscsr1|TRCSSCSR1}}, x17 // encoding: [0x51,0x19,0x11,0xd5] +// CHECK: msr {{trcsscsr2|TRCSSCSR2}}, x11 // encoding: [0x4b,0x1a,0x11,0xd5] +// CHECK: msr {{trcsscsr3|TRCSSCSR3}}, x4 // encoding: [0x44,0x1b,0x11,0xd5] +// CHECK: msr {{trcsscsr4|TRCSSCSR4}}, x14 // encoding: [0x4e,0x1c,0x11,0xd5] +// CHECK: msr {{trcsscsr5|TRCSSCSR5}}, x22 // encoding: [0x56,0x1d,0x11,0xd5] +// CHECK: msr {{trcsscsr6|TRCSSCSR6}}, x3 // encoding: [0x43,0x1e,0x11,0xd5] +// CHECK: msr {{trcsscsr7|TRCSSCSR7}}, x11 // encoding: [0x4b,0x1f,0x11,0xd5] +// CHECK: msr {{trcsspcicr0|TRCSSPCICR0}}, x2 // encoding: [0x62,0x10,0x11,0xd5] +// CHECK: msr {{trcsspcicr1|TRCSSPCICR1}}, x3 // encoding: [0x63,0x11,0x11,0xd5] +// CHECK: msr {{trcsspcicr2|TRCSSPCICR2}}, x5 // encoding: [0x65,0x12,0x11,0xd5] +// CHECK: msr {{trcsspcicr3|TRCSSPCICR3}}, x7 // encoding: [0x67,0x13,0x11,0xd5] +// CHECK: msr {{trcsspcicr4|TRCSSPCICR4}}, x11 // encoding: [0x6b,0x14,0x11,0xd5] +// CHECK: msr {{trcsspcicr5|TRCSSPCICR5}}, x13 // encoding: [0x6d,0x15,0x11,0xd5] +// CHECK: msr {{trcsspcicr6|TRCSSPCICR6}}, x17 // encoding: [0x71,0x16,0x11,0xd5] +// CHECK: msr {{trcsspcicr7|TRCSSPCICR7}}, x23 // encoding: [0x77,0x17,0x11,0xd5] +// CHECK: msr {{trcpdcr|TRCPDCR}}, x3 // encoding: [0x83,0x14,0x11,0xd5] +// CHECK: msr {{trcacvr0|TRCACVR0}}, x6 // encoding: [0x06,0x20,0x11,0xd5] +// CHECK: msr {{trcacvr1|TRCACVR1}}, x20 // encoding: [0x14,0x22,0x11,0xd5] +// CHECK: msr {{trcacvr2|TRCACVR2}}, x25 // encoding: [0x19,0x24,0x11,0xd5] +// CHECK: msr {{trcacvr3|TRCACVR3}}, x1 // encoding: [0x01,0x26,0x11,0xd5] +// CHECK: msr {{trcacvr4|TRCACVR4}}, x28 // encoding: [0x1c,0x28,0x11,0xd5] +// CHECK: msr {{trcacvr5|TRCACVR5}}, x15 // encoding: [0x0f,0x2a,0x11,0xd5] +// CHECK: msr {{trcacvr6|TRCACVR6}}, x25 // encoding: [0x19,0x2c,0x11,0xd5] +// CHECK: msr {{trcacvr7|TRCACVR7}}, x12 // encoding: [0x0c,0x2e,0x11,0xd5] +// CHECK: msr {{trcacvr8|TRCACVR8}}, x5 // encoding: [0x25,0x20,0x11,0xd5] +// CHECK: msr {{trcacvr9|TRCACVR9}}, x25 // encoding: [0x39,0x22,0x11,0xd5] +// CHECK: msr {{trcacvr10|TRCACVR10}}, x13 // encoding: [0x2d,0x24,0x11,0xd5] +// CHECK: msr {{trcacvr11|TRCACVR11}}, x10 // encoding: [0x2a,0x26,0x11,0xd5] +// CHECK: msr {{trcacvr12|TRCACVR12}}, x19 // encoding: [0x33,0x28,0x11,0xd5] +// CHECK: msr {{trcacvr13|TRCACVR13}}, x10 // encoding: [0x2a,0x2a,0x11,0xd5] +// CHECK: msr {{trcacvr14|TRCACVR14}}, x19 // encoding: [0x33,0x2c,0x11,0xd5] +// CHECK: msr {{trcacvr15|TRCACVR15}}, x2 // encoding: [0x22,0x2e,0x11,0xd5] +// CHECK: msr {{trcacatr0|TRCACATR0}}, x15 // encoding: [0x4f,0x20,0x11,0xd5] +// CHECK: msr {{trcacatr1|TRCACATR1}}, x13 // encoding: [0x4d,0x22,0x11,0xd5] +// CHECK: msr {{trcacatr2|TRCACATR2}}, x8 // encoding: [0x48,0x24,0x11,0xd5] +// CHECK: msr {{trcacatr3|TRCACATR3}}, x1 // encoding: [0x41,0x26,0x11,0xd5] +// CHECK: msr {{trcacatr4|TRCACATR4}}, x11 // encoding: [0x4b,0x28,0x11,0xd5] +// CHECK: msr {{trcacatr5|TRCACATR5}}, x8 // encoding: [0x48,0x2a,0x11,0xd5] +// CHECK: msr {{trcacatr6|TRCACATR6}}, x24 // encoding: [0x58,0x2c,0x11,0xd5] +// CHECK: msr {{trcacatr7|TRCACATR7}}, x6 // encoding: [0x46,0x2e,0x11,0xd5] +// CHECK: msr {{trcacatr8|TRCACATR8}}, x23 // encoding: [0x77,0x20,0x11,0xd5] +// CHECK: msr {{trcacatr9|TRCACATR9}}, x5 // encoding: [0x65,0x22,0x11,0xd5] +// CHECK: msr {{trcacatr10|TRCACATR10}}, x11 // encoding: [0x6b,0x24,0x11,0xd5] +// CHECK: msr {{trcacatr11|TRCACATR11}}, x11 // encoding: [0x6b,0x26,0x11,0xd5] +// CHECK: msr {{trcacatr12|TRCACATR12}}, x3 // encoding: [0x63,0x28,0x11,0xd5] +// CHECK: msr {{trcacatr13|TRCACATR13}}, x28 // encoding: [0x7c,0x2a,0x11,0xd5] +// CHECK: msr {{trcacatr14|TRCACATR14}}, x25 // encoding: [0x79,0x2c,0x11,0xd5] +// CHECK: msr {{trcacatr15|TRCACATR15}}, x4 // encoding: [0x64,0x2e,0x11,0xd5] +// CHECK: msr {{trcdvcvr0|TRCDVCVR0}}, x6 // encoding: [0x86,0x20,0x11,0xd5] +// CHECK: msr {{trcdvcvr1|TRCDVCVR1}}, x3 // encoding: [0x83,0x24,0x11,0xd5] +// CHECK: msr {{trcdvcvr2|TRCDVCVR2}}, x5 // encoding: [0x85,0x28,0x11,0xd5] +// CHECK: msr {{trcdvcvr3|TRCDVCVR3}}, x11 // encoding: [0x8b,0x2c,0x11,0xd5] +// CHECK: msr {{trcdvcvr4|TRCDVCVR4}}, x9 // encoding: [0xa9,0x20,0x11,0xd5] +// CHECK: msr {{trcdvcvr5|TRCDVCVR5}}, x14 // encoding: [0xae,0x24,0x11,0xd5] +// CHECK: msr {{trcdvcvr6|TRCDVCVR6}}, x10 // encoding: [0xaa,0x28,0x11,0xd5] +// CHECK: msr {{trcdvcvr7|TRCDVCVR7}}, x12 // encoding: [0xac,0x2c,0x11,0xd5] +// CHECK: msr {{trcdvcmr0|TRCDVCMR0}}, x8 // encoding: [0xc8,0x20,0x11,0xd5] +// CHECK: msr {{trcdvcmr1|TRCDVCMR1}}, x8 // encoding: [0xc8,0x24,0x11,0xd5] +// CHECK: msr {{trcdvcmr2|TRCDVCMR2}}, x22 // encoding: [0xd6,0x28,0x11,0xd5] +// CHECK: msr {{trcdvcmr3|TRCDVCMR3}}, x22 // encoding: [0xd6,0x2c,0x11,0xd5] +// CHECK: msr {{trcdvcmr4|TRCDVCMR4}}, x5 // encoding: [0xe5,0x20,0x11,0xd5] +// CHECK: msr {{trcdvcmr5|TRCDVCMR5}}, x16 // encoding: [0xf0,0x24,0x11,0xd5] +// CHECK: msr {{trcdvcmr6|TRCDVCMR6}}, x27 // encoding: [0xfb,0x28,0x11,0xd5] +// CHECK: msr {{trcdvcmr7|TRCDVCMR7}}, x21 // encoding: [0xf5,0x2c,0x11,0xd5] +// CHECK: msr {{trccidcvr0|TRCCIDCVR0}}, x8 // encoding: [0x08,0x30,0x11,0xd5] +// CHECK: msr {{trccidcvr1|TRCCIDCVR1}}, x6 // encoding: [0x06,0x32,0x11,0xd5] +// CHECK: msr {{trccidcvr2|TRCCIDCVR2}}, x9 // encoding: [0x09,0x34,0x11,0xd5] +// CHECK: msr {{trccidcvr3|TRCCIDCVR3}}, x8 // encoding: [0x08,0x36,0x11,0xd5] +// CHECK: msr {{trccidcvr4|TRCCIDCVR4}}, x3 // encoding: [0x03,0x38,0x11,0xd5] +// CHECK: msr {{trccidcvr5|TRCCIDCVR5}}, x21 // encoding: [0x15,0x3a,0x11,0xd5] +// CHECK: msr {{trccidcvr6|TRCCIDCVR6}}, x12 // encoding: [0x0c,0x3c,0x11,0xd5] +// CHECK: msr {{trccidcvr7|TRCCIDCVR7}}, x7 // encoding: [0x07,0x3e,0x11,0xd5] +// CHECK: msr {{trcvmidcvr0|TRCVMIDCVR0}}, x4 // encoding: [0x24,0x30,0x11,0xd5] +// CHECK: msr {{trcvmidcvr1|TRCVMIDCVR1}}, x3 // encoding: [0x23,0x32,0x11,0xd5] +// CHECK: msr {{trcvmidcvr2|TRCVMIDCVR2}}, x9 // encoding: [0x29,0x34,0x11,0xd5] +// CHECK: msr {{trcvmidcvr3|TRCVMIDCVR3}}, x17 // encoding: [0x31,0x36,0x11,0xd5] +// CHECK: msr {{trcvmidcvr4|TRCVMIDCVR4}}, x14 // encoding: [0x2e,0x38,0x11,0xd5] +// CHECK: msr {{trcvmidcvr5|TRCVMIDCVR5}}, x12 // encoding: [0x2c,0x3a,0x11,0xd5] +// CHECK: msr {{trcvmidcvr6|TRCVMIDCVR6}}, x10 // encoding: [0x2a,0x3c,0x11,0xd5] +// CHECK: msr {{trcvmidcvr7|TRCVMIDCVR7}}, x3 // encoding: [0x23,0x3e,0x11,0xd5] +// CHECK: msr {{trccidcctlr0|TRCCIDCCTLR0}}, x14 // encoding: [0x4e,0x30,0x11,0xd5] +// CHECK: msr {{trccidcctlr1|TRCCIDCCTLR1}}, x22 // encoding: [0x56,0x31,0x11,0xd5] +// CHECK: msr {{trcvmidcctlr0|TRCVMIDCCTLR0}}, x8 // encoding: [0x48,0x32,0x11,0xd5] +// CHECK: msr {{trcvmidcctlr1|TRCVMIDCCTLR1}}, x15 // encoding: [0x4f,0x33,0x11,0xd5] +// CHECK: msr {{trcitctrl|TRCITCTRL}}, x1 // encoding: [0x81,0x70,0x11,0xd5] +// CHECK: msr {{trcclaimset|TRCCLAIMSET}}, x7 // encoding: [0xc7,0x78,0x11,0xd5] +// CHECK: msr {{trcclaimclr|TRCCLAIMCLR}}, x29 // encoding: [0xdd,0x79,0x11,0xd5] |