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| author | Jack Carter <jcarter@mips.com> | 2013-01-17 00:28:20 +0000 |
|---|---|---|
| committer | Jack Carter <jcarter@mips.com> | 2013-01-17 00:28:20 +0000 |
| commit | c147b678206db510336ee95c3b55dc9c0ff19595 (patch) | |
| tree | 149a8e0783cd344d4681ba19348a00a07a60e7c2 /test/MC | |
| parent | e06bfe8d90aba9b6adf00ccc20a0144e90938b00 (diff) | |
| download | external_llvm-c147b678206db510336ee95c3b55dc9c0ff19595.zip external_llvm-c147b678206db510336ee95c3b55dc9c0ff19595.tar.gz external_llvm-c147b678206db510336ee95c3b55dc9c0ff19595.tar.bz2 | |
This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
| -rw-r--r-- | test/MC/Disassembler/Mips/mips32.txt | 6 | ||||
| -rw-r--r-- | test/MC/Disassembler/Mips/mips32_le.txt | 6 | ||||
| -rw-r--r-- | test/MC/Mips/mips-alu-instructions.s | 5 | ||||
| -rw-r--r-- | test/MC/Mips/mips64-alu-instructions.s | 6 |
4 files changed, 23 insertions, 0 deletions
diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt index a193319..7022486 100644 --- a/test/MC/Disassembler/Mips/mips32.txt +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -404,3 +404,9 @@ # CHECK: xori $9, $6, 17767 0x38 0xc9 0x45 0x67 + +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop +0x7c 0x05 0xe8 0x3b diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index 08b3672..48fa8e2 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -404,3 +404,9 @@ # CHECK: xori $9, $6, 17767 0x67 0x45 0xc9 0x38 + +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop +0x3b 0xe8 0x05 0x7c diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s index ee2a9a0..52fd900 100644 --- a/test/MC/Mips/mips-alu-instructions.s +++ b/test/MC/Mips/mips-alu-instructions.s @@ -81,6 +81,10 @@ # CHECK: sub $6, $zero, $7 # encoding: [0x22,0x30,0x07,0x00] # CHECK: subu $6, $zero, $7 # encoding: [0x23,0x30,0x07,0x00] # CHECK: addu $7, $8, $zero # encoding: [0x21,0x38,0x00,0x01] +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c] add $9,$6,$7 add $9,$6,17767 addu $9,$6,-15001 @@ -98,3 +102,4 @@ neg $6,$7 negu $6,$7 move $7,$8 + rdhwr $5, $29 diff --git a/test/MC/Mips/mips64-alu-instructions.s b/test/MC/Mips/mips64-alu-instructions.s index a77ed43..d30ddee 100644 --- a/test/MC/Mips/mips64-alu-instructions.s +++ b/test/MC/Mips/mips64-alu-instructions.s @@ -78,6 +78,11 @@ # CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00] # CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00] # CHECK: daddu $7, $8, $zero # encoding: [0x2d,0x38,0x00,0x01] +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c] + dadd $9,$6,$7 dadd $9,$6,17767 daddu $9,$6,-15001 @@ -92,3 +97,4 @@ multu $3,$5 dsubu $4,$3,$5 move $7,$8 + rdhwr $5, $29 |