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authorJyotsna Verma <jverma@codeaurora.org>2013-05-14 18:54:06 +0000
committerJyotsna Verma <jverma@codeaurora.org>2013-05-14 18:54:06 +0000
commita29a8965e206e689d292d7f2e42f2548770e30d3 (patch)
tree138b51a358b8faf8b5ad4c153e4e653590ace1a2 /test
parentf276c70bb8ff25e7c0ef13e9afc59623a3c135ba (diff)
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Hexagon: Pass to replace tranfer/copy instructions into combine instruction
where possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181817 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/Hexagon/args.ll9
-rw-r--r--test/CodeGen/Hexagon/tfr-to-combine.ll35
2 files changed, 38 insertions, 6 deletions
diff --git a/test/CodeGen/Hexagon/args.ll b/test/CodeGen/Hexagon/args.ll
index f8c9e44..aea4ffe 100644
--- a/test/CodeGen/Hexagon/args.ll
+++ b/test/CodeGen/Hexagon/args.ll
@@ -1,11 +1,8 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched -disable-hexagon-misched < %s | FileCheck %s
; CHECK: memw(r29{{ *}}+{{ *}}#0){{ *}}={{ *}}#7
-; CHECK: r0 = #1
-; CHECK: r1 = #2
-; CHECK: r2 = #3
-; CHECK: r3 = #4
-; CHECK: r4 = #5
-; CHECK: r5 = #6
+; CHECK: r1:0 = combine(#2, #1)
+; CHECK: r3:2 = combine(#4, #3)
+; CHECK: r5:4 = combine(#6, #5)
define void @foo() nounwind {
diff --git a/test/CodeGen/Hexagon/tfr-to-combine.ll b/test/CodeGen/Hexagon/tfr-to-combine.ll
new file mode 100644
index 0000000..e3057cd
--- /dev/null
+++ b/test/CodeGen/Hexagon/tfr-to-combine.ll
@@ -0,0 +1,35 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s
+
+; Check that we combine TFRs and TFRIs into COMBINEs.
+
+@a = external global i16
+@b = external global i16
+@c = external global i16
+
+; Function Attrs: nounwind
+define i64 @test1() #0 {
+; CHECK: combine(#10, #0)
+entry:
+ store i16 0, i16* @a, align 2
+ store i16 10, i16* @b, align 2
+ ret i64 10
+}
+
+; Function Attrs: nounwind
+define i64 @test2() #0 {
+; CHECK: combine(#0, r{{[0-9]+}})
+entry:
+ store i16 0, i16* @a, align 2
+ %0 = load i16* @c, align 2
+ %conv2 = zext i16 %0 to i64
+ ret i64 %conv2
+}
+
+; Function Attrs: nounwind
+define i64 @test4() #0 {
+; CHECK: combine(#0, ##100)
+entry:
+ store i16 100, i16* @b, align 2
+ store i16 0, i16* @a, align 2
+ ret i64 0
+}