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| author | Mihai Popa <mihail.popa@gmail.com> | 2013-05-13 14:10:04 +0000 |
|---|---|---|
| committer | Mihai Popa <mihail.popa@gmail.com> | 2013-05-13 14:10:04 +0000 |
| commit | f86e436fb95670ed110818fefa403f21ae104639 (patch) | |
| tree | 11d3a6071ea91ee9dfb1dbb09c606eb103dc567d /test | |
| parent | d26c93d3a8a484c5b42f06163ae5de787f0ac276 (diff) | |
| download | external_llvm-f86e436fb95670ed110818fefa403f21ae104639.zip external_llvm-f86e436fb95670ed110818fefa403f21ae104639.tar.gz external_llvm-f86e436fb95670ed110818fefa403f21ae104639.tar.bz2 | |
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181705 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 14 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/basic-arm-instructions.txt | 4 |
2 files changed, 15 insertions, 3 deletions
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 71b5b5d..5227bdd 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1062,10 +1062,18 @@ Lforward: @ MRC/MRC2 @------------------------------------------------------------------------------ mrc p14, #0, r1, c1, c2, #4 + mrc p15, #7, apsr_nzcv, c15, c6, #6 + mrc p15, #7, pc, c15, c6, #6 mrc2 p14, #0, r1, c1, c2, #4 - -@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee] -@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe] + mrc2 p10, #7, apsr_nzcv, c15, c0, #1 + mrc2 p10, #7, pc, c15, c0, #1 + +@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee] +@ CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0xee] +@ CHECK: mrc p15, #7, pc, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0xee] +@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe] +@ CHECK: mrc2 p10, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xfa,0xff,0xfe] +@ CHECK: mrc2 p10, #7, pc, c15, c0, #1 @ encoding: [0x30,0xfa,0xff,0xfe] @------------------------------------------------------------------------------ @ MRRC/MRRC2 diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index 9f63e1e..c92322e 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -757,10 +757,14 @@ # MRC/MRC2 #------------------------------------------------------------------------------ # CHECK: mrc p14, #0, r1, c1, c2, #4 +# CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 # CHECK: mrc2 p14, #0, r1, c1, c2, #4 +# CHECK: mrc2 p9, #7, apsr_nzcv, c15, c0, #1 0x92 0x1e 0x11 0xee +0xd6 0xff 0xff 0xee 0x92 0x1e 0x11 0xfe +0x30 0xf9 0xff 0xfe #------------------------------------------------------------------------------ # MRRC/MRRC2 |