Add an option and stuff implementation of a dag isel emitter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23236 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 45 insertions, 0 deletions

diff --git a/utils/TableGen/DAGISelEmitter.h b/utils/TableGen/DAGISelEmitter.h
new file mode 100644
index 0000000..7b5f4f8
--- /dev/null
+++ b/utils/TableGen/DAGISelEmitter.h
@@ -0,0 +1,38 @@
+//===- DAGISelEmitter.h - Generate an instruction selector ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by Chris Lattner and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This tablegen backend emits a DAG instruction selector.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef DAGISEL_EMITTER_H
+#define DAGISEL_EMITTER_H
+
+#include "TableGenBackend.h"
+#include "CodeGenTarget.h"
+
+namespace llvm {
+
+/// InstrSelectorEmitter - The top-level class which coordinates construction
+/// and emission of the instruction selector.
+///
+class DAGISelEmitter : public TableGenBackend {
+  RecordKeeper &Records;
+  CodeGenTarget Target;
+
+public:
+  DAGISelEmitter(RecordKeeper &R) : Records(R) {}
+
+  // run - Output the isel, returning true on failure.
+  void run(std::ostream &OS) {}
+};
+
+} // End llvm namespace
+
+#endif
diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index 55ccf21..baa15eb 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -24,6 +24,7 @@
 #include "InstrInfoEmitter.h"
 #include "AsmWriterEmitter.h"
 #include "InstrSelectorEmitter.h"
+#include "DAGISelEmitter.h"
 #include <algorithm>
 #include <cstdio>
 #include <fstream>
@@ -34,6 +35,7 @@ enum ActionType {
   GenEmitter,
   GenRegisterEnums, GenRegister, GenRegisterHeader,
   GenInstrEnums, GenInstrs, GenAsmWriter, GenInstrSelector,
+  GenDAGISel,
   PrintEnums,
   Parse
 };
@@ -59,6 +61,8 @@ namespace {
                                "Generate assembly writer"),
                     clEnumValN(GenInstrSelector, "gen-instr-selector",
                                "Generate an instruction selector"),
+                    clEnumValN(GenDAGISel, "gen-dag-isel",
+                               "Generate a DAG instruction selector"),
                     clEnumValN(PrintEnums, "print-enums",
                                "Print enum values for a class"),
                     clEnumValN(Parse, "parse",
@@ -465,6 +469,9 @@ int main(int argc, char **argv) {
     case GenInstrSelector:
       InstrSelectorEmitter(Records).run(*Out);
       break;
+    case GenDAGISel:
+      DAGISelEmitter(Records).run(*Out);
+      break;
     case PrintEnums:
     {
       std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);