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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2013-03-15 22:51:13 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2013-03-15 22:51:13 +0000 |
commit | 64110ffc9eecbe999c29ac9d9f6697447a110036 (patch) | |
tree | eb9508b024f2155f69ce92062ce9d399972e189d /utils | |
parent | dfe91cefd25614bc9ac1626d67df4d5ad5d3553f (diff) | |
download | external_llvm-64110ffc9eecbe999c29ac9d9f6697447a110036.zip external_llvm-64110ffc9eecbe999c29ac9d9f6697447a110036.tar.gz external_llvm-64110ffc9eecbe999c29ac9d9f6697447a110036.tar.bz2 |
Add SchedRW as an Instruction field.
Don't require instructions to inherit Sched<...>. Sometimes it is more
convenient to say:
let SchedRW = ... in {
...
}
Which is now possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177199 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r-- | utils/TableGen/CodeGenSchedule.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/utils/TableGen/CodeGenSchedule.cpp b/utils/TableGen/CodeGenSchedule.cpp index 92408c4..0b1fb6c 100644 --- a/utils/TableGen/CodeGenSchedule.cpp +++ b/utils/TableGen/CodeGenSchedule.cpp @@ -217,7 +217,7 @@ void CodeGenSchedModels::collectSchedRW() { for (CodeGenTarget::inst_iterator I = Target.inst_begin(), E = Target.inst_end(); I != E; ++I) { Record *SchedDef = (*I)->TheDef; - if (!SchedDef->isSubClassOf("Sched")) + if (SchedDef->isValueUnset("SchedRW")) continue; RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW"); for (RecIter RWI = RWs.begin(), RWE = RWs.end(); RWI != RWE; ++RWI) { @@ -529,7 +529,7 @@ void CodeGenSchedModels::collectSchedClasses() { // instruction definition that inherits from class Sched. for (CodeGenTarget::inst_iterator I = Target.inst_begin(), E = Target.inst_end(); I != E; ++I) { - if (!(*I)->TheDef->isSubClassOf("Sched")) + if ((*I)->TheDef->isValueUnset("SchedRW")) continue; IdxVec Writes, Reads; findRWs((*I)->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); @@ -553,7 +553,7 @@ void CodeGenSchedModels::collectSchedClasses() { E = Target.inst_end(); I != E; ++I) { Record *SchedDef = (*I)->TheDef; std::string InstName = (*I)->TheDef->getName(); - if (SchedDef->isSubClassOf("Sched")) { + if (!SchedDef->isValueUnset("SchedRW")) { IdxVec Writes; IdxVec Reads; findRWs((*I)->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); @@ -584,7 +584,7 @@ void CodeGenSchedModels::collectSchedClasses() { } continue; } - if (!SchedDef->isSubClassOf("Sched") + if (SchedDef->isValueUnset("SchedRW") && (SchedDef->getValueAsDef("Itinerary")->getName() == "NoItinerary")) { dbgs() << "No machine model for " << (*I)->TheDef->getName() << '\n'; } @@ -627,7 +627,7 @@ unsigned CodeGenSchedModels::getSchedClassIdx( // If this opcode isn't mapped by the subtarget fallback to the instruction // definition's SchedRW or ItinDef values. - if (Inst.TheDef->isSubClassOf("Sched")) { + if (!Inst.TheDef->isValueUnset("SchedRW")) { RecVec RWs = Inst.TheDef->getValueAsListOfDefs("SchedRW"); return getSchedClassIdx(RWs); } @@ -719,7 +719,7 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) { // class because that is the fall-back class for other processors. Record *ItinDef = (*I)->getValueAsDef("Itinerary"); SCIdx = SchedClassIdxMap.lookup(ItinDef->getName()); - if (!SCIdx && (*I)->isSubClassOf("Sched")) + if (!SCIdx && !(*I)->isValueUnset("SchedRW")) SCIdx = getSchedClassIdx((*I)->getValueAsListOfDefs("SchedRW")); } unsigned CIdx = 0, CEnd = ClassInstrs.size(); |