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author | Andrew Trick <atrick@apple.com> | 2012-06-22 03:58:51 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2012-06-22 03:58:51 +0000 |
commit | d85934b3e5a96040e199e1b098705eb56cde584a (patch) | |
tree | d4fc16ec73599d4d8860172ba7adec80357e1d3c /utils | |
parent | e208c491726bb1efbfc4fc05a9f73ad808432979 (diff) | |
download | external_llvm-d85934b3e5a96040e199e1b098705eb56cde584a.zip external_llvm-d85934b3e5a96040e199e1b098705eb56cde584a.tar.gz external_llvm-d85934b3e5a96040e199e1b098705eb56cde584a.tar.bz2 |
Use "NoItineraries" for processors with no itineraries.
This makes it explicit when ScoreboardHazardRecognizer will be used.
"GenericItineraries" would only make sense if it contained real
itinerary values and still required ScoreboardHazardRecognizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158963 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r-- | utils/TableGen/SubtargetEmitter.cpp | 78 |
1 files changed, 41 insertions, 37 deletions
diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp index 870b8ad..19b0550 100644 --- a/utils/TableGen/SubtargetEmitter.cpp +++ b/utils/TableGen/SubtargetEmitter.cpp @@ -422,15 +422,18 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, // Get processor itinerary name const std::string &Name = Proc->getName(); - // Skip default - if (Name == "NoItineraries") continue; - - // Create and expand processor itinerary to cover all itinerary classes - std::vector<InstrItinerary> ItinList; - ItinList.resize(NItinClasses); - // Get itinerary data list std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID"); + std::vector<InstrItinerary> ItinList; + + // Add an empty itinerary. + if (ItinDataList.empty()) { + ProcList.push_back(ItinList); + continue; + } + + // Expand processor itinerary to cover all itinerary classes + ItinList.resize(NItinClasses); // For each itinerary data for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) { @@ -559,8 +562,6 @@ EmitProcessorData(raw_ostream &OS, const std::string &Name = Itin->getName(); // Skip default - if (Name == "NoItineraries") continue; - // Begin processor itinerary properties OS << "\n"; OS << "static const llvm::InstrItineraryProps " << Name << "Props(\n"; @@ -570,42 +571,45 @@ EmitProcessorData(raw_ostream &OS, EmitItineraryProp(OS, Itin, "HighLatency", ' '); OS << ");\n"; - // Begin processor itinerary table - OS << "\n"; - OS << "static const llvm::InstrItinerary " << Name << "Entries" - << "[] = {\n"; - // For each itinerary class std::vector<InstrItinerary> &ItinList = *ProcListIter++; - assert(ItinList.size() == ItinClassList.size() && "bad itinerary"); - for (unsigned j = 0, M = ItinList.size(); j < M; ++j) { - InstrItinerary &Intinerary = ItinList[j]; - - // Emit in the form of - // { firstStage, lastStage, firstCycle, lastCycle } // index - if (Intinerary.FirstStage == 0) { - OS << " { 1, 0, 0, 0, 0 }"; - } else { - OS << " { " << - Intinerary.NumMicroOps << ", " << - Intinerary.FirstStage << ", " << - Intinerary.LastStage << ", " << - Intinerary.FirstOperandCycle << ", " << - Intinerary.LastOperandCycle << " }"; - } + if (!ItinList.empty()) { + assert(ItinList.size() == ItinClassList.size() && "bad itinerary"); - OS << ", // " << j << " " << ItinClassList[j]->getName() << "\n"; + // Begin processor itinerary table + OS << "\n"; + OS << "static const llvm::InstrItinerary " << Name << "Entries" + << "[] = {\n"; + + for (unsigned j = 0, M = ItinList.size(); j < M; ++j) { + InstrItinerary &Intinerary = ItinList[j]; + + // Emit in the form of + // { firstStage, lastStage, firstCycle, lastCycle } // index + if (Intinerary.FirstStage == 0) { + OS << " { 1, 0, 0, 0, 0 }"; + } else { + OS << " { " << + Intinerary.NumMicroOps << ", " << + Intinerary.FirstStage << ", " << + Intinerary.LastStage << ", " << + Intinerary.FirstOperandCycle << ", " << + Intinerary.LastOperandCycle << " }"; + } + OS << ", // " << j << " " << ItinClassList[j]->getName() << "\n"; + } + // End processor itinerary table + OS << " { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n"; + OS << "};\n"; } - - // End processor itinerary table - OS << " { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n"; - OS << "};\n"; - OS << '\n'; OS << "static const llvm::InstrItinerarySubtargetValue " << Name << " = {\n"; OS << " &" << Name << "Props,\n"; - OS << " " << Name << "Entries\n"; + if (ItinList.empty()) + OS << " 0\n"; + else + OS << " " << Name << "Entries\n"; OS << "};\n"; } } |