misched: Added MultiIssueItineraries.

This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 33 insertions, 1 deletions

diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp
index 986c50f..764fc88 100644
--- a/utils/TableGen/SubtargetEmitter.cpp
+++ b/utils/TableGen/SubtargetEmitter.cpp
@@ -478,6 +478,17 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS,
   OS << BypassTable;
 }
 
+void SubtargetEmitter::EmitItineraryProp(raw_ostream &OS, const Record *R,
+                                         const char *Name, char Separator) {
+  OS << "  ";
+  int V = R->getValueAsInt(Name);
+  if (V >= 0)
+    OS << V << Separator << " // " << Name;
+  else
+    OS << "DefaultItineraryProps." << Name << Separator;
+  OS << '\n';
+}
+
 //
 // EmitProcessorData - Generate data for processor itineraries.
 //
@@ -485,6 +496,8 @@ void SubtargetEmitter::
 EmitProcessorData(raw_ostream &OS,
                   std::vector<Record*> &ItinClassList,
                   std::vector<std::vector<InstrItinerary> > &ProcList) {
+  OS << "static const llvm::InstrItineraryProps " << "DefaultItineraryProps;";
+
   // Get an iterator for processor itinerary stages
   std::vector<std::vector<InstrItinerary> >::iterator
       ProcListIter = ProcList.begin();
@@ -502,9 +515,19 @@ EmitProcessorData(raw_ostream &OS,
     // Skip default
     if (Name == "NoItineraries") continue;
 
+    // Begin processor itinerary properties
+    OS << "\n";
+    OS << "static const llvm::InstrItineraryProps " << Name << "Props(\n";
+    EmitItineraryProp(OS, Itin, "IssueWidth", ',');
+    EmitItineraryProp(OS, Itin, "MinLatency", ',');
+    EmitItineraryProp(OS, Itin, "LoadLatency", ',');
+    EmitItineraryProp(OS, Itin, "HighLatency", ' ');
+    OS << ");\n";
+
     // Begin processor itinerary table
     OS << "\n";
-    OS << "static const llvm::InstrItinerary " << Name << "[] = {\n";
+    OS << "static const llvm::InstrItinerary " << Name << "Entries"
+       << "[] = {\n";
 
     // For each itinerary class
     std::vector<InstrItinerary> &ItinList = *ProcListIter++;
@@ -531,6 +554,13 @@ EmitProcessorData(raw_ostream &OS,
     // End processor itinerary table
     OS << "  { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n";
     OS << "};\n";
+
+    OS << '\n';
+    OS << "static const llvm::InstrItinerarySubtargetValue "
+       << Name << " = {\n";
+    OS << "  &" << Name << "Props,\n";
+    OS << "  " << Name << "Entries\n";
+    OS << "};\n";
   }
 }
 
diff --git a/utils/TableGen/SubtargetEmitter.h b/utils/TableGen/SubtargetEmitter.h
index ff01274..b153cde 100644
--- a/utils/TableGen/SubtargetEmitter.h
+++ b/utils/TableGen/SubtargetEmitter.h
@@ -47,6 +47,8 @@ class SubtargetEmitter : public TableGenBackend {
                      std::map<std::string, unsigned> &ItinClassesMap,
                      std::vector<Record*> &ItinClassList,
                      std::vector<std::vector<InstrItinerary> > &ProcList);
+  void EmitItineraryProp(raw_ostream &OS, const Record *R, const char *Name,
+                         char Separator);
   void EmitProcessorData(raw_ostream &OS,
                          std::vector<Record*> &ItinClassList,
                          std::vector<std::vector<InstrItinerary> > &ProcList);