diff options
26 files changed, 31 insertions, 35 deletions
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index e172edf..55619de 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -1168,7 +1168,7 @@ public: /// InVals array with legal-type return values from the call, and return /// the resulting token chain value. virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, + LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 284b984..6468679 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -5735,7 +5735,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, } SmallVector<SDValue, 4> InVals; - Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, + Chain = LowerCall(Chain, Callee, RetTy, CallConv, isVarArg, isTailCall, Outs, Ins, dl, DAG, InVals); // Verify that the target's LowerCall behaved as expected. diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 3e42be3..0c8e58a 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -895,7 +895,7 @@ void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter /// nodes. SDValue -ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, +ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index a408943..e4c32f9 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -317,7 +317,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, + LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 0bbe567..980db13 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -219,7 +219,7 @@ static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) { #include "AlphaGenCallingConv.inc" SDValue -AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee, +AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h index 0f17025..9f73d77 100644 --- a/lib/Target/Alpha/AlphaISelLowering.h +++ b/lib/Target/Alpha/AlphaISelLowering.h @@ -120,7 +120,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, + LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/lib/Target/Blackfin/BlackfinISelLowering.cpp b/lib/Target/Blackfin/BlackfinISelLowering.cpp index 269707a..0e729b8 100644 --- a/lib/Target/Blackfin/BlackfinISelLowering.cpp +++ b/lib/Target/Blackfin/BlackfinISelLowering.cpp @@ -272,6 +272,7 @@ BlackfinTargetLowering::LowerReturn(SDValue Chain, SDValue BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee, + const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/Blackfin/BlackfinISelLowering.h b/lib/Target/Blackfin/BlackfinISelLowering.h index 5f39910..147f414 100644 --- a/lib/Target/Blackfin/BlackfinISelLowering.h +++ b/lib/Target/Blackfin/BlackfinISelLowering.h @@ -63,7 +63,7 @@ namespace llvm { DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, + LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index fe0f019..b6a8fad 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -1138,7 +1138,7 @@ static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) { } SDValue -SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, +SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/CellSPU/SPUISelLowering.h b/lib/Target/CellSPU/SPUISelLowering.h index 3c51177..3625f91 100644 --- a/lib/Target/CellSPU/SPUISelLowering.h +++ b/lib/Target/CellSPU/SPUISelLowering.h @@ -156,7 +156,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, + LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp index ef81f51..d948e6f 100644 --- a/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -271,7 +271,7 @@ MSP430TargetLowering::LowerFormalArguments(SDValue Chain, } SDValue -MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee, +MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/MSP430/MSP430ISelLowering.h b/lib/Target/MSP430/MSP430ISelLowering.h index 87a790b..c4b70b1 100644 --- a/lib/Target/MSP430/MSP430ISelLowering.h +++ b/lib/Target/MSP430/MSP430ISelLowering.h @@ -153,7 +153,7 @@ namespace llvm { DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, + LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 6d932ec..4426e76 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -684,7 +684,7 @@ static bool CC_MipsO32(unsigned ValNo, EVT ValVT, /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. /// TODO: isVarArg, isTailCall. SDValue -MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, +MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index d8b453c..c8256e7 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -116,7 +116,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, + LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp index 7754a4f..d9add7f 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -1353,7 +1353,7 @@ GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain, } SDValue -PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee, +PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/PIC16/PIC16ISelLowering.h b/lib/Target/PIC16/PIC16ISelLowering.h index de14520..e67f8bc 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.h +++ b/lib/Target/PIC16/PIC16ISelLowering.h @@ -142,7 +142,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, + LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 2a4fb02..310ace8 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2674,7 +2674,7 @@ PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, } SDValue -PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, +PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index 9c390ac..4bf70b8 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -430,7 +430,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, + LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index e67002a..d5d61ea 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -250,7 +250,7 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain, } SDValue -SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, +SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h index 2ee73c1..8765de8 100644 --- a/lib/Target/Sparc/SparcISelLowering.h +++ b/lib/Target/Sparc/SparcISelLowering.h @@ -85,7 +85,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, + LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index f7405a5..8146666 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -249,6 +249,7 @@ SystemZTargetLowering::LowerFormalArguments(SDValue Chain, SDValue SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee, + const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/SystemZ/SystemZISelLowering.h b/lib/Target/SystemZ/SystemZISelLowering.h index 36ff994..ee06957 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.h +++ b/lib/Target/SystemZ/SystemZISelLowering.h @@ -124,7 +124,7 @@ namespace llvm { DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, + LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index d05de21..228244f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1778,7 +1778,7 @@ EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, } SDValue -X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, +X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, @@ -1791,8 +1791,8 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, if (isTailCall) // Check if it's really possible to do a tail call. - isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, - Outs, Ins, DAG); + isTailCall = IsEligibleForTailCallOptimization(Callee, RetTy, CallConv, + isVarArg, Outs, Ins, DAG); assert(!(isVarArg && CallConv == CallingConv::Fast) && "Var args not supported with calling convention fastcc"); @@ -2247,6 +2247,7 @@ unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, /// optimization should implement this function. bool X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, + const Type *RetTy, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, @@ -2328,14 +2329,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, return true; // If the return types match, then it's safe. - // Don't tail call optimize recursive call. - GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); - if (!G) return false; // FIXME: common external symbols? - if (const Function *CalleeF = dyn_cast<Function>(G->getGlobal())) { - const Type *CalleeRetTy = CalleeF->getReturnType(); - return CallerRetTy == CalleeRetTy; - } - return false; + return CallerRetTy == RetTy; } FastISel * diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 193ef05..0b906e6 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -627,7 +627,7 @@ namespace llvm { /// IsEligibleForTailCallOptimization - Check whether the call is eligible /// for tail call optimization. Targets which want to do tail call /// optimization should implement this function. - bool IsEligibleForTailCallOptimization(SDValue Callee, + bool IsEligibleForTailCallOptimization(SDValue Callee, const Type *RetTy, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, @@ -707,7 +707,7 @@ namespace llvm { DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, + LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index bf8c38f..e1e73a4 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -609,7 +609,7 @@ SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { /// XCore call implementation SDValue -XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee, +XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/XCore/XCoreISelLowering.h b/lib/Target/XCore/XCoreISelLowering.h index f7b620e..c0b707d 100644 --- a/lib/Target/XCore/XCoreISelLowering.h +++ b/lib/Target/XCore/XCoreISelLowering.h @@ -147,7 +147,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals); virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, + LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, |