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-rw-r--r--lib/CodeGen/LiveIntervalAnalysis.cpp9
-rw-r--r--lib/CodeGen/LiveVariables.cpp2
-rw-r--r--lib/CodeGen/MachineBasicBlock.cpp2
-rw-r--r--lib/CodeGen/MachineInstr.cpp2
-rw-r--r--lib/CodeGen/Makefile2
-rw-r--r--lib/CodeGen/PHIElimination.cpp2
-rw-r--r--lib/CodeGen/PrologEpilogInserter.cpp8
-rw-r--r--lib/CodeGen/RegAllocLocal.cpp2
-rw-r--r--lib/CodeGen/RegAllocSimple.cpp4
-rw-r--r--lib/CodeGen/TwoAddressInstructionPass.cpp2
-rw-r--r--lib/CodeGen/VirtRegMap.cpp2
11 files changed, 18 insertions, 19 deletions
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 9367a7e..0b4ce4d 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -122,7 +122,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
// perform a final pass over the instructions and compute spill
// weights, coalesce virtual registers and remove identity moves
const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
- const TargetInstrInfo& tii = tm_->getInstrInfo();
+ const TargetInstrInfo& tii = *tm_->getInstrInfo();
for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
mbbi != mbbe; ++mbbi) {
@@ -424,7 +424,7 @@ void LiveIntervals::computeIntervals()
for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
mi != miEnd; ++mi) {
const TargetInstrDescriptor& tid =
- tm_->getInstrInfo().get(mi->getOpcode());
+ tm_->getInstrInfo()->get(mi->getOpcode());
DEBUG(std::cerr << getInstructionIndex(mi) << "\t";
mi->print(std::cerr, *tm_));
@@ -455,7 +455,7 @@ void LiveIntervals::joinIntervals()
{
DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
- const TargetInstrInfo& tii = tm_->getInstrInfo();
+ const TargetInstrInfo& tii = *tm_->getInstrInfo();
for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
mbbi != mbbe; ++mbbi) {
@@ -464,8 +464,7 @@ void LiveIntervals::joinIntervals()
for (MachineBasicBlock::iterator mi = mbb->begin(), mie = mbb->end();
mi != mie; ++mi) {
- const TargetInstrDescriptor& tid =
- tm_->getInstrInfo().get(mi->getOpcode());
+ const TargetInstrDescriptor& tid = tii.get(mi->getOpcode());
DEBUG(std::cerr << getInstructionIndex(mi) << '\t';
mi->print(std::cerr, *tm_););
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index f1a7d9e..f652e09 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -159,7 +159,7 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
}
bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
- const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
+ const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
RegInfo = MF.getTarget().getRegisterInfo();
assert(RegInfo && "Target doesn't have register information?");
diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp
index c72b247..43ac49b 100644
--- a/lib/CodeGen/MachineBasicBlock.cpp
+++ b/lib/CodeGen/MachineBasicBlock.cpp
@@ -81,7 +81,7 @@ void ilist_traits<MachineInstr>::transferNodesFromList(
MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator()
{
- const TargetInstrInfo& TII = getParent()->getTarget().getInstrInfo();
+ const TargetInstrInfo& TII = *getParent()->getTarget().getInstrInfo();
iterator I = end();
while (I != begin() && TII.isTerminatorInstr((--I)->getOpcode()));
if (I != end() && !TII.isTerminatorInstr(I->getOpcode())) ++I;
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 8d2cc93..a75c579 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -322,7 +322,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
OS << " = ";
++StartOp; // Don't print this operand again!
}
- OS << TM.getInstrInfo().getName(getOpcode());
+ OS << TM.getInstrInfo()->getName(getOpcode());
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
const MachineOperand& mop = getOperand(i);
diff --git a/lib/CodeGen/Makefile b/lib/CodeGen/Makefile
index 3f45da3..7cd63ae 100644
--- a/lib/CodeGen/Makefile
+++ b/lib/CodeGen/Makefile
@@ -8,7 +8,7 @@
##===----------------------------------------------------------------------===##
LEVEL = ../..
-PARALLEL_DIRS = InstrSched SelectionDAG
+#PARALLEL_DIRS = InstrSched SelectionDAG
LIBRARYNAME = codegen
include $(LEVEL)/Makefile.common
diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index 0cfeb24..895dadd 100644
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -66,7 +66,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
return false; // Quick exit for normal case...
LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
- const TargetInstrInfo &MII = MF.getTarget().getInstrInfo();
+ const TargetInstrInfo &MII = *MF.getTarget().getInstrInfo();
const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
// VRegPHIUseCount - Keep track of the number of times each virtual register
diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index 4082019..52ed5bc 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -82,7 +82,7 @@ FunctionPass *llvm::createPrologEpilogCodeInserter() { return new PEI(); }
///
void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
- const TargetFrameInfo &FrameInfo = Fn.getTarget().getFrameInfo();
+ const TargetFrameInfo &FrameInfo = *Fn.getTarget().getFrameInfo();
// Get the callee saved register list...
const unsigned *CSRegs = RegInfo->getCalleeSaveRegs();
@@ -170,7 +170,7 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
}
// Add code to restore the callee-save registers in each exiting block.
- const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
+ const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI) {
// If last instruction is a return instruction, add an epilogue
if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) {
@@ -191,7 +191,7 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
/// abstract stack objects...
///
void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
- const TargetFrameInfo &TFI = Fn.getTarget().getFrameInfo();
+ const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
bool StackGrowsDown =
TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
@@ -245,7 +245,7 @@ void PEI::insertPrologEpilogCode(MachineFunction &Fn) {
Fn.getTarget().getRegisterInfo()->emitPrologue(Fn);
// Add epilogue to restore the callee-save registers in each exiting block
- const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
+ const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
// If last instruction is a return instruction, add an epilogue
if (!I->empty() && TII.isReturn(I->back().getOpcode()))
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 0b5fdc5..d0df270 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -520,7 +520,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
// loop over each instruction
MachineBasicBlock::iterator MI = MBB.begin();
for (; MI != MBB.end(); ++MI) {
- const TargetInstrDescriptor &TID = TM->getInstrInfo().get(MI->getOpcode());
+ const TargetInstrDescriptor &TID = TM->getInstrInfo()->get(MI->getOpcode());
DEBUG(std::cerr << "\nStarting RegAlloc of: " << *MI;
std::cerr << " Regs have values: ";
for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 1b7f547..4e825b2 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -159,7 +159,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// a preliminary pass that will invalidate any registers that
// are used by the instruction (including implicit uses)
unsigned Opcode = MI->getOpcode();
- const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
+ const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
const unsigned *Regs = Desc.ImplicitUses;
while (*Regs)
RegsUsed[*Regs++] = true;
@@ -184,7 +184,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
if (op.isDef()) {
- if (!TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) || i) {
+ if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) {
physReg = getFreeReg(virtualReg);
} else {
// must be same register number as the first operand
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index a992baf..066260c 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -77,7 +77,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
DEBUG(std::cerr << "Machine Function\n");
const TargetMachine &TM = MF.getTarget();
const MRegisterInfo &MRI = *TM.getRegisterInfo();
- const TargetInstrInfo &TII = TM.getInstrInfo();
+ const TargetInstrInfo &TII = *TM.getInstrInfo();
LiveVariables* LV = getAnalysisToUpdate<LiveVariables>();
bool MadeChange = false;
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 5cec9e9..8fc687d 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -191,7 +191,7 @@ namespace {
bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap& vrm) {
mf_ = &mf;
tm_ = &mf_->getTarget();
- tii_ = &tm_->getInstrInfo();
+ tii_ = tm_->getInstrInfo();
mri_ = tm_->getRegisterInfo();
vrm_ = &vrm;
p2vMap_.assign(mri_->getNumRegs(), 0);
generated by cgit v1.1 at 2025-01-21 04:58:24 +0000