diff options
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 12 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/thumb-printf.txt | 5 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/thumb-tests.txt | 4 |
3 files changed, 15 insertions, 6 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 993ff73..cc7f0d6 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -82,8 +82,16 @@ const char *ARMUtils::OpcodeName(unsigned Opcode) { // FIXME: Auto-gened? static unsigned getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) { - // For this purpose, we can treat rGPR as if it were GPR. - if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID; + if (RegClassID == ARM::rGPRRegClassID) { + // Check for The register numbers 13 and 15 that are not permitted for many + // Thumb register specifiers. + if (RawRegister == 13 || RawRegister == 15) { + B->SetErr(-1); + return 0; + } + // For this purpose, we can treat rGPR as if it were GPR. + RegClassID = ARM::GPRRegClassID; + } // See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm(). unsigned RegNum = diff --git a/test/MC/Disassembler/ARM/thumb-printf.txt b/test/MC/Disassembler/ARM/thumb-printf.txt index 6245b7c..09f54ab 100644 --- a/test/MC/Disassembler/ARM/thumb-printf.txt +++ b/test/MC/Disassembler/ARM/thumb-printf.txt @@ -26,7 +26,8 @@ # CHECK-NEXT: mov r2, r5 # CHECK-NEXT: ldr r3, [sp] # CHECK-NEXT: bl #-8390 -# CHECK-NEXT: sub.w sp, r7, #8 +# Data bytes (corresponds to an invalid instruction) +# But not: sub.w sp, r7, #8 # CHECK-NEXT: pop.w {r4, r5, r7, lr} # CHECK-NEXT: add sp, #16 # CHECK-NEXT: bx lr @@ -63,7 +64,7 @@ 0x2a 0x46 0x00 0x9b 0xfd 0xf7 0x9d 0xff -0xa7 0xf1 0x08 0x0d +# 0xa7 0xf1 0x08 0x0d 0xbd 0xe8 0xb0 0x40 0x04 0xb0 0x70 0x47 diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index fb53f59..6052069 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -42,8 +42,8 @@ # CHECK: ldrd r0, r1, [r7, #64]! 0xf7 0xe9 0x10 0x01 -# CHECK: lsls.w r0, pc, #1 -0x5f 0xea 0x4f 0x00 +# CHECK: lsls.w r0, r5, #1 +0x5f 0xea 0x45 0x00 # CHECK: mov r11, r7 0xbb 0x46 |