diff options
| -rw-r--r-- | lib/Target/CellSPU/SPUISelDAGToDAG.cpp | 12 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/storestruct.ll | 13 |
2 files changed, 23 insertions, 2 deletions
diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index c3c2b39..9afdb2b 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -941,13 +941,21 @@ SPUDAGToDAGISel::Select(SDNode *N) { && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0 && RN->getReg() != SPU::R1))) { NewOpc = SPU::Ar32; + Ops[1] = Op1; if (Op1.getOpcode() == ISD::Constant) { ConstantSDNode *CN = cast<ConstantSDNode>(Op1); Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT); - NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32); + if (isInt<10>(CN->getSExtValue())) { + NewOpc = SPU::AIr32; + Ops[1] = Op1; + } else { + Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILr32, dl, + N->getValueType(0), + Op1), + 0); + } } Ops[0] = Op0; - Ops[1] = Op1; n_ops = 2; } } diff --git a/test/CodeGen/CellSPU/storestruct.ll b/test/CodeGen/CellSPU/storestruct.ll new file mode 100644 index 0000000..47185e8 --- /dev/null +++ b/test/CodeGen/CellSPU/storestruct.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=cellspu | FileCheck %s + +%0 = type {i32, i32} +@buffer = global [ 72 x %0 ] zeroinitializer + +define void@test( ) { +; Check that there is no illegal "a rt, ra, imm" instruction +; CHECK-NOT: a {{\$., \$., 5..}} +; CHECK: a {{\$., \$., \$.}} + store %0 {i32 1, i32 2} , + %0* getelementptr ([72 x %0]* @buffer, i32 0, i32 71) + ret void +} |