diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAGNodes.h | 12 | ||||
| -rw-r--r-- | include/llvm/Target/TargetSelectionDAG.td | 5 |
2 files changed, 0 insertions, 17 deletions
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index 6cea5d6..7d74825 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -327,18 +327,6 @@ namespace ISD { /// elements 1 to N-1 of the N-element vector are undefined. SCALAR_TO_VECTOR, - // EXTRACT_SUBREG - This node is used to extract a sub-register value. - // This node takes a superreg and a constant sub-register index as operands. - // Note sub-register indices must be increasing. That is, if the - // sub-register index of a 8-bit sub-register is N, then the index for a - // 16-bit sub-register must be at least N+1. - EXTRACT_SUBREG, - - // INSERT_SUBREG - This node is used to insert a sub-register value. - // This node takes a superreg, a subreg value, and a constant sub-register - // index as operands. - INSERT_SUBREG, - // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing // an unsigned/signed value of type i[2*N], then return the top part. MULHU, MULHS, diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index 5d1b37d..7f39bb2 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -406,11 +406,6 @@ def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; -def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG", - SDTypeProfile<1, 2, []>>; -def insert_subreg : SDNode<"ISD::INSERT_SUBREG", - SDTypeProfile<1, 3, []>>; - // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use // these internally. Don't reference these directly. def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", |